Method for improving nanoscale small nappe PL blackening of perovskite crystalline silicon bottom cell

Abstract

The present application relates to the technical field of perovskite battery, and particularly relates to a method for improving nanoscale small napped PL blackening of perovskite crystalline silicon bottom cell, a micropore array is prepared on a silicon wafer with nanoscale napping, the micropore array is used as an impurity trap to transfer metal impurities from an active region to micropores; further comprising an ion exchange resin adsorption step, the ion exchange resin adsorption is the last step, impurities washed out of the silicon wafer and impurities appearing in a tank during the cleaning process are adsorbed by resin ball particles to prevent secondary diffusion of the impurities from adhering to the silicon wafer. After the nanoscale napped silicon wafer is processed, the nanoscale napped silicon wafer PL blackening defect is reduced from 30% to 0.01% or less, and the product yield is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of perovskite battery, and particularly relates to a method for improving nanoscale small-textured PL blackening of perovskite crystalline silicon bottom cell. BACKGROUND

[0002] The single crystal silicon textured surface is a pyramid structure formed by corrosion of sodium hydroxide or potassium hydroxide alkaline solution. Although this micron-level concave-convex surface can increase light absorption, the structure is composed of dense micron-level pyramid structures, and the grooves and gaps are easy to adsorb particulate matter and organic residues. Contaminants such as etching solution, additives, metal ions and dust are easily embedded in the gaps between the pyramids, and it is difficult to completely remove them by conventional rinsing, which brings challenges to cleaning. Especially on perovskite / silicon-based laminated solar cells, perovskite silicon-based laminated cells require smaller texturing, and the size of the textured surface is changed from micron level to nanometer level. The purpose is that the nanotexture has better wettability to the perovskite solution, can achieve conformal coverage, and avoid the problem of film rupture or hole caused by large pyramid structure. At the same time, the confinement effect of nanoscale can induce vertical growth of perovskite grains, and improve the crystal quality. On the other hand, the nanostructure can promote carrier separation and collection, and the nano-textured surface can help release the residual stress of the perovskite film and improve the stability of the perovskite laminated cell device.

[0003] Although the nanoscale textured surface has excellent properties as a perovskite laminated substrate, the nanoscale textured surface can cause deep retention of contaminants. After the subsequent PECVD process, the deep retention area of the contaminants will form a local high-resistance area or a micro-short circuit channel. When PL (photoluminescence) detection is performed, the carrier recombination in this area is intensified, and dark spots appear, resulting in blackening. After the product cell is made, the performance of the laminated cell will be deteriorated. The main reason is that the nanotexture is composed of dense sub-micron grooves or holes (typical size <500nm), and the depth can reach micron level, forming a super-high aspect ratio structure. Once the external contaminants (such as metal particles and organic matter) enter the groove bottom, the conventional water flow shear force cannot remove them. On the other hand, the nano-scale pores produce strong capillary force, which actively adsorbs impurity particles in the liquid, making it easier for contaminants to embed inside the structure rather than stay on the surface.

[0004] Currently, in order to improve the problem of contamination residue or incomplete cleaning of the nanoscale textured surface, the following methods are used: adjusting the bubble parameters to enhance the permeability of the etching solution, increasing the water flow to improve the hydrophobicity, optimizing the slow pulling speed to reduce the liquid film residue, high-frequency ultrasonic cleaning, low-surface-tension solvent cleaning, etc. This method is effective for micron-level textured surfaces, but it is not significant for nanoscale textured surfaces. Therefore, new technical means and new device systems are needed to solve the problems of contamination residue and deep retention during the growth of nanoscale textured surfaces. SUMMARY

[0005] The application aims to provide a method for improving nano-scale small-textured PL blackening of perovskite crystalline silicon bottom cell, and solve the technical problem of residual and deep retention of pollutants in the growth process of nano-scale textured surface in the prior art.

[0006] The application discloses a method for improving nano-scale small-textured PL blackening of perovskite crystalline silicon bottom cell, and a micropore array is prepared on a silicon wafer with nano-scale textured surface, the micropore array is used as an impurity trap to transfer metal impurities from an active region to micropores.

[0007] Further, the micropore diameter of the micropore array is 10-50 nm.

[0008] Further, the micropore array is obtained through helium ion treatment and then annealing.

[0009] Further, the micropore array is prepared by injecting helium ions and annealing at 750-850 DEG C for 4-10 minutes to form the micropore array.

[0010] Further, the helium ions are injected at an energy of 5-20 keV, and the injection dose is 1x10 12 -1x10 13 cm -2 .

[0011] Further, the method further comprises an ion exchange resin adsorption step, the ion exchange resin adsorption is the last step, impurities washed out of the silicon wafer and impurities appearing in the tank during the cleaning process are adsorbed by resin ball particles to prevent secondary diffusion of the impurities and adhere to the silicon wafer.

[0012] Further, the ion exchange resin adsorption step comprises removing a phosphosilicate glass and an impurity layer on the surface of the silicon wafer and cleaning residual cleaning chemicals on the surface of the silicon wafer.

[0013] Further, the removing of the phosphosilicate glass and the impurity layer on the surface of the silicon wafer specifically comprises: placing the silicon wafer in cleaning chemicals mixed with first ion exchange resin for cleaning, the cleaning time is 60-120 s, and the temperature is 20-30 DEG C, so that the phosphosilicate glass and the impurity layer on the surface of the silicon wafer are removed.

[0014] Further, the first ion exchange resin is a macroporous adsorption resin, which mechanically intercepts suspended solids and adsorbs hydrophobic organic matter.

[0015] Further, the cleaning chemicals are HF / HCL = 1:0.2-0.3 in volume ratio.

[0016] Further, the cleaning of the residual cleaning agent on the surface of the silicon wafer is specifically placing the silicon wafer into pure water mixed with the second ion exchange resin, cleaning for 60-120s, and at a temperature of 20-30℃, thereby simultaneously removing the residual anions and cations and improving the purity, and adsorbing the hydrophobic organic matter.

[0017] Further, the second ion exchange resin is a resin uniformly mixed with positive and negative resins.

[0018] Further, after the cleaning of the residual cleaning agent is completed, rinsing and drying are performed to complete the treatment.

[0019] Further, the rinsing is performed in a slow pull slot containing third ion exchange resin balls, the cleaning time is 200-300s, and the temperature is 50-70℃.

[0020] Further, the third ion exchange resin balls are mixed bed resins.

[0021] Further, after the preparation of the micropore array is completed, the steps of cleaning, high-temperature phosphorus diffusion deep treatment, bulk plasma discharge etching, and ion exchange resin adsorption are further included.

[0022] Further, after annealing is completed, cleaning is performed to remove the surface residues and metal impurities migrated to the surface layer.

[0023] Further, the cleaning is specifically: first, using a 0.8% concentration of HF solution to treat and dissolve the surface silicon oxide micropore array generated by annealing, cleaning for 30-120s, and at a temperature of 20-125℃, thereby avoiding blocking the penetration of subsequent cleaning agents; second, using an ammonia-hydrogen peroxide mixed solution to remove organic matter, particulate contaminants, and complexed alkali metals (sodium and potassium ions), and the process parameters are 60-80℃ for 3-5 minutes; third, using a hydrochloric acid-hydrogen peroxide mixed solution to remove transition metals (iron, copper, etc.) and SC-1 residues, and the process parameters are 60-80℃ for 3-5 minutes; and finally, performing pure water cleaning and drying.

[0024] Further, the size of the silicon wafer surface is 100-900nm, and the depth is 100-900nm.

[0025] Further, the high-temperature phosphorus diffusion deep treatment is to precipitate the impurities in the deep trenches of the nano surface to the surface by high-temperature phosphorus gettering.

[0026] Further, the plasma discharge etching is to ionize the impurities precipitated by the high-temperature phosphorus diffusion deep treatment and the impurities in the deep trenches of the surface, so as to make them into a loose delamination state.

[0027] Further, the plasma discharge etching uses a mixed gas of CF4 and O2 as the plasma source material, the volume ratio of CF4:O2 is 1:0.05-0.15, the radio frequency power is 100-300 W, the processing time is 1-3 minutes, and the chamber pressure is 50-200 Pa.

[0028] A perovskite crystalline silicon bottom cell is prepared by using the method.

[0029] Compared with the prior art, the present application has the beneficial effects that:

[0030] 1. The present application sequentially performs body surface helium ion primary treatment, internal high-temperature phosphorus diffusion deep layer treatment and overall plasma bombardment on the nanoscale textured silicon wafer, forming a systematic process of impurity removal from the surface to the interior to the whole, effectively removing the surface contaminants and the deep retention of the textured nanoscale silicon wafer;

[0031] 2. The present application cleans the silicon wafer containing ion exchange resin ball tank after systematic treatment, on the one hand ensuring that the impurities cleaned out of the silicon wafer are adsorbed, and on the other hand ensuring that the impurities existing in the solution are adsorbed, thereby forming the simultaneous adsorption of the dirt of the silicon wafer and the dirt of the solution on the resin ball particles, preventing the secondary diffusion of the contaminants in the tank body and adhering to the silicon wafer, so as to actively adsorb the impurity particles in the liquid by the strong capillary force generated by the pores of the nanoscale textured silicon wafer, preventing the embedding of the contaminants in the structure interior and surface;

[0032] 3. By performing external, internal and overall systematic impurity absorption + ion exchange resin ball adsorption cleaning on the nanoscale textured silicon wafer, the effect of 1+1>2 is realized, the PL blackening defect of the nanoscale textured silicon wafer after treatment is reduced from 30% to 0.01% or less, and the product yield is greatly improved; the nanoscale textured minority carrier lifetime after the process treatment is improved from 970us to 2500us, and finally the conversion efficiency of the stacked battery is improved by 0.8%. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only represent some embodiments of the present application, and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0034] Fig. 1 The PL test diagram of the nanoscale textured silicon wafer after the process treatment of the embodiments of the present application.

[0035] Fig. 2 The PL test diagram of the nanoscale textured silicon wafer after the process treatment of the comparative example 1. DETAILED DESCRIPTION

[0036] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application are described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments.

[0037] Embodiment 1

[0038] A method for improving the nanoscale small-textured PL blackening of a perovskite crystalline silicon bottom cell is disclosed in this embodiment, comprising the following steps:

[0039] Step 1: Pre-clean, phosphorus gettering, texturing, acid washing, water washing and drying are performed on a single crystal silicon wafer to obtain a nanotextured silicon wafer, the nanotextured silicon wafer has a textured size of 500 nm and a depth of 500 nm.

[0040] Step 2: The surface of the nanotextured silicon wafer is subjected to helium ion primary treatment, helium ions are implanted, and annealing is performed at 800℃ for 6 minutes. After annealing, a micropore array with a diameter of 30 nm is formed. These micropores act as impurity traps and can transfer metal impurities from the active region to the micropores. The helium ions are implanted at an energy of 10 keV and an implantation dose of 1×1015 cm-2. 13 -2 .

[0041] Step 3: After annealing, cleaning is performed to remove surface residues and metal impurities that may have migrated to the surface layer. First, a 0.5% concentration of HF solution is used to dissolve the surface silicon oxide generated during annealing, the cleaning time is 80 s and the temperature is 50℃ to avoid blocking the penetration of subsequent cleaning agents. Second, an ammonia-hydrogen peroxide mixed solution is used to remove organic matter, particulate contaminants and complex alkali metal ions (sodium and potassium ions), the process parameters are 80℃ for 5 minutes. Third, a hydrochloric acid-hydrogen peroxide mixed solution is used to remove transition metals (iron, copper, etc.) and SC-1 residues, the process parameters are 80℃ for 3 minutes. Finally, pure water cleaning and drying are performed.

[0042] Step 4: High-temperature phosphorus diffusion deep treatment is performed on the inside of the nanotextured surface to extract impurities from the deep trenches of the nanotextured surface to the surface.

[0043] Step 5: The nanotextured silicon wafer is subjected to overall plasma discharge etching to ionize the impurities adsorbed by the micropores, the impurities extracted after phosphorus diffusion treatment and the impurities in the deep trenches of the textured surface into a loose delamination state. The plasma source material is a mixed gas of CF4 and O2, the reaction gas ratio is CF4:O2=1:0.05 (volume ratio), the radio frequency power is 100 W, the treatment time is 3 minutes and the chamber pressure is 100 pa.

[0044] ​Step 6: The nano-silicon wafer is placed in an ion exchange resin ball tank for cleaning. The impurities cleaned out of the silicon wafer and the impurities present in the tank during the cleaning process are adsorbed by the resin ball particles, preventing the impurities from being attached to the silicon wafer again. This step specifically includes the following steps:

[0045] (1) First, the silicon wafer is placed in an HF / HCL tank containing ion exchange resin balls to remove the phosphor-silicon glass and impurity layer on the surface of the silicon wafer. The ion exchange resin in the tank is a macroporous adsorption resin that mechanically traps suspended solids and adsorbs hydrophobic organic matter. The cleaning solution is HF / HCL = 1:0.2 (volume ratio), the cleaning time is 120 seconds, and the temperature is 25°C.

[0046] (2) The silicon wafer is placed in a pure water tank containing ion exchange resin balls to clean the residual cleaning solution on the surface of the silicon wafer. The ion exchange resin in the tank is a mixture of positive and negative resins that simultaneously remove residual anions and cations, improve purity, and adsorb hydrophobic organic matter. The cleaning time is 100 seconds, and the temperature is 25°C.

[0047] (3) The silicon wafer is placed in a slow pull tank containing ion exchange resin balls for final rinsing. The cleaning time is 300 seconds, and the temperature is 70°C.

[0048] (4) Drying;

[0049] Step 7: The front and back of the finished nano-silicon wafer is coated with amorphous silicon / microcrystalline silicon film using PECVD, and the minority carrier lifetime and PL are detected.

[0050] Step 9: Transparent conductive film is coated on the front and back of the silicon wafer using PVD.

[0051] Step 10: Metal electrodes are printed on the P-silicon wafer, and a hole transport layer, perovskite layer, organic passivation layer, electron transport layer, tin oxide buffer layer, transparent conductive film layer, and metal electrodes are sequentially deposited on the N-silicon wafer to form a stacked battery.

[0052] Step 11: Test the electrical performance efficiency of the stacked battery.

[0053] Example 2

[0054] Based on Example 1, the only change is that Step 2 is annealed at 850°C for 5 minutes to form a 50 nm diameter micropore array. These micropores act as impurity traps, allowing metal impurities to be transferred from the active region to the micropores. Helium ions are injected at an energy of 15 keV, with an injection dose of 1×10 12 cm -2 .

[0055] Example 3

[0056] The only change based on Example 1 is that in step 6, the nanometer silicon wafer is placed in an ion exchange resin ball tank for cleaning, wherein the cleaning solution formula is HF / HCL=1:0.3 (volume ratio), the cleaning time is 100s, and the temperature is 30℃.

[0057] Comparative Example 1

[0058] The only change based on Example 1 is that the bottom cell and the stacked cell are prepared by using a traditional process, that is, only step 1 of the traditional process is used to pre-clean, phosphorus gettering, texturing, acid washing, water washing, and drying of the single crystal silicon wafer to obtain a nanometer textured silicon wafer, the textured silicon wafer has a size of 500nm and a depth of 500nm, and then the traditional process steps such as CVD and PVD are performed to process the silicon wafer to prepare a finished product battery.

[0059] Comparative Example 2

[0060] The only change based on Example 1 is that step 2 of primary treatment of the nanometer textured silicon wafer by helium ions is not included, that is, step 1 is directly followed by step 4 and subsequent steps.

[0061] Comparative Example 3

[0062] The only change based on Example 1 is that step 6 of placing the nanometer silicon wafer in an ion exchange resin ball tank for cleaning is not included, but a traditional cleaning process is used for cleaning, that is, a traditional cleaning tank is placed with chemical solution, without placing or designing any adsorption device and structure.

[0063] Comparative Example 4

[0064] The only change based on Example 1 is that after the injection of helium ions in step 2, annealing is performed at a temperature of 500℃ for 3 minutes, and a micropore array with a diameter of 10nm is formed after annealing.

[0065] Comparative Example 5

[0066] The only change based on Example 1 is that in step 6, instead of using an ion resin tank for cleaning and adsorption, a traditional filter core is used for cleaning and adsorption.

[0067] PL, minority carrier lifetime, and conversion efficiency comparison tests are performed on the examples and comparative examples:

[0068] (1) PL test

[0069] That is, the photoluminescence test is performed by using a 500-800nm wavelength laser as an excitation light source, the laser excitation of the silicon wafer causes the silicon wafer to emit infrared light with a peak wavelength of about 1150nm, then a high-sensitivity and high-resolution camera is used for photosensing and imaging, and finally data processing is performed to obtain the defects on the surface of the solar cell wafer.

[0070] After the nano suede silicon wafer is treated by the inventive process, after a CVD process, PL is tested, and the test results are shown in Table 1.

[0071] Table 1 PL defect comparison

[0072]

[0073] As shown in Table 1, the PL ratio of the examples is between 0.00% and 0.01%, and the PL ratio of the comparative examples is between 7.66% and 30.08%. The PL improvement effect of the inventive process on the nano suede silicon wafer is remarkable, and the PL defect ratio decreases from 30% to less than 0.01%. From Figs. 1-2 It can be seen that there are a large number of defects in the PL test graph of the nano suede treated by the process of the comparative example, and the PL is black. There is no abnormal PL in the PL test graph of the nano suede treated by the process of the example.

[0074] As shown in Comparative Example 1 (traditional process), the PL defect ratio of the nano suede silicon wafer prepared by the traditional process reaches 22.85%-30.08%, and the PL defect ratio is the highest.

[0075] As shown in Comparative Example 2, the nano suede silicon wafer is not subjected to the primary helium ion surface treatment of step 2, but directly enters step 4 and the subsequent steps after step 1. Although the defect ratio decreases by about 50% compared with Comparative Example 1, the overall ratio is still 9.56%-30.08%. Of course, it also reflects that the nano suede silicon wafer treated by the subsequent process of the application will also be improved without step 2.

[0076] As shown in Comparative Example 3, step 6 places the nano silicon wafer in the ion exchange resin ball tank for cleaning, but uses the traditional cleaning process, i.e. the traditional cleaning tank is placed with chemical liquid, and does not place or design any adsorption device and structure. As the number of cleaning times of the silicon wafer increases, the PL defect ratio begins to increase. From silicon wafer batch 1 to silicon wafer batch 5, the PL defect ratio gradually increases from 9.17% to 13.15%→13.67%→15.29%→18.07%, which shows that as the number of cleaning times increases, the impurities remaining in the liquid increase, thereby affecting the cleaning ability of the liquid on the silicon wafer and causing secondary residues on the silicon wafer. Thus, it is proved that the silicon wafer treated by the process of the application is cleaned by the ion exchange resin ball tank, which on the one hand ensures that the impurities cleaned out of the silicon wafer are adsorbed, and on the other hand ensures that the impurities existing in the solution are adsorbed, so that the dirt of the silicon wafer and the dirt of the solution are simultaneously adsorbed by the resin ball particles, preventing the secondary diffusion of pollutants in the tank and adhering to the silicon wafer, so that the tank solution remains clean, thereby actively adsorbing the impurity particles in the liquid by the strong capillary force generated by the nano suede silicon wafer pores, and embedding the pollutants in the structure inside and on the surface.

[0077] From the comparative example 4, it can be seen that after the injection of helium ions, the annealing at 500 DEG C for 3 minutes forms a micropore array with a diameter of 10 nm. Compared with the temperature annealing of 750-850 DEG C of the embodiment, the insufficient annealing of the comparative example 4 leads to incomplete micropore formation and incomplete impurity removal, and the PL is still high at 15.20%-21.33%.

[0078] From the comparative example 5, it can be seen that the ion resin tank cleaning and adsorption is not used in the process of step 6, and the tank cleaning and adsorption is carried out by using a traditional filter core. Although the filter core has a certain adsorption capacity, the PL ratio of the PL is still 8%-15%, and the PL ratio gradually increases with the increase of the cleaning times, and the PL ratio reaches 15.13%. The process of the present application proposes that different ion resin tank cleaning and adsorption is used for different tanks, such as the acid washing tank which uses a macroporous adsorption resin to mechanically intercept suspended solids and adsorb hydrophobic organic matter; the water washing tank which uses a mixed resin of positive and negative resins; and the slow pulling tank which uses a mixed bed resin to clean and adsorb, so as to provide a higher pure cleaning environment for the tank, ensure the cleanliness of the nanoscale silicon wafer surface, prevent the formation of recombination centers on the surface of the silicon wafer, and thus improve the PL.

[0079] (2) Minority carrier lifetime test

[0080] The sinton minority carrier lifetime tester of the United States is used, the model is WCT-120, the quasi-steady-state photoconductivity (QSSPC) test principle is adopted, the quality is evaluated by measuring the minority carrier lifetime of the silicon wafer under light. The principle is based on the recombination process of the photo-generated carriers of the semiconductor material under light, and the material defects (such as trap density, surface recombination, etc.) are revealed by analyzing the change of the recombination rate.

[0081] After the nanotextured silicon wafer is treated by the process of the present application, the minority carrier lifetime is tested after the CVD process, and the test results are shown in Table 2.

[0082] Table 2: Comparison of minority carrier lifetime test data

[0083]

[0084] From Table 2, it can be seen that the minority carrier lifetime of the embodiment is between 2197 μs and 2503 μs, and the comparative example is between 970 μs and 1719 μs. The embodiment of the process of the present application significantly improves the minority carrier lifetime of the nanotextured silicon wafer, and the minority carrier lifetime is increased from 970 μs to 2503 μs. The higher the minority carrier lifetime means the lower the defect density, the higher the probability of collecting photo-generated carriers, and the fewer the carrier recombination, so as to improve the battery efficiency.

[0085] From the comparative example 1 (traditional process), it can be seen that the minority carrier lifetime of the nanotextured silicon wafer prepared by the traditional process is between 970 μs and 1329 μs, and the minority carrier lifetime is the lowest.

[0086] From the comparative example 2, it can be seen that, without the step 2 of primary treatment of the body surface of the nanometer-sized suede silicon wafer by helium ions, i.e. directly entering the step 4 and the subsequent steps after the step 1, although the minority carrier lifetime is increased by about 500 μs relative to the comparative example 1, the overall minority carrier lifetime is still in the range of 1528 μs-1709 μs, and of course, it is also reflected that the nanometer-sized suede silicon wafer is not treated by the subsequent process of the application without the step 2, and there is also an improvement.

[0087] From the comparative example 3, it can be seen that, in the step 6, the nanometer-sized silicon wafer is cleaned in the ion exchange resin ball tank, and the traditional cleaning process is used for cleaning, i.e. the traditional cleaning tank is placed with chemical liquid, and there is no any adsorption device and structure, and with the increase of the cleaning times of the silicon wafer, the minority carrier lifetime starts to decrease, and from the silicon wafer batch 1 to the silicon wafer batch 5, the minority carrier lifetime gradually decreases from 1699 μs to 1652 μs→1530 μs→1406 μs→1364 μs, which shows that with the increase of the cleaning times, the impurities remaining in the tank liquid are increased, thereby affecting the cleaning ability of the tank liquid to the silicon wafer and being secondarily remained on the silicon wafer to form a recombination center and decrease the minority carrier lifetime. Thus, it is proved that the silicon wafer treated by the process of the application is cleaned in the ion exchange resin ball tank, on the one hand, the impurities cleaned out of the silicon wafer are adsorbed, and on the other hand, the impurities existing in the solution are adsorbed, so that the dirt of the silicon wafer and the dirt of the solution are simultaneously adsorbed on the resin ball particles, the secondary diffusion of the pollutants on the silicon wafer in the tank is prevented, the solution in the tank is kept clean, the impurity particles in the liquid are actively adsorbed by the strong capillary force generated by the pores of the nanometer-sized suede silicon wafer, and the pollutants are prevented from being embedded in the internal structure and the surface.

[0088] From the comparative example 4, it can be seen that, after the injection of helium ions, the annealing is performed at a temperature of 500 ℃ for 3 minutes, and the micropore array with a diameter of 10 nm is formed after the annealing, and compared with the temperature annealing of 750-850 ℃ in the embodiment, the insufficient annealing of the comparative example 4 will lead to incomplete formation of the micropores and incomplete removal of the impurities, and the minority carrier lifetime is in the range of 1307 μs-1554 μs, which is about 800 μs-1000 μs lower than the minority carrier lifetime of 2197 μs-2503 μs in the embodiment.

[0089] From the comparative example 5, it can be seen that the ion resin tank cleaning adsorption is not used in the step 6 process, and the tank cleaning adsorption using the traditional filter core filtering has a certain adsorption capacity, but without ion conversion function, the minority carrier lifetime is 1406-1937 μs, which is lower than the minority carrier lifetime of the embodiment by about 600-7000 μs. With the increase of cleaning times, the minority carrier lifetime decreases. The present application process proposes to use different ion resin tank cleaning adsorption for different tanks, such as the acid pickling tank using macroporous adsorption resin, mechanically intercepting suspended solids and adsorbing hydrophobic organic matter; the water washing tank using uniformly mixed resin of positive and negative resin; the slow pulling tank using mixed bed resin cleaning adsorption to provide a higher pure cleaning environment for the tank, ensure the cleanliness of the nanoscale silicon wafer surface, and make the silicon wafer surface not produce recombination centers, thereby ensuring the high minority carrier lifetime.

[0090] (3) Photoelectric conversion efficiency test

[0091] Under the standard test conditions (STC), AM1.5 spectrum, 1000 W / m2 irradiance, 25 °C battery temperature environment, the nanometer suede prepared into a laminated battery after the process of the present application is tested for efficiency, and the test results are shown in Table 3:

[0092] Table 3 Photoelectric conversion efficiency comparison

[0093]

[0094] From Table 3, it can be seen that the average efficiency of the laminated battery prepared by the process of the present application is 31.56%, and the laminated battery prepared by the comparative example is 30.75%, the efficiency of the process of the present application is higher than that of the comparative example by 0.81%, and the electrical performance of the comparative example is mainly lower than that of the embodiment in open circuit voltage and fill factor. From the comparative example 1 (traditional process), it can be seen that the conversion efficiency of the laminated battery prepared by the traditional process is the lowest, which is 19.37%, which is lower than that of the comparative example by 1.19%, and the main open circuit voltage is lower by 0.4 V and the fill factor is lower by 0.65%, which shows that the nanoscale silicon wafer is not clean, there are high-density defects or pollution, which leads to the intensification of bulk recombination and surface recombination, resulting in the phenomenon of blackening and open circuit voltage drop in PL test, and the recombination center will hinder the carrier transport, increase the equivalent series resistance, and thus reduce the fill factor. Comparative examples 2-5 use the local process of the present application, so the conversion efficiency is higher than that of comparative example 1. In summary, the process of the present application has significant advantages in yield improvement, minority carrier lifetime improvement and conversion efficiency improvement.

[0095] The above are the embodiments enumerated by the present embodiment, but the present embodiment is not limited to the optional embodiments described above, and those skilled in the art can obtain other various embodiments by arbitrarily combining the above-described modes with each other. Any person can obtain other various forms of embodiments under the inspiration of the present embodiment. The above specific embodiments should not be understood as limiting the protection scope of the present embodiment, and the protection scope of the present embodiment should be defined by the claims, and the specification can be used to explain the claims.

Claims

1. A method for improving the nanoscale matte PL blackening of a perovskite crystalline silicon bottom cell, the method comprising: The silicon wafer with nano-scale surface is used to prepare a micropore array, which is used as an impurity trap to transfer metal impurities from an active region to the micropores; ​ The ion exchange resin adsorption step is also included, which is the last step, to adsorb the impurities washed out from the silicon wafer and the impurities in the tank during the cleaning process by the resin ball particles, so as to prevent the secondary diffusion of the impurities on the silicon wafer. The micropore array is obtained by helium ion treatment and then annealing; The helium ions are implanted with an energy of 5-20 keV, an implantation dose of 1 x 10 12 -1 x 10 13 cm -2 -2, and the annealing is ambient annealing at 750-850 °C for 4-10 minutes.

2. The method for improving the nanoscale small matte PL blackening of a perovskite crystalline silicon bottom cell according to claim 1, characterized in that: The micropore diameter of the micropore array is 10-50 nm.

3. The method for improving the nanoscale matt PL blackening of a perovskite crystalline silicon bottom cell according to claim 1, characterized in that: The exchange resin adsorption step includes removing the phosphosilicate glass and impurity layer on the surface of the silicon wafer and cleaning the residual cleaning chemical solution on the surface of the silicon wafer.

4. The method for improving the nanoscale matt PL blackening of a perovskite crystalline silicon bottom cell according to claim 3, characterized in that: The removing of the phosphosilicate glass and impurity layer on the surface of the silicon wafer specifically includes placing the silicon wafer in a cleaning chemical solution mixed with a first ion exchange resin for cleaning, with a cleaning time of 60-120 s and a temperature of 20-30℃.

5. The method for improving the nanoscale matt PL blackening of a perovskite crystalline silicon bottom cell according to claim 3, characterized in that: The cleaning of the residual cleaning chemical solution on the surface of the silicon wafer specifically includes placing the silicon wafer in pure water mixed with a second ion exchange resin, with a cleaning time of 60-120 s and a temperature of 20-30℃, to simultaneously remove the residual anions and cations and improve the purity, and to adsorb hydrophobic organic matter.

6. The method for improving the nanoscale matt PL blackening of a perovskite crystalline silicon bottom cell according to claim 1, characterized in that: The micropore array preparation further includes cleaning, high-temperature phosphorus diffusion deep treatment, overall plasma discharge etching and ion exchange resin adsorption steps.

7. The method for improving the nanoscale matt PL blackening of a perovskite crystalline silicon bottom cell according to claim 1, characterized in that: The size of the surface of the silicon wafer is 100-900 nm, and the depth is 100-900 nm.

8. A perovskite crystalline silicon bottom cell, characterized by: The method is prepared by using the method for improving the PL blackening of the nano-scale small surface of the perovskite crystalline silicon bottom cell according to any one of claims 1-7.

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