Optoelectronic device and method of manufacture

Abstract

A device wafer includes an optoelectronic device epitaxial structure on a substrate wafer, the device epitaxial structure including a porous region of group III nitride material; etching the device epitaxial structure into a plurality of device platforms; depositing a liner dielectric layer over the plurality of device platforms; forming a plurality of metal vias extending through the liner dielectric layer to respective device lands; and bonding the device wafer to a drive wafer including drive circuitry such that the drive circuitry is operably coupled to the plurality of device platforms through the metal vias. An optoelectronic device includes: a driving wafer including a driving circuit; a plurality of optoelectronic device platforms, each device platform configured to emit light from a light emitting side of the device in response to a drive current from the drive circuit; a porous region of group III nitride material epitaxially connected to one or more of the device platforms; and a pad dielectric layer between the drive wafer and the device stage; each opto-electronic device platform is operably coupled to the driver circuit by a plurality of metal vias extending through the liner dielectric layer.

Description

Technical Field

[0001] The present invention relates to an optoelectronic device and a method for manufacturing an optoelectronic device. In particular, the present invention relates to a monolithic optoelectronic semiconductor device array with enhanced optical properties. Background Art

[0002] Group III-V semiconductor materials have received particular attention in semiconductor device design, especially Group III nitride semiconductor materials.

[0003] “III-V” semiconductors include binary, ternary, and quaternary alloys of Group III elements (e.g., Ga, Al, and In) and Group V elements (e.g., N, P, As, and Sb) and have garnered significant interest in many applications, including electronic and optoelectronic devices.

[0004] Of particular interest are semiconductor materials known as "Group III nitrides," which include gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and their ternary and quaternary alloys. (Al,In)GaN is a term encompassing AlGaN, InGaN, and GaN. Group III nitride materials have not only achieved commercial success in solid-state lighting and power electronics but also exhibit unique advantages in quantum light sources and light-matter interactions.

[0005] While various Group III nitride materials have received commercial attention, gallium nitride (GaN) is widely considered to be one of the most important new semiconductor materials and is of particular interest in many applications.

[0006] The present invention will be described primarily with reference to GaN and InGaN, but may be advantageously applied to alternative Group III nitride material combinations.

[0007] It is known that introducing porosity into bulk III-nitrides (e.g., GaN) can significantly affect their material properties (optical, mechanical, electrical, and thermal). Therefore, the possibility of tuning various material properties of GaN and III-nitride semiconductors by varying their porosity has attracted significant attention in optoelectronic applications.

[0008] The inventors have also discovered that by using a porous Group III nitride material as a substrate or template for the epitaxial growth of additional semiconductor layers and semiconductor devices, the porous layer can impart beneficial properties, such as strain relaxation, to the epitaxially grown device. However, after epitaxial growth of the desired semiconductor device, it may be necessary to remove the semiconductor device from the porous template and transfer the semiconductor device to another carrier for fabrication into an electronic or optoelectronic device. The present invention is intended to facilitate the safe and reliable removal of a semiconductor device from a substrate on which a semiconductor device has been grown.

[0009] In the present invention, a region or layer of semiconductor material may be made porous by electrochemical etching as described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0010] Issues to be resolved

[0011] Integrating different semiconductor devices or components into an integrated end product is a major challenge in device manufacturing.

[0012] To manufacture integrated semiconductor devices in which multiple different types of semiconductor devices (e.g., multiple LEDs emitting different colors) are integrated onto a single device chip, it is often necessary to grow the different semiconductor devices separately, often using different semiconductor materials, on their own template wafers. The different semiconductor devices can then be removed from their growth templates and integrated onto a common carrier wafer, which is then processed into the end product. For example, it is often necessary to integrate multiple different LED types (emitting different peak emission wavelengths) onto a single carrier wafer for the manufacture of a multi-color display device.

[0013] To avoid the complexity and cost of separate growth, transfer, and integration steps, it is highly desirable to manufacture all required semiconductor devices monolithically—that is, on the same wafer template. After epitaxially growing the different semiconductor devices on the wafer, the required devices are already positioned on the shared wafer at the desired locations where they need to be processed into the final product. This eliminates the need to grow individual devices separately and transfer them to the shared wafer, thereby speeding up device manufacturing and reducing cost and complexity.

[0014] Currently, there is no viable monolithic wafer integration method for display applications or other light-emitting applications because commonly used III-nitride LEDs (standard LEDs, sub-millimeter LEDs, micro-LEDs, and nano-LEDs) can typically only emit one color at a time. This means that for multi-color light-emitting devices, multiple single-color LEDs with different epitaxial structures, usually formed from different semiconductor materials, must be separately manufactured and then integrated onto a common wafer.

[0015] For "large" (not sub-millimeter, micron, or nanometer) LEDs, packaging innovations exist that allow three separate LEDs emitting red (R), green (G), and blue (B) to be packaged in a single die or package, or three packaged R, G, and B LEDs to be mounted on the same PCB or circuit board. These red, green, and blue LEDs can be made from the same material system or different material systems. For example, the red, green, and blue LEDs can be based on GaN, AlInGaP, or GaAs.

[0016] For sub-millimeter LEDs, similar to "large" LEDs, sub-millimeter LEDs of different colors can be packaged together using mass transfer or pick-and-place technology, where LED chips of different colors are integrated, mounted or packaged on the same circuit in a single die.

[0017] For micron-sized LEDs, the above-mentioned packaging, mounting, or mass transfer / pick-and-place methods do not work well with reasonable yield and cost-effectiveness due to the small size of micron-sized LEDs and the required pixel density.

[0018] The key issue is that a single LED epitaxial wafer, or LED chip, can traditionally produce only one color of LED. Heterogeneous integration of multiple individual chips is already difficult and complex. Furthermore, red and blue-green LEDs are typically grown from different semiconductor materials, requiring different lift-off processes, further complicating integration of different colors.

[0019] There have been efforts to display all three colors of RGB (red, green, blue) LEDs on the same substrate / wafer, using:

[0020] 1. Selective area epitaxy or nanowire / nanorod / nanocone / nanoplate method – by changing the mask / window (usually dielectric material as mask, SiO2 or SiN x ) The size of the opening is used to limit the selective area of ​​the LED epitaxial growth and control the size of the nanostructure, thereby controlling the MQW and In% on the sidewall or surface of the nanostructure to emit different colors.

[0021] 2. Stacking method, which uses vertical stacking or horizontal stacking:

[0022] Vertical stacking involves manufacturing R, G, and B LEDs (of any size) (and the R, G, and B LED epitaxy / materials can be obtained from the same or different material systems), processing and singulating the LEDs, and lapping, polishing, thinning, and removing the original substrate. Each color LED is then stacked on top of the other to form a pixel. This process is very complex and has low yield, considering that all R, G, and B LED epitaxy must be performed on a foreign substrate and the active LED pn junction is a very thin layer. These shortcomings make this method unsuitable for commercial device manufacturing. Furthermore, this technology faces the problem of light absorption from the LEDs, as the vertical stacking of the R, G, and B LEDs can result in different pixel optical performance and crosstalk issues. Each color LED has completely different optical and electrical characteristics, and each LED requires its own electrical contacts, further complicating this technology. Overall, the vertical stacking integration process is extremely complex and, at the very least, potentially unsuitable for display applications.

[0023] Lateral stacking – Similar to the mass transfer process, lateral stacking requires stacking / transferring each R, G, and B LED side by side in a sub-pixel format, one color following the next. This technology suffers from the same challenges of complex processing, low yields, and the drawbacks of combining different LEDs with varying characteristics.

[0024] Therefore, monolithically integrating RGB LEDs on the same wafer presents numerous challenges and requires improvement in multiple areas. Yield losses in existing technologies contribute to high manufacturing costs. It is desirable to create monolithically integrated devices using simple epitaxy, without the need for transfer, stacking, or selective area epitaxy, as this would result in lower costs and higher yields for the integrated end product. Display applications require high performance and color uniformity. For display applications, system integration, and power management, it is also beneficial for different semiconductor devices on the integrated wafer to have similar optical and / or electrical characteristics.

[0025] The object of the present invention is to solve these problems and to provide a manufacturing method with high yield and simple processing in the entire display manufacturing process.

[0026] To simplify LED manufacturing and reduce mass production costs, Poro Technologies has introduced LEDs featuring an embedded nanoporous structure that enables GaN-based LEDs to output a full range of colors. These LEDs are described, for example, in international patent applications PCT / GB2021 / 050152 (published as WO2021 / 148808) and PCT / GB2021 / 052020 (published as WO2022 / 029434). Summary of the Invention

[0027] In the present invention, an embedded nanoporous structure enables multiple optoelectronic semiconductor devices to be monolithically integrated on a single wafer. For example, the present invention enables multiple LEDs with different emission colors (different peak emission wavelengths) to be monolithically integrated on a single semiconductor wafer.

[0028] The present invention is defined in the independent claim, to which reference should now be made. Preferred or advantageous features of the invention are set out in the appended dependent claims.

[0029] In a first aspect of the present invention, a method for manufacturing a photovoltaic device is provided. The method for manufacturing a photovoltaic device may be a method for integrating a photovoltaic device with a driving circuit.

[0030] This first aspect of the present invention provides a method for manufacturing a photovoltaic device, comprising the following steps:

[0031] Providing a device wafer comprising an optoelectronic device epitaxial structure on a substrate wafer, the device epitaxial structure comprising a porous region of a Group III nitride material;

[0032] etching the device epitaxial structure into a plurality of device platforms;

[0033] depositing a liner dielectric layer over the plurality of device lands;

[0034] forming a plurality of metal vias extending through the pad dielectric layer to respective device platforms; and

[0035] The device wafer is bonded to a driver wafer including a driver circuit such that the driver circuit is operatively coupled to the plurality of device platforms through the metal vias.

[0036] The pad dielectric layer may include a material compatible with CMOS drivers. The pad dielectric layer may be made of, for example, SiO2 or silicon nitride (SiN).

[0037] The device wafer is preferably bonded to the driver wafer so that each metal via is electrically coupled to its own CMOS driver in the driver circuit.

[0038] The method preferably includes the step of depositing a dielectric fill material over the plurality of device platforms after the liner dielectric layer has been deposited. The dielectric fill material may advantageously be planarized or flattened to provide a flat upper surface on the device wafer. The metal vias may then be formed so as to extend from the flat upper surface of the device wafer through the dielectric fill material and the liner dielectric layer to the respective device platforms. The flat upper surface of the device wafer may then be bonded to the driver wafer, which preferably has its own flat upper surface.

[0039] Example 1

[0040] In a preferred first embodiment of the present invention, the method comprises the step of depositing a dielectric fill material directly over the liner dielectric layer. The method may thus involve depositing the liner dielectric layer over the device platform and then depositing a planarizing dielectric fill material layer over the liner dielectric layer.

[0041] The step of forming the metal vias may then include etching a plurality of channels from the planar upper surface of the wafer through the dielectric filler material and the pad dielectric layer to the device platform. The method then includes depositing metal in the plurality of channels to form metal vias. The metal vias thus form a conductive path between the device platform and the planar upper surface of the wafer.

[0042] Etching through the pad dielectric layer involves forming an opening through the pad dielectric layer that exposes a contact region of the respective device platform. This exposed contact region is an area of ​​the device platform that, once metal is deposited, makes electrical contact with the metal via. The size of the contact region, and therefore the lateral dimensions of the metal via, can be controlled by varying the width of the channel etched through the dielectric fill material and the pad dielectric layer.

[0043] The size (lateral area) of the opening through the pad dielectric layer controls the area of ​​the exposed portion of the device platform. This in turn determines the area of ​​contact between the device platform and the metal contact. The opening through the pad dielectric layer provides a contact area because, in use, the drive current provided to the device platform from the drive circuit must pass through this contact area to reach the device platform. Forcing a drive current of a given magnitude to flow through a small contact area will produce a high current density in the device platform area near the contact area, whereas applying the same magnitude of drive current through a larger contact area will allow the drive current to be distributed over the larger contact area, thereby causing the device platform to experience a lower current density. Therefore, the size of the contact area and the magnitude of the drive current determine the drive current density experienced by the device platform during use.

[0044] In a particularly preferred embodiment of the present invention, discussed further below, the device platform is a variable-wavelength LED that emits different peak emission wavelengths in response to different drive current densities. Controlling the contact areas on the device platform can therefore advantageously provide a means of additionally controlling the drive current density provided to the variable-wavelength LEDs, and thus controlling the peak emission wavelength of those LEDs.

[0045] The contact area on each device platform can be controlled by controlling the size of the opening through the liner dielectric layer, which in turn controls the area of ​​the metal contact formed in the opening. By controlling the contact area, the drive current density experienced by the device platform at a given drive current can be controlled.

[0046] The size of the contact area can be different between device platforms. For example, a first contact area can be formed on the first device platform by etching an opening in the liner dielectric layer to expose a portion of a first device platform, the exposed portion having the size of the first contact area. A second contact area can be formed on the second device platform by etching an opening in the liner dielectric layer to expose a portion of a second device platform, the exposed portion having the size of the second contact area. The size of the second contact area can be different from the size of the first contact area. By providing contact areas of different sizes on different device platforms, the drive current density that those device platforms will experience can be controlled. If the contact areas have different sizes, the first and second device platforms will experience different drive current densities even if the drive circuit provides the same amount of drive current to the two device platforms.

[0047] Once the metal vias are formed, the planar top surface of the wafer is then bonded to the device wafer so that the metal vias align with and contact the respective metal vias or pads of the driver circuit to make electrical connections between the driver circuit and the respective device platform.

[0048] Example 2

[0049] In a preferred second embodiment of the present invention, the method includes, after depositing the spacer dielectric layer above the plurality of device platforms, a step of depositing a reflective layer above the plurality of device platforms. The reflective layer is preferably a metal layer. The spacer dielectric is deposited on the edges and sidewalls of the device platforms to electrically isolate the device platforms from the subsequently deposited reflective layer. The reflective layer can advantageously cover the sidewalls and top of the device platforms to reflect any light that is not emitted in the intended direction of emission.

[0050] The reflective layer may be formed by depositing a metal layer over the pad dielectric layer.

[0051] The reflective layer can be formed by depositing a metal over the pad dielectric layer as a filler material to fill the trenches between the device platforms. Thus, the metal can serve as both a filler material and a reflective layer surrounding the device platforms. The method can then include a step of planarizing the metal to form a flat surface that is flush with the pad dielectric layer extending over the top of the device platforms.

[0052] The method may optionally include the steps of depositing a reflective layer, then depositing a metal fill material over the reflective layer, and planarizing the metal fill material to be flush with a pad dielectric layer extending over the device platform before depositing the dielectric fill material.

[0053] Preferably, a layer of dielectric fill material is deposited on the planarized metal surface so that the dielectric fill material provides a planar upper surface of the device wafer and metal vias can be formed through the dielectric fill material to connect to respective device platforms.

[0054] Prior to depositing the reflective layer, the method may include etching a plurality of openings through the pad dielectric layer above the plurality of device mesas, such that a portion of each device mesas is exposed through the openings in the pad dielectric layer before depositing the reflective layer and / or the metal filler. When the reflective layer and / or the metal filler are deposited over the pad dielectric, the metal fills the openings in the pad dielectric, forming metal contacts that extend through the pad dielectric and contact the exposed portion of each device mesas.

[0055] As described above, the size of the contact areas on the device platform can vary, and contact areas of different sizes can be formed on different device platforms.

[0056] In addition to forming openings to expose the device platform, openings may also be formed through the dielectric layer at other locations on the device wafer, such as in trenches, to expose portions of the material beneath the pad dielectric.

[0057] The method may preferably include the step of depositing a metal landing, or metal pad, over each opening in the liner dielectric layer, the metal pad forming an electrical contact for each device platform.

[0058] Preferably, after the metal pads have been deposited, a dielectric fill material is deposited over the device wafer. Optionally, after an additional step of planarizing or flattening the dielectric fill material, the dielectric fill material advantageously provides a planar upper surface on the device wafer.

[0059] Once the dielectric fill material is deposited, the metal vias are formed so as to extend from the planar top surface of the device wafer through the dielectric fill material to the respective metal pads. The planar top surface of the device wafer is then bonded to the driver wafer so that the metal vias are electrically connected to the corresponding conductive pads or vias on the driver wafer.

[0060] The step of forming the metal vias may include etching a plurality of channels from the planar upper surface of the wafer through the dielectric filling material to the metal pad, and then depositing metal in the plurality of channels to form the metal vias.

[0061] Common characteristics

[0062] The following features apply to both the first and second embodiments described above.

[0063] The step of etching the device epitaxial structure into a plurality of device platforms may include etching trenches in the device epitaxial structure. Conventional semiconductor processing techniques may be used to control the etching to determine the depth to which the trenches are etched into the epitaxial structure.

[0064] To form discrete device platforms, each of which can be individually operated as an optoelectronic semiconductor device, the trenches are preferably etched to a depth below the depth of the active light emitting region in the device epitaxial structure. Thus, each discrete device platform preferably has its own light emitting region.

[0065] The trench can be etched through the entire depth of the device epitaxial structure and any underlying semiconductor layer so that the trench extends down to the device substrate and the device platforms on opposite sides of the trench are electrically isolated from each other. Alternatively, the trench can be etched only partway through the device epitaxial structure and any underlying semiconductor layer so that some complete epitaxial layer extends below the trench to connect the device platforms on either side of the trench. For example, the trench can be etched to the level of an n-doped layer or a p-doped layer below the active light emitting region (on the substrate side) in the device epitaxial structure. Alternatively, the device platforms can be epitaxially grown on one or more conductive layers of semiconductor material that extend below the level of the trench and provide an electrical path between the device platforms on either side of the trench.

[0066] The step of etching the device epitaxial structure into a plurality of device platforms may include performing an isolation etch, wherein an isolation trench is etched through the entire depth of the device epitaxial structure to electrically isolate the device platforms on opposite sides of the isolation trench. Preferably, the isolation trench is etched through all epitaxial layers down to the substrate wafer.

[0067] One or more metal vias may be formed in the isolation trench such that the isolation trench metal via extends from the planar wafer surface, through the dielectric fill material and the liner dielectric layer, to the substrate wafer.

[0068] In some preferred embodiments, for example, when a reflective layer is deposited as described above, the isolation trenches may be filled with a metal filler. One or more metal pads may be placed on the metal-filled isolation trenches. The isolation trench metal vias may extend from the planar wafer surface through the dielectric filler material to a metal pad located in the isolation trench or on a metal pad filling the isolation trench.

[0069] Etching the device epitaxial structure into a plurality of device mesas may include performing a mesa etching process to form a mesa trench partially through the device epitaxial structure. The mesa trench preferably does not extend through at least one conductive layer of the device wafer, such that device mesas on either side of the mesa trench are not electrically isolated from each other.

[0070] One or more metal vias may be formed in the mesa trench. The mesa trench metal vias may extend from the flat wafer surface, through the dielectric filler material and the liner dielectric layer, to the epitaxial layer below the liner dielectric. The epitaxial layer below the liner dielectric layer may be an n-type or p-type layer of the device epitaxial structure, or a conductive connecting layer between the device epitaxial structure and the substrate wafer, or a porous layer of a Group III nitride material between the device epitaxial structure and the substrate wafer.

[0071] One or more openings can be etched through the pad dielectric layer in the mesa trench to expose the layers of the device epitaxial structure below the pad dielectric layer. This has the advantage of providing a common electrical connection for the driver circuit after bonding, which can improve circuit control and functionality. The common electrical connection can be a cathode or an anode.

[0072] The mesa trench metal via can extend from the planar wafer surface, through the dielectric fill material and the liner dielectric layer, to a layer in the device epitaxial structure below the mesa trench.

[0073] The method may include depositing a plurality of metal pads above the metal via for routing and bonding to the driver wafer.

[0074] The device epitaxial structure can be etched so that the lateral dimensions of the device platforms are non-uniform. By controlling the spacing of the trenches etched into the device epitaxial structure, the lateral dimensions of each individual device platform can be controlled. It may be desirable to form some device platforms with larger lateral areas than others in order to control the lateral area of ​​the light-emitting region. By controlling the lateral area of ​​the light-emitting region of the device platform, the luminosity of the device platform can be controlled, and the current density of the drive current passing through the device platform can be controlled.

[0075] The device epitaxial structure can be etched so that the device platforms are unevenly spaced across the device wafer. The relative positions of the device platforms on the device wafer can be determined by controlling the spacing of the grooves etched into the device epitaxial structure and the width of the grooves etched into the device epitaxial structure. Thus, the lateral spacing between adjacent device platforms can be controlled by varying the width of the grooves separating the platforms. It may be desirable to make the spacing between the device platforms uneven in order to provide desired results in terms of the optical emission characteristics of the resulting optoelectronic device. For example, it may be desirable to space a first group of device platforms closely together with narrow grooves between them so that the first group of device platforms forms a first display pixel, wherein each of the first group of device platforms serves as a sub-pixel of the display pixel. It may then be desirable to form a second group of device platforms on the same wafer, with the second group of device platforms serving as a second display pixel. The spacing between the first device pixel and the second device pixel can then be controlled by varying the width of the grooves separating the two groups of sub-pixels.

[0076] Using the present invention, the lateral size and shape of the device platforms, as well as the separation of the device platforms, can be controlled and varied by controlling the location, width, and number of trenches etched into the device epitaxial structure. This creates a vast range of design possibilities for the resulting optoelectronic devices, which is not achievable using the inflexible pick-and-place integration methods of the prior art.

[0077] Some preferred embodiments of the method include removing the substrate wafer to form the light-emitting side of the device after bonding the device wafer to the driver wafer. The device wafer is flipped over so that the original top surface of the device wafer is bonded to the top surface of the driver wafer. The substrate wafer, which formed the bottom surface of the device wafer during its manufacturing process, is then removed, for example, by grinding or thinning, and the side of the assembled device from which the substrate wafer has been removed becomes the light-emitting side of the device.

[0078] In embodiments where some or all of the isolation trenches are already filled with metal, the method may include, after removing the substrate wafer, etching an opening through the liner dielectric layer to expose the metal in the isolation trenches. The exposed metal in the isolation trenches can then advantageously provide a metal pad for wire bonding. Specifically, the metal pad can improve the ease of performing a subsequent wire bonding step.

[0079] Alternatively, in the case where the isolation trench is not filled with metal, the method may include, after removing the substrate wafer, depositing a metal pad over the isolation trench. The metal pad is electrically connected to one or more metal vias that extend through the liner dielectric layer and any other intermediate layers of the device to the driver wafer.

[0080] The method may include the step of depositing one or more microlenses on some or all of the device platforms on the light emitting side of the device. Microlenses can improve the directionality of light emitted by the device. This is particularly advantageous in devices containing micron-sized LEDs, where the light emission angle is wide and Lambertian. This is also particularly advantageous in applications such as augmented reality or virtual reality displays, and in heads-up displays or near-eye applications. In such applications, the use of microlenses can facilitate the collimation or use of waveguides and module optics. The use of microlenses can also increase the brightness of micron-sized LEDs, or increase the candela per square meter measurement.

[0081] As discussed further below with respect to the second aspect of the present invention, the device wafer preferably comprises a porous region of Group III nitride material. Preferably, the device wafer comprises a porous region of Group III nitride material located between the device epitaxial structure and the substrate wafer, and / or a porous region of Group III nitride material located in the device epitaxial structure above or below the light emitting region.

[0082] In a particularly preferred embodiment, the device epitaxial structure is an LED structure. Thus, each device platform is an LED. Preferably, as further discussed below with respect to the second aspect of the present invention, each device can be a sub-millimeter-scale LED, a micrometer-scale LED, or a nanometer-scale LED structure.

[0083] Particularly preferably, the method comprises the step of etching the variable wavelength LED structure into a plurality of device platforms. In this case, the driving circuit is preferably configured to provide a variable amount of driving current to each of the device platforms.

[0084] The method may include etching the variable wavelength LED structure into a plurality of device platforms having a plurality of lateral dimensions. For example, a trench may be etched into the variable wavelength LED structure to form a first device platform having a first lateral region and a second device platform having a second lateral region different from the first lateral region. The first and second platforms may be first and second variable wavelength LED sub-pixels, wherein a pair of the first and second device platforms form a display pixel. Optionally, the variable wavelength LED epitaxial device structure may be etched to form a third device platform having a third lateral region different from the first and second lateral regions, with the first, second, and third device platforms forming three sub-pixels that together provide a display pixel.

[0085] The method may include etching the device epitaxial structure into a plurality of display pixels, each display pixel comprising one or more device platforms. For example, a single variable wavelength LED device platform may form a display pixel that can emit different peak wavelengths by varying the drive current provided by the driver circuit. In another embodiment, a first and second variable wavelength LED device platform pair may function as two sub-pixels that, when combined, create a device pixel. Each of the two sub-pixels can be independently controlled by the driver circuit to emit a peak wavelength tuned by the drive current provided by the driver circuit to the sub-pixel. In another embodiment, three device platforms—a first, second, and third variable wavelength LED device platform—may function as three sub-pixels that, when combined, create a device pixel. Each of the three sub-pixels can be independently controlled by the driver circuit to emit a peak wavelength tuned by the drive current provided by the driver circuit to the sub-pixel.

[0086] The driving circuit can be configured to control the power, current, or voltage of the power supply provided to each variable wavelength LED device platform. The driving circuit can be configured to provide pulsed, CW, or quasi-CW power to the variable wavelength LED device platform.

[0087] Manufacturing method of variable wavelength LED

[0088] The variable wavelength LED epitaxial device structure can be fabricated by a method comprising the following steps of growing:

[0089] n-doped part;

[0090] p-doped portion; and

[0091] A light emitting region is located between the n-doped portion and the p-doped portion, and includes a light emitting layer that emits light of a peak emission wavelength under an electrical bias.

[0092] The method may include the step of epitaxially growing the n-doped portion, the p-doped portion, and the light emitting region above the porous region of the Group III nitride material.

[0093] The method may include the steps of forming a porous region of Group III nitride material in at least one of the n-doped portion or the p-doped portion, and forming the light emitting region over the porous region of Group III nitride material.

[0094] The method may optionally include the step of removing the porous region from the LED structure (the n-doped portion, the p-doped portion, and the light emitting region) after the n-doped portion, the p-doped portion, and the light emitting region have been formed.

[0095] The light-emitting layer can emit light with a peak emission wavelength between 400 and 800 nm, or between 450 and 800 nm, or between 500 and 800 nm, or between 550 and 800 nm, or between 610 and 800 nm under an electrical bias.

[0096] The LED structure, including the n-doped part, the p-doped part and the light-emitting region, can be an LED structure for emitting a wavelength shorter than the peak emission wavelength of the LED, so that the porous region of the Group III nitride material red-shifts the emission wavelength of the light-emitting region to the peak emission wavelength.

[0097] The n-doped portion, the p-doped portion, and the light emitting region are preferably formed of a Group III nitride semiconductor material.

[0098] In a preferred embodiment, the light emitting region may include a light emitting indium gallium nitride layer for emitting a peak wavelength at 500nm-550nm or 550nm-600nm, wherein epitaxial growth on the porous region of the Group III nitride material shifts the emission wavelength of the light emitting region to a peak wavelength between 600 and 750nm under an electrical bias.

[0099] The light-emitting region may include a light-emitting indium gallium nitride layer configured to emit light with a peak wavelength between 500 and 550 nm, or between 500 and 580 nm, or between 510 and 570 nm, or between 530 and 560 nm, or between 550 and 600 nm. The light-emitting indium gallium nitride layer may be one or more layers known to emit at these wavelengths when grown in conventional LEDs, such as on a non-porous GaN substrate. However, the inventors have discovered that growing a conventional yellow or green LED structure on a porous Group III nitride layer produces an LED that emits light with a peak wavelength between 600 and 750 nm under electrical bias.

[0100] The method may include the step of growing a yellow or green LED structure on the porous region of the Group III nitride material.

[0101] In a preferred embodiment, the light-emitting layer is a light-emitting indium gallium nitride layer. The LED preferably also includes a region of GaN material. Due to the lattice mismatch between GaN and InGaN, the stress relaxation effect generated by the porous region is particularly beneficial.

[0102] The method may include the steps of forming a light-emitting active region having carrier localization centers in a quantum well (preferably an InGaN QW), such as multiple types of QW regions with different indium compositions and well widths, and quantum barriers that cause well width fluctuations, uneven, or fragmented, or broken, or gapped, or discontinuous quantum wells, InGaN quantum dots or nanostructures, and quantum wells formed on polar, semi-polar or non-polar surfaces.

[0103] The method may include the step of forming a plurality of quantum wells (QWs), wherein the quantum wells are non-uniform, fragmented, or discontinuous.

[0104] The plurality of QWs may include fluctuations in indium composition and / or well width fluctuations.

[0105] The method may include the step of forming one or more V-shaped pits in the LED structure so that the V-shaped pits extend through the thickness of the light emitting region. Preferably, the method includes the step of forming at least 0.1 V-shaped pits per square micron, or at least 1 V-shaped pit per square micron, or at least 2 V-shaped pits per square micron. Preferably, the method includes the step of forming at least 1×10 7 pieces / cm 2 , for example, at least 5×10 7 pieces / cm 2 or at least 1×10 8 pieces / cm 2 The V-shaped pit density, for example, 1×10 7 pieces / cm 2 to 5×10 9 pieces / cm 2 Preferably, the method comprises forming a V-shaped pit density of less than 5×10 9 pieces / cm 2 The V-shaped pit density is less than 1×10 9 pieces / cm 2 or less than 5×10 8 pieces / cm 2 The density of the V-shaped pits increases with the step size.

[0106] V-pits are a well-known phenomenon in epitaxial semiconductor growth, and methods for growing V-pits in semiconductor structures are known in the art. For example, the previous article "The effect of nanometer-scale V-pits on electronic and optical properties and efficiency droop of GaN-based greenlight-emitting diodes" (Zhou et al., Scientific Reports, 2018, 8:11053, DOI: 10.1038 / s41598-018-29440-4) describes V-pits and their growth.

[0107] The V-shaped pits can be grown in the semiconductor structure so that they end up in the layer below the active light emitting region. This means that the V-shaped pits must extend through the thickness of the active light emitting region.

[0108] By controlling the growth conditions during epitaxial deposition of a layer over a layer containing threading dislocations, V-shaped pits can be grown from the threading dislocations in the semiconductor structure. As additional layers are grown over the layer containing the threading dislocations, the threading dislocations continue upward through the structure, and by controlling the growth conditions, the dislocations are widened into V-shaped pits.

[0109] The V-shaped pits can optionally be grown using a 3D epitaxial growth mode. 3D epitaxial deposition techniques are known in the art and are commonly used to grow "islands" or "cones" of semiconductor material on a template. By controlling the deposition of the LED structure using 3D epitaxial deposition techniques, the V-shaped pits can be artificially grown at the desired location without the need for line difference rows to be "seeded" to form the V-shaped pits. By using this deposition control, the bottom (bottommost point) of the pit can be created at the desired location in the structure - the desired lateral position and the desired height in the structure, for example, in a specific layer below the active light-emitting area in the semiconductor structure.

[0110] The bottom of the V-shaped pit may be located in a connection layer of the semiconductor structure. The connection layer may be located between the porous region and the n-doped portion.

[0111] The bottom of the V-shaped pit may be located in a pre-strained layer in the semiconductor structure. The pre-strained layer may be located above the n-doped portion and below the light-emitting region.

[0112] Preferably, the LED comprises a plurality of V-shaped pits extending through the active light emitting area.

[0113] The density and size (depth) of the V-shaped pits can be controlled. The size of the V-pits can be controlled by the position and growth conditions of the pre-strained layer and the low-temperature nGaN layer at the beginning of the pits.

[0114] The quantum wells (QWs) in the active light emitting region may be deposited such that the quantum wells are continuous and / or have a uniform thickness. Alternatively, the quantum wells (QWs) in the active light emitting region may be deposited such that the quantum wells are segmented or discontinuous.

[0115] Manufacturing steps

[0116] The n-type region, the light emitting region and the p-type region (which may be referred to as an LED structure) are preferably grown on a semiconductor template containing the porous region. The semiconductor template may also contain a plurality of semiconductor material layers arranged to provide a suitable substrate for epitaxially growing the LED structure.

[0117] The method may include a first step of electrochemically porosifying the Group III nitride material layer to form a porous region of the Group III nitride material. This may be achieved using the wafer-scale porosification processes described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0118] The method may preferably include forming a porous region of the Group III nitride material by electrochemical porosification through a non-porous layer of the Group III nitride material, whereby the non-porous layer of the Group III nitride material forms a non-porous intermediate layer. The non-porous intermediate layer may advantageously provide a smooth surface for epitaxial growth of other layers, such as one or more connecting layers of the Group III nitride material.

[0119] The porous region can be formed by making one or more layers or regions of a Group III nitride material on a substrate porous. The substrate can be silicon, sapphire, SiC, or β-Ga2O3. The substrate can have a polar, semi-polar, or non-polar crystal orientation. The substrate thickness typically ranges from 100 μm to 1500 μm.

[0120] The porous region can be a porous layer. The method thus comprises the steps of epitaxially growing the following on the porous layer of the Group III nitride material: an n-doped portion; a p-doped portion; and an LED light-emitting region. Preferably, the porous region can be a continuous porous layer, for example, formed from a continuous layer of porous Group III nitride material.

[0121] The porous region may comprise a plurality of porous layers, and optionally a plurality of non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, the top surface of the stack defining the top of the porous region, and the bottom surface of the stack defining the bottom of the porous region.

[0122] Alternatively, the porous region may be a layer of Group III nitride material containing one or more porous regions, such as one or more porous regions in an otherwise non-porous layer of Group III nitride material.

[0123] In a preferred embodiment, the porous region, or porous layer, may have the same lateral dimensions (width or length) as the substrate wafer on which the porous layer or region is grown. For example, a common substrate wafer size may have a variety of sizes, such as 1 cm 2, or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter. However, by patterning one or more layers and / or depositing regions of different charge carrier concentrations in the same layer, smaller porous regions that do not span the entire substrate can be formed. Thus, the lateral dimensions of the porous layer or region can vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0124] Prior to the porosification step, a doped region of n-doped III-nitride semiconductor material may be deposited on the substrate, preferably comprising a layer or a stack of layers. The III-nitride layer may contain one or a combination of the following elements: Al, Ga, In (ternary or quaternary layers). The thickness of the III-nitride stack is preferably between 10 and 4000 nm. The III-nitride region may have a thickness of 1 x 10 17 cm -3 Up to 5x 10 20 cm -3 between the doping concentrations.

[0125] Preferably, before the porosification step, an intermediate layer of undoped Group III nitride material is deposited on the doped material. This intermediate layer preferably has a thickness between 1 nm and 3000 nm, more preferably between 5 nm and 2000 nm. Because the intermediate layer is undoped, it remains non-porous after the porosification step, which advantageously provides a good surface for epitaxial growth of other semiconductor layers.

[0126] In a preferred embodiment, the doped region is composed of an alternating stack of doped and undoped layers. In a preferred embodiment, the stack contains between 5 and 50 pairs of layers. The thickness of each highly doped layer can vary between 10 nm and 200 nm, and the lowly doped or undoped layers can have a thickness between 5 and 180 nm.

[0127] As is known in the art, the electrochemical porosification removes material from the n-type doped region of the Group III nitride material and creates pores in the semiconductor material.

[0128] In a preferred embodiment, the LED structure is formed on a stack of multiple porous layers of a Group III nitride material. Thus, the porous region may be a stack of Group III nitride material layers, at least some of which are porous, rather than a single porous Group III nitride layer. The stack of porous layers may preferably be an alternating stack of porous and non-porous layers.

[0129] The method may preferably include the steps of depositing one or more III-nitride material connection layers on the surface of the III-nitride material intermediate layer, and then epitaxially growing the n-doped region, the LED light-emitting region and the p-doped region on the connection layer.

[0130] Alternatively, in the absence of a non-porous intermediate layer on the porous region, the method may include the step of depositing a connecting layer of Group III-nitride material on the surface of the porous region of Group III-nitride material.

[0131] The method may further include the step of epitaxially growing the n-doped region, the LED light-emitting region, and the p-doped region on the connection layer.

[0132] Photoelectric devices

[0133] According to a second aspect of the present invention, there is provided a photovoltaic device comprising:

[0134] a driver wafer comprising a driver circuit;

[0135] a plurality of optoelectronic device platforms, each device platform configured to emit light from a light emitting side of the device in response to a drive current from the drive circuit;

[0136] and

[0137] a pad dielectric layer located between the driver wafer and the device platform;

[0138] Each optoelectronic device platform is operatively coupled to the driver circuit via a plurality of metal vias extending through the pad dielectric layer.

[0139] The optoelectronic device is preferably a device manufactured by the method of the first aspect of the present invention. Therefore, any features described with respect to the first aspect are applicable to the second aspect of the present invention, and vice versa.

[0140] The optoelectronic device may comprise a porous region of a Group III nitride material epitaxially connected to one or more device platforms. Alternatively, the porous material may be removed during fabrication, such as when the growth substrate is removed from the epitaxial structure.

[0141] The device may include a dielectric fill material between the driver wafer and the pad dielectric layer, wherein the metal via extends through the dielectric fill material and the pad dielectric layer.

[0142] The optoelectronic device epitaxial structure preferably includes an n-doped region, a p-doped region, and a light-emitting region disposed between the n-doped region and the p-doped region.

[0143] Preferably, each device platform has the same device epitaxial structure. Since the device platforms are formed by etching a single epitaxial structure into multiple individual device platforms, the composition and layer arrangement of each device platform will be the same.

[0144] While the epitaxial layer design is identical for each device platform, different device platforms can optionally have different lateral dimensions, resulting in light-emitting areas of different sizes. This can be achieved by varying the trench pitch to control the lateral dimensions of the platform formed between the etched trenches.

[0145] The device may include two or more device platforms electrically connected to each other via a common conductive layer of semiconductor material. The electrically connected device platforms may be separated by a platform barrier located between the device platforms, wherein the platform barrier does not extend through the common conductive layer.

[0146] The common conductive layer can be an n-type layer or a p-type layer that forms part of the device epitaxial structure of the device platform, or a doped connection layer that extends across the device and connects to multiple device platforms above the platform barrier, or a porous layer of semiconductor material located above the platform barrier and connected to multiple device platforms.

[0147] During the manufacturing process, a terrace barrier is formed where a trench etched into the device epitaxial structure is filled with material, transforming the empty trench into an electrically insulating barrier. The terrace barrier can be formed of a dielectric filler material covered by the liner dielectric layer. Alternatively, the terrace barrier can be formed of a metal covered by the liner dielectric layer.

[0148] The device may include two or more electrically isolated device platforms. The electrically isolated device platforms may be separated by an electrically insulating isolation barrier. Similar to the platform barrier, the isolation barrier is formed where the isolation trenches etched into the device epitaxial structure during fabrication are filled with material, transforming the empty isolation trenches into electrically insulating isolation barriers between the device platforms. The isolation barrier may be formed from a dielectric filler material covered by the liner dielectric layer. Alternatively, the isolation barrier may be formed from a metal pad surrounded by the liner dielectric layer.

[0149] The device may include a reflective layer adjacent to the pad dielectric layer, the reflective layer being located between the pad dielectric layer and the driver wafer. The reflective layer preferably surrounds the sidewalls of the device platform to form a sidewall reflective structure configured to reflect emitted light toward the light-emitting side of the device.

[0150] In some preferred embodiments, the device can include a plurality of microlenses disposed on the light emitting side of the device, each microlens positioned above a respective device platform and configured to transmit light emitted by an underlying optoelectronic device platform.

[0151] The device may include one or more metal pads on the light-emitting side of the device, each metal pad being electrically connected to the driver circuit via one or more metal vias. Such metal pads may advantageously provide convenient locations for wire bonding. The metal pads may be positioned on the surface of the light-emitting side of the device, or the metal pads may form part of an isolation barrier between device platforms located below the light-emitting side surface of the device.

[0152] Preferably, each device platform is electrically coupled to its own CMOS driver in the driver circuit so that each device platform can be independently driven by the driver circuit.

[0153] Porous area

[0154] The optoelectronic device preferably comprises one or more porous regions of a Group III nitride material.

[0155] The n-type region, the light-emitting region, and the p-type region (which may be referred to as an LED structure or LED diode structure) are preferably grown on a semiconductor template containing the porous region. The semiconductor template may also contain a plurality of semiconductor material layers arranged to provide a suitable substrate for epitaxial growth of the LED structure.

[0156] The porous region may be a porous layer, so that the light emitting diode comprises a porous layer of a group III nitride material. Preferably, the porous region may be a continuous porous layer, for example formed by a continuous porous group III nitride material layer.

[0157] The porous region may comprise a plurality of porous layers, and optionally a plurality of non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, with the top surface of the stack defining the top of the porous region and the bottom surface of the stack defining the bottom of the porous region. The light-emitting region may be formed above the porous region of the stack of porous layers comprising a Group III nitride material.

[0158] Each device platform can contain its own porous region of Group III nitride material, or alternatively, a shared porous region can be epitaxially connected to multiple device platforms. For example, a porous region can extend above one or more platform barriers between the device platform and the light emitting surface of the device.

[0159] The device can include a porous region of Group Ill-nitride material located above the device platform, between some or all of the device platform and the light emitting surface of the device.

[0160] The porous region can take a variety of forms and perform a variety of functions to enhance the optical characteristics of the optoelectronic device. For example, the porous region can be configured to improve light extraction from the device by acting as an antireflection layer, a reflective layer, or a wavelength-specific filter. The porous region can provide a variety of optical engineering functions to the device and can be configured to provide DBRs, alternating layers, filters, reflectors, bandpass filters, bandstop filters, and / or mirrors.

[0161] In some preferred embodiments, the device wafer includes a distributed Bragg reflector (DBR) positioned above the device platform, such that the device platform is disposed between the DBR and the light-emitting surface of the device. The DBR comprises multiple porous layers of a Group III nitride material and can be configured to act as an optical filter that transmits light at a first emission wavelength emitted from the light-emitting side of the device and reflects other emission wavelengths. Thus, the DBR can act as a wavelength-specific filter that allows only selected wavelengths to be transmitted based on the layer thickness of the layered DBR structure.

[0162] The porous region can be configured to act as a wavelength selective transmission layer on the light emitting side of the device, such that the wavelength selective transmission layer allows some wavelengths to be transmitted therethrough while preventing other wavelengths from being transmitted.

[0163] The device may include a porous region of Group III nitride material between some or all of the device platforms and the driver wafer. For example, each device platform may include a porous region. The porous region may be part of the device epitaxial structure. For example, an n-type layer or a p-type layer of the device epitaxial structure may be porous, or a porous layer may be located within another epitaxial layer within the device platform.

[0164] In another preferred embodiment, the device may include a distributed Bragg reflector (DBR) positioned between the device platform and the driver wafer. The DBR comprises multiple porous layers of a Group III nitride material and is configured to reflect emitted light away from the light-emitting side of the device. This advantageously improves light extraction efficiency by reflecting emitted light that would otherwise be lost and not directed away from the light-emitting side of the device.

[0165] The or each porous region in the device may have the same thickness and porosity.For example, the entire device epitaxial structure from which each device platform is etched may be formed on the same porous layer of Group III nitride material.

[0166] Alternatively, the device may comprise multiple porous regions having different thicknesses and / or porosities, such that different device platforms are aligned with different porous regions.

[0167] The porosity characteristics of the porous region can vary at different lateral locations on the device. For example, a first porous region can have a first thickness, and a second porous region at a separate lateral location in the device can have a second thickness that is different from the first thickness. Thus, the optical behavior of the porous region can vary at different locations on the device and for different optoelectronic device platforms.

[0168] The device can comprise a multi-region filter comprising a plurality of porous regions of varying thickness, each porous region having a varying thickness being located on a different device platform.

[0169] Photoelectric device type

[0170] In a particularly preferred embodiment, the device is a display device, and each device platform is an LED. Preferably, each device platform is a sub-millimeter-scale LED, a micrometer-scale LED, or a nanometer-scale LED.

[0171] The device can include a monolithic array of LED device platforms, wherein each device platform is an LED sub-pixel, and wherein groups of LED device platforms form device pixels.

[0172] The LED epitaxial device structure shared by each device platform may include a light emitting region, which preferably includes a multiple quantum well (MQW) containing multiple quantum wells (QWs), or quantum dots, quantum wires, or other quantum nanostructures.

[0173] The LED includes an n-doped portion, a p-doped portion, and a light-emitting region located between the n-doped portion and the p-doped portion. The light-emitting region includes a light-emitting layer that emits light at a peak emission wavelength under an electrical bias.

[0174] The light-emitting area, and / or the LED, may have lateral dimensions (width and length) greater than 100 μm and less than 300 μm. In this case, the LED may be referred to as a "sub-millimeter LED." In a preferred embodiment, the sub-millimeter LED may be square, circular, or square with rounded corners, and have dimensions such as 300 μm x 300 μm, 200 μm x 200 μm, or 100 μm x 100 μm.

[0175] The light emitting region, and / or the LED, may optionally have lateral dimensions (width and length) less than 100 μm. In this case, the LED may be referred to as a "micro-LED." The micro-LED may preferably have lateral dimensions less than 80 μm, or 70 μm, or 60 μm, or 50 μm, or 30 μm, or 25 μm, or 20 μm, or 15 μm, or 10 μm, or 5 μm, or 3 μm, or 2 μm.

[0176] In a preferred embodiment, the micron-sized LED may be square or circular or a square with rounded corners, and have a size such as 75μm×75μm, 50μm×50μm, 40μm×40μm, 30μm×30μm, 25μm×25μm, 20μm×20μm or 10μm×10μm, or 5μm×5μm, or 2μm×2μm, or 1μm×1μm, or 500nm×500nm or smaller.

[0177] The light emitting region, and / or the LED, may optionally have lateral dimensions (width and length) less than 1 μm. In this case, the LED may be referred to as a "nanoscale LED." The nanoscale LED may preferably have lateral dimensions less than 500 nm, 200 nm, 100 nm, or 50 nm.

[0178] The LED can be circular, triangular, rectangular, square, elliptical, diamond-shaped, hexagonal, pentagonal, or any combination of these shapes. In the case of irregularly shaped pixels, at least one dimension should fall within the above-defined dimensions in order for the LED to be classified as a sub-millimeter or micrometer-scale LED. For example, the width or diameter of the LED is preferably less than 100 μm in order for the LED to be classified as a micrometer-scale LED.

[0179] Some or all of the device platforms may be single-emission wavelength LED structures that emit a single peak emission wavelength in response to a driving current.

[0180] In a particularly preferred embodiment, each device platform is a variable wavelength LED. Each variable wavelength LED in the device is preferably independently controllable. Alternatively, the device may include multiple groups of variable wavelength LEDs, each group being controllable independently of the other groups.

[0181] The device may include multiple device platforms having multiple lateral dimensions. For example, the device may include a first variable-wavelength LED device platform having a first lateral region, and a second variable-wavelength LED device platform having a second lateral region different from the first lateral region. The first and second platforms may be first and second variable-wavelength LED sub-pixels, wherein a pair of the first and second device platforms form a display pixel. Optionally, the device may further include a third variable-wavelength LED device platform having a third lateral region different from the first and second lateral regions, wherein the first, second, and third variable-wavelength LED device platforms form three variable-wavelength LED sub-pixels that together provide a display pixel.

[0182] In each device platform, the device platform is contacted via a respective metal via extending through an opening in the liner layer, or optionally via a metal contact extending through an opening in the liner layer, the metal contact being electrically connected to the metal via. The size of the opening in the liner dielectric layer defines a contact area for the device platform to be electrically contacted.

[0183] During use, the drive current provided by the driver circuit to the device platform must pass through this contact area to reach the device platform. Forcing a drive current of a given magnitude to flow through a small contact area will produce a high current density in the area of ​​the device platform near the contact area, while applying the same drive current through a larger contact area will allow the drive current to be distributed over the larger contact area, so that the device platform experiences a lower current density. Therefore, the size of the contact area and the magnitude of the drive current determine the drive current density experienced by the device platform during use.

[0184] In a particularly preferred embodiment of the present invention, discussed further below, the device platform is a variable-wavelength LED that emits different peak emission wavelengths in response to varying drive current densities. Thus, controlling the contact areas on the device platform advantageously provides an additional means of controlling the drive current density provided to the variable-wavelength LEDs, and thus, the peak emission wavelength of those LEDs.

[0185] The contact areas between the device platforms can have different sizes. For example, a first device platform can have a first contact area that is in electrical contact with a first metal via. A second device platform can have a second contact area that is in contact with a second metal via. The size of the second contact area can be different from the size of the first contact area. By providing different sized contact areas on different device platforms, the drive current densities that those device platforms will experience can be controlled. If the contact areas have different sizes, then when the driver circuit provides the same amount of drive current to the first and second device platforms, the first and second device platforms will experience different drive current densities.

[0186] The device may include multiple display pixels, each display pixel comprising one or more device platforms. For example, a single variable-wavelength LED device platform may form a display pixel that can emit different peak wavelengths by varying the drive current provided to the device platform by the driver circuit. In another embodiment, a pair of first and second variable-wavelength LED device platforms may be two sub-pixels that, when combined, form a device pixel. Each of the two sub-pixels can be independently controlled by the driver circuit to emit a tunable peak wavelength, which can be tuned by varying the drive current provided to the sub-pixel by the driver circuit. In another embodiment, three device platforms—a first, second, and third variable-wavelength LED device platform—may serve as three sub-pixels that, when combined, create a device pixel. Each of the three sub-pixels can be independently controlled by the driver circuit to emit a peak wavelength that is tuned by the drive current provided to the sub-pixel by the driver circuit.

[0187] The driving circuit can be configured to control the power, current, or voltage of the power supply supplied to each variable wavelength LED device platform. The driving circuit can be configured to provide pulsed, CW, or quasi-CW power to the variable wavelength LED device platform.

[0188] Variable wavelength LED

[0189] In a particularly preferred embodiment, each device platform has an identical variable wavelength LED device epitaxial structure. Thus, each device platform in the device is a separate variable wavelength LED configured to emit a variable peak emission wavelength in response to changes in the drive current supplied to the LED. By individually driving the variable wavelength LED device platforms through the driver circuit, the emission wavelength of each device platform can be advantageously tuned by providing different drive currents to the variable wavelength LED device platforms.

[0190] Preferably, some or all of the device platforms are variable wavelength LEDs configured to emit a variable peak emission wavelength in response to changes in a drive current supplied to the LEDs, wherein the peak emission wavelength of the LEDs can be continuously controlled over an emission wavelength range of at least 40 nm by varying the drive current supplied to the LEDs. By varying the drive current, the peak emission wavelength can preferably be varied over an emission wavelength range of at least 50 nm, or at least 60 nm, or at least 70 nm, or at least 80 nm, and preferably over a range of up to 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 180 nm, or 200 nm, or 400 nm, or 450 nm.

[0191] The driving circuit is preferably configured to provide a variable amount of driving current to the variable wavelength LED device platform to change the peak emission wavelength of the variable wavelength LED device platform.

[0192] A variable wavelength light emitting diode (LED) preferably comprises:

[0193] n-doped part;

[0194] p-doped part;

[0195] a light-emitting region located between the n-doped portion and the p-doped portion, the light-emitting region comprising a light-emitting layer that emits light at a peak emission wavelength under an electrical bias;

[0196] The LED is configured to receive a power source, wherein by varying or controlling the power source, the peak emission wavelength of the LED can be continuously controlled within an emission wavelength range. By varying or controlling the power source, the peak emission wavelength of the variable wavelength LED can preferably be continuously controlled or continuously varied within an emission wavelength range of at least 40 nm.

[0197] Since the peak emission wavelength of the variable wavelength LED can be continuously controlled or continuously varied within the emission wavelength range, the LED can be described as a variable wavelength LED.

[0198] The variable wavelength emission behavior of the LED structure is achieved by the fact that the LED structure (the n-doped portion, the light emitting region and the p-doped portion) is grown on a template containing a porous region. The inventors have found that the presence of the porous region of the III-nitride material in the template structure prior to epitaxial growth of the LED structure produces higher quality crystal growth, thereby bringing significant benefits, including the possibility of changing the emission wavelength of the LED light emitting region. The mechanism by which the porous region enables variable wavelength emission of the LED is the subject of ongoing research. The benefits provided by the porous region to the LED include strain relaxation, increased lattice parameter, reduced wafer bowing, and mechanical and thermal effects during the growth of the light emitting region at high temperature.

[0199] The variable wavelength LED is configured to receive a power supply or driving current from a power source or LED driver. As used herein, the term "power source" refers to the power or current provided to drive the LED during use.

[0200] Preferably, by changing or controlling the magnitude of the driving current supplied to the variable wavelength LED, the peak emission wavelength of the LED can be continuously controlled or continuously varied within the emission wavelength range.

[0201] In conventional LED devices, changes in the drive current supplied to the LED produce a very small shift in the emission wavelength. However, the present inventors have discovered that this wavelength shift can be broadened or controlled to a greater extent than with conventional LED materials. Unlike the several-nanometer emission range of prior art devices, the LEDs of the present invention can be controlled to emit over a much wider range (e.g., a range of at least 40 nm). Because the LEDs of the present invention can be tuned to emit over such a wide wavelength range, they can be referred to as variable-wavelength LEDs.

[0202] The LED may be a dynamically color-tunable LED, wherein the peak emission wavelength of the LED may be adjusted by changing the driving conditions of the power supplied to the LED.

[0203] The LED is preferably drivable to emit a single peak emission wavelength in response to a stable power source, and to emit different peak emission wavelengths in response to variations in the power source. Thus, the LED can be used to emit a specific color for an extended period of time, or the LED can be driven to emit a variety of different wavelengths by providing varying driving conditions.

[0204] Preferably, the n-doped portion, the p-doped portion and the light emitting region all comprise or consist of a Group III nitride material, preferably GaN, InGaN, AlGaN or AlInGaN.

[0205] The variable wavelength LED preferably comprises a single epitaxially grown diode structure comprising the n-doped portion, the p-doped portion and the light emitting region. Thus, the variable peak emission wavelengths of the LED are all emitted by the same LED diode structure and components.

[0206] The LED preferably comprises a porous region of a Group III nitride material. The light-emitting region of the LED is preferably formed above the porous region of the Group III nitride material. In some embodiments, either the n-doped portion or the p-doped portion may comprise the porous region of the Group III nitride material. In other embodiments, the n-doped portion, the p-doped portion, and the light-emitting region are provided on a substrate comprising the porous region of the Group III nitride material. During epitaxial growth of the LED, the light-emitting region is preferably epitaxially grown after the porous region has been formed.

[0207] The present inventors have discovered that porous regions of a III-nitride material enable the same LED to emit a range of peak emission wavelengths, rather than just a specific wavelength. By varying the power supplied to the LED, the peak emission wavelength of the LED can be varied within the emission wavelength range. Thus, the present invention provides a variable-wavelength LED that can be controlled to emit any wavelength within a continuous range of emission wavelengths. By varying the driving conditions of the power supplied to the LED, the LED can emit any wavelength within the LED's emission wavelength range, rather than just a discrete peak emission wavelength.

[0208] The present inventors have discovered that the ability of an LED to emit at tunable wavelengths over a broad emission range can be imparted by incorporating a porous region of a Group III nitride semiconductor material into the LED structure, or forming the LED diode structure on a porous region of a Group III nitride semiconductor material. The porous region provides benefits to the LED, including strain relaxation, increased lattice parameter, reduced wafer bow, and beneficial mechanical and thermal effects during the growth of the light-emitting region at high temperatures.

[0209] During the manufacturing process, the light-emitting region of the LED is preferably formed above a porous region of Group III nitride material, so that the porous region influences the structure and mechanical properties of the semiconductor layer epitaxially deposited above the porous region. The semiconductor material layer deposited on the porous region during growth has advantages such as reduced strain, increased lattice parameter, and reduced wafer bow. These advantages are imparted to the light-emitting region of the LED and influence its structure and light-emitting behavior.

[0210] Once the LED light-emitting (active) region has been epitaxially grown over the porous region, and the quality of the active region has been enhanced by the porous region, the beneficial effects of the porous region on the emission characteristics are permanently imparted to the LED active region. Thus, the LED diode structure can remain on the porous region, in which case the variable wavelength LED comprises a porous region of Group III nitride material, or the porous region can be removed from the LED structure after epitaxial growth during fabrication of the LED into a device.

[0211] The width of the emission wavelength range can vary depending on the structure and composition of the LED structure (the n-doped portion, the light-emitting region, and the p-doped portion), and the structure and porosity of the porous region. The width of the emission wavelength range can also vary depending on the size and shape of the LED (pixel size and shape).

[0212] In preferred embodiments, the peak emission wavelength can be controlled by varying the power supply to within an emission wavelength range of at least 40 nm, or at least 50 nm, or at least 60 nm, or at least 70 nm, or at least 80 nm. More preferably, the peak emission wavelength can be controlled within an emission wavelength range of up to 100 nm, or 110 nm, or 120 nm, or 130 nm, or 140 nm, or 150 nm, or 160 nm, or 170 nm, or 180 nm, or 190 nm, or 200 nm, or 400 nm, or 450 nm. Thus, the emission wavelength range achievable by the LED of the present invention is significantly greater than that achievable by LEDs of the prior art.

[0213] The variable wavelength LED is advantageously controllable to emit any peak emission wavelength within its emission wavelength range. Thus, the variable wavelength LED can be controlled to emit any selected peak emission wavelength within this range by varying the characteristics of the power supply and the LED pixel size and shape.

[0214] The emission wavelength of the variable wavelength LED preferably responds to the driving conditions provided by the power supply that continuously changes within the driving condition range, and is continuously variable within the emission wavelength range.

[0215] The position of the emission wavelength range within the electromagnetic spectrum can also vary depending on the design of the variable-wavelength LED structure (the n-doped portion, the light-emitting region, and the p-doped portion). For example, the wavelengths included in the emission wavelength range can depend on the number and composition of the light-emitting layers in the variable-wavelength LED. Various LED active regions are known in the art that can emit at different wavelengths within the visible spectrum. Therefore, by forming the light-emitting regions of the LED of the present invention with different light-emitting regions, an emission wavelength range covering different parts of the spectrum can be achieved.

[0216] The variable wavelength LED can emit a wavelength range between 400 nm and 850 nm, or between 400 nm and 800 nm, or between 400 nm and 690 nm, or between 400 nm and 675 nm. The emission wavelength range can be a sub-range within the range of 400 nm to 750 nm. By selecting different LED active areas and controlling the size and shape of the LED pixels, the emission wavelength range can be tuned to cover any portion of this range.

[0217] Preferably, the emission wavelength range of the variable wavelength LED extends from a lower end below 410 nm, 430 nm, 450 nm, 470 nm, 500 nm, 520 nm, 540 nm, or 560 nm to an upper end above 570 nm, 580 nm, 600 nm, 610 nm, 630 nm, 650 nm, or 675 nm. As described above, the first and second ends of the emission wavelength range can be tuned based on the selection of the LED structure, LED shape, and LED size.

[0218] For example, in a preferred embodiment, the lower end of the emission wavelength may be between 400 nm and 450 nm (purple) or between 450 nm and 500 nm (blue) or between 500 nm and 570 nm (green), and the upper end of the emission wavelength may be between 570 nm and 590 nm (yellow), or between 590 nm and 610 nm (orange), or between 610 nm and 700 nm (red).

[0219] In a preferred embodiment, the variable wavelength LED can emit a wavelength range extending from below 500 nm on the lower end to above 610 nm on the upper end, so that the peak emission wavelength of the LED can be changed by varying the power supply, emitting any wavelength from blue (below 500 nm) to red (above 610 nm). Providing a single LED design that can be controlled to emit blue wavelengths (450–500 nm), green (500–570 nm), yellow (570–590 nm), orange (590–610 nm), and red (610 nm–760 nm) is very advantageous and can provide significant advantages for LED displays.

[0220] In other preferred embodiments, the wavelength range of the variable wavelength LED emission can be extended between 520 nm and 660 nm, or between 550 nm and 650 nm by changing the power supply to the LED.

[0221] In a particularly preferred embodiment, the peak emission wavelength can be controlled between 540nm and 680nm, or between 560nm and 675nm, by varying the power supply. Thus, the same LED can be controlled to emit any peak emission wavelength between 540nm green and 680nm red. Green and red LEDs have historically been more difficult to manufacture than shorter wavelength blue LEDs due to issues such as difficulty incorporating the required indium content into the light emitting area. Therefore, providing a single LED design that can be controlled to emit green wavelengths (500–570nm), yellow (570–590nm), orange (590–610nm), and red (610–760nm) is very advantageous and can provide significant advantages for LED displays.

[0222] In another preferred embodiment, the peak emission wavelength can be controlled between 520 nm and 675 nm, or between 550 nm and 650 nm by varying the power supply.

[0223] Although the variable wavelength LED can emit a continuous range of emission wavelengths, in some embodiments, it may be desirable to control the LED to operate in a plurality of distinct emission modes, for example, in response to a power supply having multiple drive modes. For example, by driving the LED in a plurality of different modes corresponding to distinct emission colors, a simplified color display can be provided, wherein the distinct emission colors are mixed to produce a desired visual effect using known methods.

[0224] The variable wavelength LED is preferably controllable to emit at least two distinct peak emission wavelengths by varying a driving condition provided by a power supply between two distinct driving conditions (e.g., two distinct magnitudes of driving current). The LED can be controlled to emit a first peak emission wavelength in response to a first driving condition provided by the power supply (which may be a driving current having a first magnitude), and to emit a second peak emission wavelength in response to a second driving condition provided by the power supply (which may be a driving current having a second magnitude different from the first magnitude).

[0225] The variable wavelength LED is preferably controllable by varying the driving conditions provided by the power supply to emit at least three distinct peak emission wavelengths. Thus, the peak emission wavelength of the variable wavelength LED can be varied across at least three "colors" in the EM spectrum.

[0226] The variable wavelength LED can be controlled to emit a first peak emission wavelength in response to a first driving condition provided by the power supply, a second peak emission wavelength in response to a second driving condition provided by the power supply, and a third peak emission wavelength in response to a third driving condition provided by the power supply.

[0227] Preferably, the variable wavelength LED can be controlled to emit a blue peak emission wavelength in response to a first driving condition provided by the power supply, emit a green peak emission wavelength in response to a second driving condition provided by the power supply, and emit a red peak emission wavelength in response to a third driving condition provided by the power supply.

[0228] The variable wavelength LED can be controlled to emit a first peak emission wavelength in the range of 400-500nm in response to a first driving condition provided by the power supply, a second peak emission wavelength in the range of 500nm-550nm in response to a second driving condition provided by the power supply, and a third peak emission wavelength greater than 600nm in response to a third driving condition provided by the power supply.

[0229] Preferably, the variable wavelength LED can be controlled to emit a first peak emission wavelength in the range of 430–460 nm in response to a first driving condition provided by the power supply, a second peak emission wavelength in the range of 510–560 nm in response to a second driving condition provided by the power supply, and a third peak emission wavelength in the range of 600–660 nm in response to a third driving condition provided by the power supply.

[0230] The first, second, and third driving conditions may be first, second, and third current densities, or the first, second, and third driving conditions may be first, second, and third power densities.

[0231] The morphology of the quantum wells (QWs) in the active light-emitting region can vary. For example, the light-emitting region can contain uniform QWs with well-defined interfaces, fragmented QWs with less well-defined interfaces, fragments, or QW well width / composition fluctuations, or quantum dots with localized centers. This control over QW morphology can determine the range of variable emission wavelengths that can be controlled and manipulated.

[0232] The light emitting region preferably comprises a plurality of quantum wells (QWs). The QWs may be continuous, fragmented or discontinuous.

[0233] The variable wavelength LED may include a current confinement layer, or current-confining layer, which is a dielectric layer configured to limit the lateral region through which current is conducted in the LED. The use of the current confinement layer can advantageously allow further control of the current density, thereby better controlling the peak emission wavelength of the LED.

[0234] The current confinement layer may advantageously enable manipulation of the power density supplied to the variable wavelength LED in order to control the peak emission wavelength.

[0235] The current confinement layer is preferably a dielectric material layer. For example, the current confinement layer can be any dielectric material, such as SiO2, SiN or SiN x .

[0236] The current confinement layer can be located at various positions in the variable wavelength LED as long as it can limit the lateral area through which the current flows in the LED. The current confinement layer can be located between an electrical n-contact and an electrical p-contact in the LED.

[0237] The current confinement layer can be located adjacent to the n-doped portion or the p-doped portion of the LED. For example, the current confinement layer can be located between the n-doped portion and the light-emitting region. Alternatively, the current confinement layer can be located between the light-emitting region and the p-doped portion. The current confinement layer can be located between an electrical contact and the LED structure (n-doped portion, p-doped portion, and light-emitting region).

[0238] The current confinement layer preferably includes a hole extending through the current confinement layer, or one or more holes extending through the current confinement layer. The hole may preferably be located in the center of the current confinement layer. For example, the current confinement layer may include a circular opening in the center of the LED structure.

[0239] The variable wavelength LED may be configured such that an electrical contact contacts the LED structure through an aperture in the current confinement layer, such that an area of ​​the aperture defines a contact region over which the contact contacts the LED structure.

[0240] The or each aperture preferably has a lateral dimension that is much smaller than the lateral dimension of the LED.By providing an aperture through the dielectric current confinement layer, a high local current density may be achieved, which may advantageously enable improved control of the power through the LED.

[0241] For example, the lateral width (or diameter) of the hole may be equal to or less than 50% of the lateral width of the LED structure (the LED platform). The width of the hole may be equal to or less than 45%, 40%, 35%, 30%, 25%, or 20% of the width of the LED structure.

[0242] The relative area of ​​the aperture compared to the total area of ​​the current confining layer (blocking region) can be varied to modify the local current density.

[0243] The light emitting region preferably comprises a multiple quantum well (MQW) comprising a plurality of quantum wells (QWs), or quantum dots, quantum wires, or other quantum nanostructures.

[0244] In some embodiments, the light emitting region comprises a plurality of quantum wells (QWs), and the QWs are continuous.

[0245] The present inventors have discovered that non-uniformities in the light-emitting region have a significant effect on broadening the emission wavelength range (the range over which the light-emitting region can emit light in response to variations in the power supplied to the LED). In the prior art, non-uniformities in the light-emitting region were generally considered problematic defects that were undesirable and should be avoided at all costs, as the goal is generally high-quality, low-defect semiconductor wafers. The present inventors have circumvented this bias in the art and discovered that intentionally creating non-uniformities in the light-emitting region can advantageously broaden the emission wavelength range and produce variable-wavelength LEDs that can emit a much wider range of wavelengths than was previously possible.

[0246] In alternative embodiments of the present invention, the light-emitting region is non-uniform, fragmented, or discontinuous. This light-emitting region can be intentionally introduced to achieve the effect of carrier confinement centers in the InGaN quantum wells, such as multiple types of QW regions with different indium compositions and well widths, quantum barriers that cause well width fluctuations, non-uniform, fragmented, broken, gapped, or discontinuous quantum wells, InGaN quantum dots or nanostructures, and quantum wells formed on polar, semi-polar, or non-polar planes.

[0247] In a preferred embodiment, the light emitting region comprises a plurality of quantum wells (QWs), and the quantum wells are non-uniform, fragmented or discontinuous.

[0248] The plurality of QWs may include well width fluctuations. For example, the well width of the QWs may fluctuate by at least 2%, 5%, 10%, 20%, 25%, 50%, or 75%. The well width fluctuations may include variations between quantum wells (vertical direction) and variations within a quantum well (lateral direction).

[0249] The plurality of QWs may include fluctuations in alloy composition. For example, the indium composition of the QWs may vary by at least 2%, 5%, 10%, 20%, 25%, 50%, or 75% across the light emitting area.

[0250] The present inventors have discovered that fluctuations in well width and / or alloy composition can induce carrier confinement centers at the upper or lower interface of the QW. Any carrier confinement center will induce variable wavelength in the variable-wavelength LED of the present invention. The greater the density of these carrier confinement centers, the greater the achievable variable wavelength range.

[0251] The variable wavelength LED may include a V-shaped pit extending or propagating through the light emitting active area. Preferably, the LED includes a plurality of V-shaped pits extending through the light emitting area.

[0252] Preferably, the variable wavelength LED may include at least 1×10 7 pieces / cm 2 , for example, at least 5×10 7 pieces / cm 2 or at least 1×10 8 pieces / cm 2 The V-shaped pit density (measured by looking down at the LED structure from above), for example, 1×10 7 pieces / cm 2 to 5×10 9 pieces / cm 2 The density of V-shaped pits.

[0253] The variable wavelength LED may contain less than 5×10 9 pieces / cm 2The V-shaped pit density is less than 1×10 9 pieces / cm 2 or less than 5×10 8 pieces / cm 2 The density of V-shaped pits.

[0254] V-pits are a well-known phenomenon in epitaxial semiconductor growth, and methods for growing them in semiconductor structures are known in the art. For example, V-pits and their growth are previously described in the paper "The effect of nanometer-scale V-pits on electronic and optical properties and efficiency droop of GaN-based green light-emitting diodes" (Zhou et al., Scientific Reports, 2018, 8:11053, DOI: 10.1038 / s41598-018-29440-4).

[0255] These V-shaped pits appear V-shaped when viewed in cross-section, but are actually conical or funnel-shaped voids in semiconductor structures grown from the bottom up using common epitaxial growth methods. Although the pit is V-shaped in cross-section, it is typically hexagonal when viewed from above. The point of the V-shaped pit always points downward toward the earlier deposited layers of the semiconductor structure, as the pit widens as subsequent epitaxial layers are deposited on top of the structure.

[0256] While V-shaped pits are known in the art, they are generally considered problematic defects in semiconductor structures, which is undesirable since the goal is generally high-quality, low-defect semiconductor wafers.

[0257] In the unusual case of V-pits introduced into semiconductor structures in the past, they have been used as a screening mechanism to create a higher bandgap region, preventing current carriers from following leakage paths down the line arrays.

[0258] However, in some preferred embodiments of the present invention, V-shaped pits are intentionally incorporated into the variable wavelength LED structure. The V-shaped pits extend far enough down into the semiconductor structure that they terminate in a layer below the active light emitting region. This means that the V-shaped pits must extend through the thickness of the active light emitting region.

[0259] The present inventors have discovered that a V-shaped pit extending across the light emitting region of the LED structure can advantageously broaden the range of emission wavelengths that can be emitted by the variable wavelength LED.

[0260] Because the V-shaped pit extends through the active area of ​​the LED, the quantum well (QW) layer (which is flat across the rest of the structure) grows on the sloped sidewalls of the V-shaped pit during epitaxial growth from the bottom up. The QWs deposited on the pit sidewalls are twisted and stretched around the sides of the pit, ultimately having a different thickness and composition than the flat QWs across the entire structure.

[0261] Around the V-shaped pit, the QW layer of semiconductor material grows as a flat layer. Therefore, the active light-emitting area is flat around the V-shaped pit. However, at the location of the V-shaped pit, the active layer is distorted and stretched down along the sidewalls into the V-shaped pit. This stretching effect changes the thickness of the QWs on the pit sidewalls, so that their thickness is different from the flat QW layer formed above the rest of the LED structure.

[0262] The present inventors have discovered that V-pits can create local strain relaxation, and the MQWs deposited on the sidewalls of these V-pits will have different thickness and composition than the rest of the MQWs, so the MQWs in the V-pit region will produce different emission wavelengths.

[0263] The quantum wells grown on the sidewalls of the V-shaped pit are thinner than the bulk planar QWs elsewhere in the structure, which can affect the QW bandgap and allow the QWs in this region to emit at different wavelengths than the flat QWs elsewhere in the structure. In addition, the QWs on the sidewalls of the pit can ultimately have a higher indium (In) content than the surrounding flat QWs because the sidewalls expose the semipolar face of the QW - this face incorporates more indium during the epitaxial growth process, so the QWs in the V-shaped pit region can have higher indium than the flat QWs surrounding the pit. Higher indium incorporation generally results in a longer peak emission wavelength. Both QW thickness and indium content affect the emission wavelength produced by the light-emitting region. Therefore, the presence of the V-shaped pit in the LED structure can advantageously modify the composition and thickness of the QWs in the light-emitting region, and this modification expands the range of emission wavelengths over which the LED can be driven to emit light.

[0264] V-shaped pits typically grow from dislocations in a semiconductor structure. As additional layers are grown on top of the layer containing the dislocations, the dislocations continue upward in the structure, and at some point they widen into a V-shaped pit. Generally, the goal is to keep the dislocation concentration low in order to produce "high-quality," low-defect wafers.

[0265] The V-shaped pits can also be grown optionally using a 3D epitaxial growth mode. 3D epitaxial deposition techniques are known in the art and are typically used to grow “islands” or “cones” of semiconductor material on a template. By controlling the deposition of the LED structure using 3D epitaxial deposition techniques, V-shaped pits can be artificially grown at the desired location without the need for line arrays to “seed” the formation of the V-shaped pits. By using this deposition control, the bottom (lowest point) of the pit can be created at the desired location in the structure – at the desired lateral position and at the desired height in the structure, for example, at a specific layer below the active light-emitting area in the semiconductor structure.

[0266] The bottom of the V-shaped pit may be located in a connection layer of the semiconductor structure. The connection layer may be located between the porous region and the n-doped portion.

[0267] The bottom of the V-shaped pit may be located in a pre-strained layer of the semiconductor structure. The pre-strained layer may be located above the n-doped portion and below the light emitting region.

[0268] Preferably, the variable wavelength LED comprises a plurality of V-shaped pits extending through the active light emitting area.

[0269] Preferably, the variable wavelength LED comprises at least 1×10 7 pieces / cm 2 , for example, at least 5×10 7 pieces / cm 2 or at least 1×10 8 pieces / cm 2 The V-shaped pit density (measured from above looking down at the LED structure) can be less than 5×10 9 pieces / cm 2 The V-shaped pit density is less than 1×10 9 pieces / cm 2 or less than 5×10 8 pieces / cm 2 The density of V-shaped pits.

[0270] For example, the variable wavelength LED may include 1×10 7 pieces / cm 2 to 5×10 9 pieces / cm 2 , or 5×10 7 pieces / cm 2 to 5×10 9 pieces / cm 2 , or 1×10 8 pieces / cm 2 to 5×10 8 pieces / cm 2 The density of V-shaped pits.

[0271] The variable wavelength LED may include more than 0.1 V-shaped pits per square micron, or more than 1 V-shaped pit per square micron, or more than 2 V-shaped pits per square micron.

[0272] The concentration of V-pits in the variable wavelength LED is preferably controlled, as excessive V-pits may negatively impact the LED's light emission by disrupting radiative recombination. For example, the LED may contain fewer than 10 V-pits per square micron, fewer than 8 V-pits per square micron, or fewer than 6 V-pits per square micron.

[0273] In a preferred embodiment, the LED structure may include no more than 10^9 dislocations per square centimeter. Preferably, the semiconductor structure beneath the active light-emitting region (typically the substrate, porous region, and interconnect layer) includes no more than 10^9 dislocations per square centimeter. The dislocation density is preferably limited to this level so that further epitaxial growth does not create excessive V-shaped pits in the light-emitting region.

[0274] The density and size (depth) of the V-shaped pits can be controlled. The size of the V-pits can be controlled by the position and growth conditions of the pre-strained layer and the low-temperature nGaN layer at the beginning of the pits.

[0275] The morphology of the quantum wells (QWs) in the active light-emitting region can vary. For example, the light-emitting region can contain uniform QWs with well-defined interfaces, fragmented QWs with less well-defined interfaces, fragments, or QW well width / composition fluctuations, or quantum dots with localized centers. This control over QW morphology can determine the range of variable emission wavelengths that can be controlled and manipulated.

[0276] The light emitting region preferably comprises a plurality of quantum wells (QWs). The QWs may be continuous, fragmented or discontinuous.

[0277] If the QW is continuous and very uniform in thickness and composition, the recombination of charge carriers can only occur in a well-defined manner. On the other hand, if the QW is fragmented or discontinuous, this creates a large number of nanostructures, resulting in different band gaps and, therefore, different colors of emission. BRIEF DESCRIPTION OF THE DRAWINGS

[0278] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0279] Figures 1A-1D A step-by-step diagram of the prior art method of "wafer bonding" for integrating RGB sub-pixels into a display device;

[0280] Figures 2A-2Dis a step-by-step diagram of the prior art method of "mass transfer" for integrating RGB sub-pixels into a display device;

[0281] Figures 3A-3I is a step-by-step diagram of a method of manufacturing a photovoltaic device according to an embodiment of the present invention;

[0282] Figures 4A-4J is a step-by-step illustration of a method of manufacturing a photovoltaic device according to an alternative embodiment of the present invention;

[0283] Figure 5 is a schematic diagram of a porous region of a Group III nitride material according to a preferred embodiment of the present invention, wherein the porous region is configured as a DBR for improving light extraction in an optoelectronic device;

[0284] Figure 6 is a schematic diagram of a porous region of a Group III nitride material according to a preferred embodiment of the present invention, wherein the porous region is configured as an anti-reflection layer for improving light extraction in an optoelectronic device;

[0285] Figure 7 is a schematic diagram of a porous region of a Group III nitride material according to a preferred embodiment of the present invention, wherein the porous region is configured as a color filter for improving light extraction in an optoelectronic device;

[0286] Figure 8 is a schematic diagram of an optoelectronic device according to a preferred embodiment of the present invention, which contains porous III-nitride regions as DBR / AF pairs on both sides of the device structure;

[0287] Figure 9A and Figure 9B is a schematic diagram of a porous region of a III-nitride material etched into multiple layers of a multi-region optical filter / AF layer;

[0288] Figure 10 This is a series of five EL images of the same micron-sized LED pixel driven at different currents in constant wave mode (CW), showing five different emission colors;

[0289] Figure 11A This is a graph of emission wavelength versus current density for a 25μm×25μm 100×100 variable wavelength LED pixel array driven in a pulsed mode with a 100μm pulse and a 1% duty cycle.

[0290] Figure 11B This is a graph of emission wavelength versus current density for a 30μm×30μm 100×100 variable wavelength LED pixel array driven in a pulse mode with a 100μm pulse and a 1% duty cycle.

[0291] Figure 12 This is a graph showing the intensity versus wavelength of a single variable wavelength LED in a pulsed driving mode with a 100 μm pulse and a 1% duty cycle, driven at different currents.

[0292] Figure 13A -G shows an alternative embodiment of a non-uniform, segmented or discontinuous light emitting area of ​​a variable wavelength LED that can be used in the preferred embodiment of the present invention;

[0293] Figure 14A This is a cross-sectional TEM image of a commonly used non-variable wavelength LED.

[0294] Figure 14B is a TEM image of the light emitting region of a variable wavelength LED including a V-shaped pit that can be used in an embodiment of the present invention;

[0295] Figure 14C It is applicable to the preferred embodiment of the present invention Figure 14B TEM image of a variable wavelength LED showing a porous region and a light-emitting region containing multiple V-shaped pits;

[0296] Figure 15A This is a graph of peak emission wavelength versus driving current density for commonly used non-variable wavelength LEDs;

[0297] Figure 15B is a graph of peak emission wavelength versus driving current density of a variable wavelength LED according to an embodiment of the present invention;

[0298] Figure 15C is a graph of peak emission wavelength versus driving current density of a variable wavelength LED according to another embodiment of the present invention;

[0299] Figure 16A is a graph of peak emission wavelength versus driving current density for another variable wavelength LED that can be used in the present invention;

[0300] Figure 16B -D is Figure 16A Photograph of a variable-wavelength LED with an inset of the emission spectrum showing the different peak emission wavelengths at different drive current densities. DETAILED DESCRIPTION

[0301] Figures 1A-1D A step-by-step illustration of the prior art method of "wafer bonding" for integrating RGB sub-pixels into a display device.

[0302] exist Figure 1AIn the present invention, a driver wafer 10 containing three CMOS LED drivers 20 is integrated with a red (R) LED device wafer 30, which includes red LEDs 40 formed in an epitaxial structure above a growth substrate wafer 60. The red LED device wafer 30 is flip-chip bonded to the driver wafer 10 using conventional wafer bonding techniques. The red LED wafer 30 contains one red LED 40, which is aligned to electrically connect to one of the three CMOS LED drivers 20 when the red LED wafer is bonded to the driver wafer. Conductive vias 50 extending through the device wafer are aligned with the other two CMOS drivers 20. After bonding to the driver wafer 10, the growth substrate wafer 60 is removed from the red LED device wafer 30 to expose the top surface of the device wafer.

[0303] exist Figure 1B In FIG. 1 , a green (G) LED device wafer 70 is flip-chip bonded to the top surface of a red LED device wafer 30 using conventional wafer bonding techniques. Green LED wafer 70 includes green LEDs 80 formed in an epitaxial structure above a growth substrate wafer 60. Green LEDs 80 are aligned to electrically connect to one of the two CMOS LED drivers 20 that are not connected to the red LED. Conductive vias 50 extending through green LED device wafer 70 are aligned with the red LEDs 40 and the remaining CMOS drivers. After being bonded to red LED device wafer 30, growth substrate wafer 60 is removed from green LED device wafer 70.

[0304] exist Figure 1C In FIG. 1 , a blue (B) LED device wafer 90 is flip-chip bonded to the top surface of a green LED device wafer 70 using conventional wafer bonding techniques. This blue LED wafer includes blue LEDs 100 formed in an epitaxial structure above a growth substrate wafer 60. Blue LEDs 100 are aligned to electrically connect to the only remaining CMOS LED driver 20 that is not connected to any of the other LEDs. Conductive vias 50 extending through the blue LED device wafer 90 are aligned with the red LEDs 40 and the green LEDs 80. After being bonded to the green LED device wafer, the growth substrate wafer 60 is removed from the blue LED device wafer 90.

[0305] Figure 1D The integrated device 110 is shown after the growth substrate wafer 60 has been removed from the blue LED device wafer 90 and after further conventional processing has been performed, such as attaching electrical contacts (not shown). Each of the R, G, and B LEDs is electrically connected to its own CMOS LED driver 20 so that each LED can be turned on and off individually.

[0306] Figures 2A-2D A step-by-step illustration of the prior art method of "mass transfer" for integrating RGB sub-pixels into a display device.

[0307] In this “pick-and-place” integration approach, e.g. Figure 2A As shown, the red (R), green (G) and blue (B) LEDs 40, 80, 100 are each grown on their own growth substrate 60 and then "picked up" (removed) from their growth substrate. Figure 2B As shown, all three individual LEDs are then transferred and bonded to a common RGB device wafer 120 which serves as a temporary substrate. Figure 2C As shown, the common RGB device wafer is then flip-chip bonded to the driver wafer 10 using conventional wafer bonding techniques. Each of the R, G, and B LEDs 40, 80, 100 is aligned with its own CMOS LED driver 20 in the driver circuit of the driver wafer 10 so that each LED can be driven separately from the others. Figure 2D As shown, the temporary substrate 60 is removed, leaving the R, G, and B LEDs bonded to the display device 130 driving the wafer 10 .

[0308] like Figures 1A-1D As shown, for simplicity, some standard device processing steps are not shown.

[0309] Example 1

[0310] Figures 3A-3I is a step-by-step illustration of a method of manufacturing an optoelectronic device 300 according to an embodiment of the present invention.

[0311] Figure 3A A device wafer 310 is shown including a semiconductor device epitaxial structure 320 formed over a porous layer 330 of a Group III nitride material on a substrate wafer 340 .

[0312] Further layers of semiconductor material may be provided above or below the porous layer, but are omitted from the illustration for simplicity.

[0313] Although GaN is shown in the figures, a variety of Group III nitride semiconductor materials can be used. Preferably, all semiconductor materials used in the present invention are Group III nitride semiconductor materials. Therefore, preferably, the wafer includes multiple Group III nitride semiconductor material layers on the substrate. Each semiconductor layer in the wafer (excluding the substrate) is also preferably formed of one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0314] The porous layer 330 can take a variety of forms, as discussed further below. For example, depending on the intended application of the device, the porous layer can be a multi-layer porous region comprising multiple layers of porous and optionally non-porous Group III nitride materials.

[0315] Prior to the epitaxial growth of the device epitaxial structure, the porous layer 330 may be made porous by electrochemical etching as described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0316] The substrate wafer 340 can be silicon, sapphire, SiC, or β-Ga2O3. The substrate can have a polar, semi-polar, or non-polar orientation. The substrate thickness can typically vary from 100 μm to 1500 μm. The wafer can have various sizes, such as 1 cm 2 or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter or larger.

[0317] The present invention can utilize a variety of device epitaxial structures 320. The device epitaxial structure can be any optoelectronic semiconductor device, such as a VCSEL, but will be described herein with reference to a light emitting diode (LED) structure having an n-type region 355, a light emitting region 365, and a p-type region 375.

[0318] For example, the device epitaxial structure 320 may be a conventional LED epitaxial structure.

[0319] The device epitaxial structure 320 may be, for example, an LED as described in International Patent Applications PCT / GB2021 / 050152 (published as WO 2021 / 148808) and PCT / GB2021 / 052020 (published as WO 2022 / 029434).

[0320] In a particularly preferred embodiment, the device epitaxial structure 320 may be as described above and below with reference to Figure 10-16E The variable wavelength LED epitaxial structure is further described.

[0321] like Figure 3BAs shown, a device wafer 310 is etched into a plurality of discrete device platforms 350 by etching a series of trenches through the device structure. Each device platform 350 is a "tower-like" structure containing an n-type region 355, a light-emitting region 365, and a p-type region 375. Because all device platforms 350 are etched from the same epitaxial structure 320, the layered structure of each platform is identical. However, the lateral dimensions of the device platforms can vary depending on the lateral spacing of the trenches. By controlling the spacing of the trenches, the device platforms can be formed into, for example, sub-millimeter-scale LEDs, micrometer-scale LEDs, or nanometer-scale LEDs.

[0322] Device wafer 310 can be etched using common etching techniques known to those skilled in the art. For example, the device wafer can be etched using wet chemical or sputter etching methods using argon. This step can be followed by wet or dry etching of the III-nitride structure. Inductively coupled plasma reactive ion etching (ICP), reactive ion etching alone, or neutral beam etching can be used to create mesas in the III-nitride layer. The dry etching process can include one or more of Cl, Ar, BCl3, and SiCl4 gases.

[0323] After the dry etch process, a wet etch process may be performed to remove dry etch damage from the sidewalls of the mesa. The wet chemistry may involve KOH (1-20%), TMAH, or other alkaline chemicals.

[0324] like Figure 3B As shown, trenches may be etched to varying depths in the device structure 310 .

[0325] An isolation etch may be performed in which isolation trenches 360 are etched completely through the depth of the semiconductor structure 320 so that the bottom of the trench reaches the substrate wafer 340. These isolation trenches cut off all electrical paths between device platforms on either side of the isolation trenches so that the platforms on either side of the isolation trenches are electrically isolated from each other.

[0326] Shallow terrace trenches 370 can be etched into the device wafer 310 without reaching all the way through to the substrate wafer 340. Terrain trenches 370 should be etched to a depth greater than the depth of the LED light-emitting area so that the light-emitting areas of the individual device terraces 350 are separated from one another. Depending on how deep the terrace trenches extend into the epitaxial structure, the device terraces on either side of the terrace trench can be electrically connected to one another, for example, if the conductive layer of the device wafer extends completely below the depth of the terrace trenches, allowing for electrical conduction between the device terraces. For example, in the illustrated embodiment, the terrace trenches are shown as not being etched completely through the n-type layer of the semiconductor device structure so that the n-type layer will be electrically connected to all terraces epitaxially connected to the same portion of the n-type layer.

[0327] The position of the device platform 350 can be varied and controlled by selecting the location and size of the trenches etched into the wafer.

[0328] After etching the device wafer into a plurality of device platforms, a liner dielectric layer 380 is deposited over the wafer and the device platforms, such as Figure 3C The liner dielectric layer may be formed of, for example, silicon dioxide or silicon nitride dielectric.

[0329] like Figure 3D As shown, a dielectric fill material 390 is deposited over the device wafer. The dielectric fill material fills the mesa trenches 370 and the isolation trenches 360 and is planarized to provide a flat, or planar, upper surface 400 on the device wafer.

[0330] Then as Figure 3E As shown, metal vias 410 are formed in device wafer 310 by etching channels through dielectric fill material 390 and forming openings through the underlying liner dielectric layer, exposing contact areas on the top surface of each device platform 350. Conventional masking and etching processes can be used to selectively etch the channels at certain locations.

[0331] The size of the channel can be controlled to control the size of the contact area on each device platform 350.

[0332] Once the channels are etched in the desired locations, metal is deposited into the etched channels, forming metal vias 410 that electrically connect the underlying semiconductor material to the planar upper surface 400 of the device wafer.

[0333] The metal vias 410 are preferably formed on each device platform 350, but may also be formed in the isolation trenches 360 and / or platform trenches 370, as shown. Figure 3E shown, depending on the electrical requirements of a given installation.

[0334] like Figure 3F As shown, additional dielectric fill material and / or metal layers may be deposited to provide bond pads 420 of appropriate shape and size for bonding to the driver wafer 430 .

[0335] Figure 3G The device wafer 310 is shown flipped upside down and integrated with a driver wafer 430 to provide an integrated device. The driver wafer contains driver circuitry for driving all of the LED device platforms 350, so that each metal via 410 in the device wafer 310 is electrically connected to a contact pad 450 in the driver circuitry. The two wafers are bonded together using conventional wafer bonding techniques.

[0336] Once flipped upside down, the dielectric liner's mesa trenches 370 and isolation trenches 360 become barriers separating the individual device mesas 350 .

[0337] The driver circuit (not shown) can take a variety of forms depending on the design requirements of any particular device, but preferably connects each LED device platform to its own LED driver so that the driver circuit is configured to drive each LED device platform in the device wafer 310.

[0338] like Figure 3H As shown, the substrate wafer 340 of the device wafer 310 can then be removed from the integrated device. When the substrate wafer 340 is removed, the remaining surface of the device wafer forms the light emitting surface 460 of the device, with the porous layer 330 located between the light emitting surface 460 and the device platform 350. An additional non-porous layer (not shown) may be present between the light emitting surface and the porous layer.

[0339] Further processing steps can then be performed to Figure 3H The device is processed into an operable optoelectronic device 300. For example, Figure 3I Micro lenses 470 are shown positioned above some LED device platforms to improve the light emission characteristics of those LED device platforms. Metal pads 480 for wire bonding may also be deposited on the light emitting surface so that the metal pads are positioned above the isolation trenches 360 and electrically contact the driver circuitry through metal vias 410 extending through the isolation trenches.

[0340] Example 2

[0341] Figures 4A-4J is a step-by-step illustration of a method of manufacturing an optoelectronic device 500 according to an alternative embodiment of the present invention.

[0342] Figure 4A The device wafer 310 shown in FIG. 3 may be compared to the device wafer 310 shown in FIG. Figure 3A The device wafers described are identical.

[0343] Figures 4A-4C The steps in Figures 3A-3C The steps described are the same.

[0344] exist Figure 4D In the embodiment of the present invention, rather than depositing dielectric fill material 380 into the trench to cover the device platform 350, an opening 520 can be etched through the liner dielectric layer 380 at the location where electrical contact is required. As described above, the size of the opening can be different between platforms in order to vary the contact area on different device platforms.

[0345] After etching openings 520 through the pad dielectric layer 380, metal 510 can be deposited over the device wafer to fill the openings 520 in the pad dielectric layer, covering the pad dielectric layer 380 and the device mesa 350. The metal 510 acts as a filler for the mesa trench 370 and the isolation trench 360, and also forms a reflective layer 530 surrounding and covering the LED device mesa 350.

[0346] like Figure 4E As shown, the metal fill 510 and the liner dielectric 380 on top of the platform 350 are planarized so that the platform is electrically isolated. Figure 4F As shown, metal pads 540 are then deposited over the planarized metal and device mesas where electrical contact is desired before covering the pads and the device wafer with a dielectric fill material 380. The dielectric fill material 380 is then planarized to provide a flat or planar upper surface 400 on the device wafer.

[0347] Then as Figure 4G As shown, metal vias 410 are formed in the device wafer by etching a via through the dielectric fill material 380 to reach the metal pad 540. Conventional masking and etching processes can be used to selectively etch the via in certain locations.

[0348] like Figure 4G As shown, additional dielectric fill material and / or metal layers may be deposited to provide bond pads 420 of appropriate shape and size for bonding to the driver wafer 430 .

[0349] Figure 4H The device wafer 310 is shown flipped upside down and integrated with the driver wafer 430 to provide an integrated device. The driver wafer 430 contains driver circuitry (not shown) for driving all of the LED device platforms, such that each metal via in the device wafer is electrically connected to a contact pad 450 in the driver circuitry. The two wafers are bonded together using conventional wafer bonding techniques.

[0350] The driver circuit can take a variety of forms depending on the design requirements of any particular device, but preferably has each LED device platform connected to its own LED driver so that the driver circuit is configured to drive each LED device platform in the device wafer.

[0351] like Figure 4I As shown, the substrate wafer 340 of the device wafer 310 can then be removed from the integrated device. When the substrate wafer is removed, the remaining surface of the device wafer forms the light emitting surface 460 of the device, with the porous layer 330 located between the light emitting surface 460 and the device platform 350. An additional non-porous layer (not shown) may be present between the light emitting surface and the porous layer.

[0352] Further processing steps can then be performed to Figure 4I The device is processed into an operable optoelectronic device 500. For example, Figure 4J Micro lenses 470 are shown positioned over some of the LED device platforms 350 to improve the light emission characteristics of those LED device platforms. By etching openings in the liner dielectric layer lining the isolation trenches, the metal fill material filling the isolation trenches can be converted into metal pads 550 for wire bonding.

[0353] In this embodiment, the embedded metal reflective layer 530 improves light extraction from the optoelectronic device by surrounding the light emitting device platform and reflecting any misdirected light away from the light emitting surface of the device.

[0354] Porous regions for optical enhancement

[0355] As described above, the porous region, or porous layer, of the device wafer can take a variety of different forms depending on the application of a given device. The porous region can provide a variety of optical engineering functions for the device. For example, the porous region can be configured to provide a DBR, alternating layers, filters, reflectors, bandpass filters, bandstop filters, and / or mirrors.

[0356] exist Figure 5 9 , the driver wafer and the rest of the device are not shown, and for simplicity, only the porous region and the epitaxially connected LED device platform are shown.

[0357] Porous Group III nitride materials can be advantageously used to provide a variety of optical enhancements to optoelectronic devices. The porous region can be a single layer or multilayer structure, and the thickness, layer sequence, and refractive index of each layer can be precisely and individually configured by controlling the doping level and layer design during epitaxial growth and by making the n-doped layer porous using the electrochemical porosification technique described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0358] Figure 5 FIG. 1 is a schematic diagram of a porous region of a III-nitride material according to a preferred embodiment of the present invention, wherein the porous region is configured as a DBR for improving light extraction in an optoelectronic device.

[0359] Because porosity modifies the refractive index of III-nitride materials, porous III-nitride materials can be very effectively used to form distributed Bragg reflectors (DBRs), which selectively reflect certain wavelengths of light. The structure and fabrication of porous DBRs are described, for example, in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0360] A DBR containing a porous layer of a Group III nitride material can be formed on either side (above or below) of the semiconductor device structure 600 including the light emitting region. The DBR should be grown on the correct side of the light emitting region to achieve the desired function after the device wafer is flipped and bonded to the driver wafer.

[0361] When a DBR is positioned below the light-emitting region in a finished device, so that the light-emitting region is between the DBR and the device's light-emitting surface, the DBR acts as a mirror, reflecting any misdirected light back toward the device's light-emitting surface. This significantly improves light extraction because emitted light is no longer directed toward the driver wafer and wasted.

[0362] The specific thickness and arrangement of the layers in the DBR will vary depending on the wavelengths to be reflected and / or transmitted by the DBR.

[0363] Figure 6 Figure 2 is a schematic diagram of a porous region of a Group III nitride material configured as an antireflection layer for improving light extraction in an optoelectronic device, according to a preferred embodiment of the present invention. In this embodiment, a DBR is positioned between the device's light-emitting layer and the light-emitting surface. Any emitted light that is undesirably reflected back into the device due to reflections from the light-emitting surface is reflected back by the DBR, enhancing overall light extraction.

[0364] Figure 7 A schematic diagram of a porous region of a III-nitride material configured as a color filter for improving light extraction in an optoelectronic device, according to a preferred embodiment of the present invention. Optically filtering emitted light using porous III-nitride materials is described in International Patent Application PCT / GB2021 / 052366 (published as WO2022 / 053831) and provides improved light extraction and a narrower emission bandwidth by reflecting unwanted wavelengths and preventing them from transmitting through the device's light-emitting surface.

[0365] Figure 8 is a schematic diagram of an optoelectronic device according to a preferred embodiment of the present invention, which contains porous III-nitride regions as DBR / AF pairs on both sides of the device structure. Figure 5 and Figure 6 The advantage of this is that one DBR reflects emitted light emitted in a direction away from the light emitting surface of the device, while the other DBR acts as an anti-reflective coating, which prevents the emitted light from being reflected by the light emitting surface back into the device.

[0366] Figure 9A and Figure 9B Schematic diagram of porous regions of a multi-layer III-nitride material etched into a multi-region optical filter / AF layer. Rather than having a uniform porous region extending across the entire device wafer and across multiple device platforms in a finished optoelectronic device, the porous region can be customized for a specific device platform.

[0367] For example, Figure 9A Shows a uniform multi-layer porous region located above three separate LED device platforms. Figure 9B The invention shows how selective etching of the porous region can be performed to vary the thickness of the porous region on selected device platforms. Thus, the optical properties imparted by the porous region can be varied between device platforms. Since each device platform is preferably a pixel or sub-pixel of a display device, the porous region can be patterned to impart specific properties to some sub-pixels and different properties to other sub-pixels.

[0368] Variable wavelength LED

[0369] In a particularly preferred embodiment of the present invention, the device epitaxial structure forming all device platforms is a variable wavelength LED epitaxial structure. Particularly advantageously, a single variable wavelength LED epitaxial structure can be grown on a porous region of a wafer-level III-nitride material to form a Figure 3A and Figure 4A The device wafer is shown.

[0370] This entire wafer-level device structure can be formed during a single epitaxial growth process, and the method of the present invention can then be used to process the resulting device wafer into optoelectronic devices in which each individual device platform acts as an individual variable wavelength LED.

[0371] This opens up a wealth of possibilities for display devices, as the "color" (peak emission wavelength) emitted by each LED can be controlled by controlling the drive current density supplied to a particular LED platform.

[0372] Therefore, the driver circuit can be configured to drive the variable wavelength LED in the device in a variety of different ways, depending on the desired result:

[0373] Each variable wavelength LED in the device can be dynamically driven by the driving circuit, wherein each variable wavelength LED receives a driving current density whose magnitude varies in real time during a display frame, so that the same variable wavelength LED can be controlled to emit multiple different wavelengths during a single display frame.

[0374] Each variable-wavelength LED can be driven by the driver circuit at a fixed drive current density, so that the variable-wavelength LED functions as a fixed-wavelength emitter when in use. However, the driver circuit can be configured to provide different drive current densities to different variable-wavelength LEDs in the device. Even if different variable-wavelength LEDs are formed from the same epitaxial wafer and have the same device structure, the different drive current densities control the different device platforms to emit different fixed peak emission wavelengths. Therefore, by providing different fixed drive conditions to different device platforms, a multi-color display can be provided from a single device epitaxial wafer.

[0375] A hybrid of these two options may also be provided, wherein the driver circuit is configured to dynamically control some device platforms in the device and control other device platforms to be fixed wavelength emitters by providing a fixed drive current to the other device platforms.

[0376] During manufacturing, the size, shape, and position of the variable wavelength LED can be controlled by controlling the size, shape, depth, and position of the trenches etched into the device wafer.

[0377] By epitaxially forming all individual device platforms from a single wafer, many of the time-consuming, low-yield, and expensive processing steps required for device integration in the prior art can be eliminated.

[0378] In a preferred embodiment of the present invention, the driver circuit and some or all of the variable wavelength LEDs are preferably configured to receive a variable amount of drive current from the driver circuit, so that the amount of drive current provided to each variable wavelength LED is variable. By varying the amount of drive current provided to each variable wavelength LED, the peak emission wavelength of that LED can be varied as the display device is used. The drive current provided to each variable wavelength LED can be individually controllable, so that the peak emission wavelength of each variable wavelength LED in the display can be individually controlled and varied. Alternatively, the device and driver circuit can be configured so that the same drive conditions are simultaneously provided to a group of variable wavelength LEDs, so that all variable wavelength LEDs in the group emit light of the same peak emission wavelength when the drive current is turned on, and the peak emission wavelength of the entire group can be varied by varying the amount of the drive current.

[0379] In an alternative embodiment, the driver circuit can be configured to provide a fixed (i.e., non-variable) drive current to some or all of the variable-wavelength LEDs in the display device when the driver circuit is turned on or off. When the fixed drive current is on, the variable-wavelength LEDs will behave like conventional LEDs, emitting a single peak emission wavelength determined by the driving conditions provided to the LEDs. Thus, variable-wavelength LEDs configured to receive a fixed drive current can be used as fixed-emission-wavelength LEDs in the display device.

[0380] Preferably, the driving circuit is configured to control at least one sub-pixel in each pixel to become a dynamically variable wavelength LED, whose peak emission wavelength can be changed within a single display frame.

[0381] The driver circuit can be configured to individually control the drive current provided to each of the plurality of LEDs so that each of the plurality of LEDs can be driven individually. The driver circuit can be configured to provide a plurality of different drive currents to the plurality of LEDs so that the individual LEDs can be driven to emit different peak emission wavelengths in response to the different drive currents.

[0382] Alternatively, the driver circuit can be configured to independently control two or more LED groups so that each LED in the group emits the same peak emission wavelength. The driver circuit can be configured to provide different drive currents to different LED groups so that the individual LED groups can be driven in response to the different drive currents to emit different peak emission wavelengths.

[0383] Figure 10 This is a series of five EL images of the same variable-wavelength micron-sized LED InGaN pixel driven in constant-wave mode (CW) at different currents, showing five different emission colors. In the left-hand image, at a drive current of 50μA, the emission color of this micron-sized LED appears red. In the second image from the left, at a drive current of 100μA, the emission color of this micron-sized LED appears reddish-orange. In the third image from the left, at a drive current of 1mA, the emission color of this micron-sized LED appears orange. In the fourth image from the left, at a drive current of 10mA, the emission color of this micron-sized LED appears yellow-green. In the right-hand image, at a drive current of 20mA, the emission color of this micron-sized LED appears green.

[0384] By varying the drive current between 50 μA and 20 mA, the same micron-sized LED can emit wavelengths ranging from red to green. The spectral width of this emission wavelength range is approximately 90 nm (from approximately 570 nm to approximately 660 nm). This is significantly greater than the emission wavelength range achievable with a single LED using previous technologies.

[0385] Figure 11A Graph of emission wavelength versus current density for a 25 μm×25 μm InGaN LED pixel array (100×100 array, containing 10,000 pixels) driven in pulsed mode with 100 μs pulses and a 1% duty cycle. Figure 16B Graph of emission wavelength versus current density for a 30 μm×30 μm InGaN LED pixel array (100×100 array, containing 10,000 pixels) driven in pulsed mode with 100 μs pulses and a 1% duty cycle.

[0386] Both figures demonstrate the controllability of peak emission wavelength using a pulsed drive power supply. Specifically, wavelength is linearly related to current density (plotted on a logarithmic scale). This linearity can also be manipulated when driving with a pulsed voltage supply. Thus, variable emission wavelengths can be controlled using voltage or current drive schemes in either CW or pulsed modes, all standard approaches for display driver ICs.

[0387] This linear relationship between the driving current density and the resulting emission wavelength is very beneficial for the design of LED displays because the emission wavelength can be precisely controlled by changing the current density of the power supply.

[0388] Figure 12 This is a graph of the intensity versus wavelength of a variable wavelength InGaN LED driven at different DC currents. The power supply was operated in pulse mode with 100 μs pulses and a 1% duty cycle.

[0389] Figure 12 This again demonstrates that the LED's peak emission wavelength gradually and continuously shifts with changes in supply current. At a drive current of 200mA, the peak emission wavelength is approximately 575nm, with an intensity of approximately 10μW / nm. However, as the drive current decreases, the peak emission wavelength gradually shifts to longer wavelengths and lower emission intensities. When the drive current reaches 7mA, the peak emission wavelength is approximately 675nm, with an intensity of approximately 0.1μW / nm.

[0390] Figure 13A -G shows an alternative embodiment of the light emitting region of a variable wavelength LED that can be used as the semiconductor device in the embodiment of the present invention.

[0391] Example of MQW:

[0392] 1. Consecutive MQWs

[0393] 2. V-pit

[0394] 3. Broken QWs, QWs with gaps, and QWs with fragments

[0395] 4.QD

[0396] 5. Well width fluctuation

[0397] 6. Alloy composition

[0398] 7. Different combinations of MQW and underlying layers

[0399] These structural features can be identified and examined by standard materials characterization techniques, such as cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD), energy dispersive X-ray spectroscopy (EDX or EDS), and 3D atom probe (3DAP).

[0400] Figure 13A A continuous MQW light emitting region of an LED is shown, wherein three identical quantum barriers (QBs) are provided between four identical QWs.

[0401] Figure 13B Figure 18A shows a continuous MQW with a V-shaped pit extending across the light emitting area. The V-shaped pit terminates in a threading dislocation and has a QW on its semipolar plane.

[0402] Figure 13C An MQW is shown where the QW layer contains discontinuities or gaps in the semiconductor material.

[0403] Figure 13D An MQW is shown where quantum dots (QDs) create non-uniformities in the MQW. The QDs may be provided on or in a QB or QW layer, such as in the gaps in a QW structure.

[0404] Figure 13E An MQW with well width fluctuation is shown, where the thickness of the QW layer is not uniform across the light emitting area. QWs can have different widths from one another, and can also have varying widths within a single QW.

[0405] Figure 13F An MQW showing fluctuating alloy compositions in the light-emitting region. The compositions of the QB and QW vary from layer to layer. Specifically, the indium (In)% composition varies within the same QW, with QW2 varying between 10-12%, 10-15%, 10-25%, and 10-35%.

[0406] Figure 13GMQWs with different combinations of MQWs and underlayers are shown. Different QWs have different In% compositions. For example, QW1 has 15% In%, QW2 has 25% In%, and QW3 has 30% In%. In an embodiment of the present invention, lower-In% QWs are preferably located at the bottom of the MQW due to strain and thermal effects, while higher-In% QWs are preferably located at the top. In a preferred embodiment, for example, QW1 is a blue-emitting QW, QW2 is a green-emitting QW, and QW3 is a red-emitting QW.

[0407] Figure 14A This is a cross-sectional TEM image of a conventional non-variable wavelength LED. In this non-variable wavelength LED, the MQWs at the upper and lower interfaces are uniform and smooth (five MQWs are shown here).

[0408] Figure 14B and Figure 14C This is a TEM image of a variable-wavelength LED containing a V-shaped pit, which can be used in embodiments of the present invention. In this variable-wavelength LED, the MQW is non-uniform. This non-uniformity can be caused by a variety of methods. One example is the V-pit and semi-polar surface, which incorporate more indium and thinner QWs. Figure 14B Another example is also shown in FIG. 1 , that is, the MQW is non-uniform in terms of broken QWs, discontinuous QWs, fragmented QWs, QWs with well width or composition fluctuations.

[0409] Figure 14C show Figure 14B A cross section of a variable wavelength LED is shown, showing a porous region and a light emitting region comprising a plurality of V-shaped pits that can be used in a preferred embodiment of the present invention.

[0410] In this structure, the light emitting region contains intentionally introduced multiple emission wavelength regions, such as multiple types of QW regions with V-shaped pits extending across the light emitting region.

[0411] A V-shaped pit (V-pit) is actually a hexagonal pit when viewed from above, with the V-shape observed in cross-section. During the growth of InGaN, GaN, InGaN / InGaN superlattice, or InGaN / GaN superlattice structures beneath MQWs, V-pits initiate at each dislocation position under specialized epitaxial growth conditions, such as low growth temperature (e.g., <1000°C, <900°C, <800°C, or <700°C) and nitrogen atmosphere.

[0412] Figure 15A This is a graph of the peak emission wavelength versus driving current density for a conventional non-variable wavelength LED. By varying the driving current density applied to the LED, the emission wavelength varies slightly within an emission wavelength range of approximately 15 nm.

[0413] Figure 15B This graph plots the peak emission wavelength versus drive current density for a variable wavelength LED that can be used as the first or second semiconductor device in embodiments of the present invention. In a variable wavelength LED, varying the current density of the driver can significantly alter the peak emission wavelength (WLP) of the LED. In this embodiment, the peak emission wavelength (WLP) of the LED is significantly altered between approximately 0.1 and 100 A / cm2. 2 Changing the driving current density between the two causes the peak emission wavelength to change from about 635 nm to about 550 nm - the emission wavelength range is about 85 nm.

[0414] Figure 15C FIG2 is a graph of peak emission wavelength versus drive current density for a variable wavelength LED according to another embodiment of the present invention. In this embodiment, varying the drive current density shifts the peak emission wavelength from approximately 720 nm to approximately 580 nm, with an emission wavelength range of approximately 140 nm.

[0415] Figure 16A FIG. 1 is a graph of peak emission wavelength versus driving current density for another variable wavelength LED according to the present invention. In this embodiment, at about 0.1 and 200 A / cm 2 Changing the drive current density shifts the peak emission wavelength from 615 nm to 508 nm—a wavelength range of approximately 100 nm. Due to limited testing capabilities, the data in this figure only extends to 514.5 nm. Therefore, the current density at 508 nm is an estimate. However, the achievable emission wavelength range can be significantly expanded.

[0416] Figure 16B -D is Figure 16A A photo of a variable-wavelength LED shows the same variable-wavelength LED emitting four different wavelengths within its emission wavelength range. The inset emission spectrum shows the different peak emission wavelengths at different drive current densities. This shows the same variable-wavelength LED emitting peak emission wavelengths of orange (615nm), yellow (556nm), green (534nm), and blue (508nm) in response to different drive current densities.

Claims

1. A method for manufacturing a photovoltaic device, comprising the following steps: providing a device wafer comprising an optoelectronic device epitaxial structure on a substrate wafer, the device epitaxial structure comprising a porous region of a Group III nitride material; etching the device epitaxial structure into a plurality of device platforms; depositing a liner dielectric layer over the plurality of device platforms; forming a plurality of metal vias extending through the pad dielectric layer to respective device platforms; and The device wafer is bonded to a driver wafer including driver circuitry such that the driver circuitry is operably coupled to the plurality of device platforms through the metal vias. 2 . The method of claim 1 , wherein the device wafer is bonded to the driver wafer such that each metal via is electrically coupled to its own CMOS driver in the driver circuit.

3. The method according to claim 1 or 2, comprising the step of depositing a dielectric fill material over the plurality of device platforms after the liner dielectric layer has been deposited to provide a planar upper surface on the device wafer; wherein the metal vias extend from the planar upper surface through the dielectric fill material and the liner dielectric layer to the respective device platforms, and wherein the planar upper surface of the device wafer is bonded to the driver wafer. The method of claim 3 , comprising the step of depositing the dielectric fill material directly over the liner dielectric layer.

5. The method according to claim 3 or 4, wherein the step of forming the metal vias comprises etching a plurality of channels from the planar upper surface of the wafer through the dielectric filling material and the pad dielectric layer to the device platform, and then depositing metal in the plurality of channels to form metal vias. 6 . The method according to claim 1 , further comprising the step of depositing a reflective layer over the plurality of device platforms after the step of depositing the liner dielectric layer over the plurality of device platforms, preferably wherein the reflective layer is a metal layer.

7. The method of claim 6, wherein the reflective layer is formed by depositing metal over the pad dielectric layer to fill the trenches between the device mesas, and including the step of planarizing the metal to be flush with the pad dielectric layer extending over the top of the device mesas.

8. The method of claim 6, comprising the steps of depositing a reflective layer, then depositing a metal fill material over the reflective layer, and planarizing the metal fill material to be flush with a pad dielectric layer extending over the device platform before depositing the dielectric fill material.

9. The method of any one of claims 6 to 8, comprising the step of etching a plurality of openings through the liner dielectric layer above the plurality of device mesas before depositing the reflective layer.

10. The method of claim 9, including the step of depositing a metal pad over each of the openings in the liner dielectric layer, the metal pad forming an electrical contact for each of the device platforms.

11. The method of claim 10 , comprising the step of depositing a dielectric fill material over the plurality of device platforms to provide a planar upper surface on the device wafer after the metal pads have been deposited; wherein the metal vias extend from the planar upper surface through the dielectric fill material to respective metal pads, and wherein the planar upper surface of the device wafer is bonded to the driver wafer.

12. The method according to claim 11, wherein the step of forming the metal vias comprises etching a plurality of vias from the planar upper surface of the wafer through the dielectric filling material to the metal pads, and then depositing metal in the plurality of vias to form metal vias.

13. The method according to any one of the preceding claims, wherein the step of etching the device epitaxial structure into a plurality of device mesas comprises: performing isolation etching, wherein isolation trenches are etched through the entire depth of the device epitaxial structure to electrically isolate device mesas on opposite sides of the isolation trenches.

14. The method of claim 13, comprising the step of forming one or more metal vias in the isolation trench. 15 . The method of claim 13 , wherein the isolation trench metal via extends from the planar wafer surface, through the dielectric filling material and the liner dielectric layer, to the substrate wafer. 16 . The method of claim 13 , wherein the isolation trench metal via extends from the planar wafer surface, through the dielectric filling material, to a metal pad in the isolation trench.

17. The method of any one of the preceding claims, wherein etching the device epitaxial structure into a plurality of device mesas comprises performing a mesa etch wherein a mesa trench is etched through a partial depth of the device epitaxial structure, the mesa trench not extending through at least one conductive layer of the device wafer such that device mesas on either side of the mesa trench are not electrically isolated from each other.

18. The method of claim 17, comprising the step of forming one or more metal vias in the mesa trench.

19. The method of claim 17 or 18, comprising the step of etching one or more openings through the pad dielectric region in the mesa trench to expose layers in the device epitaxial structure below the pad dielectric layer.

20. The method of claim 17, 18, or 19, wherein the mesa trench metal via extends from the planar wafer surface, through the dielectric fill material and the liner dielectric layer, to a layer in a device epitaxial structure underlying the mesa trench.

21. The method according to any one of the preceding claims, comprising the step of depositing a plurality of metal pads over the metal vias for routing and bonding to the driver wafer.

22. The method of any preceding claim, wherein the method comprises the step of removing the substrate wafer to form the light emitting side of the device after bonding the device wafer to the driver wafer.

23. The method according to claim 22, comprising the step of etching an opening through the liner dielectric layer to the isolation trench after removing the substrate wafer to expose metal in the isolation trench, wherein the exposed metal in the isolation trench forms a metal pad for wire bonding.

24. The method of claim 22, comprising the step of depositing metal pads over the isolation trenches after removing the substrate wafer, the metal pads being electrically connected to one or more metal vias extending through the device to the driver wafer.

25. A method according to any one of claims 22, 23 or 24, comprising the step of depositing one or more microlenses on some or all of the device platforms on the light emitting side of the device.

26. The method of any preceding claim, wherein the device epitaxial structure is an LED structure, such that each device platform is an LED, preferably a sub-millimeter-scale LED, micrometer-scale LED or nanometer-scale LED structure.

27. The method of any preceding claim, wherein the device wafer comprises a porous region of Ill-nitride material between the device epitaxial structure and the substrate wafer.

28. The method of any preceding claim, wherein the device wafer comprises porous regions of Group Ill-nitride material in the device epitaxial structure.

29. A photovoltaic device comprising: a driver wafer comprising a driver circuit; a plurality of optoelectronic device platforms, each device platform configured to emit light from a light emitting side of the device in response to a drive current from the drive circuit; a porous region of Group III-nitride material epitaxially connected to one or more of the device platforms; and a pad dielectric layer located between the driver wafer and the device platform; Each optoelectronic device platform is operatively coupled to the driver circuit via a plurality of metal vias extending through the liner dielectric layer.

30. The optoelectronic device of claim 29, comprising a dielectric fill material between the driver wafer and the pad dielectric layer; wherein the metal via extends through the dielectric fill material and the pad dielectric layer.

31. The optoelectronic device of claim 29 or 30, wherein each device platform has the same device epitaxial structure.

32. The optoelectronic device of claim 29, 30, or 31, wherein the device epitaxial structure comprises an n-doped region, a p-doped region, and a light emitting region disposed between the n-doped region and the p-doped region.

33. An optoelectronic device according to any one of claims 29 to 32, wherein each device platform is electrically coupled to its own CMOS driver in the drive circuit such that each device platform can be independently driven by the drive circuit.

34. The optoelectronic device of any one of claims 29 to 33, wherein different device platforms have different lateral dimensions, such that different device platforms have light emitting areas of different sizes.

35. The optoelectronic device of any one of claims 29 to 34, wherein the device comprises two or more device platforms electrically connected to each other via a common conductive layer of semiconductor material.

36. The optoelectronic device of claim 35, wherein electrically connected device platforms are separated by platform barriers located between the device platforms, wherein the platform barriers do not extend through the common conductive layer.

37. An optoelectronic device according to claim 35 or 36, wherein the common conductive layer is an n-type layer or a p-type layer forming part of the device epitaxial structure, a doped connection layer connected to multiple device platforms, or a porous layer of semiconductor material connected to multiple device platforms.

38. The optoelectronic device according to claim 35, 36 or 37, wherein the mesa barrier is formed by a dielectric filling material covered by the liner dielectric layer.

39. The optoelectronic device according to claim 35, 36 or 37, wherein the mesa barrier is formed of metal covered by the liner dielectric layer.

40. The optoelectronic device of any one of claims 29 to 39, wherein the device comprises two or more device platforms that are electrically isolated from each other.

41. The optoelectronic device of claim 40, wherein the electrically isolated device platforms are separated by electrically insulating isolation barriers.

42. The optoelectronic device according to claim 41, wherein the isolation barrier is formed of a dielectric filling material covered by the liner dielectric layer.

43. The optoelectronic device of claim 41, wherein the isolation barrier is formed by a metal pad surrounded by the liner dielectric layer.

44. The optoelectronic device of any one of claims 29 to 39, wherein the device comprises a reflective layer adjacent to the pad dielectric layer, the reflective layer being located between the pad dielectric layer and the driver wafer.

45. The optoelectronic device of claim 41, wherein the reflective layer surrounds sidewalls of the device platform to form a sidewall reflective structure configured to reflect emitted light toward a light emitting side of the device.

46. ​​The optoelectronic device of any one of claims 29 to 45, wherein the device comprises a plurality of microlenses arranged on a light emitting side of the device, each microlens positioned above a respective device platform and configured to transmit light emitted by an underlying optoelectronic device platform.

47. An optoelectronic device according to any one of claims 29 to 46, wherein the device comprises one or more metal pads on a light emitting side of the device, each metal pad being electrically connected to the drive circuit via one or more metal vias.

48. The optoelectronic device of any one of claims 29 to 47, wherein the device is a display device, and wherein each device platform is preferably a sub-millimeter-scale LED, a micrometer-scale LED, or a nanometer-scale LED.

49. An optoelectronic device according to any one of claims 29 to 48, wherein some or all of the device platforms are variable wavelength LEDs, which are configured to emit a variable peak emission wavelength in response to changes in the drive current provided to the LEDs, wherein by changing the drive current provided to the LEDs, the peak emission wavelength of the LEDs can be continuously controlled over an emission wavelength range of at least 40 nm.

50. The optoelectronic device of claim 49, wherein the peak emission wavelength is variable within an emission wavelength range of at least 50 nm, or at least 60 nm, or at least 70 nm, or at least 80 nm, preferably up to 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 180 nm, or 200 nm, or 400 nm, or 450 nm, by varying the drive current.

51. The optoelectronic device of claim 49 or 50, wherein the drive circuit is configured to provide a variable amount of drive current to the variable wavelength LED device platform to change the peak emission wavelength of the variable wavelength LED device platform.

52. The optoelectronic device of any one of claims 29 to 48, wherein the device comprises a monolithic array of LED device platforms, wherein each device platform is an LED sub-pixel, and wherein groups of LED device platforms form device pixels.

53. An optoelectronic device according to any one of claims 29 to 48, comprising one or more porous regions of a Group III nitride material.

54. The optoelectronic device of claim 53, wherein each device platform comprises its own porous region of Group III nitride material, or wherein common porous regions are epitaxially connected to multiple device platforms.

55. The optoelectronic device of claim 53 or 54, wherein the device comprises a porous region of Group Ill-nitride material located above the device platform, between some or all of the device platform and the light emitting surface of the device.

56. An optoelectronic device according to claim 53, 54 or 55, wherein the device wafer includes a distributed Bragg reflector (DBR) located above the device platform so that the device platform is arranged between the DBR and the light emitting surface of the device, the DBR including multiple porous layers of a group III nitride material, and the DBR is configured to act as a filter that transmits light of a first emission wavelength and reflects other emission wavelengths.

57. An optoelectronic device according to claim 53, 54, 55 or 56, wherein the porous region is configured to act as an anti-reflective layer on the light emitting side of the device.

58. The optoelectronic device of claim 53 or 54, wherein the device comprises a porous region of Group Ill-nitride material between some or all of the device platform and the driver wafer.

59. An optoelectronic device according to claim 58, wherein the device includes a distributed Bragg reflector (DBR) located between the device platform and the driver wafer, the DBR comprising multiple porous layers of a group III nitride material, and the DBR is configured to reflect emitted light out of the light emitting side of the device.

60. An optoelectronic device according to any one of claims 53 to 59, wherein the or each porous region in the device has the same thickness and porosity.

61. The optoelectronic device of any one of claims 53 to 59, wherein the device comprises multiple porous regions having different thicknesses and / or porosities, such that different device platforms are aligned with different porous regions.

62. The optoelectronic device of claim 61, wherein the porosity characteristics of the porous region vary at different lateral locations on the device.

63. The optoelectronic device of claim 62, wherein a first porous region has a first thickness and a second porous region in a separate lateral location in the device has a second thickness different from the first thickness.

64. The optoelectronic device of claim 62 or 63, wherein the device comprises a multi-region filter comprising a plurality of porous regions of varying thickness, respective porous regions of varying thickness being located above different device platforms.

65. An optoelectronic device according to any one of claims 53 to 64, wherein the porous region comprises a stack of porous layers of Group III nitride material, and optionally one or more non-porous layers of Group III nitride material between the porous layers of Group III nitride material.

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