Processing method for inertial MEMS device and wafer level packaging method
By combining bulk processing and surface processing techniques, the processing method of inertial MEMS devices is optimized, which solves the contradiction between volume and integration of inertial MEMS devices, achieves a balance between thickness and planar size of sensitive structures, and improves device performance.
Patent Information
- Application Number
- CN202510608326.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-09-16
AI Technical Summary
Existing inertial MEMS devices have a contradiction in terms of volume and integration. It is difficult to achieve a structure with small planar size and large thickness at the same time, which affects the device performance.
By combining bulk processing and surface processing techniques, silicon oxide and polysilicon are deposited on an SOI substrate, patterned and bonded, achieving a balance between the thickness and planar dimensions of the sensitive structure. Deep silicon etching and grinding and polishing techniques are used to optimize the process.
The thickness of the sensitive structure layer can reach more than 60 microns and the anchor point width can reach 10 microns, which improves the capacitance and structural quality of the device and enhances the device performance.
Smart Images
Figure CN120646757A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of inertial measurement technology, and in particular to a processing method for inertial MEMS devices and a wafer-level packaging method. Background Art
[0002] Inertial MEMS devices are manufactured using MEMS methods and are capable of measuring inertial physical quantities such as the angular velocity and acceleration of an object. They offer advantages such as small size, low cost, and low power consumption, and are widely used in defense, inertial navigation, industrial control, and other fields. Inertial MEMS devices primarily include MEMS gyroscopes and MEMS accelerometers.
[0003] Typically, the core of an inertial MEMS device is a silicon sensitive structure. There are many processing options, which can generally be divided into two categories: bulk processing and surface processing. Surface processing is similar to semiconductor processing, where insulating layers, leads, and sensitive structures are grown layer by layer on a silicon substrate. Its advantage is a small processing line width, but its disadvantage is that the thickness of the sensitive structure is constrained by factors such as process stress and is difficult to increase. Therefore, this process is primarily suitable for products with lower precision but higher volume and integration, such as monolithic three-axis gyroscopes and monolithic six-axis gyroscopes plus a meter. The biggest difference between bulk processing and surface processing is that the sensitive structure is fixed to the silicon substrate through a bonding process, allowing for a larger structure thickness. However, due to the requirements of the bonding process itself, the planar dimensions of the bonding anchor points are relatively large, restricting the overall size of the product. Therefore, this process is primarily suitable for products with higher precision, such as high-precision gyroscopes and high-precision accelerometers. Summary of the Invention
[0004] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.
[0005] To this end, the present invention provides a processing method and wafer-level packaging method for inertial MEMS devices. This method combines the advantages of both bulk and surface processing techniques, enabling small planar dimensions and large thickness dimensions, achieving a balance between volume, integration, and performance.
[0006] The technical solutions of the present invention are as follows:
[0007] According to one aspect, a method for processing an inertial MEMS device is provided, the method comprising:
[0008] Step 1: depositing a layer of silicon oxide on the surface of an SOI substrate, wherein the SOI substrate sequentially comprises a device layer, an insulating layer, and a substrate layer, the silicon oxide being deposited on the device layer, and the device layer being used to fabricate a sensitive structure of a MEMS device;
[0009] Step 2: patterning the silicon oxide to produce an anchor point pattern;
[0010] Step 3, depositing a layer of polysilicon on the silicon oxide layer;
[0011] Step 4: patterning the polysilicon layer obtained in step 3 to produce interconnection leads;
[0012] Step 5: depositing an insulating sacrificial layer on the multi-layer silicon layer;
[0013] Step 6: Bond a new silicon wafer to the surface of the sacrificial layer. The silicon wafer is used as the substrate of the MEMS device.
[0014] Step 7: removing the substrate layer and the insulating layer of the SOI wafer;
[0015] Step 8: Patterning the SOI wafer device layer to produce sensitive structure patterns;
[0016] Step 9: Remove the sacrificial layer to release the structure;
[0017] Step 10: Make a pad on the polysilicon layer.
[0018] Furthermore, in step 3, the polysilicon is also subjected to grinding and polishing.
[0019] Furthermore, in step 5, the surface of the sacrificial layer is made flat and smooth by grinding and polishing technology.
[0020] Furthermore, in step 8, the SOI wafer device layer is patterned using deep silicon etching technology.
[0021] Furthermore, in step 4, the lead includes a single layer of lead or multiple layers of lead, wherein, in the case of multiple layers of lead, the multiple layers of lead are realized by alternate deposition or etching.
[0022] Furthermore, when the thickness of the sensitive structure layer is greater than 200 microns, the SOI substrate can be replaced with an ordinary silicon wafer, and the method accordingly does not include step 7.
[0023] According to another aspect, a method for wafer-level packaging of an inertial MEMS device is provided, the method comprising:
[0024] Step 1: depositing a layer of silicon oxide on the surface of an SOI substrate, wherein the SOI substrate sequentially comprises a device layer, an insulating layer, and a substrate layer, the silicon oxide being deposited on the device layer, and the device layer being used to fabricate a sensitive structure of a MEMS device;
[0025] Step 2: patterning the silicon oxide to produce an anchor point pattern;
[0026] Step 3, depositing a layer of polysilicon on the silicon oxide layer;
[0027] Step 4: patterning the polysilicon layer obtained in step 3 to produce interconnection leads;
[0028] Step 5: depositing an insulating sacrificial layer on the multi-layer silicon layer;
[0029] Step 6: Bond a new silicon wafer to the surface of the sacrificial layer. The silicon wafer is used as the substrate of the MEMS device.
[0030] Step 7: removing the substrate layer and the insulating layer of the SOI wafer;
[0031] Step 8: Patterning the SOI wafer device layer to produce sensitive structure patterns;
[0032] Step 9: Remove the sacrificial layer to release the structure;
[0033] Step 10: Making a pad on the polysilicon layer;
[0034] Step 11: Bond the silicon capping layer to the sensitive structure layer obtained in step 8.
[0035] Furthermore, a cavity is processed in the silicon capping layer to provide space for the movement of the sensitive structure.
[0036] Furthermore, in step 10, the silicon capping layer is bonded to the sensitive structure layer obtained in step 8 by direct bonding or eutectic bonding.
[0037] By applying the above-mentioned technical solution, the processing of the sensitive structure and leads of the present invention is primarily achieved through surface machining processes, resulting in small planar dimensions and high machining precision. Furthermore, the thickness of the sensitive structure is not limited by the surface machining process, thereby achieving greater capacitance and structural quality, which is beneficial for improving device performance. By adopting the present solution, the thickness of the sensitive structure layer can reach over 60 microns, while the main process still uses surface machining. The size of various structures, such as the anchor points, can be very small. The anchor point width of the present solution can be as small as 10 microns, while the anchor point width of bulk machining processes is generally no less than 50 microns. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings are included to provide a further understanding of the embodiments of the present invention, constitute a part of the specification, illustrate the embodiments of the present invention, and together with the description, explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0039] Figure 1It is a cross-sectional diagram of a typical surface processing process.
[0040] Among them, 1 is a silicon substrate layer; 11 is an insulating layer; 12 is polysilicon; 13 is a sacrificial layer; 14 is a silicon sensitive structure layer; 15 is a sensitive structure pattern; and 16 is a pad.
[0041] Figure 2 It is a cross-sectional schematic diagram of the processing process of the present invention.
[0042] Among them, 2 is the SOI substrate; 21 is the silicon oxide layer; 22 is the device layer; 23 is the insulating layer; 24 is the substrate layer; 25 is the polysilicon layer; 26 is the sacrificial layer; 27 is the silicon substrate layer; 28 is the sensitive structure pattern; and 29 is the pad.
[0043] Figure 3 This is a schematic diagram of a wafer-level packaging solution proposed by the present invention.
[0044] Among them, 22 is the device layer; 27 is the silicon substrate layer; 29 is the pad; 31 is the silicon capping layer; 32 is the silicon chamber; and 33 is the solder. DETAILED DESCRIPTION
[0045] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0046] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0047] Unless otherwise specifically stated, the relative arrangement of the parts and steps, the numerical expressions and the numerical values set forth in these embodiments do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific values should be interpreted as being merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.
[0048] Typical surface processing process flow Figure 1 As shown, the structural layer of this scheme is processed through a growth process, the stress is relatively large, and the thickness is constrained, generally not exceeding 25 microns.
[0049] The embodiment of the present invention optimizes some process steps of a typical surface processing process, so that a structural layer can be processed on a silicon substrate through a bonding process, thereby obtaining a greater structural thickness.
[0050] like Figure 2 In one embodiment of the present invention, a processing method for an inertial MEMS device is provided, the processing method comprising:
[0051] Step 1: deposit a layer of silicon oxide on the surface of the SOI substrate 2 to obtain a silicon oxide layer 21. The SOI substrate 2 comprises a device layer 22, an insulating layer 23 and a substrate layer 24. The device layer 22 is used to make the sensitive structure of the MEMS device.
[0052] In this step, the thickness of the device layer 22 can be selected according to needs, and can generally be 60 μm thick;
[0053] Step 2: Patterning the surface silicon oxide layer 21 to produce an anchor point pattern;
[0054] Step 3: depositing a layer of polysilicon and performing grinding and polishing to obtain a polysilicon layer 25;
[0055] Step 4: patterning the polysilicon layer 25 to form interconnection leads;
[0056] Step 5: depositing an insulating sacrificial layer 26, and making the surface of the sacrificial layer 26 smooth by grinding and polishing technology;
[0057] Step 6: Bond a new silicon wafer to the sacrificial layer. This silicon wafer is used for the silicon substrate layer 27 of the MEMS device.
[0058] Step 7: removing the substrate layer 24 and the insulating layer 23 of the SOI substrate 2;
[0059] Step 1: patterning the device layer 22 of the SOI substrate 2 using deep silicon etching technology to produce a sensitive structure pattern 28;
[0060] Step 9: The sacrificial layer 26 is removed to release the structure;
[0061] Step 10: Making the soldering pad 29.
[0062] By adopting this solution, the thickness of the sensitive structure layer is not restricted by the stress of the growth process and can reach more than 60 microns. At the same time, the main process still uses surface processing technology, and the size of each structure such as the anchor point can be made very small. For example, the anchor point width of this solution can be 10 microns, while the anchor point width of the bulk processing process is generally not less than 50 microns.
[0063] By applying the above technical solution, the processing of the sensitive structure and leads of the present invention is mainly achieved by surface processing technology, with small planar dimensions and high processing accuracy; at the same time, the thickness of the sensitive structure is not limited by the surface processing technology, so that a larger capacitance and structural quality can be obtained, which is beneficial to improving device performance.
[0064] According to one embodiment of the present invention, the SOI substrate 2 in step 1 can be replaced with a common silicon wafer, especially when the thickness of the sensitive structure layer 22 is relatively large, such as greater than 200 microns. It should be understood by those skilled in the art that when the SOI substrate 2 is replaced with a common silicon wafer, the method naturally does not include step 7.
[0065] In addition, the grinding and polishing treatments in steps 3 and 5 are mainly used to improve the flatness of the substrate surface to facilitate subsequent processes such as photolithography and bonding, and are not necessary steps.
[0066] In the above embodiment, the leads in step 4 of the solution are not limited to a single layer of leads, and multiple layers of leads can be achieved by alternately depositing and etching.
[0067] In addition, the technical solution adopted by the present invention is also applicable to wafer-level packaging solutions, such as Figure 3 As shown, this solution comprises a three-layer structure: a silicon capping layer 31, a silicon sensitive structure layer 22, and a silicon substrate layer 27. Compared to the previous solution, the silicon capping layer 31 is added. Because the silicon sensitive structure layer 22 is placed between the other two layers, it provides better protection. This solution also enables wafer-level vacuum packaging or hermetic packaging, making it particularly suitable for MEMS devices such as microelectromechanical gyroscopes, microaccelerometers, and pressure sensors.
[0068] Silicon capping layer 31 is machined with silicon cavities 32 to provide space for the sensitive structure to move. Silicon capping layer 31 and sensitive structure layer 22 can be bonded together through direct bonding or eutectic bonding. If eutectic bonding is used, eutectic solder 33 must be processed. This solution is also suitable for multi-cavity wafer-level packaging, allowing the integration of MEMS chips such as microelectromechanical gyroscopes and microaccelerometers.
[0069] The technical solution of the present invention is also applicable to other wafer-level packaging solutions, for example, bonding the silicon capping layer 31 to the silicon substrate layer 27 instead of the sensitive structure layer 22 .
[0070] Features described and / or illustrated above for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with or used in place of features in other embodiments.
[0071] It should be emphasized that the term "include / comprises" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or combinations thereof.
[0072] The above methods of the present invention can be implemented by hardware, or by a combination of hardware and software. The present invention relates to a computer-readable program that, when executed by a logic component, enables the logic component to implement the apparatus or components described above, or to implement the various methods or steps described above. The present invention also relates to a storage medium for storing the above program, such as a hard disk, magnetic disk, optical disk, DVD, flash memory, etc.
[0073] The many features and advantages of these embodiments are apparent from this detailed description, and thus, the appended claims are intended to cover all such features and advantages of these embodiments that fall within the true spirit and scope thereof. Furthermore, since numerous modifications and changes will readily occur to those skilled in the art, it is not intended that the embodiments of the invention be limited to the exact construction and operation illustrated and described, but rather that all suitable modifications and equivalents be covered within the scope thereof.
[0074] Parts of the present invention that are not described in detail are well known to those skilled in the art.
Claims
1. A processing method for an inertial MEMS device, characterized in that: The processing method comprises: Step 1: depositing a layer of silicon oxide on the surface of an SOI substrate, wherein the SOI substrate sequentially comprises a device layer, an insulating layer, and a substrate layer, the silicon oxide being deposited on the device layer, and the device layer being used to fabricate a sensitive structure of a MEMS device; Step 2: patterning the silicon oxide to produce an anchor point pattern; Step 3, depositing a layer of polysilicon on the silicon oxide layer; Step 4: patterning the polysilicon layer obtained in step 3 to produce interconnection leads; Step 5: depositing an insulating sacrificial layer on the multi-layer silicon layer; Step 6: Bond a new silicon wafer to the surface of the sacrificial layer. The silicon wafer is used as the substrate of the MEMS device. Step 7: removing the substrate layer and the insulating layer of the SOI wafer; Step 8: Patterning the SOI wafer device layer to produce sensitive structure patterns; Step 9: Remove the sacrificial layer to release the structure; Step 10: Make a pad on the polysilicon layer.
2. A processing method for an inertial MEMS device according to claim 1, characterized in that: In the step 3, the polysilicon is further subjected to grinding and polishing.
3. The processing method for an inertial MEMS device according to claim 1, characterized in that: In step 5, the surface of the sacrificial layer is made flat and smooth by grinding and polishing technology.
4. A processing method for an inertial MEMS device according to any one of claims 1 to 3, characterized in that: In step 8, the SOI device layer is patterned using deep silicon etching technology.
5. A processing method for an inertial MEMS device according to any one of claims 1 to 4, characterized in that: In step 4, the lead includes a single layer of lead or multiple layers of lead, wherein, in the case of multiple layers of lead, the multiple layers of lead are realized by alternate deposition or etching.
6. The processing method for an inertial MEMS device according to claim 1, characterized in that: When the thickness of the sensitive structure layer is greater than 200 microns, the SOI substrate can be replaced with an ordinary silicon wafer, and the method accordingly does not include step 7.
7. A method for wafer-level packaging of inertial MEMS devices, characterized in that: The method comprises: Step 1: depositing a layer of silicon oxide on the surface of an SOI substrate, wherein the SOI substrate sequentially comprises a device layer, an insulating layer, and a substrate layer, the silicon oxide being deposited on the device layer, and the device layer being used to fabricate a sensitive structure of a MEMS device; Step 2: patterning the silicon oxide to produce an anchor point pattern; Step 3, depositing a layer of polysilicon on the silicon oxide layer; Step 4: patterning the polysilicon layer obtained in step 3 to produce interconnection leads; Step 5: depositing an insulating sacrificial layer on the multi-layer silicon layer; Step 6: Bond a new silicon wafer to the surface of the sacrificial layer. The silicon wafer is used as the substrate of the MEMS device. Step 7: removing the substrate layer and the insulating layer of the SOI wafer; Step 8: Patterning the SOI wafer device layer to produce sensitive structure patterns; Step 9: Remove the sacrificial layer to release the structure; Step 10: Making a pad on the polysilicon layer; Step 11: Bond the silicon capping layer to the sensitive structure layer obtained in step 8.
8. The wafer-level packaging method for inertial MEMS devices according to claim 7, characterized in that: A cavity is processed in the silicon capping layer to provide space for the movement of sensitive structures.
9. The wafer-level packaging method for inertial MEMS devices according to claim 7, characterized in that: In step 10, the silicon capping layer is bonded to the sensitive structure layer obtained in step 8 by direct bonding or eutectic bonding.