A high-precision comparison method for transistor on-resistance

Abstract

This invention belongs to the field of power electronics and semiconductor device technology, and proposes a high-precision comparison method for transistor on-resistance. The method includes: generating and outputting a DC voltage capable of rapid adjustment and load-bearing capacity via a DC voltage adjustment module; generating and outputting a rapidly adjustable pulse signal based on the DC voltage and a pulse voltage via a gate drive module; applying the pulse signal to the transistor under test (TUT) via a power module and measuring the TUT's on-resistance under the gate drive voltage; switching the gate drive voltage within a delay on the order of microseconds to nanoseconds, and measuring the TUT's on-resistance under the switched gate drive voltage based on the pulse signal. This method can test the on-resistance of TUTs under different gate drive voltages in a pulse circuit, reducing the measurement delay from several minutes in traditional dual-pulse circuits to several nanoseconds, effectively improving the performance of transistor reliability evaluation circuits.

Description

Technical Field

[0001] This invention relates to the field of power electronics and semiconductor device technology, and in particular to a high-precision comparison method for transistor on-resistance. Background Technology

[0002] The semiconductor field has developed rapidly in recent years, with various new materials and structures emerging from traditional silicon (Si)-based field-effect transistors (MOSFETs), improving transistor characteristics in certain key areas. For example, materials such as gallium nitride (GaN), silicon carbide (SiC), gallium oxide (Ga2O3), and aluminum nitride (AlN) possess higher electron mobility and wider band gaps, resulting in transistors with higher switching frequencies and excellent high-voltage withstand capabilities. The "p-type GaN gate high electron mobility transistor structure," "Schottky-ohm hybrid gate structure," and "p-FET junction high electron mobility transistor structure" have further enhanced transistor performance, and these achievements are gradually moving from laboratory scientific research to practical applications in society.

[0003] Before transistors made from various novel materials and with novel structures can be mass-produced, they still need to undergo "reliability characterization" to verify their ability to operate normally under various working environments. Based on the different stages from transistor fabrication to application, reliability characterization can be divided into "wafer-level reliability characterization," "device-level reliability characterization," and "circuit-level reliability characterization." As the names suggest, these represent quality assessments during wafer fabrication, quality assessments after the transistor structure is fabricated, and quality assessments under actual application in circuits (with certain voltage and current stresses), respectively. Among these, the test conditions for circuit-level reliability characterization are closest to the real-world application scenarios of transistors, and its data have significant reference value.

[0004] The dual-pulse circuit is a commonly used circuit in "circuit-level reliability characterization." It consists of a high-voltage power supply, a stabilizing capacitor, a power inductor, a freewheeling diode, and the transistor under test (TUT). Dual-pulse testing is performed by applying a dual-pulse waveform to the gate of the TUT. It can test the switching characteristics and on-resistance of the TUT under specific gate drive voltage, drain voltage stress, and load current. Experiments have shown that when comparing the on-resistance of transistors under different drive conditions (gate drive voltage), the traditional dual-pulse circuit struggles to adjust the drive voltage quickly enough, resulting in long delays between test data sets and low reliability of the comparative data. Summary of the Invention

[0005] Therefore, one object of the present invention is to propose a high-precision comparison method for transistor on-resistance to solve the problems mentioned in the background art and overcome the shortcomings of the prior art.

[0006] To achieve the above objectives, the present invention provides a high-precision comparison method for transistor on-resistance, comprising:

[0007] The DC voltage adjustment module generates and outputs a DC voltage that can be quickly adjusted and has load-carrying capacity. ;

[0008] The gate drive module is based on the DC voltage and pulse voltage Generates and outputs pulse signals with rapidly adjustable voltage. ;

[0009] A pulse signal is applied to the transistor under test via the power module. And based on the pulse signal Measure the on-resistance of the transistor under test at the gate drive voltage;

[0010] Switching the gate drive voltage within a delay on the order of microseconds to nanoseconds, based on the pulse signal. The on-resistance of the transistor under test is measured under different gate drive voltages, enabling high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages.

[0011] Preferably, the DC voltage adjustment module includes a digital-to-analog converter chip and an operational amplifier, wherein the digital-to-analog converter chip and the operational amplifier are connected via DC voltage. Power supply is provided, the output terminal of the digital-to-analog converter chip is connected to the operational amplifier, and the output terminal of the operational amplifier is connected to the gate drive module.

[0012] Preferably, the gate driving module includes a first CMOS inverter and a second CMOS inverter. The output terminal of the operational amplifier is connected to the power supply pins of the first CMOS inverter and the second CMOS inverter, and the input pin of the first CMOS inverter is connected to a pulse voltage. The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter. The ground pins of the first CMOS inverter and the second CMOS inverter are both grounded. The output pin of the second CMOS inverter is connected to the power module.

[0013] Preferably, the power module includes a freewheeling diode and a power inductor. The gate of the transistor under test is connected to the output pin of the second CMOS inverter. The drain of the transistor under test is connected to the anode of the freewheeling diode and one end of the power inductor. The cathode of the freewheeling diode and the other end of the power inductor are connected to the anode of the high-voltage power supply. The source of the transistor under test and the cathode of the high-voltage power supply are grounded. A voltage-regulating capacitor is connected in parallel with the high-voltage power supply.

[0014] Preferably, the digital-to-analog converter chip of the DC voltage adjustment module is controlled by a digital signal to generate and output a high-speed adjustable DC voltage. Subsequently, the operational amplifier operates in voltage follower mode, converting the DC signal output by the digital-to-analog converter chip into a DC voltage capable of driving a load. .

[0015] Preferably, the first CMOS inverter and the second CMOS inverter of the gate driving module form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module... Power supply, via pulse voltage Controls the on / off switching of the gate drive module voltage output; adjustable DC voltage. and pulse voltage The pulse signal that controls the output voltage of the gate drive module to be adjusted rapidly. .

[0016] Preferably, the switching gate drive voltage is based on the pulse signal. Measuring the on-resistance of a transistor under switching gate drive voltages, and achieving a high-precision comparison of transistor on-resistance under different gate drive voltages, includes: repeatedly switching the gate drive voltage of the transistor under test under a fixed drain voltage stress, based on the pulse signal. Real-time monitoring of the on-resistance changes and curves of the transistor under test before it degrades to a steady state under different gate drive voltages.

[0017] Preferably, the multiple switching of the gate drive voltage of the transistor under test includes periodically switching the gate drive voltage of the transistor under test, incrementally switching the gate drive voltage of the transistor under test, or incrementally switching the gate drive voltage of the transistor under test.

[0018] Preferably, in the push-pull output structure formed by the first CMOS inverter and the second CMOS inverter of the gate driving module, the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor or a gallium nitride-based N-channel enhancement-mode transistor.

[0019] Preferably, when the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor, its threshold voltage is 2-4V, and the pulse voltage... The high level is approximately 5V; when the lower transistor of the first CMOS inverter and the second CMOS inverter is a gallium nitride-based N-channel enhancement-mode transistor, its threshold voltage is 1-2V, and the pulse voltage... The high level is approximately 3.3V.

[0020] Compared with the prior art, the advantages and beneficial effects of the present invention are as follows:

[0021] The high-precision comparison method for transistor on-resistance of the present invention forms a brand-new transistor on-resistance comparison system through close collaboration of circuit architecture, timing control and comparison method. It achieves a breakthrough improvement in the accuracy and timeliness of transistor on-resistance comparison under different gate drive voltages, and realizes high-precision comparison of transistor on-resistance.

[0022] At the circuit architecture level, the DC voltage adjustment module and the gate drive module form the circuit foundation for switching the transistor gate drive voltage from microseconds to nanoseconds. At the timing control level, based on the real-time voltage regulation capability of the digital-to-analog converter chip of the DC voltage adjustment module and the precise timing of the control signal of the gate drive module, multiple sets of different drive voltages are rapidly switched during pulse testing, so that different drive voltages are applied to the transistors that have not yet degraded to a steady state, thereby realizing on-resistance measurement. At the comparison method level, by synchronizing the voltage switching with a delay of microseconds to nanoseconds with the pulse window, the interval of the traditional multi-stage test is compressed from the minute level to the nanosecond level, ultimately achieving a breakthrough improvement in the accuracy and timeliness of on-resistance comparison and improving the reliability of data comparison.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1 This is a circuit diagram of each stage of a traditional dual-pulse circuit;

[0026] Figure 2 This is a typical test waveform diagram of a traditional dual-pulse circuit (including a drain clamping module);

[0027] Figure 3 It is the on-resistance of a gallium nitride transistor after being subjected to different drain voltage stresses for different durations;

[0028] Figure 4 It is the on-resistance of a gallium nitride transistor after being subjected to different driving voltages and drain voltage stresses;

[0029] Figure 5 This is a flowchart of a method according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of a novel test waveform designed according to an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of a novel test circuit designed according to an embodiment of the present invention;

[0032] Figure 8 This is a schematic diagram of the digital-to-analog converter chip circuit according to an embodiment of the present invention;

[0033] Figure 9 This is a flowchart of a novel testing method designed according to an embodiment of the present invention;

[0034] Figure 10 This is an illustration of a novel test waveform implementation method designed according to an embodiment of the present invention.

[0035] In the diagram: 1. DC voltage adjustment module; 2. Gate drive module; 3. Power module. Detailed Implementation

[0036] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0037] Figure 1 This is a circuit diagram illustrating the various stages of a traditional double-pulse circuit. It consists of a high-voltage power supply, a voltage regulator capacitor, a power inductor, a freewheeling diode, and a transistor under test (TUT). A double-pulse (two consecutive switching) test is performed by applying a double-pulse waveform to the gate of the TUT. It can test the switching characteristics and on-resistance of the TUT under a specific gate drive voltage, drain voltage stress, and load current. (a) to (f) show the circuit states at different stages. The dashed line represents the TUT being off, and the solid line represents the TUT being on. The dashed arcs represent voltage stress paths, and the solid arcs represent current loop paths. (a) represents the first stage, where the TUT is not on and experiences drain voltage stress. (b) represents the second stage, where the TUT is on for the first time, and the voltage regulator capacitor charges the power inductor. (c) represents the third stage, where the TUT is off for the first time, the power inductor current cannot change abruptly, freewheels through the Schottky diode, and the drain of the TUT experiences drain voltage stress. (d) indicates the fourth stage, where the transistor under test (TUT) is turned on for the second time, and the charge from the voltage regulator capacitor flows through the TUT to charge the power inductor. (e) indicates the fifth stage, where the TUT is turned off for the second time, the power inductor current cannot change abruptly, and freewheeling occurs through the Schottky diode, with the drain of the TUT experiencing drain voltage stress. (f) indicates the sixth stage, where the inductor current gradually decreases until it disappears during freewheeling, at which point no current flows through the power inductor, and the drain of the TUT experiences drain voltage stress.

[0038] Figure 2This is a typical test waveform for a traditional double-pulse circuit (including a drain clamping module). The horizontal axis represents time, and the test time for a double-pulse waveform is generally several microseconds. A breakpoint is set before time 0 on the horizontal axis, indicating that some time (microseconds to several hours) before the double-pulse test begins, the drain of the transistor under test has already begun to experience voltage stress from the high-voltage power supply. The time before T1 corresponds to... Figure 1 (a), ~ correspond Figure 1 (b), ~ correspond Figure 1 (c), ~ correspond Figure 1 (d), after time T4 Figure 1 (e) and (f), where (e) and (f) are not... Figure 2 The following is a detailed explanation. The vertical axis, from top to bottom, represents the gate (drive) voltage, drain voltage, (drain) clamp voltage, and drain-source current, respectively. The gate voltage serves as the control signal, while the drain voltage, clamp voltage, and drain-source current are signals measured by the oscilloscope. When the gate voltage is low, the transistor under test (DUT) is off, resulting in a high drain voltage and a 0A drain-source current. When the gate voltage is high, the DUT is on, resulting in a low drain voltage and a gradually increasing drain-source current. The (drain) clamp voltage represents the drain voltage of the DUT measured by the drain clamp module in the dual-pulse circuit. The drain clamp module is added to improve the accuracy of drain voltage testing when the DUT is on. Since the drain clamp module is not the focus of this study, it is not discussed further. Figure 1 The circuit schematic is shown.

[0039] Figure 3 This refers to the on-resistance of a gallium nitride (GaN) transistor after being subjected to different drain voltage stresses for varying durations. The improvement of this invention lies in the combination of circuit innovation and testing method innovation. The focus is not on the transistor under test; the use of a GaN transistor here is merely for illustrative purposes. Figure 3 The on-resistance of the transistor under test (TST) was measured at room temperature with a fixed gate drive voltage of 6 volts in a traditional dual-pulse test circuit. The data shows the change in on-resistance under different drain voltage stress durations. As the drain voltage stress duration increases, the on-resistance initially increases and then stabilizes.

[0040] Figure 4 This refers to the on-resistance of a gallium nitride (GaN) transistor under different driving voltages and drain voltage stresses. Experiments investigated the on-resistance of the transistor under test (TST) at different driving voltages, finding that increasing the driving voltage can suppress the degradation of the TST's on-resistance. However... Figure 3 It has been shown that the on-resistance exhibits a "first increases, then stabilizes" characteristic as the drain voltage stress duration changes. Figure 4 The experimental data measures the on-resistance of the transistor under test (TUT) in its steady state after being subjected to "long-term" drain voltage stress. While the initial stages of the experiment allow for testing the TUT's steady-state data and comparing its on-resistance under different drive voltages, the traditional dual-pulse circuit exhibits significant limitations for TUT reliability assessment, real-time on-resistance monitoring, and degradation mechanism analysis. Specifically, it cannot rapidly adjust the gate drive voltage under short measurement delays (nanosecond-level delays), thus making it impossible to compare the TUT's on-resistance under different drive voltages with arbitrary drain voltage stress durations (when the TUT may not have degraded to a steady state).

[0041] Based on this, an embodiment of the present invention provides a high-precision comparison method for transistor on-resistance, such as... Figure 5 Shown, including:

[0042] Step S1: Generate and output a DC voltage that can be quickly adjusted and has load-carrying capacity through DC voltage adjustment module 1. ;

[0043] Step S2: Gate drive module 2 based on the DC voltage and pulse voltage Generates and outputs pulse signals with rapidly adjustable voltage. ;

[0044] Step S3: Apply a pulse signal to the transistor under test via power module 3. And based on the pulse signal Measure the on-resistance of the transistor under test at the gate drive voltage;

[0045] Step S4: Switch the gate drive voltage within a delay on the order of microseconds to nanoseconds, based on the pulse signal. The on-resistance of the transistor under test is measured under different gate drive voltages, enabling high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages.

[0046] The high-precision comparison method for transistor on-resistance of the present invention forms a brand-new transistor on-resistance comparison system through close collaboration of circuit architecture, timing control and comparison method. It achieves a breakthrough improvement in the accuracy and timeliness of transistor on-resistance comparison under different gate drive voltages, and realizes high-precision comparison of transistor on-resistance.

[0047] At the circuit architecture level, the DC voltage adjustment module 1 and the gate drive module 2 constitute the circuit foundation for switching the transistor gate drive voltage from microseconds to nanoseconds. At the timing control level, based on the real-time voltage regulation capability of the digital-to-analog converter chip of the DC voltage adjustment module 1 and the precise timing of the control signal of the gate drive module 2, multiple sets of different drive voltages are rapidly switched during pulse testing, so that different drive voltages act on the transistors that have not yet degraded to a steady state, thereby realizing on-resistance measurement. At the comparison method level, by synchronizing the voltage switching with a delay from microseconds to nanoseconds with the pulse window, the interval of the traditional multi-stage test is compressed from the minute level to the nanosecond level, ultimately achieving a breakthrough improvement in the accuracy and timeliness of on-resistance comparison and improving the reliability of data comparison.

[0048] It is understood that the pulse signal of the present invention It can be a dual-pulse signal in traditional dual-pulse testing, or a single-pulse signal or a multi-pulse signal. That is, the present invention can test the waveform of pulse signals with any number of different gate drive voltages applied to the gate of the transistor under test.

[0049] Figure 6 This is a schematic diagram of a novel test waveform designed according to an embodiment of the present invention. The horizontal axis represents time, and the vertical axis, from top to bottom, represents "Gate Voltage 1", "Gate Voltage 2", "Gate Voltage 3", "Gate Voltage 4", and "Gate Voltage 5", indicating five possible gate voltage control waveforms. Gate Voltage 1 represents a typical waveform in a traditional dual-pulse test circuit when comparing the on-resistance of the transistor under test under different gate drive voltages. Gate Voltage 2 and Gate Voltage 3 represent gate drive waveforms when the drive voltage needs to be changed once and the on-resistance of the transistor under test needs to be compared. Gate Voltage 4 and Gate Voltage 5 represent gate drive waveforms when the drive voltage needs to be changed multiple times and the on-resistance of the transistor under test needs to be compared. The figure only shows the waveform when the drive voltage is changed twice, while the waveforms when the drive voltage is changed multiple times are similar to those when the drive voltage is changed twice, and are not shown in the figure. The shaded areas are the parts that need to be focused on and the data read by the oscilloscope. The oscilloscope tests the drain voltage and drain-source current data of the transistor under test during the time period of the shaded area, and then obtains the on-resistance of the transistor under test at this time. Gate Voltage 1 represents the waveform when testing different gate drive voltages in a traditional dual-pulse circuit ( , The waveform of the transistor under test is shown. Testing different gate drive voltages generally requires manual adjustment of the external voltage divider module, a process that typically takes several minutes. The longer time delay is represented by "breakpoints" on the coordinate axis. Gate voltage 2 is one of the optimized solutions proposed in this invention, occurring during the second pulse voltage... The value applied several microseconds later is The pulse voltage, this scheme has moderate requirements for circuit performance and cost. Gate voltage 3 is a further optimized scheme proposed in this invention, in the second pulse voltage. After a delay on the order of nanoseconds, the applied value is The pulse voltage method, while demanding high circuit performance and cost, reduces the measurement delay to the nanosecond level, enabling high-precision comparison of on-resistance. Gate voltage 4 is a waveform diagram illustrating the multiple changes in the gate drive voltage, specifically during the second pulse voltage... The value applied several microseconds later is A pulse voltage is applied, followed by a microsecond-level delay. Gate voltage 5 is a further optimization of gate voltage 4 proposed in this invention, in the second pulse voltage... After a delay on the order of nanoseconds, the applied value is A pulse voltage, followed by a delay of several nanoseconds, is applied with a value of The pulse voltage. It is worth noting that the voltage values ​​that can be applied to gate voltage 4 and gate voltage 5 are not limited to three values; multiple voltage values ​​can be set according to experimental needs, as shown in the figure. , , This is for illustrative purposes only.

[0050] As one implementation method, such as Figure 7 As shown, the DC voltage adjustment module 1 includes a digital-to-analog converter chip and an operational amplifier. The digital-to-analog converter chip and the operational amplifier are connected via DC voltage. Power supply is provided, the output terminal of the digital-to-analog converter chip is connected to the operational amplifier, and the output terminal of the operational amplifier is connected to the gate drive module 2.

[0051] As one implementation method, such as Figure 7 As shown, the gate driving module 2 includes a first CMOS inverter and a second CMOS inverter. The output terminal of the operational amplifier is connected to the power supply pins of the first CMOS inverter and the second CMOS inverter. The input pin of the first CMOS inverter is connected to a pulse voltage. The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter. The ground pins of the first CMOS inverter and the second CMOS inverter are both grounded. The output pin of the second CMOS inverter is connected to the power module 3.

[0052] like Figure 7As shown, it can be understood that both the first CMOS inverter and the second CMOS inverter consist of two enhancement-mode field-effect transistors, one an NMOS field-effect transistor and the other a PMOS field-effect transistor.

[0053] As one implementation method, such as Figure 7 As shown, the power module 3 includes a freewheeling diode D and a power inductor L. The gate of the transistor under test Q is connected to the output pin of the second CMOS inverter. The drain of the transistor under test Q is connected to the positive terminal of the freewheeling diode D and one end of the power inductor L. The negative terminal of the freewheeling diode D and the other end of the power inductor L are connected to the high-voltage power supply. The positive terminal of the transistor Q under test is connected to the source of the transistor Q, and the high voltage power supply is connected to the source of the transistor Q under test. The negative terminal is grounded, and the high-voltage power supply is connected in parallel with a voltage-stabilizing capacitor C.

[0054] Figure 7 This is a schematic diagram of the novel test circuit designed in this invention. Figure 7 This is the macroscopic structure of a high-precision transistor on-resistance comparison circuit. The circuit comprises three modules: a DC voltage adjustment module 1, a gate drive module 2, and a power module 3. The DC voltage adjustment module 1 provides rapidly changing DC power; the gate drive module 2 uses a pulse control signal and a rapidly changing DC power output level to generate a pulse signal; and the power module 3 is used for pulse testing of the transistor under test to obtain its on-resistance. The DC voltage adjustment module 1 uses a digital-to-analog converter chip to generate a high-speed adjustable DC power supply. Then, the operational amplifier is operated in voltage follower mode to convert the DC signal output by the digital-to-analog converter chip. It can be converted into direct current that can carry a load (output a certain current). DC voltage It supplies power to the digital-to-analog converter chip and the operational amplifier chip. Gate driver module 2 contains two CMOS inverter modules forming a push-pull output. Gate driver module 2 uses the adjustable DC voltage output from DC voltage adjustment module 1. Power supply. Pulse voltage. This is a control signal used to control whether the gate drive module 2 outputs voltage. With adjustable DC power Ultimately, it can output a pulse waveform signal with rapidly adjustable voltage. Power module 3 uses a pulse waveform signal with rapidly adjustable voltage. Drive the transistor under test and extract the on-resistance of the transistor under test from the test waveform for comparative analysis. Figure 8This is an example of a high-speed digital-to-analog converter (DAC) chip according to an embodiment of the present invention. The DAC chip is a DAC08 manufactured by Analog Devices (ADI). The setup time of the analog signal output by the DAC08 is 85ns. The DAC08 contains 8 digital signal control bits, according to... Figure 8 After the circuit schematic shown is connected, a high-frequency varying analog voltage can be output at the IOUT pin. Experiments have proven that this digital-to-analog converter chip can indeed switch and output different DC values ​​on a nanosecond scale.

[0055] More specifically, such as Figure 8 As shown, the V+ pin of the DAC08 digital-to-analog converter chip is connected to a 15V DC power supply; the VREF+ pin is connected to a 10V reference DC power supply via resistor R1; the VREF- pin is grounded via resistor R2; the COMP pin is connected to a -15V DC power supply via capacitor C1; the VLC pin is grounded; the IOUT- pin is connected to a 10V DC power supply via resistor R3; the V- pin is connected to a -15V DC power supply; the IOUT pin is connected to a 10V DC power supply via resistor R4; and the IOUT pin outputs DC power. The B1-B8 pins of the digital-to-analog converter chip DAC08 are connected to the corresponding digital input voltage sources via resistors R12-R5, respectively. - .

[0056] In one implementation, the digital-to-analog converter chip of the DC voltage adjustment module 1 is controlled by a digital signal to generate and output a high-speed adjustable DC voltage. Subsequently, the operational amplifier operates in voltage follower mode, converting the DC signal output by the digital-to-analog converter chip into a DC voltage capable of driving a load. .

[0057] In one implementation, the first CMOS inverter and the second CMOS inverter of the gate driving module 2 form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module 1... Power supply, via pulse voltage Controls the opening and closing of the voltage output of the gate drive module 2, adjustable DC voltage. and pulse voltage The control gate drive module 2 output voltage can be rapidly adjusted via a pulse signal. .

[0058] Figure 9This is a flowchart of the novel testing method designed in this invention. First, a digital signal is input to the digital-to-analog converter (DAC) chip according to experimental requirements. The DAC chip generates a rapidly adjustable DC current, which, combined with an operational amplifier, enables the DC current to carry a load, resulting in a load-carrying and rapidly adjustable DC voltage. This DC power supply is then used to power the gate drive module 2, and a control signal is used to determine the time range of the output voltage of the gate drive module 2. Finally, a rapidly adjustable, load-carrying pulse voltage is used to drive the gate of the transistor under test (TUT) for a dual-pulse test under different drive voltages with a short measurement delay. This allows the on-resistance of the TUT under different drive voltages with a short measurement delay to be obtained.

[0059] As one implementation, the switching gate drive voltage is based on the pulse signal. Measuring the on-resistance of a transistor under switching gate drive voltages, and achieving a high-precision comparison of transistor on-resistance under different gate drive voltages, includes: repeatedly switching the gate drive voltage of the transistor under test under a fixed drain voltage stress, based on the pulse signal. Real-time monitoring of the on-resistance changes and curves of the transistor under test before it degrades to a steady state under different gate drive voltages.

[0060] In one implementation, the multiple switching of the gate drive voltage of the transistor under test includes periodically switching the gate drive voltage of the transistor under test, incrementally switching the gate drive voltage of the transistor under test, or incrementally switching the gate drive voltage of the transistor under test.

[0061] It is understood that the multiple switching of the gate drive voltage of the transistor under test, specifically multiple times, means greater than or equal to 1.

[0062] In one embodiment, switching the gate drive voltage of the transistor under test multiple times specifically involves periodically switching the gate drive voltage of the transistor under test, for example, switching the gate drive voltage of the transistor under test in a 5V-6V-5V-6V sequence, with a switching time interval of 100 nanoseconds.

[0063] In one embodiment, switching the gate drive voltage of the transistor under test multiple times specifically involves periodically switching the gate drive voltage of the transistor under test, for example, switching the gate drive voltage of the transistor under test according to 5V-6V-7V-5V-6V-7V, with a switching time interval of 100 nanoseconds.

[0064] In one embodiment, the gate drive voltage of the transistor under test is switched multiple times in an incremental manner, for example, by switching the gate drive voltage of the transistor under test in the order of 5V-6V-7V-8V, with a switching time interval of 200 nanoseconds.

[0065] In one embodiment, switching the gate drive voltage of the transistor under test multiple times specifically involves: switching the gate drive voltage of the transistor under test in a decreasing manner, for example, switching the gate drive voltage of the transistor under test in a 7V-6V-5V manner, with a switching time interval of 10 microseconds.

[0066] It is understood that the above-mentioned switching of the gate drive voltage of the transistor under test is exemplary. The switching of the gate drive voltage of the transistor under test in this invention includes voltage magnitude, voltage interval, number of switching, and switching time interval, which are not limited to these. Any switching of the gate drive voltage of the transistor under test that can achieve high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages through the high-precision comparison method of the transistor on-resistance of this invention is within the protection scope of this invention.

[0067] In one implementation, in the push-pull output structure formed by the first CMOS inverter and the second CMOS inverter in the gate driving module 2, the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor or a gallium nitride-based N-channel enhancement-mode transistor.

[0068] As one implementation, when the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor, its threshold voltage is 2-4V, and the pulse voltage... The high level is approximately 5V; when the lower transistor of the first CMOS inverter and the second CMOS inverter is a gallium nitride-based N-channel enhancement-mode transistor, its threshold voltage is 1-2V, and the pulse voltage... The high level is approximately 3.3V.

[0069] Figure 10 This is an illustration of the novel test waveform implementation method designed in this invention. Figure 10 (a) is a description of the method for generating gate voltage 2; Figure 10 (b) Explanation of the method for generating gate voltage 3; Figure 10 (c) is a description of the method for generating gate voltage 4; Figure 10 (d) describes the method for generating gate voltage 5. For ease of explanation, Figure 10 China replaces 5V Figure 6 In , Figure 10 Replaced with 6V Figure 6 In , Figure 10 7V is used instead Figure 6 In DC voltage This provides power to the digital-to-analog converter chip and the operational amplifier chip; 10V is used as an example here. Voltage This is the "rapidly adjustable" voltage output from the digital-to-analog converter chip and after passing through the operational amplifier voltage follower. The shaded area in the diagram illustrates the time windows for switching from 5V to 6V and from 6V to 7V. Pulse voltage. This is a control signal output by the microcontroller, used to control the time range of the output voltage of gate drive module 2. When the voltage is high (3.3V), gate drive module 2 is turned on. The level is equal to Level; when When the voltage is low (0V), gate drive module 2 is turned off. The voltage level is 0V or negative; in this embodiment, 0V is used. "A pulse signal with rapidly adjustable voltage." Depend on and Confirmed. It's worth noting that when a silicon-based field-effect transistor is used as the lower transistor in the push-pull circuit of the CMOS structure in gate driver module 2, its threshold voltage is typically 2–4V. Therefore, the control signal… A voltage of around 5V is required to fully turn on the lower transistor. Alternatively, a gallium nitride-based N-channel enhancement-mode transistor can be selected, with a threshold voltage typically between 1 and 2V. Using the 3.3V output from the microcontroller can fully turn on the lower transistor.

[0070] This invention relates to a high-precision comparison method and circuit for transistor on-resistance, which can output a pulse signal with rapidly adjustable voltage and test the transistor on-resistance based on the pulse circuit, ultimately achieving a high-precision comparison of transistor on-resistance under different gate drive voltages with a delay time on the order of nanoseconds.

[0071] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] It will be readily understood by those skilled in the art that this invention includes any combination of the inventive description and specific embodiments outlined in the foregoing specification, as well as the various parts shown in the accompanying drawings. Due to space limitations and for the sake of brevity, not all of these combinations have been described in detail. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0073] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision comparison method for transistor on-resistance, characterized in that, include: The DC voltage adjustment module generates and outputs a DC voltage that can be quickly adjusted and has load-carrying capacity. ; The gate drive module is based on the DC voltage and pulse voltage Generates and outputs pulse signals with rapidly adjustable voltage. ; A pulse signal is applied to the transistor under test via the power module. And based on the pulse signal Measure the on-resistance of the transistor under test at the gate drive voltage; Switching the gate drive voltage within a delay on the order of microseconds to nanoseconds, based on the pulse signal. The on-resistance of the transistor under test is measured under different gate drive voltages, enabling a high-precision comparison of the on-resistance of the transistor under test under different gate drive voltages. The DC voltage adjustment module includes a digital-to-analog converter chip and an operational amplifier, and the digital-to-analog converter chip and the operational amplifier are connected via DC voltage. Power supply; the output terminal of the digital-to-analog converter chip is connected to the operational amplifier, and the output terminal of the operational amplifier is connected to the gate drive module; The gate driving module includes a first CMOS inverter and a second CMOS inverter. The output terminal of the operational amplifier is connected to the power supply pins of the first CMOS inverter and the second CMOS inverter. The input pin of the first CMOS inverter is connected to a pulse voltage. The output pin of the first CMOS inverter is connected to the input pin of the second CMOS inverter. The ground pins of the first CMOS inverter and the second CMOS inverter are both grounded. The output pin of the second CMOS inverter is connected to the power module. The digital-to-analog converter chip generates and outputs a high-speed adjustable DC voltage. An operational amplifier then converts the DC signal output by the digital-to-analog converter chip into a load-carrying DC voltage. ; The first CMOS inverter and the second CMOS inverter are connected through the DC voltage. Power supply, via pulse voltage Control gate drive module, DC voltage and pulse voltage A pulse signal that allows for rapid adjustment of the output voltage of the control gate drive module. .

2. The high-precision comparison method for transistor on-resistance as described in claim 1, characterized in that, The power module includes a freewheeling diode and a power inductor. The gate of the transistor under test is connected to the output pin of the second CMOS inverter. The drain of the transistor under test is connected to the positive terminal of the freewheeling diode and one end of the power inductor. The negative terminal of the freewheeling diode and the other end of the power inductor are connected to the positive terminal of the high-voltage power supply. The source of the transistor under test and the negative terminal of the high-voltage power supply are grounded. A voltage-regulating capacitor is connected in parallel with the high-voltage power supply.

3. The high-precision comparison method for transistor on-resistance as described in claim 1, characterized in that, The DC voltage adjustment module's digital-to-analog converter chip is controlled by a digital signal to generate and output a high-speed adjustable DC voltage. Subsequently, the operational amplifier operates in voltage follower mode, converting the DC signal output by the digital-to-analog converter chip into a load-carrying DC voltage. .

4. The high-precision comparison method for transistor on-resistance as described in claim 1, characterized in that, The first CMOS inverter and the second CMOS inverter of the gate driving module form a push-pull output structure, and the adjustable DC voltage output by the DC voltage adjustment module... Power supply, via pulse voltage Controls the on / off switching of the gate drive module voltage output; adjustable DC voltage. and pulse voltage A pulse signal that allows for rapid adjustment of the output voltage of the control gate drive module. .

5. The high-precision comparison method for transistor on-resistance as described in claim 4, characterized in that, The switching gate drive voltage is based on the pulse signal. Measuring the on-resistance of a transistor under switching gate drive voltages, and achieving a high-precision comparison of transistor on-resistance under different gate drive voltages, includes: repeatedly switching the gate drive voltage of the transistor under test under a fixed drain voltage stress, based on the pulse signal. Real-time monitoring of the on-resistance changes and curves of the transistor under test before it degrades to a steady state under different gate drive voltages.

6. The high-precision comparison method for transistor on-resistance as described in claim 5, characterized in that, The multiple switching of the gate drive voltage of the transistor under test includes periodically switching the gate drive voltage of the transistor under test, incrementally switching the gate drive voltage of the transistor under test, or incrementally switching the gate drive voltage of the transistor under test.

7. The high-precision comparison method for transistor on-resistance as described in claim 1, characterized in that, In the push-pull output structure formed by the first CMOS inverter and the second CMOS inverter of the gate driving module, the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor or a gallium nitride-based N-channel enhancement-mode transistor.

8. The high-precision comparison method for transistor on-resistance as described in claim 7, characterized in that, When the lower transistor of the first CMOS inverter and the second CMOS inverter is a silicon-based field-effect transistor, its threshold voltage is 2-4V, and the pulse voltage... The high level is approximately 5V; when the lower transistor of the first CMOS inverter and the second CMOS inverter is a gallium nitride-based N-channel enhancement-mode transistor, its threshold voltage is 1-2V, and the pulse voltage... The high level is approximately 3.3V.

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