Neural network accelerator circuit fault detection and repair method and system for radiation environment application

Abstract

The invention discloses a radiation environment application-oriented neural network accelerator circuit fault detection and repair method and system. The method comprises the steps of determining a key path list of a neural network accelerator circuit by introducing a fault site; performing fault-tolerant design on the critical path list, generating a fault-tolerant CNN accelerator netlist, verifying a circuit operation result during operation, detecting and marking a difference result, and generating a fault flag bit; and according to the fault flag bit, the soft fault is solved through the repair site, and if the soft fault cannot be repaired, the network model is reloaded, and the affected local resources are dynamically reconstructed or reset to complete self-repair. The method has the remarkable advantages of improving reliability, automatically detecting faults, efficiently repairing the faults, reducing maintenance cost, improving system adaptability and the like, and powerful technical guarantee is provided for application of the neural network accelerator in the extreme environment.

Description

Technical Field

[0001] The present invention belongs to the technical field of artificial intelligence hardware design, and relates to a method and system for detecting and repairing circuit faults of a neural network accelerator for applications in radiation environments. Background Art

[0002] Convolutional Neural Networks (CNNs) have been widely used in various tasks, including autonomous driving, medical image analysis, and natural language processing, due to their superior performance in image processing, pattern recognition, and feature extraction. With the rapid development of commercial spaceflight, the potential application prospects of CNNs in spacecraft are becoming increasingly significant. They can effectively improve data processing efficiency and decision-making support capabilities in multiple application scenarios, such as satellite image processing, deep space exploration data analysis, and real-time monitoring systems. However, current CNN models typically have huge computational and storage requirements, which poses a severe challenge to resource-constrained spacecraft in terms of weight and power consumption. In addition, the high radiation levels in the space environment may cause single-particle effects, resulting in soft errors in node circuits, directly affecting the reliability and safety of the entire system.

[0003] As a computational model, neural networks contain a large amount of weight data and activation functions. When performing inference tasks, neural networks need to process large and intensive amounts of data. Due to their enormous computational and storage requirements, neural networks place high demands on hardware computing platforms when deployed. Common platforms for deploying convolutional neural network algorithms include central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) based on static random-access memory (SRAM). The CPU is responsible for executing instructions for computation and storage, and is the core of a computer device. Data dependencies may exist between different instructions during CPU operation, making it difficult to achieve high levels of parallelism and unsuitable for computing-intensive applications such as convolutional neural networks. GPUs contain a large number of stream processors, offering powerful computing capabilities and enabling efficient floating-point matrix multiplication. However, their high power consumption and low energy efficiency make them unsuitable for large-scale deployment in low-power scenarios such as edge devices and mobile terminals. Custom-designed ASICs offer advantages such as high speed and low power consumption, increasing data throughput and making them suitable for accelerating neural network computations. However, they lack flexibility and have long development cycles, making them difficult to universally support the rapidly evolving and iterative nature of various CNN algorithms. As a reconfigurable device, SRAM-based FPGAs address the flexibility limitations of ASICs and significantly shorten development cycles. Furthermore, SRAM-based FPGAs, with their high speed, low power consumption, and high energy efficiency, offer advantages in application scenarios with constantly evolving functional requirements. When executing different computational tasks, FPGAs can adapt to varying degrees of computational parallelism through flexible resource allocation, making them ideal for deploying neural network accelerators.

[0004] In recent years, CNN accelerators based on SRAM-based FPGAs have found new applications in autonomous driving, aerospace, defense, healthcare, cloud computing, industrial automation, and other fields. In aerospace, satellite-based systems equipped with SRAM-based FPGAs use CNNs to acquire high-resolution optical satellite imagery. This allows them to create terrain databases for various regions, which can be used for surface disaster prevention and rescue, opening up new possibilities for monitoring changes on the Earth's surface. Autonomous vehicle platoon control also relies on neural networks to analyze input from multispectral cameras and lidar to make complex control decisions. Major manufacturers also offer cloud acceleration services based on SRAM-based FPGAs, allowing users to deploy their own CNN acceleration solutions on cloud servers and access accelerated computing services at the lowest cost. Despite the numerous advantages of SRAM-based FPGAs, neural network accelerators still face soft error issues at the hardware level. Previous studies have shown that errors in neural network weight data can lead to reduced network accuracy. Researchers have attempted to mitigate the impact of these errors through methods such as software-level pruning and hardware-level parameter quantization. However, the principles of errors in neural network data differ from those in the hardware deployed. The optimization targets of network models at the algorithmic level are relatively limited, and soft error mitigation methods are not universal across network models with different data patterns. Therefore, single-event effects (SEEs) in neural network accelerators still need to be analyzed from the hardware error perspective. Research on SEEs in hardware accelerators has primarily focused on memories, as memories contain the vast amount of data information required for neural network operation. Researchers have simulated fault models using both software and hardware injection to evaluate the impact of soft errors on neural network performance. Hardware injection is closer to the actual physical injection model and offers higher evaluation accuracy, but it also carries greater implementation complexity and cost. Software injection offers lower cost and greater controllability, but its evaluation accuracy depends on the fault model, and obtaining accurate and reliable fault models remains a challenge. Researchers have evaluated the soft error susceptibility of CRAM resources in SRAM-based FPGAs through irradiation experiments and fault injection. However, existing research lacks fine-grained analysis of the criticality of circuit modules during the evaluation process, and the target circuit address range is not clear enough during fault injection.

[0005] Especially in extreme environments such as space or ground nuclear facilities, there is an urgent need for a neural network accelerator circuit fault detection and repair technology. By means of radiation-resistant neural network circuit netlist conversion, circuit redundancy and self-detection and self-repair module integration, the reliable application of neural network accelerators in extreme environments can be improved. Summary of the Invention

[0006] In response to the problems existing in the prior art, the present invention provides a method and system for detecting and repairing circuit faults in a neural network accelerator for applications in radiation environments, thereby resolving the technical problems in the prior art of poor reliability of neural network accelerators in extreme environments such as space or ground nuclear facilities, as well as insufficient automation of fault detection and repair.

[0007] The present invention is achieved through the following technical solutions: A method for detecting and repairing circuit faults in a neural network accelerator for applications in radiation environments, comprising the following steps: Determine the critical path list of neural network accelerator circuit by introducing the fault location method; Implementing fault-tolerant design on the critical path list to generate a fault-tolerant CNN accelerator netlist, performing circuit operation result verification during operation, detecting and marking discrepancies in the results, and generating a fault flag; According to the fault flag, the soft fault is resolved by repairing the site. If the fault cannot be repaired, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

[0008] Preferably, the method of introducing the fault location to determine the critical path list of the neural network accelerator circuit is specifically as follows: S11: Initialization and data preparation for CRAM and FF resource fault analysis. Specifically, the CPU control interface reads the target unit coordinates from the storage and prepares data such as weights and input images. At the same time, FF analysis also needs to extract the trigger signal name and initialize the reset and enable signals to ensure that the system is in the correct state. S12: Enter the fault introduction and system operation phase. Specifically, in CRAM analysis, a fault is introduced based on coordinates and system evaluation is initiated. In FF analysis, the fault location is refreshed, the system is started, and the FF logic state is forced to change at a selected moment to simulate a transient fault. Changes in system behavior are observed to assess the fault impact. S13: Result analysis and data output phase. Specifically, CRAM analysis transmits accuracy and precision to the host computer via the JTAG interface for evaluation. FF analysis exports a list of FF logic values ​​to analyze changes in system behavior after the fault is introduced. S14: Determine the critical path list of the neural network accelerator circuit by analyzing the output behavior of the circuit under different fault conditions.

[0009] Preferably, during the transient perturbation process, the values ​​of multiple CRAMs or FFs are perturbed at the same time, and the impact of the introduction of multi-site perturbations on the circuit is analyzed.

[0010] Preferably, when counting the critical path list of the neural network accelerator circuit, the results are divided into mild degradation, moderate degradation and severe degradation according to the degree of accuracy degradation of the neural network accelerator, among which, the accuracy between 80% and 100% is mild degradation, the accuracy between 10% and 80% is moderate degradation, and below 10% is severe degradation.

[0011] Preferably, the implementation of the fault-tolerant design includes designing an operation detection state machine, adding fault-tolerant logic to a core status register, and generating a status abnormality flag.

[0012] Preferably, the method of resolving the soft fault by repairing the site specifically includes: importing the recorded fault site coordinates from an off-chip storage, and flipping the corresponding site to repair the fault.

[0013] A neural network accelerator circuit fault detection and repair system for radiation environment applications, comprising: a critical path determination module, the critical path determination module being used to determine a critical path list of a neural network accelerator circuit by introducing a fault location method; a fault-tolerant design module, the fault-tolerant design module being used to implement fault-tolerant design on the critical path list, generate a fault-tolerant CNN accelerator netlist, perform circuit operation result verification during operation, detect and mark discrepancies in the results, and generate a fault flag; The fault repair module is used to solve the soft fault by repairing the site according to the fault flag bit. If the fault cannot be repaired, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

[0014] A computer device includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0015] A computer-readable storage medium stores a computer program, wherein the computer program / instructions are executed by a processor to implement the steps of the above method.

[0016] A computer program product comprises a computer program / instruction, which implements the steps of the above method when executed by a processor.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention discloses a method for detecting and repairing circuit faults in a neural network accelerator for applications in radiation environments. First, the method determines a critical path list by introducing a fault location method. This method can accurately identify the most sensitive or important parts of the circuit, thereby performing targeted fault-tolerant design, effectively reducing the probability of circuit failure in extreme environments and significantly improving the reliability of the neural network accelerator. Second, circuit operation results are verified during runtime, and discrepancies can be detected and marked in real time to generate a fault flag. This process is fully automated and requires no human intervention, greatly improving the efficiency and accuracy of fault detection. In addition, based on the fault flag, the system can quickly locate the fault location and resolve soft faults by repairing the location. If the fault cannot be repaired, the network model is automatically reloaded and the affected local resources are dynamically reconfigured or reset. This rapid response and efficient repair capability ensures the continued stable operation of the neural network accelerator in extreme environments. Moreover, the automation of fault detection and repair greatly reduces the need for human intervention, thereby reducing maintenance costs. At the same time, the dynamic reconstruction or reset technology is locked to the neural network level and individual operation modules, avoiding global refresh and further saving time and resources. This method is not only applicable to neural network accelerators but can also be extended to other types of circuit systems, improving their adaptability and reliability in extreme environments. In summary, the circuit fault detection and repair method for neural network accelerators in radiation environments presented in this invention offers significant advantages in terms of improved reliability, automated fault detection, efficient fault repair, reduced maintenance costs, and enhanced system adaptability. It provides a strong technical foundation for the application of neural network accelerators in extreme environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is a schematic diagram of the top-level structure of the CNN accelerator; Figure 2 It is a resource fault and failure probability analysis platform for CNN accelerators; Figure 3 is the variation of accuracy with the number of soft fault sites in the convolution module; Figure 4 is the variation of accuracy with the number of soft fault sites in the pooling module; Figure 5 is the variation of accuracy with the number of soft fault sites in the fully connected module; Figure 6 Analytical methods for the formation and impact of soft fault sites in neural network accelerators; Figure 7 Establish fault-tolerant design mechanisms for radiation-sensitive critical paths; Figure 8 Soft high-reliability circuit netlist conversion for neural network accelerator; Figure 9 Provide ideas for repairing soft fault sites in neural network accelerators; Figure 10 Implementation diagram of the neural network accelerator before and after reinforcement; Figure 11 Generate flags for key node operations and detection state machines; Figure 12 Generates the difference flag of the operation result. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0023] In the description of the embodiments of the present invention, it should be noted that if the terms "upper," "lower," "horizontal," "inner," etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is typically placed when in use. These terms are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0026] The present invention is described in further detail below with reference to the accompanying drawings: Example 1 The present invention provides a method for detecting and repairing circuit faults in a neural network accelerator for applications in radiation environments, comprising the following steps: S1: Determine the critical path list of the neural network accelerator circuit by introducing the fault location method; Specifically: S11: Initialization and data preparation for CRAM and FF resource fault analysis. Specifically, the CPU control interface reads the target unit coordinates from the storage and prepares data such as weights and input images. At the same time, FF analysis also needs to extract the trigger signal name and initialize the reset and enable signals to ensure that the system is in the correct state. S12: Enter the fault introduction and system operation phase. Specifically, in CRAM analysis, a fault is introduced based on coordinates and system evaluation is initiated. In FF analysis, the fault location is refreshed, the system is started, and the FF logic state is forced to change at a selected moment to simulate a transient fault. Changes in system behavior are observed to assess the fault impact. S13: Result analysis and data output phase. Specifically, CRAM analysis transmits accuracy and precision to the host computer via the JTAG interface for evaluation. FF analysis exports a list of FF logic values ​​to analyze changes in system behavior after the fault is introduced. S14: Determine the critical path list of the neural network accelerator circuit by analyzing the output behavior of the circuit under different fault conditions.

[0027] When counting the critical path list of the neural network accelerator circuit, the results are divided into mild degradation, moderate degradation and severe degradation according to the degree of accuracy degradation of the neural network accelerator. Among them, the accuracy between 80% and 100% is mild degradation, the accuracy between 10% and 80% is moderate degradation, and below 10% is severe degradation.

[0028] S2: Implementing fault-tolerant design on the critical path list to generate a fault-tolerant CNN accelerator netlist, performing circuit operation result verification during operation, detecting and marking difference results, and generating a fault flag; The implementation of the fault-tolerant design includes designing an operation detection state machine, adding fault-tolerant logic to a core state register, and generating a state abnormality flag.

[0029] S3: Based on the fault flag, the soft fault is resolved by repairing the site. If the repair is not possible, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

[0030] The method of resolving a soft fault by repairing a site specifically includes: importing the recorded coordinates of the fault site from an off-chip storage, and flipping the corresponding site to repair the fault.

[0031] The present invention proposes a neural network accelerator circuit fault detection and repair technology, establishes a universal high-reliability CNN accelerator design method, and enables the neural network accelerator system to operate stably and reliably in a radiation environment. The present invention performs fault analysis on the integrated CNN accelerator circuit netlist, detects the location and impact of code point faults, and establishes a fault detection and fault-tolerant design mechanism for radiation-sensitive critical paths. Through the repair method of soft fault sites, sensitive nodes are effectively repaired and the impact of faults is eliminated, thereby establishing a highly reliable network architecture. This method expands the application scope of existing commercial and industrial-grade FPGA chips to deploy neural network accelerators, including civil and commercial aerospace, satellite communications, traditional aerospace, and domestic weaponry.

[0032] The present invention has the following advantages: The impact of more than 90% of single fault locations can be controlled, and faults can be repaired in real time, meeting the requirements of low-cost, high-reliability operation of space systems. The corresponding technology can also be used in the development of a new generation of highly reliable neural network chips.

[0033] Commercial FPGAs and other chips can be equipped with neural network accelerators to realize the space application of artificial intelligence technology and meet the computing needs of on-orbit equipment. They can help partially replace aerospace chips with a unit price of over 100,000 yuan in equipment such as space stations (reducing the cost of a single chip to less than 10%), greatly control the cost of low-orbit commercial satellites and other space intelligent equipment, and ensure their on-orbit reliability.

[0034] System-level design reinforcement is extremely flexible and can be used for SoC and FPGA product transplantation projects from different vendors.

[0035] Full triple modular redundancy (TMR) technology requires ×3 basic resources and a relatively large number of logical resources, resulting in a total resource consumption greater than ×3 and inability to monitor concurrent faults in real time. The fault detection and repair technology of this invention reduces TMR costs and usage by ×1.2 to ×2.6, and can locate and repair faults in real time, improving system safety on-orbit. Existing protection technologies such as node redundancy, TMR, and ECC are not suitable for large-scale neural networks. Furthermore, existing technologies provide fault tolerance but lack timely error correction, requiring the use of blind refreshes. Refreshes must be global and require reconfiguration, resulting in significant time costs. The present invention generates fault indicators for faults, enabling real-time system refreshes or dynamic reconfigurations, or resetting some resources. This provides greater flexibility and reduces time costs.

[0036] The present invention can timely detect the system functional status due to the real-time testing and comparison of the operation module. It can better handle the global functional failure of the CNN accelerator, allowing the system to promptly detect and respond to functional anomalies in the chip.

[0037] The present invention reduces system costs and brings significant economic benefits through cost control in system-level reinforcement design.

[0038] Example 2 In order to further explain the technical solution of the present invention, the following examples are used for illustration: The present invention provides a neural network accelerator circuit fault detection and repair technology for radiation environment applications, which uses software and hardware fault analysis methods to parse the neural network circuit netlist and combines circuit redundancy and self-checking and self-correcting modules.

[0039] The present invention is achieved through the following technical solutions: (1) Neural network accelerator design A typical convolutional neural network consists of typical layers, such as convolution, pooling, and fully connected layers. Its structure is well-organized and easy to analyze. Based on the network model structure, the CNN accelerator circuit is implemented by dividing the functional modules. A sliding window module is designed using a shift sequence to read the input image. Module parameterization allows adaptation to input feature maps of varying sizes. In the convolution module, a convolution operation is used to extract target abstract features from the input feature map and map them to the output feature map. Convolution operations involve numerous multiplication and addition operations, implemented using a processing element (PE) array. Weight data and input feature maps are preloaded before computation. An activation module is designed to enhance the model's nonlinear representation capabilities. When the result from the previous module is input into this module, a flag signal determines whether to perform an activation operation. If the flag signal is 0, activation is not required and the result is output directly. If the flag signal is 1, activation is performed on the input vector and the result is output. A pooling module is used to further extract abstract information from the feature map. Dimensionality reduction reduces the data size and improves the accelerator's computational efficiency. A fully connected module is designed at the output end of the CNN accelerator to divide the features extracted by the convolution, pooling and other modules and map them to the output space to play a classification role. A top-level control module is designed to realize the connection and signal control of each sub-module. The top-level structure diagram of the CNN accelerator is shown in the figure below. Figure 1 shown.

[0040] During the first convolution layer, the output feature map is processed by the ReLU and pooling modules and then stored in the FIFO (First Input First Output) pending the next computation. The second convolution layer requires multiple loops to complete. The intermediate results of each computation are stored in a buffer, pending the completion of the next loop. The loop count signal determines whether to perform an accumulation operation. If accumulation is required, the intermediate results are read from the corresponding buffer and then combined with the output of the current convolution loop for computation. The accumulated intermediate results remain cached in the buffer. After the second convolution layer completes all computations, the output feature map passes through the ReLU and pooling modules before entering the fully connected layer for classification, ultimately outputting the classification result.

[0041] After the algorithm design is complete, the CNN accelerator circuit is synthesized and deployed to the FPGA chip to implement the hardware accelerator structure. CNN accelerator circuit synthesis requires implementing the circuit functions and signal behaviors described by the user in Verilog / VHDL (Hardware Description Language) using basic building blocks on the FPGA, generating the corresponding gate-level netlist. Logic synthesis converts the unoptimized gate-level netlist after RTL synthesis into a logic netlist composed of library cells relevant to the FPGA device through three sub-steps: area optimization, timing optimization, and process mapping. After deployment, the neural network accelerator uses the FPGA's internal memory and logic resources to implement the neural network computing functions. The necessary communication and interaction between the FPGA and peripheral chips is established.

[0042] (3) Software and hardware platform-assisted fault analysis After synthesizing the circuit netlist, EDA is used to assist in fault analysis. The location and influence of code point faults are detected. The relationship between the internal and inter-layer influences of the network is found. Figure 2 As shown in the figure, this platform utilizes hardware and software co-design, consisting of two components: FPGA hardware and host computer software. The hardware primarily includes the device under test (DUT), fault assessment core, storage module, CPU, communication control module, and serial port. The software component of the resource fault and failure probability analysis platform includes an SDK for the CPU soft core and serial port debugging software. The SDK, written in C, controls data transmission, module operation, and other operations of the hardware analysis system.

[0043] When executing the CRAM resource fault analysis process, the CPU control interface reads the linear coordinates of the target unit from off-chip storage and pulls the inject_strobe signal high for one cycle to trigger the resource fault and failure probability assessment process. Based on the linear coordinates, faults are introduced at the corresponding locations to establish a resource fault and failure model, simulating the impact of soft faults at sensitive circuit nodes on the accelerator system. After the fault and failure model is established, the start signal is pulled high to start the CNN accelerator module. The weight data of the convolutional and fully connected layers is loaded from on-chip / off-chip storage into the corresponding modules. The input image is loaded from off-chip storage into the sliding window module via the AXI bus interface. After all rounds of inference are completed, the accuracy and precision are transmitted to the host computer via the JTAG interface for post-processing.

[0044] A general-purpose matrix multiplication circuit from the benchmark test set was used as the target circuit to ensure the functional correctness of the verification platform. Matrix multiplication, which multiplies two matrices, shares the same computational principle and highly similar structure as the fully connected layer of a CNN accelerator. Matrix multiplication also involves numerous multiplication-addition operations, similar to the computational characteristics of convolutional layers. For a given input vector, the matrix multiplication output is fixed, making it suitable for performing small-scale matrix multiplication operations, comparing the output results for errors, and monitoring system functionality in real time.

[0045] When executing the FF resource fault analysis process, the introduced fault location is refreshed at the next clock cycle. First, the trigger signal names of each module are extracted from the netlist. The circuit inputs are read from the convolutional layer weight file, the fully connected layer weight file, and the input image file. Initial values ​​are assigned to the reset and enable signals. After several cycles, the reset is released, the enable signal is pulled high, and the start_cnn signal is pulled high to start the accelerator. During device operation, a signal counter determines whether all inputs have been loaded. During the calculation process of the corresponding module in the network layer, the moment when the neural network accelerator is subjected to a transient disturbance is selected. A list of the logic values ​​of all FFs in the active module at any given moment is derived, forcing the logic state of the target FF within the current cycle. After 1ns, the logic state is released and the sampling edge of the next cycle arrives. The values ​​of multiple FF signals can be perturbed simultaneously to analyze the injection of multiple transient disturbances. The transient disturbance evaluation design also uses a matrix multiplication benchmark test circuit to facilitate observation of the output response to FF transient disturbances. The test stimulus is generated by a Python script.

[0046] The statistical data are divided into three categories based on the degree of accuracy degradation of the neural network accelerator: mild degradation, moderate degradation, and severe degradation. An accuracy between 80% and 100% is classified as mild degradation, and a small decrease in CNN accuracy within this range is acceptable. An accuracy between 10% and 80% is classified as moderate degradation, indicating that soft errors have significantly impacted network performance, resulting in a significant decrease in accuracy. An accuracy below 10% is classified as severe degradation, indicating that the CNN accelerator is no longer able to perform its recognition function properly, and even circuit functions have failed.

[0047] Example 3 In order to further explain the technical solution of the present invention, it is described through the following examples: According to the experimental results of Lenet5 convolution module Figure 3As shown. The horizontal axis is the number of experimental rounds, and the number of fault sites inside the convolution module doubles in each round. A blue dot in each column represents an experiment, and there are 50 blue dots in each round of experiments. The darker the blue dot, the denser the blue dots are near the accuracy range. The scatter plot shows the distribution of the neural network recognition accuracy during the experiment. As the number of soft fault sites inside the convolution module continues to increase, the distribution center of gravity of the dark blue area gradually moves downward, indicating that when soft errors gradually accumulate in the convolution module, the accuracy of the neural network gradually decreases, and the deterioration of the module has a certain degree of impact on the overall performance of the network. For example: According to the distribution of experimental results of the Lenet5 pooling module, Figure 4 As shown, the meaning of the horizontal and vertical axes is the same as Figure 3 As can be seen from the figure, the recognition accuracy of each round of experiments is concentrated above 90%, which is close to the accuracy when there are no soft fault sites. As the number of soft fault sites increases, a small number of cases with a significant drop in accuracy appear, but the proportion is still very small, reflecting that the pooling module is relatively insensitive to soft fault sites. For example: According to the experimental results of the Lenet5 fully connected module, the distribution is as follows Figure 5 As shown in the figure, similar to the distribution of output results from the convolutional module, the densely distributed area of ​​accuracy gradually shifts downward as the number of soft fault locations increases. In the fully connected module, almost every 50 experimental results in each round produced a certain number of output errors, indicating that the key configuration bits of the fully connected module are easily affected, resulting in changes in circuit functionality. All soft fault information can be fully located and analyzed.

[0048] Based on the degradation model, the output results of the neural network are divided into three categories: mild degradation, moderate degradation, and severe degradation for analysis. CRAM soft fault analysis experiments are carried out on convolution, pooling, and fully connected modules, and the distribution and proportion of classification results are analyzed. Combining the characteristics of the neural network model and the circuit architecture, the impact mechanism of soft faults on different circuit modules is studied, and the reasons for the distribution pattern of the output results of each module are revealed. The average sensitivity ( ) indicator to measure the CRAM fault sensitivity of the circuit module, where σ is a correction factor that depends on the specific device and circuit scale. N AVE_error It represents the average number of errors observed in the final output of the circuit in each round of experiments. To avoid extreme cases, the maximum and minimum accuracy values ​​in each round of experiments are removed during calculation, and only the middle 48 groups of data are counted. N inject_bit Indicates the number of faulty bits. Average sensitivity θ AVE_cramIndicates the number of times the output misclassification increases with each 1-bit soft fault introduced in this round of experiments. The larger the value, the more sensitive the corresponding module is to soft faults and the more critical it is in the entire CNN accelerator circuit. The key FF information of each module was obtained through the experiment. ) indicator measures the module’s FF error sensitivity. Where σ has the same meaning as above, , . p critical_FF It represents the probability that any FF in the module is a critical FF. A critical FF is defined as an FF that can cause output errors when a soft fault occurs. N critical_FF is the critical FF number; N total_FF The total number of FFs contained in the module. p error_new is the fault output rate, which means the proportion of the newly added error outputs to the total outputs when an error occurs in the result; N error_new is the average number of new errors; N total_output The total number of single outputs. P error_FF The probability that an FF failure will lead to an error in the final result. The reinforcement object and method are determined based on the calculation results and the actual working conditions of the neural network circuit.

[0049] Neural network accelerator soft fault site formation, impact and repair method Figure 6 As shown in the figure, the CNN accelerator is first used as the device under test (DUT). Software tools are used to locate the coordinates of key layers in the network model, and the location information is stored in off-chip memory. Target units are flipped to create soft fault locations, and a fault impact model for sensitive accelerator nodes is established. Based on feedback signals, if the flip fails, the accelerator is repositioned. If the flip succeeds, the CNN accelerator is run to perform inference. After execution, the accuracy and precision are calculated, and the results are transmitted to the host computer for data post-processing.

[0050] Through circuit netlist conversion and analysis tools, fault tolerance protection is designed based on fault characteristics to reduce the impact and transmission of faults, and to protect the overall functional stability of the system and the accuracy of image recognition. Figure 7 The figure shows a method for establishing a fault-tolerant design mechanism based on radiation-sensitive critical paths. Based on the module resource characteristics of different network layers mapped to the hardware accelerator, the target sensitive resources in the fault model are fault-tolerantly designed in combination with real-time monitoring of the operation process, and the fault-tolerant CNN accelerator netlist is derived to achieve high-reliability neural network design. The neural network accelerator soft high-reliability circuit netlist is converted as follows: Figure 8As shown in the figure. Introduce faults into the input data stream, track the transmission path of the erroneous data during the accelerator operation and mark it. As the erroneous data accumulates and propagates, it eventually affects the output data. Through fault analysis and analysis of the criticality of this impact on the overall system, a critical path list is obtained. Based on the critical path list, the imported original circuit netlist is designed for fault tolerance and a highly reliable circuit netlist is generated. The repair ideas for the soft fault sites of the neural network accelerator are as follows: Figure 9 As shown in the figure, the recorded fault location coordinates are imported from off-chip storage and the corresponding location is flipped to repair the fault. By effectively repairing sensitive nodes and eliminating the impact of the fault, a highly reliable network architecture is established. The system determines the success of the repair by testing the functionality of the repaired CNN accelerator. If a functional fault cannot be repaired by fault location, the network model is immediately reloaded to restore the network to its original state.

[0051] The resource consumption and failure rate of the neural network accelerator's high-reliability technology are compared in Table 1. The overall resource consumption of the present invention can be as low as 1.2 times that of the standard design, while the system failure rate is <<0.1%, which is superior to the traditional full TMR design in many aspects. Figure 10 shown.

[0052] Table 1 Comparison of resource consumption and failure rate effects of high-reliability technologies for neural network accelerators

[0053] Based on the netlist conversion and analysis tools, determine the characteristics of the operation circuit and the output location of the operation results in the key process. Design the operation detection state machine for the key operation nodes of the neural network, such as Figure 11 As shown. By adding fault-tolerant logic to the core status register, generating a status abnormality flag, and combining local resource reset technology to achieve key node status protection. The circuit operation results are verified, and repeated calculations or resource-saving inverse operation verification are used for the difference results to generate a flag bit for the operation difference, as shown Figure 12 As shown. Combine dynamic reconstruction and real-time refresh technology to achieve data fault tolerance of the computing circuit. Through algorithm, circuit, and system-level fault tolerance technology, and using the model to infer the accuracy change law, the soft fault pre-assessment technology caused by the radiation of the neural network system and the protection efficiency are improved. Design a high-reliability neural network accelerator to judge the nature of the fault according to the flag bit. If the abnormality cannot be resolved, dynamic reconstruction and local reset technology are used to achieve controllable impact of more than 90% of single fault sites and realize on-orbit self-repair of error faults. This technology is different from traditional refresh, which must be a global refresh and reconfiguration, resulting in a high time cost. The present invention can generate a fault flag signal for the fault, enabling the system to refresh in real time, dynamically reconstruct, and reset some resources. It has high flexibility and low time cost.

[0054] The results of this invention are fundamental to advancing the design of highly reliable neural network accelerators, are highly forward-looking, and have strong application value. This invention breaks through key technologies for radiation hardening of neural network systems, meeting the nation's demand for advanced artificial intelligence technology in independently controllable equipment.

[0055] Example 4 In addition, the present invention also discloses a neural network accelerator circuit fault detection and repair system for radiation environment applications, comprising: a critical path determination module, the critical path determination module being used to determine a critical path list of a neural network accelerator circuit by introducing a fault location method; a fault-tolerant design module, the fault-tolerant design module being used to implement fault-tolerant design on the critical path list, generate a fault-tolerant CNN accelerator netlist, perform circuit operation result verification during operation, detect and mark discrepancies in the results, and generate a fault flag; The fault repair module is used to solve the soft fault by repairing the site according to the fault flag bit. If the fault cannot be repaired, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

[0056] In addition, a schematic diagram of a terminal device is provided in one embodiment of the present invention. The terminal device in this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of each of the aforementioned method embodiments are implemented. Alternatively, when the processor executes the computer program, the functions of each module / unit in each of the aforementioned device embodiments are implemented.

[0057] The computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to accomplish the present invention.

[0058] The terminal device may be a computing device such as a desktop computer, a notebook computer, a PDA, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0059] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0060] The memory may be used to store the computer programs and / or modules, and the processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory.

[0061] If the module / unit integrated in the terminal device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the process steps in the above-mentioned method embodiments by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals. The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for detecting and repairing circuit faults in a neural network accelerator for applications in radiation environments, characterized in that: The following steps are involved: Determine the critical path list of neural network accelerator circuit by introducing the fault location method; Implementing fault-tolerant design on the critical path list to generate a fault-tolerant CNN accelerator netlist, performing circuit operation result verification during operation, detecting and marking discrepancies in the results, and generating a fault flag; According to the fault flag, the soft fault is resolved by repairing the site. If the fault cannot be repaired, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

2. The method for detecting and repairing circuit faults in a neural network accelerator for radiation environment applications according to claim 1, characterized in that: The method of introducing fault locations to determine the critical path list of the neural network accelerator circuit is specifically as follows: S11: Initialization and data preparation for CRAM and FF resource fault analysis. Specifically, the CPU control interface reads the target unit coordinates from the storage and prepares data such as weights and input images. At the same time, FF analysis also needs to extract the trigger signal name and initialize the reset and enable signals to ensure that the system is in the correct state. S12: Enter the fault introduction and system operation phase. Specifically, in CRAM analysis, a fault is introduced based on coordinates and system evaluation is initiated. In FF analysis, the fault location is refreshed, the system is started, and the FF logic state is forced to change at a selected moment to simulate a transient fault. Changes in system behavior are observed to assess the fault impact. S13: Result analysis and data output phase. Specifically, CRAM analysis transmits accuracy and precision to the host computer via the JTAG interface for evaluation. FF analysis exports a list of FF logic values ​​to analyze changes in system behavior after the fault is introduced. S14: Determine the critical path list of the neural network accelerator circuit by analyzing the output behavior of the circuit under different fault conditions.

3. The method for detecting and repairing circuit faults in a neural network accelerator for radiation environment applications according to claim 2, characterized in that: In the process of introducing fault sites, the values ​​of multiple CRAMs or FFs are disturbed at the same time, and the impact of the introduction of multi-site disturbances on the circuit is analyzed.

4. The method for detecting and repairing circuit faults in a neural network accelerator for radiation environment applications according to claim 1, characterized in that: When counting the critical path list of the neural network accelerator circuit, the results are divided into mild degradation, moderate degradation and severe degradation according to the degree of accuracy degradation of the neural network accelerator. Among them, the accuracy between 80% and 100% is mild degradation, the accuracy between 10% and 80% is moderate degradation, and below 10% is severe degradation.

5. The method for detecting and repairing circuit faults in a neural network accelerator for radiation environment applications according to claim 1, characterized in that: The implementation of the fault-tolerant design includes designing an operation detection state machine, adding fault-tolerant logic to a core state register, and generating a state abnormality flag.

6. The method for detecting and repairing circuit faults in a neural network accelerator for radiation environment applications according to claim 1, characterized in that: The method of resolving a soft fault by repairing a site specifically includes: importing the recorded coordinates of the fault site from an off-chip storage, and flipping the corresponding site to repair the fault.

7. A neural network accelerator circuit fault detection and repair system for radiation environment applications, characterized in that: include: a critical path determination module, the critical path determination module being used to determine a critical path list of a neural network accelerator circuit by introducing a fault location method; a fault-tolerant design module, the fault-tolerant design module being used to implement fault-tolerant design on the critical path list, generate a fault-tolerant CNN accelerator netlist, perform circuit operation result verification during operation, detect and mark discrepancies in the results, and generate a fault flag; The fault repair module is used to solve the soft fault by repairing the site according to the fault flag bit. If the fault cannot be repaired, the network model is reloaded and the affected local resources are dynamically reconstructed or reset to complete self-repair.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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