Test method and test device

Abstract

The invention discloses a test method and a test device. The testing method is applied to the testing device, the testing device is used for testing a three-dimensional stacked chip, the stacked chip comprises a chip set, one chip set comprises a storage crystal grain and a logic crystal grain which are stacked up and down, the other side of a substrate is provided with a power supply end, a power supply feedback end, a grounding end and a grounding feedback end, and the testing device comprises a testing plate. The test board comprises a power supply pin and a grounding pin, the power supply pin of the test board is used for being in butt joint with the power supply end of the stacked chip, and the grounding pin of the test board is used for being in butt joint with the grounding end of the stacked chip; the test method comprises the following steps: providing a working instruction for a to-be-tested chip set, providing a standby instruction for other chip sets, providing an electric signal for a power supply end, forming a feedback signal by the electric signal through the to-be-tested chip set, and judging whether the to-be-tested chip set is qualified or not based on the feedback signal. According to the technical scheme, the three-dimensional stacked package power supply current can be effectively detected, and it is guaranteed that the detection work is smoothly carried out.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a testing method and a testing device. Background Art

[0002] With the widespread application of AI (Artificial Intelligence) technology in various industries, many application scenarios such as generative artificial intelligence, cloud big data, smart education, digital finance, and autonomous driving are booming. The market demand for AI chips continues to rise, ushering in a period of rapid development.

[0003] To meet the computing power demands of the exponential growth in training model size, AI chips are constantly being upgraded. This is driven by increasing chip size and packaging complexity. Furthermore, three-dimensional stacked packaging has emerged. By stacking chips vertically, 3D stacked packaging reduces the footprint of a single die and allows for the integration of more die both vertically and horizontally. However, this also increases the complexity of 3D stacked AI chips, significantly increasing power consumption from the mainstream 300 watts to over 3,000 watts. This increases operating current, even exceeding the detection limit, making effective detection difficult. Summary of the Invention

[0004] In view of the defects in the prior art, the present invention provides a testing method that can effectively deal with the detection of three-dimensional stacked packages and ensure that the detection work proceeds smoothly.

[0005] The present invention provides a testing method, wherein the testing device is used to test three-dimensional stacked chips, wherein the stacked chips include a plurality of chipsets laid flat on one side of a substrate, wherein the chipsets include memory crystals and logic crystals stacked up and down, wherein the logic crystals and the memory crystals are electrically connected, and a power supply terminal, a power supply feedback terminal, a ground terminal, and a ground feedback terminal are provided on the other side of the substrate, wherein the power supply terminal, the power supply feedback terminal, the ground terminal, and the ground feedback terminal are respectively passed through the substrate and electrically connected to each of the chipsets, and the testing device includes a testing board, wherein the testing board includes a power supply pin, a power supply feedback pin, a ground feedback pin, and a ground pin, wherein the power supply pin of the testing board is used to connect to the power supply terminal of the stacked chip, the ground pin of the testing board is used to connect to the ground terminal of the stacked chip, the power supply feedback pin is connected to the power supply feedback terminal, and the ground pin is connected to the ground feedback terminal;

[0006] The test method includes:

[0007] Providing a working instruction to the chipset under test and providing a standby instruction to the remaining chipsets, so that the chipset under test operates and the remaining chipsets are on standby;

[0008] An electrical signal is provided to the power supply terminal, the electrical signal forms a feedback signal via the chipset to be tested and a power supply feedback terminal, and whether the chipset to be tested is qualified is determined based on the feedback signal.

[0009] In one aspect, after providing working instructions to the chipset under test and providing standby instructions to the remaining chipsets, the method includes:

[0010] Provide work instructions to the remaining chipsets respectively, and complete the testing of the remaining chipsets in turn.

[0011] In one aspect, the test board includes a test line and a feedback resistor, the test line is connected to the power pin, and the test board also includes a first feedback line and a second feedback line, the first feedback line is connected to one end of the feedback resistor, and the second feedback line is connected to the other end of the feedback resistor;

[0012] The step of providing an electrical signal to the power supply terminal, the electrical signal forming a feedback signal via the chipset to be tested and the power supply feedback terminal, and determining whether the chipset to be tested is qualified based on the feedback signal comprises:

[0013] Providing a test current to the test line, wherein the test current generates a feedback voltage through the feedback resistor;

[0014] acquiring the feedback voltage based on the first feedback line and the second feedback line;

[0015] The feedback voltage is compared with a preset voltage range. If the feedback voltage is within the preset voltage range, it is determined that the chip group to be tested is qualified.

[0016] In one aspect, the test board further includes a first amplifier and a first processor, the first feedback line and the second feedback line are connected to the input end of the first amplifier, the output end of the first amplifier is connected to the first processor, and the preset voltage range is stored in the first processor.

[0017] In one aspect, the test board further includes a power feedback line and a ground feedback line, the power feedback line is connected to the power feedback pin, the ground feedback line is connected to the ground feedback pin, and the test current passes through the chipset to be tested to the power feedback terminal to generate a voltage signal;

[0018] After the step of providing a test current to the test line, the method further includes:

[0019] acquiring the voltage signal based on the power feedback line;

[0020] The voltage signal is converted into a feedback current, and the feedback current is compared with a preset current range. If the feedback current is within the preset current range, it is determined that the chip group to be tested is qualified.

[0021] In one aspect, the test board further includes a second amplifier and a second processor, the input end of the second amplifier is connected to the power feedback line and the ground feedback line, the output end of the second amplifier is connected to the second processor, and the preset current range is stored in the second processor.

[0022] In one aspect, the test board further includes a third feedback line, one end of the third feedback line is connected to the test line, and the other end of the third feedback line is connected to the power feedback line.

[0023] In one aspect, the test board also includes a first power supply layer and a second power supply layer, and multiple first power supply layers and multiple second power supply layers are provided, multiple first power supply layers are stacked, and multiple second power supply layers are stacked. An insulating layer is provided between two adjacent first power supply layers and between two adjacent second power supply layers. The first power supply layer is used to supply power to the storage grains, and the second power supply layer is used to supply power to the logic grains.

[0024] In addition, in order to solve the above problems, the present application also provides a testing device, which adopts the testing method as described above. The testing device also includes a display end, which is connected to the test board and is used to display the test results.

[0025] The beneficial effects of the present invention are reflected in: through a rotating test scheme that provides working instructions to the chipset under test and the remaining chipsets are on standby, only one chipset is activated at a time, while the remaining chipsets are in standby mode. The power consumption of a single chipset is significantly lower than the overall power consumption. The test equipment only needs to provide the operating current of a single chipset, reducing the total power consumption of multiple chipsets simultaneously supported, significantly reducing the instantaneous power supply pressure of the test board, and avoiding test failures due to current overload. It can effectively handle the testing of three-dimensional stacked packages and ensure smooth testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0027] Figure 1 Schematic diagram of the steps of the testing method of the present invention;

[0028] Figure 2 Schematic diagram of the steps for completing the remaining chipset tests in the testing method of the present invention;

[0029] Figure 3 This is a flow chart of the steps of judging whether a chipset is qualified based on feedback voltage in the testing method of the present invention;

[0030] Figure 4 This is a flow chart of the steps of judging whether a chipset is qualified based on feedback current in the testing method of the present invention;

[0031] Figure 5 Schematic diagram of the circuit of the test board in the test method of the present invention.

[0032] Description of the drawings: 100, power supply; 200, test line; R, feedback resistor; 310, first feedback line; 320, second feedback line; 340, power feedback line; 350, ground feedback line; U1, first amplifier; U2, second amplifier; 410, first processor; 420, second processor; 510, power pin; 520, ground pin; 530, power feedback pin; 540, ground feedback pin. DETAILED DESCRIPTION

[0033] The following embodiments of the technical solution of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention.

[0034] It should be noted that, unless otherwise specified, the technical or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0035] Please refer to Figure 1 and Figure 5 As shown, an embodiment of the present invention provides a testing method, which is applied to a testing device, and the testing device is used to test three-dimensional stacked chips, namely 3D stacked chips. The stacked chip includes a plurality of chipsets laid flat on one side of a substrate, a chipset including memory chips and logic chips stacked up and down, the logic chips and the memory chips being electrically connected, a power supply terminal, a power supply feedback terminal, a ground terminal, and a ground feedback terminal being provided on the other side of the substrate, the power supply terminal, the power supply feedback terminal, the ground terminal, and the ground feedback terminal being respectively passed through the substrate and electrically connected to each chipset, the testing device includes a test board, the test board includes a power pin 510 and a ground pin 520, the power pin 510 of the test board is used to connect to the power supply terminal and the power supply feedback terminal of the stacked chip, the ground pin 520 of the test board is used to connect to the ground terminal and the ground feedback terminal of the stacked chip, the power feedback pin is connected to the power feedback terminal, and the ground pin is connected to the ground feedback terminal.

[0036] The test device can be ATE (Automatic Test Equipment), a key piece of equipment used for automated testing of electronic products such as semiconductor chips, electronic components, and circuit boards. ATE is widely used in chip design, wafer fabrication, packaging testing, and other aspects of electronic product production. Its core function is to apply electrical signals, power, or stimuli to measure and analyze the response of the device under test to determine whether it meets design specifications or performance requirements.

[0037] The memory die and logic die are vertically electrically connected via through-silicon vias (TSVs) or copper pillars, forming a three-dimensional stacked structure. The power and ground terminals of the chipset can be understood as solder balls. The power and ground terminals penetrate the substrate through metal traces or vias and are electrically connected to the die of each chipset to achieve signal transmission. The power pin 510 is used to connect the power terminal of the stacked chip to transmit power and detection signals. The ground pin 520 is used to connect the ground terminal of the stacked chip to form a current loop and provide a stable reference ground potential. The test board and the stacked chips are electrically connected through pin docking.

[0038] Test methods include:

[0039] In step S10, the tester provides operating instructions to the chipset under test and standby instructions to the remaining chipsets, putting the chipset under test into operation and the remaining chipsets into standby mode. The tester sends control signals to the power supply terminal of the substrate via the test board's power pin 510. These signals are transmitted via internal wiring within the substrate to the configuration registers of each chipset. Based on the received instructions, the configuration registers control the power supply 100 of the corresponding chipset. For the chipset under test, the registers turn on power supply 100, putting the logic and memory chips into an operating state, such as a core voltage of 0.7V and an operating current of 500A. For the remaining chipsets, the registers cut off or significantly reduce the power supply, placing them in a low-power standby state with a current close to 0A.

[0040] In step S20, an electrical signal is provided to the power supply terminal. This signal is then fed back to the power supply feedback terminal of the chipset under test to form a feedback signal. The test device then determines whether the chipset under test is qualified based on the feedback signal. The test device supplies an operating voltage to the chipset under test via the power supply terminal, and the current forms a loop through the logic and memory chips of the chipset under test. The electrical characteristics of the chipset during operation, such as voltage fluctuations and current changes, are fed back to the power supply feedback pin of the test board.

[0041] The deviation between the actual voltage and the target value must be within the allowable range. If so, the chipset is considered qualified. The operating current should also meet the chipset design specifications. If it exceeds the design specifications, the chipset is considered qualified. Otherwise, the chipset is considered unqualified. For example, a current outside the specification range may indicate a short circuit or open circuit fault.

[0042] Further analysis shows that the technical solution of this application adopts time-sharing testing, which makes the signal characteristics of the problem chipset more prominent and facilitates rapid fault location. For example, if the feedback voltage of a chipset is abnormal, the group is directly judged as unqualified.

[0043] In this embodiment, a rotating test scheme is implemented, whereby only one chipset is activated at a time, while the remaining chipsets remain in standby mode, providing operating instructions to the chipset under test. The power consumption of a single chipset is significantly lower than the overall power consumption. The test equipment only needs to provide the operating current of a single chipset, reducing the total power consumption of multiple chipsets simultaneously supported. This significantly reduces the instantaneous power supply pressure on the test board and avoids test failures caused by current overload. This system can effectively handle the testing of three-dimensional stacked packages, ensuring smooth testing.

[0044] In addition, the requirements for the test device of this application are also reduced. The test device only needs to be able to measure a single group of chipsets, that is, to meet the test conditions of a logic chip and a storage chip to complete the test, which reduces the requirements for the test device and reduces the test cost.

[0045] See Figure 2 As shown, after the steps of providing working instructions to the chipset to be tested and providing standby instructions to the other chipsets, the method includes:

[0046] In step S30, operating instructions are provided to the remaining chipsets, allowing testing of the remaining chipsets to be completed in sequence. By cyclically activating the remaining chipsets and testing them sequentially in step S30, comprehensive testing of all chipsets is achieved. After completing testing of the current chipset under test, the testing device sends a standby instruction to the chipset, disconnecting its operating power supply 100 and restoring it to a low-power state.

[0047] According to a preset sequence, such as chipset 1→2→3→...→N, the test device sends a working instruction to the power supply terminal of the substrate through the power pin 510 of the test board to activate the next chipset to be tested.

[0048] For example, if there are 6 chipsets in total, and the initial chipset to be tested is 1, after the test is completed, the test device will activate chipset 2 and keep chipsets 1, 3 to 6 in standby mode.

[0049] For each activated chipset, the operation of step S20 is repeated: providing operating voltage, collecting voltage, feeding voltage, judging whether the chipset is qualified; and recording test data, such as power consumption curve and signal quality parameters.

[0050] Furthermore, by rotating activation, each chipset is independently tested, avoiding interference when multiple chipsets are operating simultaneously and improving fault detection rates. For example, if a chipset has a hidden short circuit, it may be masked by the normal current flow of other chipsets when multiple chipsets are operating simultaneously. Time-sharing testing can accurately locate the fault.

[0051] Furthermore, the test board only needs to support the operating current of a single chipset, such as 500A, at a time. There is no need for the ATE equipment to provide a total current covering all chipsets, such as 3000A, thus reducing hardware costs. Furthermore, the test board's heat dissipation design only needs to consider the power consumption of a single chipset, such as 550W, rather than the overall 3300W, simplifying the cooling system complexity.

[0052] In one embodiment of the present application, the test board includes a test line 200 and a feedback resistor R, the test line 200 is connected to the power pin 510, and the test board also includes a first feedback line 310 and a second feedback line 320, the first feedback line 310 is connected to one end of the feedback resistor R, and the second feedback line 320 is connected to the other end of the feedback resistor R; the test line 200 is a physical channel connecting the internal circuit of the test board with the power pin 510, and is used to transmit test current and control signals. The power pin 510 is directly connected to the power end of the stacked chip, and the electrical signal of the test line 200 is injected into the chip group under test. The feedback resistor R is set on the test line 200, and the current signal is converted into a voltage signal using Ohm's law, which is convenient for high-precision measurement. 反馈 =I*R,V 反馈 is the feedback voltage, I is the test current, and the value of the feedback resistor R is known. For example, if the test current is 500A and the feedback resistor R is 0.001Ω, the feedback voltage is 0.5V.

[0053] Feedback resistor R should be a precision component with a low temperature coefficient and high power tolerance to avoid resistance drift due to heat generation that affects measurement accuracy. The resistance is typically in the milliohm range, balancing the current measurement range and voltage signal resolution.

[0054] The first feedback line 310 is connected to the input end of the feedback resistor R to collect the voltage V1 at the front end of the resistor. The second feedback line 320 is connected to the output end of the feedback resistor R to collect the voltage V2 at the rear end of the resistor.

[0055] Feedback voltage V 反馈 =V1-V2=I*R, eliminating the resistance voltage drop of the test line 200 itself, that is, only the real voltage across the feedback resistor R is detected.

[0056] See Figure 3 As shown, in this application, an electrical signal is provided to the power supply terminal, and the electrical signal forms a feedback signal through the chipset to be tested and the power supply feedback terminal. The steps of determining whether the chipset to be tested is qualified based on the feedback signal include:

[0057] In step S210 , a test current is provided to the test line 200 . When the test current flows through the feedback resistor R, a feedback voltage is generated according to Ohm's law.

[0058] In step S220, a feedback voltage is obtained based on the first feedback line 310 and the second feedback line 320. The first feedback line 310 and the second feedback line 320 transmit the signal across the feedback resistor R to the first amplifier U1. The first amplifier U1 amplifies the microvolt-level signal to a processable range (e.g., 0-5V), and the gain is dynamically adjusted based on the resistance value of the feedback resistor R. The amplified analog signal is converted to a digital value by the ADC and transmitted to the first processor 410.

[0059] Step S230 : comparing the feedback voltage with a preset voltage range. If the feedback voltage is within the preset voltage range, it is determined that the chip set to be tested is qualified.

[0060] See Figure 5 As shown, in one embodiment of the present application, the test board also includes a first amplifier U1 and a first processor 410. The first feedback line 310 and the second feedback line 320 are connected to the input of the first amplifier U1, and the output of the first amplifier U1 is connected to the first processor 410. The first processor 410 stores a preset voltage range. The first feedback line 310 and the second feedback line 320 are respectively connected to the two ends of the feedback resistor R to collect the voltage difference across the resistor. These two lines are connected to the input of the first amplifier U1 in a differential manner. The first amplifier U1 amplifies the weak voltage difference to a range suitable for processing by the processor. The amplified signal is transmitted to the first processor 410, and its built-in analog-to-digital converter converts the analog signal into a digital value. The first processor 410 compares the digitized voltage value with the preset voltage range stored internally. If it is within the range, it indicates that the actual operating voltage of the chipset is stable and meets the design requirements. If it is outside the range, it may indicate a power supply anomaly or internal chip leakage.

[0061] See Figure 4 As shown, the test board also includes a power feedback line and a ground feedback line. The power feedback line is connected to the power feedback pin, and the ground feedback line is connected to the ground feedback pin. The test current passes through the chipset to be tested to the power feedback terminal to generate a voltage signal.

[0062] After the step of providing the test current to the test line, the step further includes:

[0063] Step S240: A voltage signal is acquired based on a power feedback line. One end of the power feedback line is connected to the power feedback terminal of the stacked chip, and the other end is connected to the input of the second amplifier U2 on the test board. The power feedback terminal directly detects the terminal node of the actual output current of the chip, and in real time, collects the actual operating voltage flowing through the chipset under test, i.e., the voltage signal, which reflects the electrical status of the logic and memory chips within the chip.

[0064] Step S250, convert the voltage signal into feedback current, compare the feedback current with the preset current range, and if the feedback current is within the preset current range, the chip set to be tested is determined to be qualified. The preset current range is, for example, 500A±5%, i.e., 475A~525A. If the actual feedback current exceeds this range, it is determined that the chipset has a short circuit or open circuit fault. For example, if the measured feedback current is 530A, which exceeds the upper limit, it may indicate an internal short circuit in the chip. The equivalent impedance of the chipset is a known design parameter, which is calculated by formula I 电流 =V 电压 / R 芯片 Calculate the feedback current, where V 电压 It is the voltage signal collected from the power feedback line, I 电流 is the feedback current, R 芯片 is the equivalent impedance of the chipset. When both the current and voltage meet the preset range, the chipset is considered qualified; otherwise, it is marked as unqualified.

[0065] The test board further includes a second amplifier U2 and a second processor 420. The input of the second amplifier U2 is connected to a power feedback line and a ground feedback line, and the output of the second amplifier U2 is connected to the second processor 420. The second processor 420 stores a preset current range. The input of the second amplifier U2 is connected to the power feedback line and the ground feedback line, respectively. The power feedback line collects the actual operating voltage of the chipset under test, and the ground feedback line is connected to the ground feedback terminal of the stacked chips to provide a reference potential.

[0066] The second processor 420 converts the amplified analog voltage signal into a digital value. By comparing the feedback current with the preset current range, it outputs a pass or fail judgment result. The data is synchronized with the first processor 410 to achieve a combined current-voltage judgment.

[0067] Combine the test line, ground line, power feedback line, and ground feedback line to form a complete Kelvin four-wire current detection path. The power end and ground end are connected as current lines, and the power feedback end and ground feedback end are connected as sensing lines.

[0068] In one embodiment of the present application, the test board also includes a first power supply layer and a second power supply layer. There are multiple first power supply layers and multiple second power supply layers. Multiple first power supply layers are stacked, and multiple second power supply layers are stacked. An insulating layer is provided between two adjacent first power supply layers and between two adjacent second power supply layers. The first power supply layer is used to supply power to the storage crystal grains, and the second power supply layer is used to supply power to the logic crystal grains. The first power supply layer is made of copper foil and is stacked to provide power to the storage crystal grains. The second power supply layer is also composed of copper foil stacked, independent of the first power supply layer, and is used to provide core power to the logic crystal grains.

[0069] Insulation layer: 50-100μm thick, isolates adjacent power supply layers to prevent short circuits. Storage chip power supply focuses on current stability and must support the transient current requirements of high-frequency data reading and writing. Logic chip power supply focuses on voltage accuracy and must suppress power supply noise from interfering with the computing core.

[0070] It can be seen from this that the power supply layers of the memory die and the logic die are physically isolated to avoid mutual interference.

[0071] Furthermore, the large copper foil area of ​​the power supply layer provides thermal conductivity, allowing the power consumption of the logic and memory chips to be quickly transferred through the test board. The stacked structure ensures more even heat distribution, preventing local overheating and improving test stability. Each power supply layer can be independently configured with voltage to accommodate chips from different process nodes. The number of power supply layers can be dynamically adjusted based on chip power consumption to support the testing needs of future higher-power chips.

[0072] The present application also provides a testing device, which adopts the testing method as described above. The testing device also includes a display terminal, which is connected to the testing board and is used to display the test results.

[0073] The specific embodiments and beneficial effects of the testing device in the present invention can be found in the above-mentioned testing method, which will not be described in detail here.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

Claims

1. A testing method, characterized in that: The testing method is applied to a testing device, which is used to test three-dimensional stacked chips. The stacked chips include a plurality of chipsets laid flat on one side of a substrate. One of the chipsets includes memory grains and logic grains stacked up and down, and the logic grains and the memory grains are electrically connected. A power supply terminal, a power supply feedback terminal, a ground terminal, and a ground feedback terminal are provided on the other side of the substrate. The power supply terminal, the power supply feedback terminal, the ground terminal, and the ground feedback terminal are respectively passed through the substrate and electrically connected to each of the chipsets. The testing device includes a testing board, and the testing board includes a power pin, a power feedback pin, a ground feedback pin, and a ground pin. The power pin of the testing board is used to connect to the power supply terminal of the stacked chip, and the ground pin of the testing board is used to connect to the ground terminal of the stacked chip. The power feedback pin is connected to the power feedback terminal, and the ground pin is connected to the ground feedback terminal. The test method includes: Providing a working instruction to the chipset under test and providing a standby instruction to the remaining chipsets, so that the chipset under test operates and the remaining chipsets are on standby; An electrical signal is provided to the power supply terminal, the electrical signal forms a feedback signal via the chipset to be tested and a power supply feedback terminal, and whether the chipset to be tested is qualified is determined based on the feedback signal.

2. The testing method according to claim 1, wherein: After providing working instructions to the chipset under test and providing standby instructions to the other chipsets, the method includes: Provide work instructions to the remaining chipsets respectively, and complete the testing of the remaining chipsets in turn.

3. The testing method according to claim 1, wherein: The test board includes a test line and a feedback resistor, the test line is connected to the power pin, the test board also includes a first feedback line and a second feedback line, the first feedback line is connected to one end of the feedback resistor, and the second feedback line is connected to the other end of the feedback resistor; The step of providing an electrical signal to the power supply terminal, the electrical signal forming a feedback signal via the chipset to be tested and the power supply feedback terminal, and determining whether the chipset to be tested is qualified based on the feedback signal comprises: Providing a test current to the test line, wherein the test current generates a feedback voltage through the feedback resistor; acquiring the feedback voltage based on the first feedback line and the second feedback line; The feedback voltage is compared with a preset voltage range. If the feedback voltage is within the preset voltage range, it is determined that the chip group to be tested is qualified.

4. The testing method according to claim 3, wherein: The test board also includes a first amplifier and a first processor. The first feedback line and the second feedback line are connected to the input end of the first amplifier. The output end of the first amplifier is connected to the first processor. The preset voltage range is stored in the first processor.

5. The testing method according to claim 3, wherein: The test board further includes a power feedback line and a ground feedback line, wherein the power feedback line is connected to the power feedback pin, and the ground feedback line is connected to the ground feedback pin, and the test current passes through the chipset to be tested to the power feedback terminal to generate a voltage signal; After the step of providing a test current to the test line, the method further includes: acquiring the voltage signal based on the power feedback line; The voltage signal is converted into a feedback current, and the feedback current is compared with a preset current range. If the feedback current is within the preset current range, it is determined that the chip group to be tested is qualified.

6. The testing method according to claim 5, characterized in that: The test board also includes a second amplifier and a second processor, the input end of the second amplifier is connected to the power feedback line and the ground feedback line, the output end of the second amplifier is connected to the second processor, and the preset current range is stored in the second processor.

7. The testing method according to claim 1, wherein: The test board also includes a first power supply layer and a second power supply layer. There are multiple first power supply layers and multiple second power supply layers. Multiple first power supply layers are stacked, and multiple second power supply layers are stacked. An insulating layer is set between two adjacent first power supply layers and between two adjacent second power supply layers. The first power supply layer is used to supply power to the storage grains, and the second power supply layer is used to supply power to the logic grains.

8. A testing device, characterized in that: The testing device adopts the testing method according to any one of claims 1 to 7. The testing device further comprises a display terminal connected to the testing board, and the display terminal is used to display the test results.

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