Signal test method and device, equipment and storage medium
By automatically extracting module connection relationships from the integrated circuit architecture connection table and generating test cases, the problem of low efficiency in control signal testing in integrated circuits is solved, and an efficient and accurate testing process is achieved.
Patent Information
- Application Number
- CN202510776083.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-09-16
AI Technical Summary
The testing efficiency of control signals in integrated circuits is low and it is easy to miss errors. The existing technology of manually writing test cases is time-consuming and error-prone.
By extracting module connection relationships from the integrated circuit architecture connection table, the target module is automatically found and test cases are generated. The module connection relationships and control signal information are used to automatically generate test cases, avoiding manual writing.
It improves the efficiency and accuracy of control signal testing, reduces the problem of module search omissions, and reduces the error rate of manually written test cases.
Smart Images
Figure CN120652256A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to signal testing methods, devices, equipment, and storage media. Background Art
[0002] In some integrated circuits, a large number of control signals are distributed. Control signals may include but are not limited to clock signals, reset signals, enable signals, etc. Take clock signals and reset signals as an example. Each clock signal may have its own corresponding clock signal attributes. Clock signal attributes include but are not limited to frequency, phase, duty cycle, etc. For example, for an integrated circuit used in the multimedia field, it may include a high-speed clock for the processor core and a low-speed clock for peripherals. Similarly, each reset signal may have its own corresponding reset signal attributes. Reset signal attributes include but are not limited to reset source, reset strategy, etc. For example, reset signal A is used to reset all modules in the integrated circuit (i.e., global reset), and reset signal B is used to reset some modules in the integrated circuit (i.e., local reset).
[0003] Based on the above description, it can be seen that the accuracy of control signals is closely related to the normal operation and fault recovery of integrated circuits. Therefore, it is necessary to test the reliability of control signals. However, due to the large number of control signals in integrated circuits, the workload of writing test cases is relatively large, which leads to relatively low control signal testing efficiency. Summary of the Invention
[0004] The present application provides a signal testing method, a signal testing device, an electronic device, and a computer-readable storage medium to at least solve the problem of low control signal testing efficiency in related technologies.
[0005] This application provides a signal testing method, including:
[0006] Extracting a module connection relationship of the integrated circuit from the integrated circuit architecture connection table, wherein the module connection relationship is used to represent a data flow path within the integrated circuit;
[0007] Searching for a target module serving as a data flow outlet in the integrated circuit based on the module connection relationship, and obtaining a control signal and control signal information of the target module from the integrated circuit architecture connection table, wherein the control signal is used to control the operation of the target module;
[0008] A test case for the target module is generated based on the control signal and control signal information of the target module, and the test case is run to test the control signal of the target module.
[0009] The present application also provides a signal testing device, comprising:
[0010] a connection relationship extraction module, configured to extract module connection relationships of an integrated circuit from an integrated circuit architecture connection table, wherein the module connection relationships are used to characterize a data flow path within the integrated circuit;
[0011] an information search module, configured to search for a target module serving as a data flow outlet in the integrated circuit based on the module connection relationship, and obtain a control signal and control signal information of the target module from the integrated circuit architecture connection table, wherein the control signal is used to control the operation of the target module;
[0012] The use case generation module is used to generate a test case of the target module according to the control signal and control signal information of the target module, and run the test case to test the control signal of the target module.
[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned signal testing methods when executing the computer program.
[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned signal testing methods are implemented.
[0015] In the technical solutions of some embodiments of the present application, by extracting the module connection relationship of the integrated circuit from the integrated circuit architecture connection table, the data flow path within the integrated circuit can be obtained, and the target module serving as the data flow outlet can be searched according to the data flow path. In this way, on the one hand, the target module can be automatically searched, and then test cases for the control signals and control signal information of the target module can be automatically generated, eliminating the need for manual test case writing, greatly improving test efficiency. In other words, it can solve the problem of relatively low control signal testing efficiency in some technologies. On the other hand, it can ensure search accuracy and avoid the problem of missing modules in the search. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0017] Figure 1 A schematic flow chart of a signal testing method provided in some embodiments of the present application;
[0018] Figure 2A partial schematic diagram of an integrated circuit architecture connection table provided for some embodiments of the present application;
[0019] Figure 3 A schematic diagram of a correspondence table provided for some embodiments of the present application;
[0020] Figure 4 A schematic diagram of a process for generating test cases provided in some embodiments of the present application;
[0021] Figure 5 A schematic diagram of a module of a signal testing device provided in some embodiments of the present application;
[0022] Figure 6 A schematic diagram of a module of an electronic device provided for some embodiments of the present application. DETAILED DESCRIPTION
[0023] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0024] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or precedence.
[0025] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0026] In this application, control signals refer to signals used to control the expected operation of an integrated circuit, such as clock signals, reset signals, interrupt signals, enable signals, etc. Testing control signals is essentially testing whether the control signals can control the integrated circuit to operate as expected. Specifically, testing of control signals may include, but is not limited to, the following aspects:
[0027] 1) Whether the control signals can control the integrated circuit as expected. For example, whether the clock signal can correctly drive the logic within each clock domain, and whether the reset signal can correctly reset all registers to their initial state when the integrated circuit is started.
[0028] 2) Whether the signal properties of the control signal (such as frequency, duty cycle, amplitude, etc.) are within the range allowed by the integrated circuit.
[0029] 3) The stability of the integrated circuit when control signals are abnormal. For example, whether the integrated circuit can continue to operate stably when the clock signal is jittery. Another example is the ability of the integrated circuit to recover when the control signal is lost.
[0030] 4) The possible operating states of the integrated circuit under the boundary conditions of the control signal. For example, the operating state of the integrated circuit at the maximum and minimum frequencies of the clock signal. Another example is the operating state of the integrated circuit under the minimum and maximum duration of the reset signal.
[0031] In practical applications, each control signal of an integrated circuit has one or more corresponding test cases. During the execution of the test cases, the amplitude, frequency, duration, sequence, etc. of the control signals can be controlled, or appropriate jitter can be added to the control signals. In this way, the test scenarios in 1) to 4) above can be simulated, and then it can be tested whether the integrated circuit can operate normally under the control of the control signals. For example, suppose there are clock signals A1, A2, and reset signal B1 in the integrated circuit, and the clock signal properties of clock signals A1 and A2 are different. Then, test cases a1 and a2 can be written for clock signal A1, test cases a3 and a4 can be written for clock signal A2, and test cases b1 to b5 can be written for reset signal B1. By running test cases a1 and a2, clock signal A1 can be tested, by running test cases a3 and a4, clock signal A2 can be tested, and by running test cases b1 to b5, reset signal B1 can be tested.
[0032] Currently, in some technologies, test cases for each control signal are manually written. However, some integrated circuits can have tens of thousands of control signals. Manually writing test cases is labor-intensive and time-consuming, leading to low control signal testing efficiency. Furthermore, it can easily lead to missed control signals, meaning some control signals may not have corresponding test cases, making it impossible to test these missing control signals.
[0033] Other technologies, such as those used to access, classify, and model control signals, can automate the generation of test cases, significantly improving control signal testing efficiency. However, these technologies require manual modification of test cases when the address space of individual IC modules changes, which also impacts testing efficiency. Furthermore, manual modification of test cases can introduce errors, reducing the reliability of control signal testing.
[0034] In view of this, the present application provides a signal testing method that can realize the automated generation and modification of test cases, improve the efficiency of test case writing and modification, and thus solve the problem of relatively low control signal testing efficiency in related technologies. At the same time, it can also avoid errors that may be introduced when manually writing or modifying test cases, and improve the reliability of control signal testing.
[0035] The signal testing method of the present application can be applied to electronic devices. The electronic devices may include but are not limited to tablet computers, laptop computers, desktop computers, servers, etc. Figure 1 , which is a flow chart of the signal testing method provided in some embodiments of the present application. Figure 1 In the signal testing method, the signal testing method includes the following steps:
[0036] Step S101 : extracting module connection relationships of an integrated circuit from an integrated circuit architecture connection table. The module connection relationships are used to represent data flow paths within the integrated circuit.
[0037] An integrated circuit architecture connection table, also known as a chip architecture connection relationship table, records the design information of the integrated circuit. This information may include, but is not limited to, the control signals used by each module within the integrated circuit, the connections between modules, signal flow, address assignments, and module functions.
[0038] Furthermore, in the case where the integrated circuit includes multiple network systems on chip (NOCs), the integrated circuit architecture connection table may include multiple network system on chip tables. Each network system on chip table is used to record system information of one of the network system on chip in the integrated circuit. The system information includes, but is not limited to, control signals used by various modules within the network system on chip, connection relationships between modules, signal flow, address allocation, and module functions.
[0039] For easier understanding, please refer to Figure 2 , which is a partial schematic diagram of an integrated circuit architecture connection table provided in some embodiments of the present application. Figure 2In the example, the integrated circuit architecture connection table includes a network system-on-chip table A_NOC and a network system-on-chip table B_NOC. The network system-on-chip table A_NOC can be used to record system information of the network system-on-chip A in the integrated circuit, and the network system-on-chip table B_NOC can be used to record system information of the network system-on-chip B in the integrated circuit. The following description uses the network system-on-chip table A_NOC as an example.
[0040] In the network system-on-chip table A_NOC, AHB_C0, AHB_C1, and AHB_C2 represent the modules that serve as data inlets in the network system-on-chip A, and B11, G00, and C22 represent the modules that serve as data outlets in the network system-on-chip A. The clock signal for modules AHB_C0, AHB_C1, and AHB_C2 is sclk_m33, and the reset signal is m33_rst_n. The clock signal for module B11 is sclk_boot, and the reset signal is sclk_boot_rst_n. The clock signal for module G00 is sclk_m33, and the reset signal is sclk_m33_rst_n. The clock signal for module C22 is HWACCLK, and the reset signal is HWACCLK_rst_n.
[0041] The row where the data flow inlet module is located and the column where the data flow outlet module is located have an intersection, and the value at the intersection is used to indicate whether the data flow inlet module and the data flow outlet module are connected. Figure 1 In the example, the row of data inlet module AHB_C0 and the column of data outlet module B11 intersect at the position indicated by the rectangular dashed box. The value at this position is "Y", indicating that data inlet module AHB_C0 and data outlet module B11 are connected. Similarly, the row of data inlet module AHB_C0 and the column of data outlet module C22 intersect at the position indicated by the oval dashed box. The value at this position is "N", indicating that data inlet module AHB_C0 and data outlet module C22 are not connected.
[0042] Normally, if there is a connection between the data flow inlet module and the data flow outlet module, it means that the data in the data flow inlet module will flow into the data flow outlet module. Conversely, if there is no connection between the data flow inlet module and the data flow outlet module, it means that there is no data interaction between the data flow inlet module and the data flow outlet module (that is, there is no data flow direction). For example Figure 1 In the example, the data in the data flow inlet module AHB_C0 will flow into the data flow outlet module B11, but there is no data interaction between the data flow inlet module AHB_C0 and the data flow outlet module C22.
[0043] Based on the above description, it can be understood that by analyzing the information in the integrated circuit architecture connection table, the module connection relationship of the integrated circuit can be extracted. Figure 1 From the information in the , we can extract the following module connection relationship: AHB_C0>B11>A00, AHB_C0>B11>ROM, AHB_C0>B11>M33, AHB_C0>G00, AHB_C1>B11, AHB_C1>G00, AHB_C2>B11, AHB_C2>G00.
[0044] In step S102 , a target module serving as a data flow outlet in the integrated circuit is searched based on the module connection relationship, and a control signal and control signal information of the target module are obtained from the integrated circuit architecture connection table. The control signal is used to control the operation of the target module.
[0045] In this embodiment, in each module connection relationship, the module at the end of the data flow direction is used as the target module. For example, in the module connection relationship AHB_C0>B11>A00, data flows from AHB_C0 to B11, and then from B11 to A00, so A00 can be used as the target module. For another example, in the module connection relationship AHB_C1>B11, data flows from AHB_C1 to B11, so B11 can be used as the target module.
[0046] For information on how to obtain the control signals of the target module from the integrated circuit architecture connection table, see Figure 2 The relevant description is not repeated here.
[0047] In this embodiment, the control signal information may include but is not limited to attribute information of the control signal, such as clock jitter, clock frequency, duty cycle, reset signal pull-up time, etc.
[0048] Step S103 : generating a test case of the target module according to the control signal and control signal information of the target module, and running the test case to test the control signal of the target module.
[0049] Specifically, the module information of the target module can be extracted from the integrated circuit architecture connection table. The control signal information and the module information of the target module are used as constraints, with the goal of maximizing test scenario coverage to generate test cases for the target module. Specifically, the module information includes, but is not limited to, the address space allocated for the target module. Maximizing test scenario coverage means covering as many test scenarios as possible while minimizing the number of test cases. This reduces the number of test cases and improves testing efficiency.
[0050] When generating test cases, the control signal information and the target module's module information are used as constraints. The linprog function is called to find the optimal solution for maximizing test scenario coverage, and test cases are constructed based on the optimal solution. The optimal solution may include, but is not limited to, a combination of properties of the control signals used for testing. For example, the properties of control signal A used for testing are: clock jitter of 10ns and clock frequency of 5kHz; the properties of control signal B used for testing are: clock jitter of 13ns and clock frequency of 20kHz.
[0051] Generating test cases according to the optimal solution can ensure that more test scenarios can be tested while executing as few test cases as possible.
[0052] Specifically, when generating test cases for the target module based on control signal information, a correspondence table between the module connection relationship, the target module and the control signal of the target module can be established based on the module connection relationship and the target module found based on the module connection relationship, and a test case for the target module can be generated based on the correspondence table and the control signal information.
[0053] For easier understanding, please refer to Figure 3 , which is a schematic diagram of a correspondence table provided in some embodiments of the present application. Figure 3 In the example, access_module represents the module connection relationship, clk_signal represents the clock signal used by the target module at the end of the module connection relationship, and rst_n_signal represents the reset signal used by the target module at the end of the module connection relationship. For example, consider the row with the module connection relationship AHB_C0 > B11 > A00. This row indicates that the clock signal for target module A00 is sclk_boot, and the reset signal is sclk_boot_rst_n.
[0054] By establishing a correspondence table between module connection relationships, target modules and control signals of target modules, and generating test cases for target modules based on the correspondence table and control signal information, the problem of missing modules when generating test cases can be avoided, thereby ensuring test accuracy.
[0055] In this embodiment, when performing a control signal test, only the control signal of the target module can be tested. This is because the target module is the endpoint of data flow. If the control signal of its upstream module is abnormal, it will affect the data processing of the target module, and thus may cause the test to fail when testing the control signal of the target module. Conversely, if the control signal test of the target module passes, it means that the control signal of the upstream module should also be normal. This can significantly reduce the testing workload.
[0056] Of course, for higher test accuracy, in addition to testing the control signals of the target module, the control signals of other data flow outlet modules outside the target module can also be tested. Specifically, for at least one module connection relationship, the module connection relationship can be split into multiple sub-connection relationships, and in each sub-connection relationship, according to the direction of data flow, the module located at the last position is used as the target module. For example, the module connection relationship AHB_C0>B11>A00 can be split into two sub-connection relationships: AHB_C0>B11 and B11>A00. In this way, in the sub-connection relationship AHB_C0>B11, B11 is the module located at the last position, and in the sub-connection relationship B11>A00, A00 is the module located at the last position, so both A00 and B11 can be used as target modules. In this way, the control signals of more modules can be tested, ensuring test accuracy.
[0057] In summary, in the technical solutions of some embodiments of the present application, by extracting the module connection relationship of the integrated circuit from the integrated circuit architecture connection table, the data flow path within the integrated circuit can be obtained, and the target module serving as the data flow outlet can be searched according to the data flow path. In this way, on the one hand, the target module can be automatically searched, and then test cases for the control signals and control signal information of the target module can be automatically generated, eliminating the need for manual test case writing, greatly improving test efficiency, and solving the problem of relatively low control signal testing efficiency in some technologies. On the other hand, the search accuracy can be guaranteed, avoiding the problem of missing modules in the search.
[0058] In some embodiments, extracting the module connection relationship of the integrated circuit from the integrated circuit architecture connection table in step S101 may include:
[0059] The information in the integrated circuit architecture connection table is converted into a first dictionary, where the value of the first dictionary is a list, and the list includes at least one sub-list, each sub-list is used to represent one row in the integrated circuit architecture connection table, the index order of each sub-list in the list is used to represent the row number order of the integrated circuit architecture connection table, and the index order of each element in the sub-list is used to represent the column number order of the integrated circuit architecture connection table.
[0060] The module connection relationship of the integrated circuit is extracted from the first dictionary.
[0061] Specifically, under normal circumstances, the integrated circuit architecture connection table can be an Excel table. Each sheet page of the integrated circuit architecture connection table is used to store the design information of one of the integrated circuits, that is, each sheet page can include Figure 2Similar content. For example, assuming that the integrated circuit architecture connection table includes 3 sheet pages, the first sheet page is named integrated circuit A and stores the design information of integrated circuit A, the second sheet page is named integrated circuit B and stores the design information of integrated circuit B, and the third sheet page is named integrated circuit C and stores the design information of integrated circuit C. According to the target integrated circuit to be tested for control signals, information can be extracted from the sheet page corresponding to the target integrated circuit. For example, assuming that the control signal of integrated circuit A needs to be tested, information can be extracted from the sheet page corresponding to integrated circuit A and the extracted information can be converted into a first dictionary.
[0062] The first dictionary may be a Python dictionary. In a Python dictionary, data may be stored in a key-value pair format, where the key is the sheet page name corresponding to the target integrated circuit, and the value is the content in the sheet page corresponding to the target integrated circuit.
[0063] Specifically, in the value field, the sheet page contents can be organized as lists. That is, each row is a sublist, and each sublist contains multiple elements, each representing the data in one of the columns of the row. For example, suppose the sheet page corresponding to the target integrated circuit is named "Integrated Circuit A," and the contents of the sheet page are shown in Table 1.
[0064] Table 1 sheet
[0065] 123 456 789 ABC EFG HIK
[0066] The first dictionary obtained by conversion can be as follows:
[0067]
[0068] In the first dictionary, the index of the sublist represents the row position. For example, the index of the list [123,456,789] can be 1, which means that the content of the list [123,456,789] is located in the first row of the sheet page "Integrated Circuit A". For another example, the index of the list [ABC,EFG,HIK] is 2, which means that the content of the list [ABC,EFG,HIK] is located in the second row of the sheet page "Integrated Circuit A". Of course, the index of the list can also be inconsistent with the row number corresponding to the list, that is, as long as the index order of the list can represent the order between the rows. For example, the index of the list [123,456,789] can be 0, and the index of the list [ABC,EFG,HIK] can be 1, which means that the list [123,456,789] is located in the previous row of the list [ABC,EFG,HIK].
[0069] Similarly, the index of each list element represents the column position. For example, in the list [123,456,789], the index of element 123 can be 1, indicating that element 123 is located in the first column of the sheet "Integrated Circuit A". Similarly, the index of element 456 can be 2, indicating that element 456 is located in the second column of the sheet "Integrated Circuit A". The index of element 789 can be 3, indicating that element 789 is located in the third column of the sheet "Integrated Circuit A". Of course, similar to the list index, the index of the element can also be inconsistent with the column number corresponding to the element, that is, as long as the index order of the elements can represent the order of the columns.
[0070] Thus, in the first dictionary, based on the key of the first dictionary and the index of each list and element in the first dictionary, the position of each element in the integrated circuit architecture connection table can be located. For example, taking the number "456" in the first dictionary as an example, since the key of the first dictionary is "Integrated Circuit A", the index of the list containing "456" is 1, and the index of "456" is 2, it can be determined that "456" is located in the first row and second column of the sheet "Integrated Circuit A".
[0071] By storing the information in the integrated circuit architecture connection table in this structured manner, it is easy to automatically extract the module connection relationship of the integrated circuit through program code, thereby improving the feasibility of the solution.
[0072] Furthermore, extracting the module connection relationship of the integrated circuit from the first dictionary may include:
[0073] Extracting information from each network system-on-chip table based on the first dictionary to obtain a second dictionary corresponding to each network system-on-chip table;
[0074] The module connection relationship of the integrated circuit is extracted according to the second dictionary.
[0075] Specifically, similar to the first dictionary, the second dictionary can also be a Python dictionary. In the second dictionary, the key can be the network system-on-chip name in the integrated circuit architecture connection table, and the value can be the content of the network system-on-chip table. For example, Figure 2 For example, two second dictionaries can be extracted. The first second dictionary's key is "A_NOC" and its value is the content in the network system-on-chip table "A_NOC". The second second dictionary's key is "B_NOC" and its value is the content in the network system-on-chip table "B_NOC". Splitting the first dictionary into multiple second dictionaries facilitates searching for module connectivity on a module-by-module basis within the network system-on-chip, reducing issues like missing modules.
[0076] Specifically, extracting the module connection relationship of the integrated circuit based on the second dictionary may include:
[0077] Extracting connection relationships between modules from each second dictionary to obtain at least one module sub-connection relationship, and extracting a module connection relationship of the integrated circuit based on the at least one module sub-connection relationship;
[0078] For example, take the above second dictionary "A_NOC" and "B_NOC" as an example.
[0079] From the second dictionary "A_NOC", the following module sub-connection relationships can be extracted:
[0080] AHB_C0>B11, AHB_C0>G00, AHB_C1>B11, AHB_C1>G00, AHB_C2>B11, AHB_C2>G00.
[0081] From the second dictionary "B_NOC", the following module sub-connection relationships can be extracted:
[0082] B11>A00, B11>ROM, B11>M33.
[0083] Based on the module sub-connection relationships extracted from different second dictionaries, the complete module connection relationship in the integrated circuit can be extracted. Simply put, according to the direction of data flow, if the module at the last position in one module sub-connection relationship is the same as the module at the starting position in another module sub-connection relationship, then the two module sub-connection relationships can be merged into one module connection relationship according to the direction of data flow. For example, take the module sub-connection relationship AHB_C0>B11 in the second dictionary "A_NOC" and the module sub-connection relationship B11>A00 in the second dictionary "B_NOC" as examples. Since the module at the last position in the module sub-connection relationship AHB_C0>B11 is B11, and the module at the starting position in the module sub-connection relationship B11>A00 is also B11, the module sub-connection relationship AHB_C0>B11 and the module sub-connection relationship B11>A00 can be merged into one module connection relationship, resulting in AHB_C0>B11>A00. In this way, the complete module connection relationship in the integrated circuit is extracted.
[0084] Furthermore, in some embodiments, obtaining the control signal and control signal information of the target module from the integrated circuit architecture connection table includes:
[0085] The control signal information of each module serving as a data flow outlet is extracted from each second dictionary respectively, and the control signal information of the target module is screened out from the extracted control signal information.
[0086] Specifically, based on the control signal information extracted from each second dictionary, a correspondence between data flow egress modules and control signal information can be established. This creates a complete correspondence table between data flow egress modules and control signal information. Furthermore, after extracting a target module, the control signal information of the target module can be searched for in the correspondence table. This improves data search efficiency.
[0087] For example, Figure 2 For example, from the second dictionary "A_NOC," we can extract the following module sub-connection relationship A: AHB_C0>B11, AHB_C0>G00, AHB_C1>B11, AHB_C1>G00, AHB_C2>B11, AHB_C2>G00. B11, G00, B11, and G00 are all modules that serve as data flow outlets. Therefore, the control signal information of B11, G00, B11, and G00 can be extracted from the second dictionary "A_NOC" and the corresponding correspondence can be established.
[0088] From the second dictionary "B_NOC," we can extract the following module sub-connection relationships: B11 > A00, B11 > ROM, and B11 > M33. A00, ROM, and M33 are all modules that serve as data flow outlets. Therefore, we can extract the control signal information for A00, ROM, and M33 from the second dictionary "B_NOC" and establish corresponding relationships.
[0089] By merging the corresponding relationships extracted from the second dictionary "A_NOC" and "B_NOC", a complete corresponding relationship table can be obtained. Furthermore, after extracting the target module based on the module connection relationship, the control signal information of the target module can be searched in the corresponding relationship table, thereby improving information search efficiency.
[0090] See also Figure 4 , which is a flowchart of generating test cases provided in some embodiments of the present application.
[0091] Figure 4 The steps include:
[0092] Step S401: converting the design information of the integrated circuit into a first dictionary.
[0093] Step S402 : extracting a second dictionary from the first dictionary according to the network system-on-chip.
[0094] Step S403: extract the control signal information of the data flow egress module and obtain a correspondence table between the data flow egress module and the control signal information.
[0095] Step S404: extracting module sub-connection relationships from each second dictionary.
[0096] Step S405: Obtain the target module and the control signal information of the target module according to the module sub-connection relationship and the corresponding relationship table.
[0097] Step S406: Convert and obtain a corresponding table of connection relationship and control signal information. Figure 3 The table shown.
[0098] Step S407: Generate test cases.
[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.
[0100] See also Figure 5 , which is a module schematic diagram of a signal testing device provided in some embodiments of the present application. Figure 5 In the signal test device, the signal test device includes:
[0101] A connection relationship extraction module 501 is used to extract the module connection relationship of the integrated circuit from the integrated circuit architecture connection table, where the module connection relationship is used to represent the data flow path within the integrated circuit;
[0102] An information search module 502 is configured to search for a target module serving as a data flow outlet in the integrated circuit based on the module connection relationship, and obtain control signals and control signal information of the target module from the integrated circuit architecture connection table. The control signals are used to control the operation of the target module.
[0103] The use case generation module 503 is used to generate a test case of the target module according to the control signal and control signal information of the target module, and run the test case to test the control signal of the target module.
[0104] In some embodiments, the connection relationship extraction module 501 is specifically used to:
[0105] Converting information in the integrated circuit architecture connection table into a first dictionary, wherein the value of the first dictionary is a list, the list includes at least one sub-list, each sub-list is used to represent a row in the integrated circuit architecture connection table, the index order of each sub-list in the list is used to represent the row number order of the integrated circuit architecture connection table, and the index order of each element in the sub-list is used to represent the column number order of the integrated circuit architecture connection table;
[0106] The module connection relationship of the integrated circuit is extracted from the first dictionary.
[0107] In some embodiments, the integrated circuit architecture connection table includes multiple network system-on-chip tables, each of which is used to record system information of one network system-on-chip in the integrated circuit; the connection relationship extraction module 501 is specifically used to:
[0108] Extracting information from each network system-on-chip table based on the first dictionary to obtain a second dictionary corresponding to each network system-on-chip table;
[0109] The module connection relationship of the integrated circuit is extracted according to the second dictionary.
[0110] In some embodiments, the connection relationship extraction module 501 is specifically used to:
[0111] Extracting connection relationships between modules from each second dictionary to obtain at least one module sub-connection relationship, and extracting a module connection relationship of the integrated circuit based on the at least one module sub-connection relationship;
[0112] And / or, the information search module 502 is specifically configured to:
[0113] The control signal information of each module serving as a data flow outlet is extracted from each second dictionary respectively, and the control signal information of the target module is screened out from the extracted control signal information.
[0114] In some embodiments, the integrated circuit includes at least one module connection relationship; the information search module 502 is specifically configured to:
[0115] In each module connection relationship, according to the direction of data flow, the module located at the last position is used as the target module.
[0116] In some embodiments, the use case generation module 503 is specifically configured to:
[0117] According to the module connection relationship and the target module found according to the module connection relationship, a corresponding relationship table among the module connection relationship, the target module and the control signal of the target module is established;
[0118] Generate test cases for the target module based on the correspondence table and control signal information.
[0119] In some embodiments, the use case generation module 503 is specifically configured to:
[0120] Extracting module information of the target module from the integrated circuit architecture connection table;
[0121] The control signal information and the module information of the target module are used as constraints, and the maximum test scenario coverage is set as the goal to generate test cases for the target module.
[0122] By extracting the module connectivity of an integrated circuit from the integrated circuit architecture connection table, the data flow path within the integrated circuit can be obtained, and the target module serving as the data flow outlet can be found according to the data flow path. This, on the one hand, enables automatic search of the target module, and then automatically generates control signal test cases based on the target module's control signals and control signal information, eliminating the need for manual test case writing. This significantly improves test efficiency and addresses the low control signal testing efficiency issue in some technologies. Furthermore, it ensures search accuracy and avoids module omissions.
[0123] See also Figure 6 An embodiment of the present application further provides an electronic device, comprising a memory 10 and a processor 20, wherein the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any one of the above-mentioned signal testing method embodiments.
[0124] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned signal testing method embodiments when running.
[0125] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.
[0126] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above signal testing method embodiments are implemented.
[0127] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned signal testing method embodiments are implemented.
[0128] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0129] The above is a detailed introduction to a signal testing method, apparatus, device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
Claims
1. A signal testing method, characterized in that: The method comprises: Extracting a module connection relationship of the integrated circuit from the integrated circuit architecture connection table, wherein the module connection relationship is used to represent a data flow path within the integrated circuit; Searching for a target module serving as a data flow outlet in the integrated circuit based on the module connection relationship, and obtaining a control signal and control signal information of the target module from the integrated circuit architecture connection table, wherein the control signal is used to control the operation of the target module; A test case for the target module is generated based on the control signal and control signal information of the target module, and the test case is run to test the control signal of the target module.
2. The method according to claim 1, characterized in that The step of extracting the module connection relationship of the integrated circuit from the integrated circuit architecture connection table includes: Converting the information in the integrated circuit architecture connection table into a first dictionary, wherein the value of the first dictionary is a list, the list including at least one sub-list, each sub-list representing a row in the integrated circuit architecture connection table, the index order of each sub-list in the list representing the row number order of the integrated circuit architecture connection table, and the index order of each element in the sub-list representing the column number order of the integrated circuit architecture connection table; The module connection relationship of the integrated circuit is extracted from the first dictionary.
3. The method according to claim 2, characterized in that The integrated circuit architecture connection table includes a plurality of network system-on-chip tables, each of the network system-on-chip tables being used to record system information of one of the network system-on-chips in the integrated circuit; The extracting the module connection relationship of the integrated circuit from the first dictionary includes: extracting information from each of the network system-on-chip tables based on the first dictionary to obtain a second dictionary corresponding to each of the network system-on-chip tables; The module connection relationship of the integrated circuit is extracted according to the second dictionary.
4. The method according to claim 3, characterized in that Extracting the module connection relationship of the integrated circuit according to the second dictionary includes: Extracting connection relationships between modules from each of the second dictionaries to obtain at least one module sub-connection relationship, and extracting the module connection relationship of the integrated circuit based on the at least one module sub-connection relationship; And / or, obtaining the control signal and control signal information of the target module from the integrated circuit architecture connection table includes: The control signal information of each module serving as a data flow outlet is extracted from each of the second dictionaries respectively, and the control signal information of the target module is screened from the extracted control signal information.
5. The method according to any one of claims 1 to 4, characterized in that: The integrated circuit includes at least one module connection relationship; The step of searching for a target module serving as a data flow outlet in the integrated circuit according to the module connection relationship includes: In each module connection relationship, according to the direction of data flow, the module located at the last position is used as the target module.
6. The method according to claim 5, characterized in that Generating a test case for the target module based on the control signal information includes: According to the module connection relationship and the target module found according to the module connection relationship, establishing a correspondence table among the module connection relationship, the target module and the control signal of the target module; A test case for the target module is generated based on the correspondence table and the control signal information.
7. The method according to claim 1, characterized in that Generating a test case for the target module based on the control signal information includes: Extracting module information of the target module from the integrated circuit architecture connection table; The control signal information and the module information of the target module are used as constraints, and the maximum test scenario coverage is used as a goal to generate test cases for the target module.
8. A signal testing device, characterized in that: The device comprises: a connection relationship extraction module, configured to extract module connection relationships of an integrated circuit from an integrated circuit architecture connection table, wherein the module connection relationships are used to characterize a data flow path within the integrated circuit; an information search module, configured to search for a target module serving as a data flow outlet in the integrated circuit based on the module connection relationship, and obtain a control signal and control signal information of the target module from the integrated circuit architecture connection table, wherein the control signal is used to control the operation of the target module; The use case generation module is used to generate a test case of the target module according to the control signal and control signal information of the target module, and run the test case to test the control signal of the target module.
9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the signal testing method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the signal testing method according to any one of claims 1 to 7.