Chip test method, test daughter board and test equipment

Abstract

The invention discloses a chip testing method, testing daughter boards and testing equipment, and relates to the field of testing, the testing equipment comprises a controller applied to the testing daughter boards of the testing equipment, the testing equipment further comprises testing mother boards, each testing mother board is provided with a plurality of testing daughter boards, the testing daughter boards are independent, the testing daughter boards are used for placing chips to be tested, and the testing daughter boards are used for testing the chips to be tested. The test mother board is connected with the upper computer; the chip test method comprises the following steps: acquiring a test demand sent by an upper computer through a test mother board; based on the test requirement, testing the chip to be tested placed on the test platform; in the testing process, selecting a preset time period to collect a testing result of the to-be-tested chip; and sending a test result to the upper computer through the test mother board. Each test daughter board can independently carry out test work, the upper computer only needs to send the test requirements to the test daughter boards through the test mother board so that the test of a plurality of chips to be tested can be carried out at the same time, the test process is more convenient and faster, and the test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of testing, and in particular to a chip testing method, a testing sub-board and a testing device. Background Art

[0002] High Temperature Operating Life (HTOL) testing is a core step in semiconductor device reliability verification, particularly in high-reliability applications such as automotive electronics, aerospace, and industrial control. HTOL accelerates the physical and chemical failure mechanisms within semiconductor chips by subjecting them to high temperatures and electrical stress (exceeding rated voltage and current). This simulates the long-term degradation of devices under actual operating conditions, assessing chip lifespan indicators, identifying potential failure modes, and ensuring compliance with industry certification standards. HTOL testing typically involves testing each chip individually. Testing a large number of chips results in extended testing time and reduced efficiency. Summary of the Invention

[0003] The purpose of the present invention is to provide a chip testing method, a test sub-board and a test device, wherein each test sub-board can perform testing work independently. The host computer only needs to send the test requirements to the test sub-board through the test motherboard to simultaneously test multiple chips to be tested. The testing process is more convenient and quick, and the test efficiency is improved.

[0004] To solve the above technical problems, the present invention provides a chip testing method, which is applied to a controller on a test daughter board of a test device, wherein the test daughter board is arranged on a test mother board of the test device, each of the test daughter boards is independent of each other, and the test daughter board is used to place the chip to be tested, and the test mother board is connected to a host computer;

[0005] The chip testing method includes:

[0006] Obtaining the test requirements sent by the host computer through the test motherboard;

[0007] Based on the test requirements, the chip to be tested placed on the device is tested;

[0008] During the test, a preset time period is selected to collect the test results of the chip to be tested;

[0009] The test result is sent to the host computer through the test motherboard.

[0010] On the other hand, the test daughter board is inserted into the mother board of the test mother board through a pin header, and the pin header of the test daughter board includes a power pin header, a ground pin header, a CAN_H pin header and a CAN_L pin header. A CAN receiver and a CAN harness are connected between the test mother board and the host computer;

[0011] Before obtaining the test requirements sent by the host computer through the test motherboard, the method further includes:

[0012] Power on through the power terminal pin header and the ground terminal pin header;

[0013] Obtaining the test requirements sent by the host computer through the test motherboard includes:

[0014] The test requirements received by the test motherboard are obtained through the CAN_H pin header and the CAN_L pin header. The test requirements received by the test motherboard are sent by the host computer through the CAN receiver and the CAN harness.

[0015] On the other hand, the test includes a power supply function test, which tests the chip to be tested placed on the chip based on the test requirements, including:

[0016] Controlling the operation of the chip under test;

[0017] Collecting the output voltage, input voltage and input current of the chip under test when it is running;

[0018] Determining the output accuracy of the voltage output pin of the chip to be tested based on the output voltage;

[0019] Determine the chip power consumption of the chip to be tested based on the input voltage and the input current;

[0020] A power function test result of the chip to be tested is determined according to the output accuracy and the chip power consumption.

[0021] On the other hand, the test includes a system function test, which tests the chip to be tested placed on the system based on the test requirements, including:

[0022] Sending a dog feeding signal to the chip under test at a preset frequency;

[0023] If the chip under test works normally based on the dog feeding signal, stop sending the dog feeding signal;

[0024] If the chip under test resets after stopping sending the watchdog signal, it is determined that the watchdog function test of the chip under test passes;

[0025] Controlling the chip to be tested to reset;

[0026] If the chip under test is reset based on the control, it is determined that the reset test passes;

[0027] Controlling the chip under test to sleep;

[0028] If the chip under test is in sleep mode based on control, determining that the sleep test passes;

[0029] The test result of the system function test is determined according to the test result of the watchdog function test, the test result of the reset test and the test result of the sleep test.

[0030] On the other hand, the test includes a communication function test, and the test sub-board also includes a communication loop test circuit. Based on the test requirements, the test chip placed on itself is tested, including:

[0031] Controlling the communication loop test circuit to send a test signal of a preset communication protocol to the chip under test, wherein the preset communication protocol includes at least one of SPI communication, UART communication, and CAN communication;

[0032] Determining whether the test signal of the preset communication protocol returned by the chip under test passes the communication verification;

[0033] If the communication verification is passed, it is determined that the chip under test has passed the communication function test.

[0034] On the other hand, the test includes a system function test, and the test sub-board also includes a simulated load circuit. Based on the test requirements, the test chip placed on the sub-board is tested, including:

[0035] Controlling the simulated load circuit to simulate a preset device, wherein the preset device includes a motor or a solenoid valve;

[0036] Controlling the chip under test to drive the preset device;

[0037] Determining whether the preset device is successfully started;

[0038] If the preset device is successfully started, it is determined that the chip system function test to be tested has passed.

[0039] On the other hand, during the test process, selecting a preset time period to collect the test results of the chip under test includes:

[0040] Determine the number of time periods that need to be collected during the test process, and set the same number of monitoring processes as the time periods that need to be collected, with the time periods corresponding to the monitoring processes one by one;

[0041] After the test starts, when any time period is reached, a monitoring signal is sent to the monitoring process corresponding to the reached time period, so that the monitoring process obtains the test result of the chip to be tested.

[0042] In order to solve the above technical problems, the present invention further provides a test daughter board, comprising:

[0043] memory for storing computer programs;

[0044] The controller is used to implement the steps of the above chip testing method when executing the computer program.

[0045] On the other hand, the test daughter board is inserted into the mother board of the test mother board through the pin header, and the pin header of the test daughter board includes a power pin header, a ground pin header, a CAN_H pin header and a CAN_L pin header;

[0046] The test daughter board is used to be powered on through the power pin header and the ground pin header, and to obtain the test requirements received by the test mother board through the CAN_H pin header and the CAN_L pin header.

[0047] To solve the above technical problems, the present invention further provides a test device, comprising the above test daughter board, wherein the test daughter board is arranged on the test mother board of the test device, each of the test daughter boards is independent of each other, the test daughter board is used to place the chip to be tested, and the test mother board is connected to the host computer;

[0048] The test motherboard is used to send the test requirements sent by the host computer to the corresponding test daughter board, and send the test results of the chip to be tested obtained by the controller of the test daughter board to the host computer;

[0049] The host computer is used to generate a test report based on the test results.

[0050] The present application provides a chip testing method, a test daughter board and a test device, which relate to the field of testing, including a controller on a test daughter board applied to a test device, the test device also including a test motherboard, each test motherboard is provided with a plurality of test daughter boards, each test daughter board is independent, the test daughter board is used to place the chip to be tested, and the test motherboard is connected to a host computer; the chip testing method includes: obtaining a test requirement sent by the host computer through the test motherboard; based on the test requirement, testing the chip to be tested placed on itself; during the test process, selecting a preset time period to collect the test results of the chip to be tested; and sending the test results to the host computer through the test motherboard. Each test daughter board can perform testing work independently, and the host computer only needs to send the test requirement to the test daughter board through the test motherboard to simultaneously test multiple chips to be tested, making the testing process more convenient and quick, thereby improving the efficiency of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 A flowchart of a chip testing method provided by the present invention;

[0053] Figure 2 A schematic structural diagram of a testing device provided by the present invention;

[0054] Figure 3 A schematic structural diagram of a test motherboard provided by the present invention;

[0055] Figure 4 A schematic structural diagram of a test sub-board provided by the present invention;

[0056] Figure 5 A flowchart of another chip testing method provided by the present invention;

[0057] Figure 6 A flow chart of a monitoring process provided by the present invention;

[0058] Figure 7 A flowchart of the operation of a host computer provided by the present invention;

[0059] Figure 8 A schematic diagram of an instruction frame of a host computer communication protocol provided by the present invention;

[0060] Figure 9 A schematic diagram of a command confirmation frame of a host computer communication protocol provided by the present invention;

[0061] Figure 10 A schematic diagram of a data frame of a host computer communication protocol provided by the present invention;

[0062] Figure 11 A schematic diagram of a data response frame of a host computer communication protocol provided by the present invention. DETAILED DESCRIPTION

[0063] The core of the present invention is to provide a chip testing method, a test sub-board and a test device. Each test sub-board can perform testing work independently. The upper computer only needs to send the test requirements to the test sub-board through the test motherboard to simultaneously test multiple chips to be tested. The testing process is more convenient and quick, and the test efficiency is improved.

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0065] Figure 1 A flowchart of a chip testing method provided by the present invention is provided. The chip testing method is applied to a controller on a test daughter board of a test device. The test daughter boards are arranged on a test mother board of the test device. Each test daughter board is independent of each other. The test daughter boards are used to place the chip to be tested. The test mother board is connected to a host computer.

[0066] Chip testing methods include:

[0067] S11: Obtain the test requirements sent by the host computer through the test motherboard;

[0068] S12: Based on the test requirements, the chip to be tested placed on itself is tested;

[0069] S13: During the test, a preset time period is selected to collect test results of the chip under test;

[0070] S14: Send the test results to the host computer through the test motherboard.

[0071] Figure 2 A structural diagram of a test device provided by the present invention, Figure 3 This is a schematic diagram of the structure of a test motherboard provided by the present invention. The high and low temperature chamber is used to stabilize and regulate the experimental environment temperature. The HTOL motherboard is used to flexibly increase or decrease the number of chips to be tested and provide a hardware environment for chip HTOL testing. The HTOL motherboard is composed of a test daughterboard and a test motherboard. A single test motherboard can carry multiple test daughterboards. The test motherboard and the test daughterboard are connected using pin headers. The test motherboards are connected to each other through power and signal lines via wiring harnesses. The CAN (Controller Area Network) transceiver and wiring harness are used to transmit and receive experimental data that meets the CAN protocol. The CAN transceiver and wiring harness transmit and receive data according to the CAN protocol and can communicate with the host computer via the USB protocol. The host computer is used to control the experimental process, print the experimental data in real time, and store it in a database.

[0072] The system of the present invention includes a HTOL motherboard, an HTOL daughterboard, a CAN wiring harness and transceiver, an excitation signal module, a signal acquisition module, a database module, and a system log module. The HTOL motherboards share power lines, ground lines, and CAN signal lines. Multiple motherboards can be fixed and spliced ​​together by screws, allowing for flexible expansion or disassembly. The HTOL daughterboards are inserted into the motherboard headers via pins, allowing one motherboard to be used with multiple daughterboards for testing without interfering with each other. The CAN wiring harness and transceiver communicate between a host computer and the daughterboards based on the CAN protocol. The excitation signal module is integrated into the host computer. After the host computer sends an excitation signal, the corresponding daughterboard receives the signal and starts the HTOL test. The signal acquisition module is integrated into the host computer for real-time acquisition of CAN data frames from the daughterboards. The database module is integrated into the host computer and can interact with the local database in real time to categorize and store HTOL experimental data. The system log module is integrated into the host computer, and the host computer can display the status of the corresponding daughterboard and various parameter data in real time through the system log module.

[0073] The system is initialized upon power-on, including controller (hereinafter referred to as MCU (Microcontroller Unit)) initialization, SPI communication initialization, CAN communication initialization, and chip under test initialization. The MCU begins to wait for the stimulus signal from the host computer. When the MCU receives the stimulus signal, it begins the HTOL test; otherwise, it continues to wait. The MCU issues control instructions to control the chip under test to perform various tests. At the same time, the MCU creates parallel tasks to monitor and save key data in real time. When the chip under test completes a round of testing, the MCU sends a CAN frame containing key data to the host computer via the CAN harness. The host computer parses the CAN frame data. If it meets the communication protocol, it displays the data in real time and saves it to the database. Otherwise, the erroneous data is discarded. The above steps are repeated until the HTOL test is completed.

[0074] The present application provides a chip testing method, which relates to the field of testing, including a controller on a test daughter board applied to a test device, the test device also including a test motherboard, each test motherboard is provided with multiple test daughter boards, each test daughter board is independent, the test daughter board is used to place the chip to be tested, and the test motherboard is connected to a host computer; the chip testing method includes: obtaining a test requirement sent by the host computer through the test motherboard; based on the test requirement, testing the chip to be tested placed on itself; during the test process, selecting a preset time period to collect the test results of the chip to be tested; and sending the test results to the host computer through the test motherboard. Each test daughter board can perform testing work independently, and the host computer only needs to send the test requirement to the test daughter board through the test motherboard to simultaneously test multiple chips to be tested, making the testing process more convenient and quick, thereby improving the efficiency of the test.

[0075] Based on the above embodiment:

[0076] Figure 4 A schematic structural diagram of a test sub-board provided by the present invention;

[0077] Figure 5 A flowchart of another chip testing method provided by the present invention;

[0078] In some embodiments, the test daughter board is inserted into the motherboard of the test motherboard through a pin header. The pin header of the test daughter board includes a power pin header, a ground pin header, a CAN_H pin header, and a CAN_L pin header. A CAN receiver and a CAN harness are connected between the test motherboard and the host computer.

[0079] Before the test motherboard obtains the test requirements sent by the host computer, it also includes:

[0080] Power on through the power pin header and the ground pin header;

[0081] The test motherboard obtains the test requirements sent by the host computer, including:

[0082] The test requirements received by the test motherboard are obtained through the CAN_H pin and CAN_L pin. The test requirements received by the test motherboard are sent by the host computer through the CAN receiver and CAN harness.

[0083] The motherboard and daughterboard designed by the present invention are connected through pin headers and mother headers. The motherboard provides power for the daughterboard. The daughterboard and the motherboard are connected to the CAN bus together. The motherboards share the power line, ground line and CAN bus. The motherboard and daughterboard can be distinguished by ID numbers. Therefore, the number of motherboards and daughterboards can be flexibly increased or decreased without changing the hardware design, while maintaining stable communication.

[0084] like Figure 4 As shown, the daughter board designed by the present invention is mainly composed of an MCU, a chip to be tested, and an auxiliary test circuit. The daughter board is connected to the motherboard through the VBAT and GND metal pins on the upper and lower sides, and is connected to the CAN bus of the motherboard through the CAN_H and CAN_L metal pins on the left and right sides. The MCU on the daughter board communicates with the chip to be tested through SPI. The MCU can control the chip to be tested to perform various functional tests, and the auxiliary test circuit is used to cooperate with the chip to be tested to perform various functions. When performing the HTOL test, the present invention cooperates with the host computer and the MCU to execute various test items. The specific steps are as follows: Figure 5 As shown:

[0085] (1) Power on and initialize the MCU and the chip under test;

[0086] (2) MCU waits for the stimulus signal from the host computer software in a loop;

[0087] (3) Determine whether the correct host computer excitation signal is received. If it is received, proceed to step (4); otherwise, proceed to step (2);

[0088] (4) MCU sends control instructions to control the chip to be tested to perform various functional tests in sequence;

[0089] (5) The chip under test performs various functional tests, and the MCU captures key experimental data in parallel;

[0090] (6) The MCU sends a CAN data frame containing key experimental data to the host computer.

[0091] In some embodiments, the test includes a power supply function test, and based on the test requirements, the chip under test placed on the chip under test is tested, including:

[0092] Control the operation of the chip under test;

[0093] Collect the output voltage, input voltage and input current of the chip under test when it is running;

[0094] Determine the output accuracy of the voltage output pin of the chip under test based on the output voltage;

[0095] Determine the chip power consumption of the chip under test based on the input voltage and the input current;

[0096] Determine the power function test results of the chip under test based on the output accuracy and chip power consumption.

[0097] Power supply function test: mainly verifies the electrical performance of the chip under test through the MCU and data acquisition module on the daughter board, such as the output accuracy of the chip voltage output pin, chip power consumption, etc.

[0098] During power supply functional testing, the core goal of controlling the chip under test is to make it operate under different test scenarios (such as startup / shutdown, output voltage regulation, and different load / input conditions). This allows the MCU and data acquisition module to fully verify its electrical performance (output accuracy, power consumption, dynamic response, etc.). The control logic must be designed in conjunction with the chip's hardware interface (control pins, communication protocol) and test requirements.

[0099] The core logic of controlling the chip under test is to use the MCU's hardware resources to send precise control signals through the chip's control interface (analog pins or digital bus), so that the chip can operate in the target test state and cooperate with the data acquisition module to complete electrical performance verification.

[0100] Specifically, the present application determines the output accuracy by verifying the output voltage of the power supply, and determines the chip power consumption by using the input voltage and input current.

[0101] In some embodiments, the test includes a system functional test, which tests the chip under test placed on the system based on the test requirements, including:

[0102] Send the dog feeding signal to the chip under test according to the preset frequency;

[0103] If the chip under test works normally based on the dog feeding signal, stop sending the dog feeding signal;

[0104] If the chip under test resets after stopping sending the watchdog signal, it is determined that the watchdog function test of the chip under test has passed;

[0105] Control the reset of the chip under test;

[0106] If the chip under test is reset based on the control, it is determined that the reset test has passed;

[0107] Control the chip under test to sleep;

[0108] If the chip under test is in sleep mode based on control, the sleep test is determined to have passed;

[0109] The test result of the system function test is determined based on the test result of the watchdog function test, the test result of the reset test and the test result of the sleep test.

[0110] System function test: mainly verifies whether the system functions of the chip under test are effective through the MCU and system function modules on the daughter board, such as the dog door, reset, sleep and other functions.

[0111] The core of the watchdog function is to trigger a reset if the watchdog is not fed within a timeout period, preventing the system from freezing. Testing requires verifying three key points: the effectiveness of feeding the watchdog, the triggering of the reset upon timeout, and the state recovery after the reset.

[0112] Reset is not triggered when the watchdog is fed normally: send the watchdog signal at the frequency required by the chip, continuously detect the pin level, and read the chip status register through the communication interface at the same time to confirm that the watchdog is not triggered.

[0113] A reset is triggered when the chip is not fed after a timeout: First, feed the chip normally to stabilize the chip, then the MCU stops sending the feeding signal. A timer records the time from when the feeding stops until the pin changes, verifying whether it is consistent with the chip's configured timeout period. After the reset, confirm the chip restart through the communication interface.

[0114] After reset, the watchdog function is reset: After the reset is triggered, the watchdog is fed again. Confirm that the chip no longer triggers reset, proving that the watchdog function is reset with the reset.

[0115] The reset function is used to restore the chip to its initial state, including hardware reset (pin trigger) and software reset (instruction / register trigger). The test needs to verify the effectiveness, thoroughness and post-reset state of the reset.

[0116] The sleep function is used to reduce chip power consumption (such as shutting down the CPU and peripheral clocks). It is necessary to verify the conditions for entering sleep mode, power consumption during sleep mode, the effectiveness of the wake-up method, and function recovery after wake-up.

[0117] In some embodiments, the test includes a communication function test. The test daughter board also includes a communication loop test circuit. Based on the test requirements, the test daughter board performs the following tests on the chip under test placed on the daughter board:

[0118] Controlling the communication loop test circuit to send a test signal of a preset communication protocol to the chip under test, where the preset communication protocol includes at least one of SPI communication, UART communication, and CAN communication;

[0119] Determine whether the test signal of the preset communication protocol returned by the chip under test passes the communication verification;

[0120] If the communication verification is passed, it is determined that the chip under test has passed the communication function test.

[0121] Communication function test: mainly verifies the communication functions of the chip under test, such as SPI communication, UART communication, CAN communication, etc., through the MCU on the daughter board and the communication loop module in the auxiliary test circuit.

[0122] Verifying the SPI, UART, and CAN communication functions of the chip under test (DUT) relies on establishing a communication loop (bidirectional communication between the DUT and the test circuit). The MCU controls the test process and determines the accuracy, stability, and speed of the communication. The specific implementation requires designing hardware loops and software verification logic based on the characteristics of different communication protocols.

[0123] The chip under test's communication interface (e.g., SPI's MOSI / MISO, UART's TX / RX) is connected to the auxiliary test circuit, forming a closed "transmit-receive" loop (either through the MCU or a direct cross-connect). Communication integrity is verified using fixed pattern data (e.g., incrementing numbers, random numbers, all 0s / all 1s) and boundary data (e.g., maximum frame length). The MCU controls the chip under test to send data, which is received and compared by the test circuit to calculate the error rate. Alternatively, the MCU can send data to verify the chip under test's receiving capability.

[0124] In some embodiments, the test includes a system function test. The test daughter board also includes a simulated load circuit. Based on the test requirements, the test daughter board performs a test on the chip to be tested, including:

[0125] Controlling the simulated load circuit to simulate a preset device, the preset device including a motor or a solenoid valve;

[0126] Control the chip under test to drive the preset device;

[0127] Determine whether the preset device is successfully started;

[0128] If the preset device is successfully started, it is determined that the chip system function test has passed.

[0129] Drive function test: mainly through the MCU on the daughter board and the simulated load module in the auxiliary test circuit to verify whether the driving capability of the chip under test meets the standard, such as driving motors, driving solenoid valves and other functions.

[0130] The core of the drive function test is to verify whether the chip under test's driving capability for various loads (such as motors, solenoid valves, etc.) meets the design standards, including output power, current / voltage stability, dynamic response, protection function, etc.

[0131] The chip under test needs to output a drive signal (such as a PWM or level signal). The MCU on the test daughterboard serves as the test control core, responsible for sending control commands to the chip under test (such as enabling and configuring drive signal parameters), collecting test data (voltage, current, and load status), and communicating with the host computer (uploading data and receiving commands). The simulated load module simulates real-world load characteristics (such as the inductance of a motor or the inductance and resistance of a solenoid valve) to replace the actual load (to avoid damage to the actual device during testing).

[0132] It may also be necessary to use a signal acquisition circuit or directly use the MCU pins to collect key parameters such as the output voltage, current, load end voltage, etc. of the chip under test (to determine the driving capability).

[0133] Protection circuits with fuses, overcurrent protection, reverse polarity protection, and other functions may also be required to prevent abnormal chip or load damage to the system during testing).

[0134] Figure 6 A flow chart of a monitoring process provided by the present invention;

[0135] In some embodiments, during the test process, selecting a preset time period to collect test results of the chip under test includes:

[0136] Determine the number of time periods that need to be collected during the test, and set the same number of monitoring processes as the time periods that need to be collected, with the time periods corresponding to the monitoring processes one by one;

[0137] After the test starts, when any time period is reached, a monitoring signal is sent to the monitoring process corresponding to the reached time period so that the monitoring process can obtain the test result of the chip to be tested.

[0138] The following example uses three time periods for data collection, determining test results for the start, middle, and end of the test. Specifically, the data at these three times is critical and can better characterize the test process. This avoids excessive real-time data collection, which would result in excessive data collection and computational inconvenience.

[0139] The MCU uses the real-time operating system FreeRTOS to perform parallel task processing. While creating and executing test tasks, it also creates monitoring tasks. Through FreeRTOS's task scheduling, it can call monitoring tasks at the beginning, middle, and end of each test item to monitor key experimental data in parallel to ensure data accuracy and real-time performance. The main steps of real-time data detection are as follows:

[0140] (1) MCU creates execution test tasks and corresponding monitoring branches 1, 2 and 3 according to the test verification item list;

[0141] (2) Execute the test task and notify the corresponding monitoring branch 1 through a signal at the start of execution;

[0142] (3) Monitoring branch 1 determines whether the monitoring signal is received. If so, it executes the monitoring task in parallel, monitors the test task data in real time and saves the data at that moment;

[0143] (4) Execute the test task and notify the corresponding monitoring branch 2 through a signal at the midpoint of the execution;

[0144] (5) Monitoring branch 2 determines whether the monitoring signal is received. If so, it executes the monitoring task in parallel, monitors the test task data in real time and saves the data at that moment;

[0145] (6) Execute the test task and notify the corresponding monitoring branch 3 through a signal at the end of the execution;

[0146] (7) Monitoring branch 3 determines whether the monitoring signal is received. If so, the monitoring task is executed in parallel, monitoring the test task data in real time and saving the data at that moment;

[0147] (8) The MCU determines whether the test verification item list is verified. If it is completed, the process ends; if not, the process returns to step (1).

[0148] Specifically, each monitoring branch is a process.

[0149] Figure 4 A schematic structural diagram of a test sub-board provided by the present invention, comprising:

[0150] Memory 41, for storing computer programs;

[0151] The controller 42 is configured to implement the steps of the above-mentioned chip testing method when executing a computer program.

[0152] For an introduction to the test sub-board provided in this application, please refer to the above embodiments and will not be repeated here.

[0153] In some embodiments, the test daughter board is inserted into the mother board of the test mother board through a pin header, and the pin header of the test daughter board includes a power pin header, a ground pin header, a CAN_H pin header, and a CAN_L pin header;

[0154] The test daughter board is used to be powered through the power pin header and the ground pin header, and obtain the test requirements received by the test mother board through the CAN_H pin header and the CAN_L pin header.

[0155] Figure 2 A schematic diagram of the structure of a test device provided by the present invention, comprising the above-mentioned test daughter boards, which are arranged on a test motherboard of the test device, each test daughter board being independent of the other, and used to place a chip to be tested, and the test motherboard being connected to a host computer;

[0156] The test motherboard is used to send the test requirements sent by the host computer to the corresponding test daughter board, and send the test results of the chip to be tested obtained by the controller of the test daughter board to the host computer;

[0157] The host computer is used to generate a test report based on the test results.

[0158] like Figure 7 As shown, the main steps of the integrated data processing flow designed by the present invention are as follows:

[0159] (1) The host computer receives CAN data through the data acquisition module;

[0160] (2) The host computer software determines whether the CAN data frame complies with the protocol through the built-in communication protocol. If it does, it proceeds to step 3; otherwise, it discards the data.

[0161] (3) The host computer software calls the real-time log module to display the experimental data in real time, and calls the database module to store the experimental data in real time;

[0162] (4) Determine whether data export is required. If an export command is received, proceed to step 5; otherwise, proceed to step (1).

[0163] (5) Export the data stored in the database as an Excel file;

[0164] (6) Import the Excel file into Python automated processing software, and use Python automated processing software to process and analyze the data;

[0165] (7) Based on the analysis results, Python automated processing software generates an experimental result report.

[0166] Furthermore, the built-in communication protocols involved in the integrated data processing process are as follows: Figure 8 、 Figure 9 、 Figure 10 and Figure 11 As shown in the figure, it mainly includes command frames, command confirmation frames, data frames, and data response frames. The command frame is sent from the host computer to the MCU via the CAN bus and is used to send excitation signals, end signals, etc. The command confirmation frame is sent from the MCU to the host computer via the CAN bus to notify the host computer that it has received the corresponding command and has begun task execution. The data frame is sent from the MCU to the host computer and mainly contains key data and test results. The host computer then parses and stores the data frame. The data response frame is sent from the host computer to the MCU within a certain period of time. If the slave computer does not receive the response frame within this time, the slave computer will resend the previous data frame. If it has received it, it will continue to send subsequent data frames. The built-in communication protocol's response mechanism further ensures task synchronization between the host computer and the MCU, and the correctness of commands and data is guaranteed through a timeout data retransmission mechanism.

[0167] For an introduction to the testing equipment provided in this application, please refer to the above embodiments and will not be repeated here.

[0168] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0169] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0170] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip testing method, characterized in that: A controller applied to a test daughter board of a test device, wherein the test daughter board is arranged on a test mother board of the test device, each of the test daughter boards is independent of each other, and the test daughter board is used to place a chip to be tested, and the test mother board is connected to a host computer; The chip testing method includes: Obtaining the test requirements sent by the host computer through the test motherboard; Based on the test requirements, the chip to be tested placed on the device is tested; During the test, a preset time period is selected to collect the test results of the chip to be tested; The test result is sent to the host computer through the test motherboard.

2. The chip testing method according to claim 1, wherein: The test daughter board is inserted into the mother board of the test mother board through the pin header, and the pin header of the test daughter board includes a power supply pin header, a ground pin header, a CAN_H pin header and a CAN_L pin header. A CAN receiver and a CAN harness are connected between the test mother board and the host computer; Before obtaining the test requirements sent by the host computer through the test motherboard, the method further includes: Power on through the power terminal pin header and the ground terminal pin header; Obtaining the test requirements sent by the host computer through the test motherboard includes: The test requirements received by the test motherboard are obtained through the CAN_H pin header and the CAN_L pin header. The test requirements received by the test motherboard are sent by the host computer through the CAN receiver and the CAN harness.

3. The chip testing method according to claim 1, wherein: The test includes a power supply function test, and based on the test requirements, the chip to be tested placed on the device is tested, including: Controlling the operation of the chip under test; Collecting the output voltage, input voltage and input current of the chip under test when it is running; Determining the output accuracy of the voltage output pin of the chip to be tested based on the output voltage; Determine the chip power consumption of the chip to be tested based on the input voltage and the input current; A power function test result of the chip to be tested is determined according to the output accuracy and the chip power consumption.

4. The chip testing method according to claim 1, wherein: The test includes a system function test, which tests the chip to be tested placed on the system based on the test requirements, including: Sending a dog feeding signal to the chip under test at a preset frequency; If the chip under test works normally based on the dog feeding signal, stop sending the dog feeding signal; If the chip under test resets after stopping sending the watchdog signal, it is determined that the watchdog function test of the chip under test passes; Controlling the chip to be tested to reset; If the chip under test is reset based on the control, it is determined that the reset test passes; Controlling the chip under test to sleep; If the chip under test is in sleep mode based on control, determining that the sleep test passes; The test result of the system function test is determined according to the test result of the watchdog function test, the test result of the reset test and the test result of the sleep test.

5. The chip testing method according to claim 1, wherein: The test includes a communication function test. The test sub-board also includes a communication loop test circuit. Based on the test requirements, the test chip placed on the sub-board is tested, including: Controlling the communication loop test circuit to send a test signal of a preset communication protocol to the chip under test, wherein the preset communication protocol includes at least one of SPI communication, UART communication, and CAN communication; Determining whether the test signal of the preset communication protocol returned by the chip under test passes the communication verification; If the communication verification is passed, it is determined that the chip under test has passed the communication function test.

6. The chip testing method according to claim 1, wherein: The test includes a system function test. The test sub-board also includes a simulated load circuit. Based on the test requirements, the test chip placed on the sub-board is tested, including: Controlling the simulated load circuit to simulate a preset device, wherein the preset device includes a motor or a solenoid valve; Controlling the chip under test to drive the preset device; Determining whether the preset device is successfully started; If the preset device is successfully started, it is determined that the chip system function test to be tested has passed.

7. The chip testing method according to any one of claims 1 to 6, characterized in that: During the test process, selecting a preset time period to collect the test results of the chip under test includes: Determine the number of time periods that need to be collected during the test process, and set the same number of monitoring processes as the time periods that need to be collected, with the time periods corresponding to the monitoring processes one by one; After the test starts, when any time period is reached, a monitoring signal is sent to the monitoring process corresponding to the reached time period, so that the monitoring process obtains the test result of the chip to be tested.

8. A test daughter board, characterized in that: include: Memory for storing computer programs; A controller, configured to implement the steps of the chip testing method according to any one of claims 1 to 7 when executing the computer program.

9. The test daughter board according to claim 8, wherein: The test daughter board is inserted into the mother board of the test mother board through the pin header, and the pin header of the test daughter board includes a power pin header, a ground pin header, a CAN_H pin header and a CAN_L pin header; The test daughter board is used to be powered on through the power pin header and the ground pin header, and to obtain the test requirements received by the test mother board through the CAN_H pin header and the CAN_L pin header.

10. A testing device, characterized in that: The test sub-board comprises the test sub-board according to claim 8 or 9, wherein the test sub-board is arranged on the test motherboard of the test equipment, each of the test sub-boards is independent of each other, the test sub-board is used to place the chip to be tested, and the test motherboard is connected to the host computer; The test motherboard is used to send the test requirements sent by the host computer to the corresponding test daughter board, and send the test results of the chip to be tested obtained by the controller of the test daughter board to the host computer; The host computer is used to generate a test report based on the test results.

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