Test mode control circuit, method and chip

Abstract

The application belongs to the chip testing field and provides a test mode control circuit, method and chip. The circuit comprises a data clock width appraisal module, a data timing generation module and a test control module, and the data timing generation module is connected with the data clock width appraisal module and the test control module. The data clock width appraisal module receives test mode data and a clock single-wire signal through an input-output pin of the chip, processes the test mode data and the clock single-wire signal, and obtains a first signal; the data timing generation module receives the test mode data and the clock single-wire signal through an input-output pin of the chip, processes the first signal according to the test mode data and the clock single-wire signal, and obtains a second signal; and the test control module detects the second signal, and if the second signal matches a preset signal, it indicates that the chip enters the test mode. According to the single-wire transmission technology, only one input-output pin of the chip is multiplexed to make the chip enter the test mode.

Description

Technical Field

[0001] This application belongs to the field of chip testing technology, and in particular relates to a test mode control circuit, method and chip. Background Technology

[0002] With the continuous increase in the complexity and integration of integrated circuits, the use of Design for Testability (DFT) in automated test equipment (ATE) testing has become an indispensable key step in the modern chip design process. Effective DFT techniques, especially the access and control of internal functional modules of the chip, greatly depend on the ability to reliably and efficiently put the chip into a specific test mode.

[0003] Currently, the industry standard for entering test mode involves multiplexing multiple functional input / output (I / O) pins of a chip and configuring these pins as "test mode entry control pins" under specific conditions (such as the power-on reset phase or a specific signal sequence combination). However, entering test mode by multiplexing multiple functional I / O pins has a series of significant and difficult-to-overcome drawbacks, such as increased test complexity and cost, increased ATE (Automatic Test Equipment) cost, increased complexity and cost of test fixtures, prolonged test time, increased debugging difficulty, and reliability risks. These problems severely restrict chip design efficiency, test cost control, and the competitiveness of the final product.

[0004] Therefore, the solution of reusing multiple functional I / O pins to enter test mode has become a key bottleneck restricting the improvement of chip integration, optimization of test costs and system reliability, and a better solution is urgently needed. Summary of the Invention

[0005] This application provides a test mode control circuit, method, and chip that can solve a series of problems existing in the scheme of implementing test modes by reusing multiple functional I / O pins, thereby overcoming the constraints on chip integration, test cost, and system reliability.

[0006] In a first aspect, embodiments of this application provide a test mode control circuit, including a data clock width discrimination module, a data timing generation module, and a test control module, wherein the data timing generation module is connected to the data clock width discrimination module and the test control module respectively;

[0007] The data clock width discrimination module is used to receive test mode data and clock single-line signal through one input / output pin of the chip, and process the test mode data and clock single-line signal to obtain a first signal; the data timing generation module is used to receive test mode data and clock single-line signal through one input / output pin of the chip, and process the first signal according to the test mode data and clock single-line signal to obtain a second signal; the test control module is used to detect the second signal, and if the second signal matches a preset signal, it indicates that the chip has entered the test mode.

[0008] In one possible implementation of the first aspect, the test mode control circuit further includes a signal gating module, the test control module is connected to the signal gating module, and the test control module and the signal gating module are respectively used to connect to multiple circuits under test;

[0009] After the chip enters the test mode, the data clock width discrimination module is further configured to receive test data and clock single-line signals through one input / output pin of the chip, and process the test data and clock single-line signals to obtain multiple third signals; the data timing generation module is further configured to receive test data and clock single-line signals through one input / output pin of the chip, and process the multiple third signals sequentially according to the test data and clock single-line signals to obtain multiple fourth signals; the test control module is further configured to generate enable signals and gating signals according to the multiple fourth signals, the enable signals are used to control the operation of all circuits under test, and the gating signals are used to control the multiple circuits under test to output test signals sequentially; the signal gating module is used to output the multiple test signals sequentially according to the enable signals and the gating signals.

[0010] In one possible implementation of the first aspect, the data clock width discrimination module includes a signal edge detection unit, a pulse width measurement unit, and a pulse width threshold judgment unit. The pulse width measurement unit is connected to the signal edge detection unit and the pulse width threshold judgment unit, respectively, and the pulse width threshold judgment unit is connected to the data timing generation module.

[0011] The signal edge detection unit is used to receive an input signal through an input / output pin of the chip, detect the rising and falling edges of the input signal, output a first detection signal when each rising edge of the input signal is detected, and output a second detection signal when each falling edge of the input signal is detected; wherein, the input signal is test mode data and clock single-line signal or test data and clock single-line signal; the pulse width measurement unit is used to start counting sequentially according to each first detection signal and stop counting according to each corresponding second detection signal to obtain multiple pulse width values; the pulse width threshold judgment unit is used to judge each pulse width value, output "1" when the pulse width value is greater than a first threshold, and output "0" when the pulse width value is less than a second threshold.

[0012] In one possible implementation of the first aspect, the data clock width discrimination module further includes a noise filtering unit, which is connected to the signal edge detection unit.

[0013] The noise filtering unit is used to receive input signals through one input / output pin of the chip and to filter noise from the input signals.

[0014] In one possible implementation of the first aspect, the data timing generation module includes multiple D flip-flops. The clock input of each D flip-flop receives an input signal through an input / output pin of the chip. The inverted output of each D flip-flop is connected to the test control module. The data input of the first D flip-flop is connected to the data clock width discrimination module. The non-inverted output of each D flip-flop is connected to the data input of the next D flip-flop and the test control module. The input signal is either a test mode data and clock single-line signal or a test data and clock single-line signal.

[0015] In one possible implementation of the first aspect, the test control module includes a data decoding unit and a data conversion unit; the data decoding unit is connected to the data timing generation module and the data conversion unit, respectively.

[0016] The data decoding unit is used to receive the second signal, decode the second signal to obtain the first decoded signal, and detect the first decoded signal. If the first decoded signal matches the preset signal, it indicates that the chip has entered the test mode.

[0017] After the chip enters the test mode, the data decoding unit is also used to receive multiple fourth signals and decode the multiple fourth signals in sequence to obtain multiple second decoded signals; the data conversion unit is used to convert the multiple second decoded signals in sequence and output enable signals and strobe signals according to the first-in-first-out principle.

[0018] In one possible implementation of the first aspect, the signal gating module includes a first switching unit and a plurality of second switching units. The control terminal of the first switching unit is connected to the test control module and receives the enable signal. The first terminal of the first switching unit is used to connect to an automatic test device through another input / output pin of the chip. The second terminal of the first switching unit is connected to the first terminal of the plurality of second switching units. The control terminal of each second switching unit is connected to the test control module and receives the gating signal. The second terminals of the plurality of second switching units are connected to the plurality of circuits under test one-to-one.

[0019] Secondly, embodiments of this application provide a test mode control method, applied to the test mode control circuit described in any one of the first aspects, comprising:

[0020] The data clock width discrimination module receives test mode data and clock single-line signal through one input / output pin of the chip, and processes the test mode data and clock single-line signal to obtain a first signal, which is a serial signal;

[0021] The data timing generation module receives test mode data and clock single-line signal through one input / output pin of the chip, processes the first signal according to the test mode data and clock single-line signal to obtain a second signal, which is a parallel signal;

[0022] The test control module detects the second signal. If the second signal matches a preset signal, it indicates that the chip has entered the test mode.

[0023] In one possible implementation of the second aspect, the method further includes:

[0024] After the chip enters the test mode, the data clock width discrimination module also receives test data and clock single-line signal through one of the chip's input / output pins, and processes the test data and clock single-line signal to obtain multiple third signals, which are serial signals;

[0025] The data timing generation module also receives test data and a clock single-line signal through an input / output pin of the chip, and processes multiple third signals sequentially according to the test data and the clock single-line signal to obtain multiple fourth signals, which are parallel signals.

[0026] The test control module generates an enable signal and a gating signal based on multiple fourth signals. The enable signal is used to control the operation of all circuits under test, and the gating signal is used to control the multiple circuits under test to output the test signal sequentially. The gating signal is a parallel signal.

[0027] The signal gating module outputs multiple signals to be tested sequentially according to the enable signal and the gating signal.

[0028] Thirdly, embodiments of this application provide a chip including the test mode control circuit described in any one of the first aspects.

[0029] The beneficial effects of the embodiments in this application compared with the prior art are:

[0030] This application provides a test mode control circuit, including a data clock width discrimination module, a data timing generation module, and a test control module, wherein the data timing generation module is connected to the data clock width discrimination module and the test control module respectively.

[0031] The data clock width discrimination module receives test mode data and clock single-line signal through one input / output pin of the chip, and processes the test mode data and clock single-line signal to obtain a first signal; the data timing generation module receives test mode data and clock single-line signal through one input / output pin of the chip, processes the first signal according to the test mode data and clock single-line signal to obtain a second signal; the test control module detects the second signal, and if the second signal matches the preset signal, it indicates that the chip has entered the test mode.

[0032] The test mode control circuit proposed in this application utilizes single-wire transmission technology to reliably enable the chip to enter DFT test mode using only one input / output pin. This eliminates the need for a dedicated test port, significantly reducing the number of ports, thereby decreasing chip size and design costs, and enhancing the chip's applicability and versatility. Compared to traditional multi-pin multiplexing schemes, this application, through single-wire transmission technology, reuses only one input / output pin, reducing test complexity, ATE costs, and test fixture complexity. It also shortens test time, reduces debugging difficulty and reliability risks, thus overcoming limitations on chip integration, test costs, and system reliability.

[0033] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic block diagram of a test mode control circuit provided in one embodiment of this application;

[0036] Figure 2 This is a schematic block diagram of a test mode control circuit provided in another embodiment of this application;

[0037] Figure 3 This is a schematic block diagram of a test mode control circuit provided in another embodiment of this application;

[0038] Figure 4 This is a schematic block diagram of a test mode control circuit provided in another embodiment of this application;

[0039] Figure 5 This is a circuit connection diagram of a test mode control circuit provided in an embodiment of this application;

[0040] Figure 6 This is a schematic block diagram of a test mode control circuit provided in another embodiment of this application;

[0041] Figure 7 This is a schematic block diagram of a test mode control circuit provided in another embodiment of this application;

[0042] Figure 8 This is a signal waveform diagram of a test mode control circuit provided in an embodiment of this application;

[0043] Figure 9 This is a signal waveform diagram of a test mode control circuit provided in another embodiment of this application;

[0044] Figure 10 This is a flowchart illustrating a test mode control method provided in an embodiment of this application;

[0045] Figure 11 This is a flowchart illustrating a test mode control method provided in another embodiment of this application.

[0046] In the diagram: 10. Data clock width discrimination module; 11. Signal edge detection unit; 12. Pulse width measurement unit; 13. Pulse width threshold judgment unit; 14. Noise filtering unit; 20. Data timing generation module; 30. Test control module; 31. Data decoding unit; 32. Data conversion unit; 40. Signal gating module; 41. First switching unit; 42. Second switching unit; 50. Circuit under test; 60. Automatic test equipment. Detailed Implementation

[0047] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0048] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0049] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0050] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0051] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0053] Currently, the industry standard for entering test mode is to reuse multiple functional I / O pins of a chip and configure these pins as "test mode entry control pins" under specific conditions. However, entering test mode by reusing multiple functional I / O pins has a series of significant and difficult-to-overcome drawbacks, such as:

[0054] (1) Increased test complexity and cost: It is necessary to accurately control the level or timing sequence of multiple functional I / O pins at the same time to reliably trigger the test mode, which is more difficult to achieve when the chip has fewer pins;

[0055] (2) Increased ATE cost: The number of drive / compare channels required by the ATE is significantly increased, which in turn drives up the cost of expensive ATE resources;

[0056] (3) Increased complexity and cost of test fixtures: The design, manufacturing and maintenance costs of test boards and probe cards are significantly increased due to the need to ensure the integrity of multiple signal paths (signal quality, timing synchronization), and the complex multi-signal wiring also increases the failure rate of the fixtures.

[0057] (4) Extended test time and increased debugging difficulty: The establishment, maintenance and verification of multi-signal combinations require longer test time, and the diagnosis of failure reasons (e.g., determining which pin signal does not meet the requirements) is also more complex and time-consuming;

[0058] (5) Reliability Risks: Specific multi-pin combinations used to enter test mode may be triggered by unexpected signal noise, interference, or specific operation sequences during normal chip operation, causing the chip to unexpectedly enter test mode, leading to system malfunctions, data errors, or even security risks. To avoid such combination conflicts, additional design constraints and more stringent verification are required, which increases the design burden. These problems severely restrict chip design efficiency, test cost control, and the competitiveness of the final product.

[0059] Therefore, the solution of reusing multiple functional I / O pins to enter test mode has become a key bottleneck restricting the improvement of chip integration, optimization of test costs and system reliability, and a better solution is urgently needed.

[0060] To address the aforementioned problems, embodiments of this application provide a test mode control circuit, applied to a chip, such as... Figure 1 As shown, the test mode control circuit includes a data clock width discrimination module 10, a data timing generation module 20, and a test control module 30. The data timing generation module 20 is connected to the data clock width discrimination module 10 and the test control module 30, respectively.

[0061] Specifically, the data clock width discrimination module 10 receives test mode data and clock single-line signals through one input / output pin (I / O pin) of the chip, and processes the test mode data and clock single-line signals: it discriminates the width of the high level and converts it into "1" or "0" to obtain a first signal, which is a serial signal. The data timing generation module 20 receives test mode data and clock single-line signals through one input / output pin of the chip, processes the first signal according to the test mode data and clock single-line signals, and obtains a second signal, which is a parallel signal. The data timing generation module 20 thus realizes the conversion from serial signal to parallel signal. The test control module 30 detects the second signal. If the second signal matches a preset signal, it indicates that the chip has entered the test mode. The preset signal is manually set and can be adjusted according to actual needs.

[0062] The test mode control circuit proposed in this application utilizes single-wire transmission technology to reliably enable the chip to enter DFT test mode using only one input / output pin. This eliminates the need for a dedicated test port, significantly reducing the number of ports, thereby decreasing chip size and design costs, and enhancing the chip's applicability and versatility. Compared to traditional multi-pin multiplexing schemes, this application, through single-wire transmission technology, reuses only one input / output pin, reducing test complexity, ATE costs, and test fixture complexity. It also shortens test time, reduces debugging difficulty and reliability risks, thus overcoming limitations on chip integration, test costs, and system reliability.

[0063] In some embodiments, such as Figure 2 As shown, the test mode control circuit also includes a signal gating module 40. The test control module 30 is connected to the signal gating module 40. The test control module 30 and the signal gating module 40 are respectively used to connect to multiple circuits under test 50. The signal gating module 40 is also used to connect to the automatic test equipment 60 through another input / output pin (I / O pin) of the chip.

[0064] Specifically, after the chip enters the test mode, the data clock width discrimination module 10 is also used to receive test data and clock single-line signals through one of the chip's input / output pins, and process the test data and clock single-line signals: it discriminates the width of the high level and converts it into "1" or "0" to obtain multiple third signals, which are serial signals. Since the test data and clock single-line signals contain multiple selection signals corresponding one-to-one with the circuit under test 50 after the chip enters the test mode, multiple third signals will be output after processing by the data clock width discrimination module 10. The data timing generation module 20 is also used to receive test data and clock single-line signals through one of the chip's input / output pins, and process the multiple third signals sequentially according to the test data and clock single-line signals to obtain multiple fourth signals, which are parallel signals. The data timing generation module 20 thus realizes the conversion from serial signals to parallel signals. The test control module 30 is also used to generate an enable signal test_enable and a strobe signal test_ctrl[n:0] based on the multiple fourth signals, where n is a natural number greater than 0. The enable signal `test_enable` controls the operation of all circuits under test (DUTs) 50. The number of bits in the strobe signal `test_ctrl[n:0]` is related to the number of DUTs 50. For example, when the number of DUTs 50 is 16, the number of bits in the strobe signal `test_ctrl[n:0]` is 4 bits. This strobe signal `test_ctrl[n:0]` controls multiple DUTs 50 to output test signals sequentially. The signal gating module 40 outputs multiple test signals sequentially according to the enable signal `test_enable` and the strobe signal `test_ctrl[n:0]`, so that the automatic test equipment 60 can test multiple DUTs 50 sequentially.

[0065] In some embodiments, such as Figure 3 As shown, the data clock width discrimination module 10 includes a signal edge detection unit 11, a pulse width measurement unit 12, and a pulse width threshold judgment unit 13. The pulse width measurement unit 12 is connected to the signal edge detection unit 11 and the pulse width threshold judgment unit 13, respectively. The pulse width threshold judgment unit 13 is connected to the data timing generation module 20.

[0066] Specifically, the signal edge detection unit 11 receives an input signal through one of the chip's input / output pins, detects the rising and falling edges of the input signal, outputs a first detection signal upon detecting each rising edge, and outputs a second detection signal upon detecting each falling edge; wherein the input signal is either test mode data and a single-wire clock signal or test data and a single-wire clock signal. The pulse width measurement unit 12 starts counting sequentially based on each first detection signal and stops counting based on each corresponding second detection signal, obtaining multiple pulse width values. The pulse width threshold judgment unit 13 judges each pulse width value, outputting "1" when the pulse width value is greater than the first threshold, and outputting "0" when the pulse width value is less than the second threshold, ultimately outputting a serial signal composed of "0" and "1". The first and second thresholds are set internally by the chip.

[0067] In some embodiments, such as Figure 4 As shown, the data clock width discrimination module 10 also includes a noise filtering unit 14, which is connected to the signal edge detection unit 11.

[0068] Specifically, the noise filtering unit 14 is used to receive the input signal through one of the chip's input / output pins and to filter the noise of the input signal to ensure the accuracy of the input signal.

[0069] In some embodiments, such as Figure 5 As shown, the data timing generation module 20 includes multiple D flip-flops. The number of D flip-flops is related to the number of circuits under test (DUT) 50. For example, when the number of DUT 50 is 16, the number of D flip-flops is 5. The clock input terminal CLK of each D flip-flop receives the input signal through an input / output pin of the chip, and the inverted output terminal of each D flip-flop... Each D flip-flop is connected to the test control module 30. The data input terminal D of the first D flip-flop is connected to the data clock width discrimination module 10. The non-inverting output terminal Q of each D flip-flop is connected to the data input terminal D of the next D flip-flop and the test control module 30, respectively. The input signal is either a test mode data and clock single-line signal or a test data and clock single-line signal.

[0070] Specifically, the data timing generation module 20 converts the serial signal output by the data clock width discrimination module 10 into a parallel signal through multiple D flip-flops. The parallel signal includes Q[n+1:0] and QN[n+1:0].

[0071] In some embodiments, such as Figure 6 As shown, the test control module 30 includes a data decoding unit 31 and a data conversion unit 32; the data decoding unit 31 is connected to the data timing generation module 20 and the data conversion unit 32 respectively.

[0072] Specifically, the data decoding unit 31 is used to receive a second signal, which includes Q[n+1:0] and QN[n+1:0], and to decode the second signal (Q[n+1:0] in the second signal) to obtain a first decoded signal. The first decoded signal is then detected. If the first decoded signal matches a preset signal, it indicates that the chip has entered the test mode.

[0073] After the chip enters the test mode, the data decoding unit 31 is also used to receive multiple fourth signals, including Q[n+1:0] and QN[n+1:0], and to decode the multiple fourth signals (Q[n+1:0] and QN[n+1:0] among the multiple fourth signals) sequentially to obtain multiple second decoded signals. The data conversion unit 32 is used to convert the multiple second decoded signals sequentially, and to output the enable signal test_enable and the strobe signal test_ctrl[n:0] according to the first-in-first-out (FIFO) principle.

[0074] In some embodiments, such as Figure 7 As shown, the signal gating module 40 includes a first switch unit 41 and multiple second switch units 42. The control terminal of the first switch unit 41 is connected to the test control module 30 and receives the enable signal test_enable. The first terminal of the first switch unit 41 is used to connect to the automatic test equipment 60 through another input / output pin of the chip. The second terminal of the first switch unit 41 is connected to the first terminal of multiple second switch units 42. The control terminal of each second switch unit 42 is connected to the test control module 30 and receives the gating signal test_ctrl[n:0]. The second terminals of multiple second switch units 42 are connected to multiple circuits under test 50 one by one.

[0075] Specifically, after the chip enters the test mode, the test control module 30 outputs an enable signal test_enable and a strobe signal test_ctrl[n:0]. The enable signal test_enable controls the first switching unit 41 to turn on, and the second switching unit 42 is controlled by the strobe signal test_ctrl[n:0]. When the strobe signal test_ctrl[n:0] controls the first circuit under test 50 to output a test signal, the second switching unit 42 corresponding to the first circuit under test 50 turns on according to the strobe signal test_ctrl[n:0], thereby transmitting the test signal output by the first circuit under test 50 to the automatic test equipment 60 so that the automatic test equipment 60 can test the first circuit under test 50. The selection principle of the remaining circuits under test 50 is the same as above.

[0076] Example 1

[0077] Assuming there are 16 circuits under test 50, then there are 5 D flip-flops in the data timing generation module 20, and the number of bits of the strobe signal test_ctrl[n:0] output by the test control module 30 is 4 bits, i.e. test_ctrl[3:0].

[0078] The data clock width discrimination module 10 receives test mode data and clock single-wire signals through one of the chip's input / output pins. The waveforms of the test mode data and clock single-wire signals are as follows: Figure 8 As shown, the signal consists of wide pulse high levels, numbered 1, 3, and 5, and narrow pulse high levels, numbered 2 and 4. The data clock width discrimination module 10 processes the test mode data and clock single-line signal: it discriminates the width of the high level and converts it into "1" or "0" to obtain the first signal. The data timing generation module 20 receives the test mode data and clock single-line signal through one of the chip's input / output pins, processes the first signal according to the test mode data and clock single-line signal, and obtains the second signal, which includes Q[4:0] and QN[4:0]. The test control module 30 detects the second signal. The specific detection process is as follows: the data decoding unit 31 decodes the second signal (only Q[4:0] in the second signal) to obtain 10101. The last digit "1" indicates that the test mode data and clock single-line signal have been sent. Then, 10101 is detected. If 10101 matches the preset signal, it indicates that the chip has entered the test mode.

[0079] After the chip enters test mode, the data clock width discrimination module 10 receives test data and clock single-wire signals through one of the chip's input / output pins. The waveforms of the test data and clock single-wire signals are as follows: Figure 9As shown, it includes 16 sets of selection signals. The first set of selection signals consists of a wide pulse high level, numbered 10, and a narrow pulse high level, numbered 6, 7, 8, and 9. The test data and clock single-line signal are processed: the width of the high level is identified and converted into "1" or "0", resulting in 16 third signals. The data timing generation module 20 receives the test data and clock single-line signal through one of the chip's input / output pins, and processes the 16 third signals sequentially according to the test data and clock single-line signal to obtain 16 fourth signals, including Q[4:0] and QN[4:0]. The test control module 30 generates an enable signal test_enable and a strobe signal test_ctrl[3:0] based on 16 fourth signals. The specific processing procedure is as follows: First, the data decoding unit 31 decodes the 16 fourth signals (Q[4:0] and QN[4:0] in the 16 fourth signals) in sequence to obtain 16 second decoded signals. Then, the data conversion unit 32 converts the 16 second decoded signals in sequence and outputs the enable signal test_enable and the strobe signal test_ctrl[3:0] according to the FIFO principle.

[0080] For the first set of selection signals, after processing, the strobe signal test_ctrl[3:0] is 0000, used to select the first circuit under test 50, and the enable signal test_enable goes high to enable all circuits under test 50. Similarly, by changing the combination of wide pulse high level and narrow pulse high level, 16 digital signals from 0000 to 1111 can be generated, namely the strobe signals test_ctrl[3:0], used to sequentially select 16 circuits under test. Finally, the signal selection module 40 sequentially outputs 16 test signals so that the automatic test equipment 60 can test the 16 circuits under test 50 sequentially. It should be noted that the last digit of each set of selection signals is "1", indicating that the selection signal has been sent.

[0081] For cases where more or fewer circuits under test 50 need to be tested, this can be achieved by increasing or decreasing the number of D flip-flops in the data timing generation module 20.

[0082] This application also provides a test mode control method, such as... Figure 10 As shown, the test mode control methods include S1-S3.

[0083] S1. The data clock width discrimination module receives test mode data and clock single-line signal through one input / output pin of the chip, and processes the test mode data and clock single-line signal to obtain the first signal, which is a serial signal.

[0084] Specifically, the data clock width discrimination module discriminates the width of the high level in the test mode data and clock single-line signal, converts it into "1" or "0", and obtains the first signal.

[0085] S2. The data timing generation module receives test mode data and clock single-line signal through one input / output pin of the chip. Based on the test mode data and clock single-line signal, it processes the first signal to obtain the second signal, which is a parallel signal.

[0086] Specifically, the data timing generation module converts the serial signal output by the data clock width discrimination module into a parallel signal based on the test mode data and the clock single-line signal.

[0087] S3. The test control module detects the second signal. If the second signal matches a preset signal, it indicates that the chip has entered the test mode. The preset signal is manually set and can be adjusted according to actual needs.

[0088] Specifically, the test control module determines whether the chip has entered the test mode by detecting the second signal: when the second signal matches the preset signal, it indicates that the chip has entered the test mode.

[0089] The test mode control method proposed in this application utilizes single-wire transmission technology to reliably enable the chip to enter DFT test mode using only one input / output pin. This eliminates the need for a dedicated test port, significantly reducing the number of ports, thereby decreasing chip size and design costs, and enhancing the chip's applicability and versatility. Compared to traditional multi-pin multiplexing schemes, this application, through single-wire transmission technology, reuses only one input / output pin, reducing test complexity, ATE costs, and test fixture complexity. It also shortens test time, reduces debugging difficulty and reliability risks, thus overcoming constraints on chip integration, test costs, and system reliability.

[0090] In some embodiments, such as Figure 11 As shown, the test mode control method also includes S4-S7.

[0091] S4. After the chip enters the test mode, the data clock width discrimination module also receives test data and clock single-line signal through one of the chip's input / output pins, and processes the test data and clock single-line signal to obtain multiple third signals, which are serial signals.

[0092] Specifically, after the chip enters test mode, the test data and clock single-line signals contain multiple selection signals that correspond one-to-one with the circuit under test. The data clock width discrimination module discriminates the width of the high level in this signal and converts it into "1" or "0", thereby generating a third signal that corresponds one-to-one with the selection signal.

[0093] S5. The data timing generation module also receives test data and clock single-line signal through one of the chip's input / output pins, and processes multiple third signals sequentially based on the test data and clock single-line signal to obtain multiple fourth signals, which are parallel signals.

[0094] Specifically, the data timing generation module converts multiple serial signals output by the data clock width discrimination module into parallel signals sequentially based on the test data and the clock single-line signal.

[0095] S6. The test control module generates an enable signal and a gating signal based on multiple fourth signals. The enable signal is used to control the operation of all circuits under test, and the gating signal is used to control multiple circuits under test to output the test signal in sequence. The gating signal is a parallel signal.

[0096] Specifically, after the chip enters the test mode, the test control module generates an enable signal based on multiple fourth signals. This signal controls all circuits under test to enter the working state. It also generates a gating signal. The number of bits in the gating signal is related to the number of circuits under test. By using different combinations of high and low levels, it controls multiple circuits under test to output the test signal in sequence.

[0097] S7. The signal gating module outputs multiple signals to be tested sequentially based on the enable signal and the gating signal.

[0098] Specifically, the signal gating module starts working under the control of the enable signal, and outputs multiple signals to be tested in sequence according to the timing logic of the gating signal, so that the automatic test equipment can test multiple circuits under test one by one.

[0099] This application also provides a chip, including the test mode control circuit described above. Since the chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0101] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A test mode control circuit, characterized in that, It includes a data clock width discrimination module, a data timing generation module, and a test control module, wherein the data timing generation module is connected to the data clock width discrimination module and the test control module respectively; The data clock width discrimination module is used to receive test mode data and clock single-line signal through one input / output pin of the chip, and process the test mode data and clock single-line signal to obtain a first signal; the data timing generation module is used to receive test mode data and clock single-line signal through the one input / output pin of the chip, and process the first signal according to the test mode data and clock single-line signal to obtain a second signal; the test control module is used to detect the second signal, and if the second signal matches a preset signal, it indicates that the chip has entered the test mode; The test mode control circuit further includes a signal gating module, the test control module is connected to the signal gating module, and the test control module and the signal gating module are respectively used to connect to multiple circuits under test; After the chip enters the test mode, the data clock width discrimination module is further configured to receive test data and clock single-line signals through one of the chip's input / output pins, and process the test data and clock single-line signals to obtain multiple third signals; the data timing generation module is further configured to receive test data and clock single-line signals through one of the chip's input / output pins, and process the multiple third signals sequentially according to the test data and clock single-line signals to obtain multiple fourth signals; the test control module is further configured to generate enable signals and gating signals according to the multiple fourth signals, the enable signals being used to control the operation of all circuits under test, and the gating signals being used to control the multiple circuits under test to output test signals sequentially; the signal gating module is configured to output the multiple test signals sequentially according to the enable signals and the gating signals. The data clock width discrimination module includes a signal edge detection unit, a pulse width measurement unit, and a pulse width threshold judgment unit. The pulse width measurement unit is connected to the signal edge detection unit and the pulse width threshold judgment unit, respectively. The pulse width threshold judgment unit is connected to the data timing generation module. The signal edge detection unit is used to receive an input signal through one of the chip's input / output pins, detect the rising and falling edges of the input signal, output a first detection signal when each rising edge of the input signal is detected, and output a second detection signal when each falling edge of the input signal is detected; the pulse width measurement unit is used to start counting sequentially according to each of the first detection signals, and stop counting according to each of the corresponding second detection signals, to obtain multiple pulse width values; The pulse width threshold judgment unit is used to judge each pulse width value. When the pulse width value is greater than the first threshold, it outputs "1" and when the pulse width value is less than the second threshold, it outputs "0". The data timing generation module includes multiple D flip-flops. The clock input of each D flip-flop receives an input signal through one of the chip's input / output pins. The inverted output of each D flip-flop is connected to the test control module. The data input of the first D flip-flop is connected to the data clock width discrimination module. The non-inverted output of each D flip-flop is connected to the data input of the next D flip-flop and the test control module. The input signal is either a test mode data and clock single-line signal or a test data and clock single-line signal.

2. The test mode control circuit according to claim 1, characterized in that, The data clock width discrimination module also includes a noise filtering unit, which is connected to the signal edge detection unit. The noise filtering unit is used to receive an input signal through one of the chip's input / output pins and to filter the noise from the input signal.

3. The test mode control circuit according to claim 1, characterized in that, The test control module includes a data decoding unit and a data conversion unit; the data decoding unit is connected to the data timing generation module and the data conversion unit respectively. The data decoding unit is used to receive the second signal, decode the second signal to obtain the first decoded signal, and detect the first decoded signal. If the first decoded signal matches the preset signal, it indicates that the chip has entered the test mode. After the chip enters the test mode, the data decoding unit is also used to receive multiple fourth signals and decode the multiple fourth signals in sequence to obtain multiple second decoded signals; the data conversion unit is used to convert the multiple second decoded signals in sequence and output enable signals and strobe signals according to the first-in-first-out principle.

4. The test mode control circuit according to claim 1, characterized in that, The signal gating module includes a first switching unit and multiple second switching units. The control terminal of the first switching unit is connected to the test control module and receives the enable signal. The first terminal of the first switching unit is used to connect to an automatic test device through another input / output pin of the chip. The second terminal of the first switching unit is connected to the first terminal of multiple second switching units. The control terminal of each second switching unit is connected to the test control module and receives the gating signal. The second terminals of the multiple second switching units are connected to multiple circuits under test one by one.

5. A test mode control method, applied to the test mode control circuit according to any one of claims 1-4, characterized in that, include: The data clock width discrimination module receives test mode data and clock single-line signal through one input / output pin of the chip, and processes the test mode data and clock single-line signal to obtain a first signal, which is a serial signal; The data timing generation module receives test mode data and clock single-line signal through one of the chip's input / output pins, processes the first signal according to the test mode data and clock single-line signal to obtain a second signal, which is a parallel signal; The test control module detects the second signal. If the second signal matches a preset signal, it indicates that the chip has entered the test mode.

6. The test mode control method according to claim 5, characterized in that, The method further includes: After the chip enters the test mode, the data clock width discrimination module also receives test data and clock single-line signal through one of the chip's input / output pins, and processes the test data and clock single-line signal to obtain multiple third signals, which are serial signals. The data timing generation module also receives test data and a clock single-line signal through one of the chip's input / output pins, and processes multiple third signals sequentially based on the test data and clock single-line signal to obtain multiple fourth signals, which are parallel signals. The test control module generates an enable signal and a gating signal based on multiple fourth signals. The enable signal is used to control the operation of all circuits under test, and the gating signal is used to control the multiple circuits under test to output the test signal sequentially. The gating signal is a parallel signal. The signal gating module outputs multiple signals to be tested sequentially according to the enable signal and the gating signal.

7. A chip, characterized in that, Includes the test mode control circuit as described in any one of claims 1-4.

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