Photoelectric co-packaging underfill isolation packaging framework and process

Abstract

The invention relates to the technical field of chip packaging, in particular to a photoelectric co-packaging underfill isolation packaging framework and process. According to the invention, the underfill glue blocking hole is additionally designed in the underfill glue diffusion area at the outer edge of the optical fiber slot hole on the adapter plate, and through the resistance effect (interface difference and liquid tension) of the underfill glue blocking hole on the flowing of the underfill glue, the glue overflow range is accurately controlled, and the underfill glue is prevented from covering the optical fiber coupler of the optical chip. By optimizing the underfill isolation design, efficient coupling of the optical chip and the optical fiber is ensured in the pollution direction of the underfill, meanwhile, the packaging gap between the photoelectric chips is reduced, and the packaging density and compactness are improved; the process tolerance, the product yield and the system performance of photoelectric packaging are remarkably improved, and the method is particularly suitable for the application fields of high-density and high-performance calculation and optical interconnection.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an underfill isolation packaging structure and process for optoelectronic co-packaging. Background Art

[0002] Co-Packaged Optics (CPO) is a key technology for achieving optical interconnection in data centers, cloud computing, AI computing, and other fields. By co-packaging optical chips and electrical chips on the same substrate, the electrical connection distance between the optical and electrical chips is significantly shortened, thereby significantly improving data transmission rate, bandwidth density, and system energy efficiency. However, during the optoelectronic co-packaging process, the coupling area between the optical fiber and the optical chip becomes a key and difficult point in process optimization due to its precision and sensitivity. The high-temperature resistance and incompatibility of optical chips with pigtails dictate that fiber-coupled packaging is usually the last packaging process (there are two reasons why the fiber must be packaged last: 1. The optical chip with pigtails is not resistant to high temperatures; 2. Even if it is resistant to high temperatures, the optical chip with pigtails is not compatible with the flip-chip process, and reflow soldering must be performed on a bare die;). Fiber couplers (such as grating couplers) are easily contaminated by underfill glue overflow, resulting in increased optical signal transmission loss, further affecting system performance.

[0003] In the prior art, the grating coupler is often designed to be away from the flip-chip packaging area of ​​the chip, and a certain amount of redundant space is reserved for the diffusion of the underfill to prevent the underfill from contaminating the grating coupler. However, this solution faces the following problems:

[0004] (1) Large package size: Due to the need to reserve sufficient space for the diffusion of the bottom filler, the package structure is not compact enough and it is difficult to meet the requirements of high-density integration.

[0005] (2) Reduced interconnection performance: The distance between the optical chip and the electrical chip increases, affecting the efficiency of the optoelectronic interconnection and system performance.

[0006] (3) Low packaging yield: The control requirements for underfill glue overflow are extremely high. A slight deviation may cause contamination of the fiber coupler, thereby reducing the packaging yield.

[0007] (4) High process precision requirements: The diffusion range of the bottom filler needs to be precisely controlled, which increases the process complexity and production cost.

[0008] Alternatively, a high-temperature resistant optical fiber array and its packaging process can be used to first couple the optical fiber to the optical chip before the flip-chip packaging process, thereby avoiding the impact of the underfill glue in the subsequent process on the optical chip. However, this solution has the following shortcomings:

[0009] (1) High-temperature resistant optical fiber technology is immature: At present, the development of high-temperature resistant optical fiber materials and their mass production are still in the exploratory stage, and their performance and stability cannot meet actual needs.

[0010] (2) Complex packaging process: High-temperature resistant fiber optic packaging involves special materials and processes, resulting in complex production processes, high manufacturing costs, and inadequate reliability verification. In addition, completing the fiber-coupled packaging first will lead to significant changes in the packaging structure. The prominent fiber array structure will cause the flip-chip packaging of the chip to face more unknown challenges, especially equipment compatibility and yield control.

[0011] In summary, existing optoelectronic co-packaging solutions still face many challenges in terms of underfill diffusion control, fiber coupling area protection, and packaging compactness. A new solution is urgently needed to achieve higher packaging density, higher coupling efficiency, lower packaging precision requirements, and higher product yield. Summary of the Invention

[0012] In response to the above-mentioned problems or shortcomings, in order to solve the problem that the existing optoelectronic co-packaging solutions cannot take into account the control of underfill diffusion, protection of the optical fiber coupling area and packaging compactness, the present invention provides an underfill isolation packaging architecture and process for optoelectronic co-packaging.

[0013] A photoelectric co-packaged bottom-fill isolation packaging architecture comprises a transfer board, an optical chip, a packaging substrate and an electrical chip.

[0014] The adapter board is provided with an adapter board soldering pad, an adapter board via-hole conductive column and an optical fiber slot through-hole, and is also provided with an underfill blocking hole.

[0015] The adapter plate pads and the adapter plate via conductive columns cooperate with the solder balls to achieve fixation and electrical connectivity between the adapter plate and the optical chip, the packaging substrate and the electrical chip.

[0016] After the packaging substrate, optical chip and electrical chip are fixed to the upper and lower surfaces of the adapter plate through their respective pads and solder balls, the gaps between the packaging substrate, optical chip, electrical chip and adapter plate are filled with underfill to provide structural support.

[0017] After assembly and fixation, the fiber slot through hole provides an accommodating channel space for aligning the external optical element with the optical coupler on the optical chip, thereby realizing optical coupling between the optical element and the optical chip during laser input or output.

[0018] There are multiple underfill blocking holes, which are arranged in the underfill diffusion area on the outer edge of the optical fiber slot hole and do not intersect with the optical fiber slot hole, and are used to block the underfill from flowing through the underfill blocking hole area.

[0019] Furthermore, the geometric size and position of the underfill blocking hole are determined by physical modeling and optimizing the design by precisely controlling the flow range of the underfill according to the viscosity coefficient and interfacial resistance of the liquid underfill in simulation software.

[0020] The resistance effect refers to the interface difference of the underfill flow area on the adapter board caused by the additional underfill blocking holes set on the adapter board, and the tension effect of the liquid underfill, which makes the underfill flow blocked by the underfill blocking holes, so that the underfill will not flow through the underfill blocking hole area, let alone flow into the optical fiber slot through-hole area.

[0021] Furthermore, the packaging substrate, optical chip and electrical chip are fixed on the surface of the adapter board by solder balls, copper-copper bonding or hybrid bonding, and the electrical interconnection between the optical chip and the electrical chip is achieved through the conductive columns of the adapter board via holes, and the electrical interconnection between the substrate redistribution circuit of the packaging substrate and the optical chip and the electrical chip is achieved.

[0022] Furthermore, the optical chip and the electrical chip are arranged on the same side surface or on different side surfaces of the adapter board.

[0023] Furthermore, the underfill blocking hole is a through hole that completely penetrates the adapter board, or a blind hole that does not completely penetrate the adapter board.

[0024] Furthermore, the shape of the underfill blocking hole is circular, rectangular or other different geometric shapes.

[0025] Furthermore, the underfill blocking holes are in a single-row array or a multi-row array.

[0026] Furthermore, a groove for accommodating the optical chip is provided on the packaging substrate to achieve a more compact packaging architecture.

[0027] Furthermore, the optical chip is a silicon photonic chip based on silicon material, an optical chip based on gallium arsenide GaAs material, an optical chip based on indium phosphide InP material, and other optoelectronic chips based on III-V compound materials.

[0028] Furthermore, the fiber coupler is a coupling structure of a grating coupler, an end coupler, a microlens, a microprism, a microreflector, a vertical surface emitting laser, and a vertical receiving detector, which is used to achieve efficient optical signal transmission coupling between the optical chip and the external optical fiber.

[0029] Compared with the prior art, the present invention has the following technical effects:

[0030] 1. Additional underfill blocking holes are designed on the adapter board to limit underfill overflow: The resistance to underfill flow (interface difference and liquid tension) created by the underfill blocking holes allows for precise control of the overflow range. In optoelectronic chip co-packaging applications, underfill contamination of fiber couplers (such as grating couplers) is effectively prevented.

[0031] 2. Compact Package Design: Precise design reduces the gap between the grating coupling area and the electronic chip (redundant space reserved for underfill diffusion), making the package more compact and improving system packaging density. Reducing the gap and optimizing overall system integration is particularly critical for high-density optical interconnect chip integration packaging.

[0032] 3. Improve process tolerance and product yield: Precise control of the overflow range reduces process complexity and fault tolerance, reduces packaging defects, and thus improves product yield.

[0033] 4. Protect the fiber coupler: By preventing the bottom filler from entering the fiber coupling area, the stability of the optical coupling performance between the fiber and the chip is ensured.

[0034] 5. Solve the compatibility of optoelectronic chip co-packaging processes: In conventional flip-chip packaging of electrical chips, the underfill will not affect the performance of the chip surface, but the surface of the optical chip needs to be coupled with the packaged optical fiber and cannot be covered and contaminated by the underfill. The traditional method is to encapsulate the optical fiber array first, and then perform high-temperature flip-chip packaging, but this requires the optical fiber array to be resistant to high temperatures and the flip-chip equipment to be modified, which faces great challenges. The present invention uses the adapter plate vias to block the underfill to protect the grating coupling area from contamination, so the optical fiber array can be packaged after the high-temperature flip-chip is completed, and conventional optical fibers and flip-chip equipment can be used, without the need for high-temperature resistant optical fibers and equipment modification.

[0035] In summary, the present invention implements precise control of the overflow range by designing additional underfill blocking holes in the underfill diffusion area on the outer edge of the fiber slot hole on the adapter board. This allows for precise control of the underfill flow through the underfill blocking holes (interface difference and liquid tension), thus preventing the underfill from covering the fiber coupler of the optical chip. By optimizing the underfill isolation design, the present invention ensures efficient coupling between the optical chip and the optical fiber in the direction of underfill contamination, while simultaneously reducing the packaging gap between the optoelectronic chips and improving packaging density and compactness. This significantly improves the process tolerance, product yield, and system performance of optoelectronic packaging, making it particularly suitable for high-density, high-performance computing and optical interconnect applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the optoelectronic co-packaging bottom fill isolation packaging architecture of the present invention.

[0037] Figure 2It is a top view of the optoelectronic co-packaging bottom fill isolation packaging structure of the present invention.

[0038] Figure 3 This is a schematic diagram of implementation case 2 of the optoelectronic co-packaging bottom fill isolation packaging architecture of the present invention.

[0039] Figure 4 This is a schematic diagram of implementation case 3 of the optoelectronic co-packaging bottom fill isolation packaging architecture of the present invention.

[0040] Figure 5 This is a schematic diagram of implementation case 4 of the optoelectronic co-packaging bottom fill isolation packaging architecture of the present invention.

[0041] Markings in the figure: (1) adapter board, (2) optical chip, (3) packaging substrate, (4) solder ball, (5) optical chip pad, (6) electrical chip, (7) bottom filler, (8) fiber coupler, (9) adapter board via conductive column, (10) substrate rewiring circuit, (11) bottom filler blocking hole, (12) fiber slot through hole, (13) adapter board rewiring. DETAILED DESCRIPTION

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0043] The specific packaging process flow of the above-mentioned optoelectronic co-packaging underfill isolation packaging architecture is as follows:

[0044] 1. The electronic chip is flip-chip packaged on one side of the adapter board using solder balls. The electrode pads of the electronic chip are electrically connected to the conductive posts of the adapter board's via holes. The adapter board is equipped with adapter board via holes, optical fiber slot holes, and underfill blocking holes. After the electronic chip is flip-chip packaged, the gap between the electronic chip and the adapter board is filled with underfill to provide structural support. During the underfill filling and curing process, the pre-cured underfill will not flow through the underfill blocking hole area, let alone the optical fiber slot through hole area, due to the sudden interface change at the edge of the underfill blocking hole relative to the adapter board and the liquid tension.

[0045] 2. The optical chip is also flip-chip packaged on the other side of the adapter board using solder balls. The electrode pads of the optical chip are electrically connected to the conductive posts of the adapter board's vias, and the opening area of ​​the fiber slot through-hole is aligned with the center of the fiber coupler area to enable the placement of the fiber array.

[0046] 3. After completing the flip-chip packaging of the optical chip, it is necessary to further fill the connection gap between the optical chip and the adapter board with underfill to provide structural support. During the underfill filling process, the underfill blocking hole will also be blocked by the interface and liquid tension, so that the underfill will not flow into the through-hole area of ​​the optical fiber slot.

[0047] 4. After encapsulating the electrical and optical chips, the entire adapter board is then soldered to the package substrate using solder balls, ensuring that the electrical chip's power supply and external signal connection ports are connected to the substrate's redistribution pads. A recess is provided in the center of the package substrate to accommodate the optical chip; the bottom surface of the optical chip is in thermal contact with the redistribution metal of the package substrate, ensuring efficient heat dissipation.

[0048] Example 1: Figure 1 As shown, the adapter board (1) is a silicon adapter board with a thickness of 200um and no redistribution layer circuit on the surface. (9) The conductive column of the adapter board via is a copper column with a diameter of 20um. The optical fiber slot hole (12) is set in the center of the adapter board, with a width of 1mm and a length of 2mm. A row of bottom filling blocking holes (11) with an aperture of 25um and a spacing of 50um are set on both sides of the optical fiber slot hole (12). The optical chip (2) is a silicon optical chip. Four single-mode optical fiber couplers (8) with a wavelength of 1550nm are set in the middle area of ​​the optical chip surface, with a channel spacing of 127um. One optical chip (2) and two electrical chips (6) are packaged on both surfaces of the adapter board through a solder ball flip-chip process. The connection gap between the chip and the adapter board is filled with epoxy resin bottom filling. The packaging substrate is an ABF substrate, which includes four layers of redistribution layers.

[0049] Principle of underfill barrier packaging architecture:

[0050] In optoelectronic co-packaging, optical chips typically need to be coupled to external optical fibers for optical signal input and output. However, conventional electronic chip packaging processes are often incompatible with optical chips, easily leading to contamination of the fiber coupling. This paper proposes a novel packaging structure to address the issue of underfill contamination in optoelectronic co-packaging.

[0051] like Figure 1 and Figure 2 The figure shows the basic structural cross-section and top view of Example 1: a plurality of bottom filling glue blocking holes (11) and optical fiber slot holes (12) are provided on the adapter plate (1), and the bottom filling glue blocking holes are arranged around the optical fiber slot holes. The geometric dimensions and positions of the bottom filling glue blocking holes are optimized and designed, and the flow range of the bottom filling glue (7) is accurately controlled by the liquid resistance.

[0052] The optical chip (2) and the electrical chip (6) are flip-chip packaged on the surface of the adapter plate (1), and the gaps between the chip, the adapter plate and the substrate are filled with bottom filler (7). Figure 2As shown, during the diffusion of the bottom fill glue, the bottom fill glue is blocked by the bottom fill glue blocking hole (11) and does not flow into the optical fiber slot hole (12), thereby protecting the optical fiber slot from contamination. The existence of the bottom fill glue blocking hole (11) can make the optical fiber slot hole closer to the edge of the electrical chip, and the packaging structure is more compact. During the flip-chip packaging process of the optical chip, it is also necessary to align the optical fiber slot hole (12) of the adapter plate (1) with the optical fiber coupler (8) on the optical chip (2) so that the optical fiber and the optical fiber coupler on the optical chip can be efficiently coupled to realize the input or output of the laser.

[0053] Example 2: Figure 3 As shown, the adapter board (1) is a silicon adapter board with a thickness of 300um and no redistribution layer circuit on the surface. (9) The conductive pillars of the adapter board via holes are copper pillars with a diameter of 25um. The optical fiber slot hole (12) is set in the center of the adapter board, which is a through hole with an aperture of 126um and a spacing of 127um. A row of bottom filling blocking holes (11) with an aperture of 25um and a spacing of 50um are set on both sides of the optical fiber slot hole (12). The optical chip (2) is a silicon optical chip. Four single-mode optical fiber couplers (8) with a wavelength of 1550nm are set in the middle area of ​​the optical chip surface, with a channel spacing of 127um. One optical chip (2) is flip-chip packaged on both surfaces of the adapter board through a hybrid bonding process, and two electrical chips (6) are flip-chip packaged through a solder ball process. The connection gap between the chip and the adapter board is filled with epoxy resin bottom filling. The packaging substrate is an ABF substrate, which includes four layers of redistribution layers.

[0054] Example 3: Figure 4 As shown, the adapter board (1) is a glass adapter board with a thickness of 200um and a redistribution layer circuit on the surface. (9) The conductive column of the adapter board via is a copper column with a diameter of 25um. The optical fiber slot hole (12) is set in the center of the adapter board, with a width of 1mm and a length of 2mm. A row of bottom filling blocking holes (11) with an aperture of 25um and a spacing of 50um are set on both sides of the optical fiber slot hole (12). The optical chip (2) is a silicon photonic chip. Four single-mode optical fiber couplers (8) with a wavelength of 1550nm are set in the middle area of ​​the optical chip surface, with a channel spacing of 127um. One optical chip (2) and two electrical chips (6) are packaged on both surfaces of the adapter board through a solder ball flip-chip process. The connection gap between the chip and the adapter board is filled with epoxy resin bottom filling. The packaging substrate is an ABF substrate, which includes 8 layers of redistribution layers.

[0055] Example 4: Figure 5As shown, the adapter board (1) is a glass adapter board with a thickness of 200um and no redistribution layer circuit on the surface. (9) The conductive column of the adapter board via is a copper column with a diameter of 25um. The optical fiber slot hole (12) is set in the center of the adapter board, with a width of 1mm and a length of 2mm. A row of bottom filling blocking holes (11) with an aperture of 25um and a spacing of 50um are respectively set on both sides of the optical fiber slot hole (12). The optical chip (2) is a silicon photonic chip. Four single-mode optical fiber couplers (8) with a wavelength of 1550nm are set in the middle area of ​​the optical chip surface, with a channel spacing of 127um. Optical chip electrode pads (5) are also required around the optical chip fiber couplers. An optical chip (2) and an electrical chip (6) are flip-chip packaged on the same side surface of the adapter board through a solder ball process. The connection gap between the chip and the adapter board is filled with epoxy resin bottom filling. The packaging substrate is an ABF substrate, comprising 16 redistribution wiring layers. Through holes of the same size are provided in the overlapping area between the packaging substrate and the optical fiber slot hole (12) on the adapter plate, ensuring that the optical fiber array can be inserted into the optical fiber slot hole (12) and contact the surface of the optical chip (2).

[0056] As can be seen from the above embodiments, the present invention achieves precise control of the overflow range by designing additional underfill blocking holes in the underfill diffusion area on the outer edge of the optical fiber slot hole on the adapter plate. The underfill blocking holes have a resistance effect on the flow of underfill (interface difference and liquid tension), thereby avoiding the underfill covering the optical chip of the optical fiber coupler. By optimizing the underfill isolation design, the present invention ensures efficient coupling between the optical chip and the optical fiber in the direction of underfill contamination, while reducing the packaging gap between the optoelectronic chips, improving the packaging density and compactness; significantly improving the process tolerance, product yield and system performance of the optoelectronic package, and is particularly suitable for high-density, high-performance computing and optical interconnect applications.

Claims

1. An underfill isolation packaging architecture for optoelectronic co-packaging, comprising an adapter board, an optical chip, a packaging substrate, and an electrical chip, characterized in that: The adapter board is provided with an adapter board solder pad, an adapter board via conductive column and an optical fiber slot through hole, and is also provided with an underfill blocking hole; The adapter plate pads and the conductive posts of the adapter plate vias cooperate with the solder balls to achieve fixation and electrical connectivity between the adapter plate and the optical chip, the packaging substrate and the electrical chip. After the package substrate, optical chip and electrical chip are fixed to the upper and lower surfaces of the adapter plate through their respective pads and solder balls, the gaps between the package substrate, optical chip, electrical chip and adapter plate are filled with underfill to provide structural support; After assembly and fixation, the fiber slot through hole provides a channel space for aligning the external optical element with the optical coupler on the optical chip, realizing optical coupling between the optical element and the optical chip during laser input or output; There are multiple bottom filling glue blocking holes, which are arranged in the bottom filling glue diffusion area on the outer edge of the optical fiber slot hole and do not intersect with the optical fiber slot hole.

2. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The geometric size and position of the underfill blocking hole are determined by physical modeling and optimizing the design by accurately controlling the flow range of the underfill according to the viscosity coefficient and interfacial resistance of the liquid underfill in simulation software; The resistance effect refers to the interface difference of the underfill flow area on the adapter board caused by the additional underfill blocking holes set on the adapter board, and the tension effect of the liquid underfill, which makes the underfill flow blocked by the underfill blocking holes, so that the underfill will not flow into the through hole area of ​​the optical fiber slot.

3. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The fixing method of the pads and solder balls between the packaging substrate, optical chip, electrical chip and the surface of the adapter board is replaced by copper-copper bonding or hybrid bonding; then the electrical interconnection between the optical chip and the electrical chip is achieved through the conductive columns of the adapter board via holes, and the electrical interconnection between the substrate redistribution circuit of the packaging substrate and the optical chip and the electrical chip is achieved.

4. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The optical chip and the electrical chip are arranged on the same side surface or on different side surfaces of the adapter board.

5. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The bottom filling blocking hole is a through hole that completely penetrates the adapter board, or a blind hole that does not completely penetrate the adapter board.

6. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The shape of the underfill blocking hole is circular, rectangular or other different geometric shapes.

7. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The bottom filling blocking holes are arranged in a single row array or a multi-row array.

8. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The packaging substrate is provided with a groove for accommodating the optical chip to achieve a more compact packaging structure.

9. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The optical chip is a silicon optical chip based on silicon material, an optical chip based on gallium arsenide (GaAs) material, an optical chip based on indium phosphide (InP) material, and other optoelectronic chips based on III-V compound materials.

10. The optoelectronic co-package underfill isolation packaging structure according to claim 1, wherein: The fiber coupler is a coupling structure of a grating coupler, an end coupler, a microlens, a microprism, a microreflector, a vertical surface emitting laser, and a vertical receiving detector, and is used to achieve efficient optical signal transmission coupling between the optical chip and the external optical fiber.

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