On-chip meta-structure surface and design method thereof, and mass storage and encryption method
By designing an on-chip metasurface consisting of a planar substrate, a waveguide layer, and a nanostructure, and combining multiple three-dimensional target images with optical diffraction calculations, the problems of low holographic information storage capacity and insufficient security on the on-chip metasurface were solved, achieving highly integrated three-dimensional holographic storage and encryption.
Patent Information
- Application Number
- CN202510634174.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-16
- Publication Date
- 2025-09-16
AI Technical Summary
In the existing technology, the on-chip metasurface holographic information storage capacity is low and the security is insufficient, which makes it difficult to meet the design requirements of high-density photonic information processing and secure optoelectronic devices.
An on-chip metasurface is designed. By constructing a unit structure consisting of a planar substrate, a waveguide layer and a nanostructure, the position and phase distribution of the nanostructure are determined using multiple three-dimensional target images and optical diffraction calculation methods, thereby achieving highly integrated three-dimensional holographic storage and encryption.
It realizes three-dimensional large-capacity holographic storage and encryption, improves the security and capacity of information storage, and is suitable for fields such as three-dimensional display, optical information storage, and encryption and anti-counterfeiting.
Smart Images
Figure CN120652673A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of micro-nano optics, and in particular relates to an on-chip metasurface and a design method thereof, as well as a large-capacity storage and encryption method. Background Art
[0002] In the field of photonic integrated circuit technology, subwavelength-scale optical waveguide systems provide an innovative platform for on-chip light field manipulation. Their unique in-plane guided mode control properties open up new dimensions for high-speed optical information processing. To overcome the functional limitations of traditional integrated photonic devices, novel integrated photonic components based on waveguide platforms (such as metasurfaces) are gradually achieving modular integration and collaborative design, significantly expanding the degrees of freedom of optical control and device functionality.
[0003] Classical metasurfaces, arrays of artificially designed subwavelength structures, demonstrate remarkable wavefront manipulation capabilities in free-space optical systems, enabling multidimensional control of lightwave phase, amplitude, and polarization. They have been widely applied in cutting-edge fields such as beam steering, precision sensing, and computational imaging. Research progress has demonstrated that heterogeneous integration of metasurfaces with waveguide systems (i.e., constructing on-chip metainterfaces) can establish a controllable coupling mechanism between guided and radiating modes. This hybrid waveguide-metasurface system combines the advantages of miniaturization with a novel control dimension, offering an innovative solution for the development of waveguide-driven holography. Notably, such systems, with their unique near-field coupling properties and zero-order diffraction suppression, are demonstrating significant value in novel photonic applications such as augmented reality displays. Although holographic encoding strategies based on multi-parameter manipulation, such as polarization multiplexing and wavelength response, have been developed, achieving ultra-high-density holographic information storage remains a bottleneck in nanophotonic devices due to the intrinsic properties of subwavelength structures.
[0004] Existing information encryption schemes mostly use linear coding strategies, which have a single encryption dimension and are vulnerable to reverse engineering attacks, making it difficult to meet the design requirements of high-security on-chip photonic devices. Summary of the Invention
[0005] In order to solve the problem that holography achieved by on-chip metasurfaces in the existing technology is limited by low information capacity and security needs to be improved, the present invention provides an on-chip metasurface and its design method, large-capacity storage and encryption method, which have the characteristics of flexible design, compact structure, and high integration. Its application will promote the coordinated development of high-density photonic information processing and secure optoelectronic devices, and provide core device support for the next generation of secure communications and intelligent display systems.
[0006] According to one aspect of the present invention, a method for designing an on-chip metasurface is provided, comprising: constructing a unit structure forming an on-chip metasurface, wherein the unit structure includes a planar substrate, a waveguide layer located above the planar substrate, and nanostructures disposed on a working surface of the waveguide layer, wherein all nanostructures included in the on-chip metasurface have the same size; Select multiple three-dimensional target images that meet the design quantity, and the multiple three-dimensional target images correspond to several random positions in the free space ( x , y , z ); Taking the position of the nanostructures in the respective unit structures as a first phase influencing factor, and taking the propagation phase of the input guided wave of a specific working wavelength in the waveguide layer as a second phase influencing factor; Based on the multiple three-dimensional target images, the positions of the nanostructures in a plurality of unit structures are determined in combination with the first phase influencing factor and the second phase influencing factor, and the designed on-chip metasurface is obtained after arrangement.
[0007] As a further technical solution, the nanostructure is a rectangular columnar structure; the directions of the two sides parallel to the working surface of the waveguide layer are respectively set as the x-axis and the y-axis to establish an xoy coordinate system, and the major axis and the minor axis of the nanostructure are parallel to the working surface of the waveguide layer; the periods of the unit structure along the x-axis direction and the y-axis direction are respectively P x 、 P y When the waveguide transmission direction is along the x-axis, the phase modulation corresponding to the working wavelength λ is expressed as: φ d +β x ;in, φ d represents the detour phase; β represents the propagation constant corresponding to the operating wavelength λ, and βx represents the propagation phase of the guided wave.
[0008] As a further technical solution, the detour phase is expressed as: φ d =2πΔ x / P x ; Among them, Δ x It represents the displacement of the nanostructure along the propagation direction of the guided wave in its respective unit structure.
[0009] As a further technical solution, the working wavelengths of the multiple three-dimensional target images are λ The corresponding phase modulation is expressed as: φ d +β x。
[0010] As a further technical solution, the tortuous phase distribution of the on-chip metasurface is calculated using an inverse optimization algorithm and an optical diffraction calculation method.
[0011] As a further technical solution, the inverse optimization algorithm adopts a simulated annealing algorithm or a gradient descent algorithm, and the optical diffraction calculation method adopts an angular spectrum method.
[0012] As a further technical solution, the material of the planar substrate is silicon dioxide, the material of the waveguide layer is silicon nitride, and the material of the nanostructure is silicon or titanium dioxide.
[0013] According to one aspect of the present invention, there is provided an on-chip metasurface, which is obtained by using the on-chip metasurface design method.
[0014] According to one aspect of the present invention, a method for large-capacity storage of an on-chip metasurface is provided, wherein a laser of a selected operating wavelength is coupled along a waveguide transmission direction to be incident on a waveguide layer in the on-chip metasurface for transmission, and observation is performed above the on-chip metasurface using a microscope. By adjusting the working distance of the microscope's objective lens, a plurality of three-dimensional target images meeting a designed number can be sequentially observed.
[0015] According to one aspect of the present invention, an encryption method for an on-chip metasurface is provided, wherein a laser of a selected working wavelength is coupled along a waveguide transmission direction to be incident on a waveguide layer in the on-chip metasurface for transmission, and a microscope is used to observe above the on-chip metasurface. The designed on-chip metahologram is encrypted by different spatial position keys ( x , y , z ) to independently reconstruct holographic images at arbitrary free-space coordinates.
[0016] One or more technical solutions provided in the present invention have at least the following technical effects or advantages: The present invention first constructs a unit structure forming an on-chip metasurface, which includes a planar substrate, a waveguide layer located above the planar substrate, and a nanostructure disposed on a working surface of the waveguide layer. All nanostructures contained in the on-chip metasurface have the same size. Then, multiple three-dimensional target images meeting the design quantity are selected, and the multiple three-dimensional target images correspond to several random positions in free space ( x , y , z); the position of the nanostructures in their respective unit structures is then used as the first phase influencing factor, and the propagation phase of the input waveguide at the operating wavelength in the waveguide layer is used as the second phase influencing factor; based on multiple three-dimensional target images, the positions of the nanostructures in several unit structures are determined in combination with the first and second phase influencing factors, and the designed on-chip metasurface is obtained after arrangement. That is, the nanostructures in the present invention have coordinate positions that can be individually set within a periodic range, and the change in their coordinate positions provides a circuitous phase modulation of the on-chip waveguide; the present invention utilizes the connection between the propagation phase accumulated on the chip of the waveguide at the operating wavelength and the circuitous phase generated by the position of the nanostructure in the unit structure to optimize the design of the holographic image projected by the on-chip metasurface at the operating wavelength, and utilizes the characteristics of optical Fresnel diffraction to achieve three-dimensional large-capacity holographic storage with spatially varying characteristics.
[0017] In addition, the present invention also provides other methods for on-chip metasurfaces. One method is to couple a laser of a selected working wavelength along a waveguide transmission direction into a waveguide layer in the on-chip metasurface for transmission, and transmit the laser to any three-dimensional coordinate ( x , y , z ) is observed using a microscope in the free space of the image. The holographic image can be displayed specifically at any position in the free space by specifying the specific target image spatial position information, thereby realizing the encryption and decryption process of the optical information.
[0018] In summary, the present invention has the characteristics of flexible design, compact structure, and high integration. It can realize three-dimensional holography by using on-chip metasurfaces and can be applied to fields such as three-dimensional display, optical information storage, and encryption and anti-counterfeiting. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1 Schematic diagram of the on-chip metasurface provided in Example 1 for achieving three-dimensional large capacity and secure encryption; Figure 2 Schematic diagram of the nanostructures and their positional arrangement in the on-chip metasurface provided in Example 1; Figure 3 Schematic diagram of achieving three-dimensional large-capacity and securely encrypted holographic projection observation using an on-chip metasurface in an application of the on-chip metasurface provided in Example 3; Figure 4 1 is a diagram showing experimental results of realizing three-dimensional large-capacity holographic projection using an on-chip metasurface in an application of the on-chip metasurface provided in Example 3; Figure 5 This is a schematic diagram of secure encryption based on three-dimensional holography of an on-chip metasurface in an application of an on-chip metasurface provided in Example 4; Figure 6 This is a diagram showing the experimental results of secure optical information transmission based on three-dimensional holography of the on-chip metasurface in the application of the on-chip metasurface provided in Example 4. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention are arbitrarily combined with each other to form a new technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention. Example 1
[0022] Example 1 provides a method for designing an on-chip metasurface, which mainly includes the following steps: Step 1: Design the metasurface structure.
[0023] A unit structure is constructed to form an on-chip metasurface. The unit structure includes a planar substrate, a waveguide layer located above the planar substrate, and nanostructures disposed on a working surface of the waveguide layer. All nanostructures included in the on-chip metasurface have the same size. That is, a plurality of the nanostructures constitute a nanostructure array, and each nanostructure in the nanostructure array has a coordinate position that can be individually set.
[0024] Among them, see Figure 1 、 Figure 2 The nanostructure can be a rectangular parallelepiped column structure, and the size parameters of the nanostructure include length L ,Width W and high H ; The directions of the two sides parallel to the working surface of the waveguide layer are respectively set as x Axis and yThe xoy coordinate system is established along the axis, and the long axis and the short axis of the nanostructure are parallel to the working surface of the waveguide layer; x Axis direction, y The periods in the axial direction are P x 、 P y .
[0025] The planar substrate is made of a low-refractive-index transparent optical material, such as silicon dioxide; the waveguide layer is made of a low-loss waveguide material, such as silicon nitride; and the nanostructure is made of a high-refractive-index dielectric material, such as silicon and titanium dioxide.
[0026] Step 2: Select the target image and operating wavelength.
[0027] Select multiple three-dimensional target images that meet the design quantity, wherein the multiple three-dimensional target images are composed of randomly distributed letters. The multiple three-dimensional target images correspond to several random positions in the free space ( x , y , z ).
[0028] The present invention can obtain a target image corresponding to the working wavelength by extracting the guided wave, and multiple three-dimensional target images (i.e., three-dimensional holographic images) are different holographic projections that can be observed at different spatial positions.
[0029] Step 3: Calculate the metasurface phase distribution and determine the location of the nanostructures.
[0030] The positions of the nanostructures in their respective unit structures are used as a first phase influencing factor, and the propagation phase of the input guided wave of the working wavelength in the waveguide layer is used as a second phase influencing factor. Based on the multiple three-dimensional target images, the positions of the nanostructures in several unit structures are determined in combination with the first phase influencing factor and the second phase influencing factor, and the designed on-chip metasurface is obtained after arrangement.
[0031] That is, the present invention arranges and designs a plurality of nanostructures in combination with the first phase influencing factor and the second phase influencing factor, so that the on-chip metasurface can obtain a target image at the working wavelength under the phase modulation of the working wavelength.
[0032] Along the waveguide transmission direction x Axis direction as an example, the working wavelength λ The corresponding phase modulation is expressed as: φ d + βx ;in, φ d Indicates a circuitous phase; βIndicates the operating wavelength λ The corresponding propagation constant, βx Denotes the propagation phase. The detour phase is expressed as: φ d =2πΔ x / P x ; Among them, Δ x Indicates that the nanostructures are located in their respective unit structures along x The present invention changes the coordinate position of the nanostructure in each unit structure by Δ x , the detour phase can be obtained φ d modulation capabilities.
[0033] Specifically, step 3 can be divided into two stages. In the first stage, the tortuous phase distribution of the on-chip metasurface is calculated using an inverse optimization algorithm (simulated annealing algorithm, gradient descent algorithm, etc.) and an optical diffraction calculation method (such as the angular spectrum method, etc.). By utilizing the characteristics of Fresnel diffraction, different holographic images can be designed for the light scattered by the on-chip metasurface at any position in the free space, thereby realizing large-capacity holographic display and storage. Therefore, the first stage can determine the phase distribution of the on-chip metasurface based on the target image. In the second stage, based on the obtained phase distribution of the on-chip metasurface and combined with the tortuous phase modulation principle, when the guided wave is transmitted along the x-direction, the coordinate position of the nanostructure in the x-direction is adjusted, and finally the complete design of the three-dimensional holographic on-chip metasurface is realized.
[0034] The on-chip metasurface obtained by the on-chip metasurface design method provided in Example 1 can realize three-dimensional holography. The following is an example of using an on-chip metasurface to realize the display of 161-channel holographic projection in three-dimensional space with reference to parameters.
[0035] See also Figure 1 、 Figure 2 The on-chip metasurface consists of nanostructures with independently configurable coordinate positions within a period along the x-direction, arranged above a waveguide layer. In this example, the nanostructures are made of silicon, the waveguide layer is made of silicon nitride, and the planar substrate is made of silicon dioxide. The thickness of the silicon dioxide planar substrate is 500 μm, the thickness of the waveguide layer is 190 nm, and the height of all nanostructures in the array is H =360 nm, the top surface length is L =90 nm, the top surface width is W =90 nm, the unit structure is along x and y The cycle settings for the direction are P x =360 nm and P y=360 nm.
[0036] The technical principle of the present invention to realize the three-dimensional holographic image display is: when the fundamental waveguide mode (TE0) propagates horizontally in the optical waveguide, its propagation constant β When the waveguide is affected by the nanostructure on the waveguide layer, scattering outcoupling occurs. At this time, the outcoupled light wave carries a circuitous phase determined by the relative position of the nanostructure within the unit period. φ d and the accumulated transmission phase when affected by the nanostructure βx , where x is set as the relative coordinate of the nanostructure in the unit structure. φ d The reverse calculation can be performed according to the optimization algorithm. βx The wavelength dependence of the working wavelength allows the light beam to project a holographic image at a specific location in the same observation area. Three-dimensional holographic display, based on Fresnel-type holography, can form different holographic images at different spatial locations directly above the metasurface. Example 2
[0037] Example 2 provides an on-chip metasurface, which is obtained using the on-chip metasurface design method described in Example 1.
[0038] The on-chip metasurface comprises a plurality of unit structures, each comprising a planar substrate, a waveguide layer positioned above the planar substrate, and nanostructures disposed on a working surface of the waveguide layer. All nanostructures contained in the on-chip metasurface have identical dimensions. The positions of the nanostructures within the unit structures are determined according to the design method described in Example 1. After arrangement, the designed on-chip metasurface is obtained. Example 3
[0039] Example 3 provides a large-capacity storage method for an on-chip metasurface, wherein a laser of a specific working wavelength is coupled along a waveguide transmission direction and incident on a waveguide layer in the on-chip metasurface as described in Example 2 for transmission. A microscope is used to observe above the on-chip metasurface. By adjusting the working distance of the objective lens of the microscope, multiple three-dimensional target images meeting the designed number can be observed in sequence.
[0040] That is, Example 3 uses a laser light source with a specific wavelength that meets the design requirements to be coupled into the waveguide along a specific direction for transmission, and a microscope is used to observe a specific position above the on-chip metasurface. The designed three-dimensional hologram is observed by adjusting the position of the objective lens.
[0041] In order to observe the three-dimensional holographic image, the Figure 3The observation setup shown. The fundamental waveguide mode required for holographic reconstruction can be incident by laser coupling in free space. The light waves scattered by the on-chip metasurface can be collected by a microscope objective lens located directly above the on-chip metasurface, and the projected holographic image can be observed through a microscope. By vertically adjusting the working distance of the objective lens, the position of the focal plane is kept consistent with the designed holographic image plane, and holographic images at different positions are observed on the same focal plane, that is, when the observation plane is located at different spatial positions directly above the on-chip metasurface When the 3D holographic image is reconstructed, different reconstructed holographic images can be observed at the corresponding positions in the 3D database. The 3D holographic image display function with up to 161 channels is successfully realized. The magnified area clearly displays the 24-channel image. The experimental results of the 3D holographic image are as follows: Figure 4 shown. Example 4
[0042] Example 4 provides an encryption method for an on-chip metasurface, wherein a laser of a specific working wavelength is coupled along a waveguide transmission direction to be incident on a waveguide layer in the on-chip metasurface as described in Example 2 for transmission, and a microscope is used to observe above the on-chip metasurface. The designed on-chip metahologram can be encrypted by using different spatial position keys ( x , y , z ) independently reconstructs the holographic image at any free space coordinate. Only by correctly identifying the precise spatial coordinates of a specific target image ( x , y , z ) in order to decrypt the corresponding holographic information, thereby greatly enhancing the security of the on-chip three-dimensional data storage library.
[0043] The overall structural layout and unit structure selection of the on-chip metasurface involved in Example 4 are designed based on the principles described in Example 1. Example 4 uses on-chip metasurface-based 3D holography to implement a customized optical data transmission encryption strategy, which is illustrated below with parameters.
[0044] Example 4: Encrypt each letter in the phrase "I LOVE WHU" based on the three-dimensional space target image position, and then use the corresponding holographic image spatial position information (key - x , key- y , key- z ) is decrypted and the letters in the phrase are successfully displayed separately.
[0045] The present invention can realize the principle of secure encryption: the encryption and decryption of optical data are determined by the spatial position of different target images ( x , y , z) is determined by the optical information. In the encryption framework, the optical information, known as plaintext, is first converted into a three-dimensional free space position. The corresponding encryption key is then linked to the spatial coordinates of the specified target image, ensuring that the optical information is securely encrypted into the three-dimensional metahologram. The decryption process is the opposite, requiring precise knowledge of the spatial position of the target image to reconstruct the holographic information, thereby achieving complete retrieval of the transmitted optical data. It is worth noting that in this encryption scheme, the spatial coordinates of the target image can be arbitrary, further improving the security of data transmission by introducing additional spatial randomness. Figure 5 、 Figure 6 Schematic diagram of secure optical information transmission and experimental results.
[0046] In summary, the present invention uses the position of the nanostructures in their respective unit structures as a first phase influencing factor, and the transmission phase of the input waveguide of the working wavelength in the waveguide layer as a second phase influencing factor; based on multiple three-dimensional target images, the positions of the nanostructures in several unit structures are determined in combination with the two phase influencing factors, and the designed on-chip metasurface is obtained after arrangement. The present invention also provides multiple applications, one of which is to achieve multiple three-dimensional target images by adjusting the working distance of the microscope objective lens and observing the position (x, y, z) of the target image in three-dimensional free space. Another is that the designed on-chip metahologram can independently reconstruct the holographic image at any free space coordinate using different spatial position keys (x, y, z), thereby improving the security of optical information transmission. The present invention has a flexible design, compact structure, and high integration, and can use on-chip metasurfaces to realize three-dimensional large-capacity holographic encryption applications.
[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.
Claims
1. A method for designing an on-chip metasurface, characterized in that: include: constructing a unit structure forming an on-chip metasurface, wherein the unit structure includes a planar substrate, a waveguide layer located above the planar substrate, and nanostructures disposed on a working surface of the waveguide layer, wherein all nanostructures included in the on-chip metasurface have the same size; Select multiple three-dimensional target images that meet the design quantity, and the multiple three-dimensional target images correspond to several random positions in the free space ( x , y , z ); Taking the position of the nanostructures in the respective unit structures as a first phase influencing factor, and taking the propagation phase of the input guided wave of a specific working wavelength in the waveguide layer as a second phase influencing factor; Based on the multiple three-dimensional target images, the positions of the nanostructures in a plurality of unit structures are determined in combination with the first phase influencing factor and the second phase influencing factor, and the designed on-chip metasurface is obtained after arrangement.
2. The method for designing an on-chip metasurface according to claim 1, wherein: The nanostructure is a rectangular columnar structure; the directions of the two sides parallel to the working surface of the waveguide layer are set as the x-axis and y-axis to establish an xoy coordinate system, and the major axis and minor axis of the nanostructure are parallel to the working surface of the waveguide layer; the periods of the unit structure along the x-axis and y-axis are respectively P x 、 P y When the waveguide transmission direction is along the x-axis, the phase modulation corresponding to the working wavelength λ is expressed as: φ d +β x ;in, φ d represents the detour phase; β represents the propagation constant corresponding to the operating wavelength λ, and βx represents the propagation phase of the guided wave.
3. The method for designing an on-chip metasurface according to claim 2, wherein: The detour phase is expressed as: φ d =2πΔ x / P x ; Among them, Δ x It represents the displacement of the nanostructure along the propagation direction of the guided wave in its respective unit structure.
4. The method for designing an on-chip metasurface according to claim 2, wherein: The working wavelengths of the multiple three-dimensional target images λ The corresponding phase modulation is expressed as: φ d +β x。 5. The method for designing an on-chip metasurface according to claim 2, wherein: The circuitous phase distribution of the on-chip metasurface is calculated using an inverse optimization algorithm and an optical diffraction calculation method.
6. The method for designing an on-chip metasurface according to claim 5, wherein: The reverse optimization algorithm adopts a simulated annealing algorithm or a gradient descent algorithm, and the optical diffraction calculation method adopts an angular spectrum method.
7. The method for designing an on-chip metasurface according to claim 1, wherein: The material of the planar substrate is silicon dioxide, the material of the waveguide layer is silicon nitride, and the material of the nanostructure is silicon or titanium dioxide.
8. An on-chip metasurface, characterized in that: The method for designing an on-chip metasurface according to any one of claims 1 to 7 is used.
9. A method for large-capacity storage of on-chip metasurfaces, characterized in that: A laser of a selected working wavelength is coupled along a waveguide transmission direction and incident on the waveguide layer in the on-chip metasurface as claimed in claim 8 for transmission. A microscope is used to observe above the on-chip metasurface. By adjusting the working distance of the objective lens of the microscope, a plurality of three-dimensional target images meeting the designed number can be observed in sequence.
10. An encryption method for an on-chip metasurface, characterized in that: A laser of a selected working wavelength is coupled along a waveguide transmission direction to be incident on the waveguide layer of the on-chip metasurface as claimed in claim 8 for transmission, and a microscope is used to observe above the on-chip metasurface. The designed on-chip metahologram is transmitted by different spatial position keys ( x , y , z ) to independently reconstruct holographic images at arbitrary free-space coordinates.