Apparatus and method for high speed input / output

Abstract

The application relates to the technical field of data processing and provides a device and a method for high-speed input and output. The device comprises cross-clock-domain sending transmission logic, which is used for periodically receiving N-tap input data of single-tap N bits according to a write clock signal, and writing the input data into the cross-clock-domain sending transmission logic bit by bit according to the value of each bit of an N-bit write enable control signal, and reading output data according to a read enable control signal; cross-clock-domain sending control logic, which is used for writing the write enable control signal into the cross-clock-domain sending control logic, reading a gate signal according to a read clock signal, and gating the read clock signal according to the gate signal to obtain the read enable control signal; and the frequency ratio of the read and write clock signals is N. In this way, the interaction between the read and write pointers across the clock domains is avoided, the logic depth and chip complexity are reduced, the speed is improved, and the power consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to an apparatus and method for high-speed input and output. BACKGROUND

[0002] In high-performance memory applications, such as the fourth-generation and fifth-generation technical specifications of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM), i.e., the technical specifications of DDR4 and DDR5, the design of the Physical Layer (PHY) of the memory proposes to transmit multiple signals from the physical layer to the Dynamic Random Access Memory (DRAM) under the premise of ensuring signal quality, and these signals may have extremely high frequencies, and the challenges of cross-clock domain transmission and the delay differences between different traces on the circuit board also need to be considered. For example, according to the technical specification of DDR5, when the transmission rate of the Data Strobe (DQ) signal is 6400 bits per second (bps), the transmission rate of the command / address (CA) signal can be as high as 3200 Mbps, which means that the frequency of the CA signal is extremely high. In addition, in addition to the CA signal, there are Chip Select (CS) signals, Command and Address Parity (PAR) signals, Activation Command (ACT) signals, Bank Address (BA) signals, Bank Group (BG) signals, etc. In the prior art, in order to meet the transmission requirements of multiple signals with high frequency and high quality, advanced manufacturing processes and complex control logic circuits are relied on to accurately control the transmission of data and signals. For example, the Chinese patent with the patent number CN113615088B discloses a cross-clock domain synchronization circuit that samples the write enable signal to obtain multiple sampling results, and selects one sampling result as the read enable signal according to the clock phase difference between the write clock signal and the read clock signal. For another example, the Chinese patent with the patent application publication number CN116541333A discloses a data synchronization method from a slow clock domain to a fast clock domain, which samples the slow clock signal in the first clock period to the Mth clock period of the fast clock signal in turn, and records them as the first sampling signal to the Mth sampling signal. Based on the first sampling signal to the Mth sampling signal, it is judged whether the transition edge of the slow clock signal is triggered in any clock period from the first clock period to the Mth clock period.Therefore, the technical solution of the cross-clock-domain transmission in the prior art needs complex control logic circuit to realize signal sampling and edge judgment, and depends on high-performance devices provided by advanced manufacturing process in the application of high-frequency signals, so it is difficult to meet the requirement of higher and higher transmission rate, and is not conducive to reducing chip complexity and control cost.

[0003] To this end, the present application provides a device and method for high-speed input and output to solve the technical problems in the prior art. SUMMARY

[0004] In a first aspect, the present application provides a device for high-speed input and output. The device comprises: cross-clock-domain sending transmission logic, configured to periodically receive N-tap input data of single-tap N bits according to a write clock signal in a write clock domain, and write the N-tap input data into a first first-in-first-out memory in the cross-clock-domain sending transmission logic bit by bit according to the value of each bit in an N-bit write enable control signal, and read the first first-in-first-out memory as output data according to a read enable control signal; cross-clock-domain sending control logic, configured to write the write enable control signal into a second first-in-first-out memory in the cross-clock-domain sending control logic, and read the second first-in-first-out memory as a gate signal according to a read clock signal in a read clock domain, and gate the read clock signal according to the gate signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and the N is a positive integer greater than 1 and equal to 1.

[0005] Through the first aspect of the present application, the interaction between the read-write pointers across the clock domains is avoided, the loss of clock signal edge judgment and jump edge triggering is avoided, and the loss of frequent measurement and determination of clock phase difference is also avoided, ensuring the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, and ensuring the correctness of parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher rate and reducing the overall power consumption, and being conducive to meeting the requirements of higher and higher transmission rate and cost control.

[0006] In a possible implementation manner of the first aspect of the present application, the input data comprises parallel port data to be transmitted and parallel port enable to be transmitted, and the output data comprises serial port sending data corresponding to the parallel port data to be transmitted and serial port sending enable corresponding to the parallel port enable to be transmitted.

[0007] In a possible implementation manner of the first aspect of the present application, the read enable control signal is used together with the write enable control signal to establish read-write pipeline control of the cross-clock-domain sending transmission logic.

[0008] In a possible implementation of the first aspect of the application, the cross-clock-domain sending control logic is configured to implement conversion of the control signal from the write clock domain to the read clock domain so as to implement timing control of the cycle stage.

[0009] In a possible implementation of the first aspect of the application, the cross-clock-domain sending transmission logic is configured to write the N shots of input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic according to the values of the respective bit positions of the N bits of the write enable control signal, respectively, including: writing the data in the bit position corresponding to the bit position of the write enable control signal whose value is 1 in the N bits of the write enable control signal into the data in the bit position corresponding to the bit position of the write enable control signal whose value is 1 in the N bits of the write enable control signal in each shot of input data in the N shots of input data.

[0010] In a possible implementation of the first aspect of the application, the cross-clock-domain sending transmission logic is configured to write the N shots of input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic according to the values of the respective bit positions of the N bits of the write enable control signal, respectively, including: writing the data in the bit position corresponding to the bit position of the write enable control signal whose value is 0 in the N bits of the write enable control signal into the data in the bit position corresponding to the bit position of the write enable control signal whose value is 0 in the N bits of the write enable control signal in each shot of input data in the N shots of input data.

[0011] In a possible implementation of the first aspect of the application, the cross-clock-domain sending control logic further includes a gating module configured to gate the read clock signal according to the gating signal to obtain the read enable control signal.

[0012] In a possible implementation of the first aspect of the application, the apparatus further includes a digital delay chain configured to adjust a delay of the read enable control signal received by the cross-clock-domain sending transmission logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross-clock-domain sending transmission logic.

[0013] In a possible implementation of the first aspect of the application, the delay control signal is configured to adjust the delay of the output data so that a middle of a data signal associated with the output data is aligned with a sampling clock edge of a data clock signal associated with the data signal.

[0014] In one possible implementation of the first aspect of this application, the device further includes a self-test module and a single-ended output module. The single-ended output module is used to selectively send data outward or send loopback data to the self-test module after receiving the output data. The self-test module is used to provide a data self-test function based on the input data and the loopback data.

[0015] In one possible implementation of the first aspect of this application, the delay control signal is used to adjust the delay of the output data so as to cooperate with the self-test module to realize the data eye diagram scanning function.

[0016] In one possible implementation of the first aspect of this application, the cross-clock domain transmission control logic is further configured to receive a set of control signals, wherein the set of control signals includes a power control signal and a terminating resistor control signal.

[0017] In one possible implementation of the first aspect of this application, the device is applied to a high-speed input / output application scenario, which includes one or more of the following: the transmitter of a serializer / deserializer, a double data rate synchronous dynamic random access memory, a low-power fifth-generation double rate memory, a high-bandwidth memory, a die-to-die interconnect, an automotive-grade chip interconnect, a data center interconnect, and an artificial intelligence platform interconnect.

[0018] Secondly, this application provides a method for high-speed input / output. The method includes: periodically receiving N-times of N-bit input data per cycle according to a write clock signal in the write clock domain via cross-clock domain transmission logic; writing the N-times of input data bit-by-bit to a first first-in-first-out (FIFO) memory in the cross-clock domain transmission logic according to the values ​​of each bit in an N-bit write enable control signal; and reading the first FIFO memory as output data according to a read enable control signal; writing the write enable control signal to a second FIFO memory in the cross-clock domain transmission control logic via cross-clock domain transmission control logic; reading the second FIFO memory as a gate signal according to a read clock signal in the read clock domain; and gating the read clock signal according to the gate signal to obtain the read enable control signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and N is a positive integer greater than or equal to 1.

[0019] By the second aspect of the present application, the interaction between the read-write pointers across the clock domains is avoided, the loss of the clock signal edge judgment and the jump edge trigger is avoided, and the loss of the frequent measurement and determination of the clock phase difference is avoided, so as to ensure the correctness of the data transmission control from the low-speed clock domain to the high-speed clock domain, and also ensure the correctness of the parallel-to-serial logic, effectively reduce the logic depth and chip complexity, help to achieve higher rate, and reduce the overall power consumption, and help to meet the requirements of higher and higher transmission rate and cost control.

[0020] In a possible implementation manner of the second aspect of the present application, the method further includes: adjusting the delay of the output data provided by the cross-clock domain sending transmission logic by adjusting the delay of the read enable control signal received by the cross-clock domain sending transmission logic through a digital delay chain according to a delay control signal.

[0021] In a possible implementation manner of the second aspect of the present application, the delay control signal is used to adjust the delay of the output data, so as to make the intermediate alignment of the data signal associated with the output data to the sampling clock edge of the data clock signal associated with the data signal. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0023] Figure 1 The schematic diagram of the device for high-speed input and output provided by the first embodiment of the present application is shown in the figure.

[0024] Figure 2 The schematic diagram of the device for high-speed input and output provided by the second embodiment of the present application is shown in the figure.

[0025] Figure 3 The schematic diagram of the timing control function of the cross-clock domain sending control logic provided by the embodiment of the present application is shown in the figure.

[0026] Figure 4 The schematic diagram of the delay adjustment function of the digital delay chain provided by the embodiment of the present application is shown in the figure.

[0027] Figure 5 The schematic diagram of the delay adjustment function of the digital delay chain provided by the embodiment of the present application is shown in the figure.

[0028] Figure 6A schematic diagram of data eye scan using data self-check function of self-check module and delay adjustment function of digital delay chain is provided for the embodiments of the present application.

[0029] Figure 7 A flowchart of a method for high-speed input and output is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be further described in details below with reference to the accompanying drawings.

[0031] It should be understood that in the description of the present application, "at least one" means one or more than one, and "multiple" means two or more than two. In addition, the words "first", "second", and the like, unless otherwise specified, are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor indicating or implying order.

[0032] Figure 1 A schematic diagram of the device for high-speed input and output of the first embodiment provided for the embodiments of the present application is shown. As shown in Figure 1 The device A100 for high-speed input and output includes cross-clock domain transmission logic A130 and cross-clock domain transmission control logic A140. The cross-clock domain transmission logic A130 is configured to periodically receive N-tap input data A110 of single-tap N bits according to a write clock signal A114 in a write clock domain, and to write the N-tap input data A110 into a first first-in-first-out memory A132 in the cross-clock domain transmission logic A130 bit by bit according to the value of each bit of an N-bit write enable control signal A120, and to read the first first-in-first-out memory A132 as output data A112 according to a read enable control signal A122. The cross-clock domain transmission control logic A140 is configured to write the write enable control signal A120 into a second first-in-first-out memory A142 in the cross-clock domain transmission control logic A140, and to read the second first-in-first-out memory A142 as a gate signal according to a read clock signal A116 in a read clock domain, and to gate the read clock signal A116 according to the gate signal to obtain the read enable control signal A122. The frequency of the read clock signal A116 is N times the frequency of the write clock signal A114, and N is a positive integer greater than 1 and equal to 1.

[0033] Figure 1The device A100 for high-speed input and output shown can be applied to high-performance memory and high-speed data transmission application scenarios, such as the fourth generation and fifth generation technical specifications of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM), that is, the related technical specifications of DDR4 and DDR5; can be used to meet the data transmission from the physical layer (PHY) of the high-performance memory to the dynamic random access memory (DRAM), including the transmission of various signals such as command address (CA) signals, chip selection (CS) signals, command and address parity (PAR) signals, activation command (ACT) signals, bank address (BA) signals, bank group (BG) signals, and the like. In addition, Figure 1 The device A100 for high-speed input and output shown can be used to ensure the conversion of data from a low-speed clock domain to a high-speed clock domain, ensure the correct control of the input and output (IO) state to realize the sending logic, and can also realize functions such as the delay of the control output data, the detection of the working state of the input and output, and the eye diagram scanning by adding additional functional modules. In addition, Figure 1 The device A100 for high-speed input and output shown can meet the needs of parallel-to-serial conversion in high-speed input and output applications, such as implementing 8-to-1 operation of data on the physical layer side, and greatly simplifying the control complexity of data transmission and the implementation difficulty of parallel-to-serial conversion logic, which is conducive to controlling the demand for advanced manufacturing processes and helps to reduce chip complexity and control costs. Therefore, Figure 1 The device A100 for high-speed input and output shown can be applied to parallel-to-serial conversion high-speed input and output application scenarios, including but not limited to: the sending end of a SERializer / DESerializer (SERDES), Double Data Rate Synchronous Dynamic Random Access Memory, Low Power Double Data Rate 5 (LPDDR5) memory, High Bandwidth Memory (HBM), Die-to-Die (D2D) interconnection, automotive-grade chip interconnection, data center internal interconnection, and artificial intelligence platform internal interconnection.

[0034] Referring to Figure 1The device A100 for high-speed input and output includes cross-clock-domain sending transmission logic A130 and cross-clock-domain sending control logic A140. The cross-clock-domain sending transmission logic A130 includes a built-in first first-in-first-out memory A132, which is a data entry memory for storing written data, such as an enable to be transmitted and data to be transmitted. The first first-in-first-out memory A132 is used to implement cross-clock-domain data transmission logic and can be regarded as a sending first-in-first-out memory (TXFIFO). Here, the write clock signal A114 in the write clock domain can correspond to a local low-speed clock (i_dfi_phy_clk) of a physical layer, and the read clock signal A116 in the read clock domain is a high-speed clock (txclk) for data sending. Therefore, from the write clock domain to the read clock domain, various challenges caused by cross-clock-domain interaction and cross-clock-domain data transmission need to be considered, including frequency difference and phase difference between different clock signals, and the requirement of ensuring high-frequency and high-transmission-rate signal transmission. The cross-clock-domain sending control logic A140 is used to control the cross-clock-domain transmission function of the signal. The cross-clock-domain sending control logic A140 includes a built-in second first-in-first-out memory A142, which is used to implement cross-clock-domain conversion and cycle-level timing control of a high-speed clock, and therefore can be regarded as a clock data control first-in-first-out memory (CDCFIFO). By using the cross-clock-domain sending control logic A140, the converted control signal can be used for fast clock control of the cross-clock-domain sending transmission logic A130, and the clock converted by the cross-clock-domain sending control logic A140 can be provided according to the number of cycles required by the cross-clock-domain sending transmission logic A130, so as to achieve read-write pipeline control together with slow clock control of the cross-clock-domain sending transmission logic A130. Such a design reduces invalid clock signal toggling of the cross-clock-domain sending transmission logic A130 and is beneficial to reducing power consumption. Furthermore, the cross-clock-domain sending control logic A140 is used to assist the cross-clock-domain sending transmission logic A130 to establish read-write pipeline control of the cross-clock-domain sending transmission logic A130, and the interaction between read-write pointers between cross clock domains is not required, the logic depth is reduced, and a higher rate can be achieved on the basis of maintaining the process level.The device A100 for high-speed input and output saves the interaction between the read-write pointers across the clock domains by the cooperation between the cross-clock-domain transmission logic A130 and the cross-clock-domain transmission control logic A140 which are optimized in design. In contrast, the prior art cross-clock-domain transmission solution needs complex control logic circuit to realize signal sampling and edge judgment, for example, sampling the write enable signal to obtain multiple sampling results and then selecting one sampling result as the read enable signal according to the clock phase difference between the write clock signal and the read clock signal, so it is difficult to avoid the interaction between the read-write pointers across the clock domains. This means that, with the same manufacturing process level, i.e. under the same process, the device A100 for high-speed input and output can achieve a higher speed and reduce the overall power consumption by the optimization design.

[0035] With reference to the preceding Figure 1The cross-clock-domain sending transmission logic A130 is configured to periodically receive N-tap input data A110 of N bits according to a write clock signal A114 in the write clock domain, and write the N-tap input data A110 into a first first-in-first-out memory A132 in the cross-clock-domain sending transmission logic A130 according to the value of each bit in the N-bit write enable control signal A120, and read the first first-in-first-out memory A132 as output data A112 according to a read enable control signal A122. In this way, the multiple valid data written in parallel are sent in a serial manner, realizing parallel-to-serial operation, that is, the N-tap input data A110 (each tap is N bits) is written into the first first-in-first-out memory A132 in parallel, and then sent in a serial manner. For example, the physical layer interface protocol of the memory stipulates 8-to-1 operation, and N can be set to 8, that is, parallel-to-serial operation is performed on 8-tap input data A110. In some embodiments, the data to be transmitted (TXDATA) and the enable to be transmitted (TXOE) can be written together. The N-bit write enable control signal A120 is a write enable control signal (WREN) with a specific data length, and the write enable control signal A120 is used to control bit-by-bit writing, that is, each tap of the input data A110 written is written according to the value of each bit in the N-bit write enable control signal A120. For example, assuming that N is equal to 8, which means that the write enable control signal A120 is 8 bits in data length, and the input data A110 is 8-tap data with 8 bits per tap; and assuming that the value of each bit in the write enable control signal A120 is “00011111”, which means that the value of the highest 3 bits in the write enable control signal A120 is 0, and the value of the lowest 5 bits is 1, which can be used to control bit-by-bit writing, so that the data on the lowest 5 bits in each tap of the input data A110 is written into the first first-in-first-out memory A132 in the cross-clock-domain sending transmission logic A130.In some embodiments, if the value of each bit in the write enable control signal A120 is 1, it means that the data on the corresponding bit in each shot of input data A110 is written into the first FIFO A132; for example, if the 8-bit write enable control signal A120 is "00011111", it means that the data on the lowest 5 bits in each shot of input data A110 is written into the first FIFO A132; in other embodiments, depending on the actual needs, it can also be set that if the value of each bit in the write enable control signal A120 is 0, it means that the data on the corresponding bit in each shot of input data A110 is written into the first FIFO A132; for example, if the 8-bit write enable control signal A120 is "00011111", it means that the data on the highest 3 bits in each shot of input data A110 is written into the first FIFO A132. Therefore, according to the value of each bit in the N-bit write enable control signal A120, the N shots of input data A110 are written into the first FIFO A132 in the cross-clock-domain sending transmission logic A130 bit by bit, which can use the bit with a value of 1 in the write enable control signal A120 as an indication of effective writing, or can use the bit with a value of 0 in the write enable control signal A120 as an indication of effective writing, thus providing more flexibility in the control level.

[0036] With reference to the foregoing Figure 1, the pipeline control of the write of the cross-clock-domain sending transmission logic A130 is based on the N-bit write enable control signal A120, for example, each write cycle is to write N-bit parallel port data of each N-tap according to the value of each bit of the write enable control signal A120; the write clock signal A114 in the write clock domain is used to coordinate when to receive the input data A110 for writing. In addition, the pipeline control of the read of the cross-clock-domain sending transmission logic A130 is based on the read enable control signal A122, that is, the first first-in-first-out memory A132 is read as the output data A112 according to the read enable control signal A122. The cross-clock-domain sending control logic A140 is used to generate the read enable control signal A122 to build the pipeline control of the read of the cross-clock-domain sending transmission logic A130. The cross-clock-domain sending control logic A140 is used to write the write enable control signal A120 to the second first-in-first-out memory A142 in the cross-clock-domain sending control logic A140, and read the second first-in-first-out memory A142 as a gating signal according to the read clock signal A116 in the read clock domain, and gate the read clock signal A116 to obtain the read enable control signal A122 according to the gating signal. Therefore, in order to ensure the correctness of the write-read timing, the read clock signal A116 is used to coordinate when to read the gating signal on the one hand, and the gating signal is used to gate the read clock signal A116 to obtain the read enable control signal A122 on the other hand. The read enable control signal A122 is used to control the read timing of the sending transmission logic, so as to ensure the correctness of the write-read timing. In this way, the write clock signal A114 in the write clock domain is used to coordinate the cross-clock-domain sending transmission logic A130 to determine when to receive the input data A110 for writing, that is, the cross-clock-domain sending transmission logic A130 periodically receives N-tap input data A110 of N-bit per tap according to the write clock signal A114 in the write clock domain; the read clock signal A116 in the read clock domain is used to generate the read enable control signal A122, that is: the cross-clock-domain sending control logic A140 reads the second first-in-first-out memory A142 as a gating signal according to the read clock signal A116 in the read clock domain, and gates the read clock signal A116 to obtain the read enable control signal A122 according to the gating signal. It can be seen that the interaction between the read-write pointers across the clock domains is avoided, the edge judgment of the write clock signal A114 is not needed, and the clock phase difference between the write clock signal A114 and the read clock signal A116 does not need to be frequently determined, so that the logic depth and circuit complexity are effectively reduced.To ensure the data conversion from the low-speed clock domain to the high-speed clock domain, and to ensure the correctness of the parallel-to-serial logic, in the cross-clock-domain sending transmission logic A130, an N-bit write enable control signal A120 is used to control the bit-by-bit write operation so as to write the N-tap input data A110 of the single-tap N-bit, where the write clock signal A114 in the write clock domain is used to coordinate the cross-clock-domain sending transmission logic A130 to periodically receive the input data A110; in the cross-clock-domain sending control logic A140, the write enable control signal A120 is written to the second first-in-first-out memory A142, where the read clock signal A116 in the read clock domain is used to coordinate the cross-clock-domain sending control logic A140 to read the second first-in-first-out memory A142 to obtain the gate signal, and the read clock signal A116 is gated according to the gate signal to obtain the read enable control signal A122. In this way, the interaction between the cross-clock-domain read and write pointers is not needed, in the write clock domain, only the data to be transmitted and the enable to be transmitted are written according to the enable of the write enable control signal A120, and in the read clock domain, only the first first-in-first-out memory A132 is read as the output data A112, such as the data sequence for sending (tx data serial) and the enable sequence for sending (tx oe serial), according to the read enable control signal A122. It should be understood that the data length of the write enable control signal A120 is N bits, where N is a parameter consistent with the parameter N in the input data A110 of the single-tap N-bit N-tap, and also consistent with the frequency of the read clock signal A116 being N times the frequency of the write clock signal A114. Therefore, N can be understood as the high-low clock frequency ratio, or the ratio of the frequency of the fast clock relative to the frequency of the slow clock. For example, N can be set to 8, that is, the data length of the write enable control signal A120 is 8 bits, which means that the input data A110 is 8-tap data of single-tap 8-bit 8-tap, and the high-low clock frequency ratio is 8 to 1. For another example, N can be set to 6, that is, the data length of the write enable control signal A120 is 6 bits, which means that the input data A110 is 6-tap data of single-tap 6-bit 6-tap, and the high-low clock frequency ratio is 6 to 1. Therefore, the parameter N as the high-low clock frequency ratio, or the ratio of the frequency of the read clock signal A116 relative to the frequency of the write clock signal A114, determines how to divide the input data A110, that is, to divide the N-tap data with N bits as the single-tap data length, and each tap is written bit by bit according to the binary value of the bit in the write enable control signal A120.

[0037] Continuing to refer to Figure 1In order to overcome the problem of data transmission across clock domains and to cope with the frequency difference and phase difference between the clock signals of the two different clock domains, in the cross-clock-domain transmission logic A130, the local low-speed clock, i.e. the write clock signal A114 in the write clock domain, is used to control the periodic reception of data that needs to be written, and the high-speed clock, i.e. the read clock signal A116 in the read clock domain, is used to control the reading of data for output. In order to ensure that the written data can be correctly read, it must be ensured that the data is written stably before being read, and in order to avoid interaction between the write and read pointers in order to reduce the logic complexity, Figure 1The device A100 for high-speed input and output shown, by using the optimization design of the cross-clock-domain transmission control logic A140 and the design constraint around the parameter N, realizes the correct reading and writing of data by controlling the timing of the high-speed clock to the cross-clock-domain transmission logic A130. That is, by using the generation mechanism of the read enable control signal A122 of the cross-clock-domain transmission control logic A140, the write enable control signal A120 is converted to the high-speed clock domain, and the read clock signal A116 is gated by the gate signal converted to the high-speed clock domain by the cross-clock-domain transmission control logic A140 to obtain the read enable control signal A122, so that the read enable control signal A122 can be used to cope with the alignment requirement of the cross-clock domain by controlling the timing of the enable signal in the high-speed clock domain to the cross-clock-domain transmission logic A130. From another perspective, the generation mechanism of the read enable control signal A122 of the cross-clock-domain transmission control logic A140 reads the second first-in-first-out memory A142 as a gate signal according to the read clock signal A116 in the read clock domain, and gates the read clock signal A116 according to the gate signal to obtain the read enable control signal A122. In this way, the write enable control signal A120 that has been written and read from the second first-in-first-out memory A142 is used as the read enable control signal A122 as the read enable control signal A122 is used as the gate signal to gate the read clock signal A116, that is, to sample the high-speed original clock signal in the high-speed clock domain, that is, the read clock signal A116 (the frequency of the read clock signal A116 is N times the frequency of the write clock signal A114), to obtain the gated clock signal, which is the read enable control signal A122, which is the control signal provided by the cross-clock-domain transmission control logic A140 for the pipeline control of data reading. In addition, the above design constraint around the parameter N also includes the implementation of parallel-to-serial logic. Taking the parameter N as 8, for example, in order to convert the write enable control signal A120 to the high-speed clock domain, for example, from a low-speed clock domain of 1 gigahertz (GHz) to a high-speed clock domain of 8 GHz, the related parallel-to-serial operation includes converting 8-bit parallel data of 8 taps to serial data, that is, converting 8-tap parallel data to 1-tap serial data. In contrast, if the high-speed to low-speed frequency ratio is 6 to 1, the related parallel-to-serial operation includes converting 6-tap parallel data to 1-tap serial data. In addition, the cross-clock-domain transmission control logic A140 can receive a series of control signals in addition to the write enable control signal A120, including power control signals and terminal resistance control signals, etc., for providing flexibility at the control level, as long as the cross-clock-domain transmission control logic A140 receives the write enable control signal A120 and performs cross-clock-domain conversion to provide the read enable control signal A122 for constructing the period-level timing control of data reading of the cross-clock-domain transmission logic A130.

[0038] In summary, Figure 1 The device A100 for high-speed input and output shown introduces the parameter N as a global parameter, and on the basis of the high-speed / low-speed clock frequency ratio (the frequency of the read clock signal A116 is N times the frequency of the write clock signal A114), the data format of the input data A110, the data format of the write enable control signal A120, and the specific way of writing the input data A110 into the first first-in-first-out memory A132 in the cross-clock-domain sending transmission logic A130 are made design constraints, and specifically, the design constraints are made: N-tap input data A110 of single-tap N bits, N-bit write enable control signal A120, and bit-by-bit writing of the N-tap input data A110 according to the value of each bit in the N-bit write enable control signal A120; on the basis of the design constraints made, the write clock signal A114 in the write clock domain is used to coordinate when to receive the input data A110 for writing, thereby constructing the pipeline control of writing of the cross-clock-domain sending transmission logic A130, and realizing the cycle-level timing control of writing; on the basis of the design constraints made, the read clock signal A116 in the read clock domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain the read enable control signal A122, thereby constructing the pipeline control of reading of the cross-clock-domain sending transmission logic A130, and realizing the cycle-level timing control of reading; in combination with the design constraints made on the data format of the input data A110, the data format of the write enable control signal A120, and the specific way of writing the input data A110 into the first first-in-first-out memory A132 in the cross-clock-domain sending transmission logic A130, the generation mechanism of the read enable control signal A122 of the cross-clock-domain sending control logic A140 is used to avoid the interaction between the read-write pointers across the clock domains, avoid the loss of clock signal edge judgment and jump edge triggering, and also avoid the loss of frequent measurement and determination of the clock phase difference, thereby ensuring the correctness of the data transmission control from the low-speed clock domain to the high-speed clock domain, and also ensuring the correctness of the parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher rates and reducing overall power consumption, and being conducive to meeting the requirements of higher and higher transmission rates and cost control requirements.

[0039] Figure 2 The schematic diagram of the device for high-speed input and output of the second embodiment provided by the embodiments of the present application. As Figure 2As shown, the device B200 for high-speed input and output includes cross-clock-domain sending transmission logic B230 and cross-clock-domain sending control logic B240. The cross-clock-domain sending transmission logic B230 is configured to periodically receive N-tap input data B210 of single-tap N bits according to a write clock signal B214 in a write clock domain, and write the N-tap input data B210 into a first first-in-first-out memory B232 in the cross-clock-domain sending transmission logic B230 bit by bit according to the value of each bit in an N-bit write enable control signal B220, and read the first first-in-first-out memory B232 as output data B212 according to a read enable control signal B222. The cross-clock-domain sending control logic B240 is configured to write the write enable control signal B220 into a second first-in-first-out memory B242 in the cross-clock-domain sending control logic B240, and read the second first-in-first-out memory B242 as a gate signal B246 according to a read clock signal B216 in a read clock domain, and gate the read clock signal B216 according to the gate signal B246 to obtain the read enable control signal B222. The frequency of the read clock signal B216 is N times the frequency of the write clock signal B214, and N is a positive integer greater than 1 and equal to 1. The cross-clock-domain sending control logic B240 further includes a gate module B244. The gate module B244 is configured to gate the read clock signal B216 according to the gate signal B246 to obtain the read enable control signal B222. It should be understood that, Figure 2 The cross-clock-domain sending control logic B240 shown is implemented by the gate module B244 to support the generation mechanism of the read enable control signal B222. As long as the generation mechanism of the read enable control signal B222 can be met, Figure 2 The cross-clock-domain sending control logic B240 shown can also be implemented by other hardware, circuits, firmware, software, etc. with gate operation characteristics.

[0040] Referring to Figure 2The device B200 for high speed input / output utilizes the cross-clock-domain transmission logic B230 and the cross-clock-domain transmission control logic B240 to ensure the data conversion from the low speed clock domain to the high speed clock domain and to guarantee the correct control of the input / output state to implement the transmission logic. The device B200 for high speed input / output can also implement the functions of delaying the control output data, detecting the working state of the input / output, and eye diagram scanning through additional functional modules. For the function of delaying the control output data, the device B200 for high speed input / output further comprises a digital delay chain B250. The digital delay chain B250 is configured to adjust the delay of the read enable control signal B222 received by the cross-clock-domain transmission logic B230 according to a delay control signal, so as to adjust the delay of the output data B212 provided by the cross-clock-domain transmission logic B230. In some embodiments, the delay control signal is configured to adjust the delay of the output data B212, so as to make the middle of the data signal associated with the output data B212 align with the sampling clock edge of the data clock signal associated with the data signal. For the function of detecting the working state of the input / output, the device B200 for high speed input / output further comprises a self-checking module B260 and a single-ended output module B262. The single-ended output module B262 is configured to selectively transmit data outwards or transmit loopback data B270 to the self-checking module B260 after receiving the output data B212. The self-checking module B260 is configured to provide a data self-checking function according to the input data B210 and the loopback data B270. For the function of eye diagram scanning, in some embodiments, the delay control signal is configured to adjust the delay of the output data B212, so as to cooperate with the self-checking module B260 to implement the data eye diagram scanning function. It should be understood that, in some embodiments, the digital delay chain B250 is deployed outside the cross-clock-domain transmission control logic B240 and the cross-clock-domain transmission logic B230. In some embodiments, the digital delay chain B250 can also be part of the cross-clock-domain transmission control logic B240, or the digital delay chain B250 can also be part of the cross-clock-domain transmission logic B230. Figure 2 In some embodiments, the digital delay chain B250 is deployed outside the cross-clock-domain transmission control logic B240 and the cross-clock-domain transmission logic B230. In some embodiments, the digital delay chain B250 can also be part of the cross-clock-domain transmission control logic B240, or the digital delay chain B250 can also be part of the cross-clock-domain transmission logic B230.

[0041] In summary, Figure 2The device B200 for high-speed input and output shown introduces parameter N as a global parameter, and makes design aspect constraints on the data format of input data B210, the data format of write enable control signal B220, and the specific way of writing input data B210 into the first first-in-first-out memory B232 in cross-clock-domain sending transmission logic B230 on the basis of the high-speed / low-speed clock frequency ratio (the frequency of the read clock signal B216 is N times the frequency of the write clock signal B214), and specifically formulates these design aspect constraints: N-tap input data B210 of single-tap N bits, N-bit write enable control signal B220, and bit-by-bit writing of the N-tap input data B210 according to the value of each bit in the N-bit write enable control signal B220; on the basis of the formulated design aspect constraints, the write clock signal B214 in the write clock domain is used to coordinate when to receive input data B210 for writing, thereby constructing the pipeline control of writing of cross-clock-domain sending transmission logic B230, and realizing the cycle-level timing control of writing; on the basis of the formulated design aspect constraints, the read clock signal B216 in the read clock domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain read enable control signal B222, thereby constructing the pipeline control of reading of cross-clock-domain sending transmission logic B230, and realizing the cycle-level timing control of reading; in combination with the design aspect constraints made on the data format of input data B210, the data format of write enable control signal B220, and the specific way of writing input data B210 into the first first-in-first-out memory B232 in cross-clock-domain sending transmission logic B230, the generation mechanism of read enable control signal B222 of cross-clock-domain sending control logic B240 is used to avoid the interaction between read-write pointers across clock domains, avoid the loss of clock signal edge judgment and jump edge triggering, also avoid the loss of frequent measurement and determination of clock phase difference, ensure the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, also ensure the correctness of parallel-to-serial logic, effectively reduce the logic depth and chip complexity, help to achieve higher rates and reduce overall power consumption, and be conducive to meeting the requirements of higher and higher transmission rates and cost control requirements. In addition, Figure 2The device B200 for high-speed input and output shown, by deploying functional modules to realize additional control characteristics. Specifically, by adjusting the read enable control signal B222 received by the cross-clock-domain transmission logic B230 through the digital delay chain B250 to adjust the delay of the output data B212 provided by the cross-clock-domain transmission logic B230, so as to realize the delay adjustment logic, which can indirectly adjust the data delay through the clock delay, and then realize the data and clock alignment on the DRAM side. In addition, by the self-test module B260 and the single-ended output module B262 to provide loopback function to support the path test of serial link, etc.

[0042] Referring to Figure 1 and Figure 2 In a possible implementation, the input data includes parallel port data to be transmitted and parallel port enable to be transmitted, and the output data includes serial port transmission data corresponding to the parallel port data to be transmitted and serial port transmission enable corresponding to the parallel port enable to be transmitted. In this way, the parallel-to-serial operation is realized, and the interaction between the read and write pointers across the clock domains is avoided, the loss of clock signal edge judgment and jump edge triggering is avoided, and the loss of frequent measurement and determination of clock phase difference is also avoided, ensuring the correctness of the data transmission control from the low-speed clock domain to the high-speed clock domain, effectively reducing the logic depth and chip complexity, helping to achieve higher rates and lower overall power consumption, and being conducive to meeting the requirements of higher and higher transmission rates and cost control requirements.

[0043] In a possible implementation, the read enable control signal is used together with the write enable control signal to establish read-write pipeline control of the cross-clock-domain sending transmission logic. In this way, parameter N is introduced as a global parameter, and on the basis of a high-to-low clock frequency ratio (the frequency of the read clock signal is N times the frequency of the write clock signal), design constraints are made on the data format of the input data, the data format of the write enable control signal, and the specific way of writing the input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic A130. On the basis of the established design constraints, the write clock signal in the write clock domain is used to coordinate when to receive the input data for writing, thereby constructing the pipeline control of the writing of the cross-clock-domain sending transmission logic, and realizing the cycle-level timing control of the writing. On the basis of the established design constraints, the read clock signal in the read clock domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain the read enable control signal, thereby constructing the pipeline control of the reading of the cross-clock-domain sending transmission logic, and realizing the cycle-level timing control of the reading. The interaction between the read-write pointers across the clock domains is avoided, and there is no need to make edge judgment on the write clock signal, nor to frequently determine the clock phase difference between the write clock signal and the read clock signal, which effectively reduces the logic depth and circuit complexity.

[0044] In a possible implementation, the cross-clock-domain sending control logic is used to realize conversion of the control signal from the write clock domain to the read clock domain to realize cycle-level timing control. In this way, in order to ensure that the written data can be correctly read, it must be ensured that the data is read after it is stably written, and in order to avoid interaction between the write-read pointers to reduce the logic complexity, the correct reading and writing of data is realized by controlling the timing of the high-speed clock reaching the cross-clock-domain sending transmission logic through the optimization design of the cross-clock-domain sending control logic and the design constraints around parameter N. The generation mechanism of the read enable control signal of the cross-clock-domain sending control logic is used to convert the write enable control signal to the high-speed clock domain, and the read enable control signal is obtained by gating the read clock signal through the gating signal converted to the high-speed clock domain by the cross-clock-domain sending control logic. In this way, the read enable control signal can be used to control the time when the enable signal in the high-speed clock domain reaches the cross-clock-domain sending transmission logic to meet the alignment requirement of the cross-clock domain.

[0045] In a possible implementation, the cross-clock-domain sending transmission logic is configured to write the N shots of input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic according to the values of the N bits of the write enable control signal, respectively, including: writing the data in each shot of the N shots of input data corresponding to the position of the bit with a value of 1 in the N bits of the write enable control signal according to the position of the bit with a value of 1 in the N bits of the write enable control signal. In this way, N is used as a global parameter, the data length of the write enable control signal is N bits, which is consistent with the parameter N in the single-shot N-bit N-shot input data, and is also consistent with the fact that the frequency of the read clock signal is N times the frequency of the write clock signal. Based on the parameter N, the specific way of writing input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic is constrained in terms of design, parallel-to-serial conversion logic is implemented, and the interaction between the read and write pointers across the clock domains is avoided, so that edge judgment of the write clock signal is not needed, and the clock phase difference between the write clock signal and the read clock signal does not need to be determined frequently, which effectively reduces the logic depth and circuit complexity.

[0046] In a possible implementation, the cross-clock-domain sending transmission logic is configured to write the N shots of input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic according to the values of the N bits of the write enable control signal, respectively, including: writing the data in each shot of the N shots of input data corresponding to the position of the bit with a value of 1 in the N bits of the write enable control signal according to the position of the bit with a value of 1 in the N bits of the write enable control signal. In this way, N is used as a global parameter, the data length of the write enable control signal is N bits, which is consistent with the parameter N in the single-shot N-bit N-shot input data, and is also consistent with the fact that the frequency of the read clock signal is N times the frequency of the write clock signal. Based on the parameter N, the specific way of writing input data into the first first-in-first-out memory in the cross-clock-domain sending transmission logic is constrained in terms of design, parallel-to-serial conversion logic is implemented, and the interaction between the read and write pointers across the clock domains is avoided, so that edge judgment of the write clock signal is not needed, and the clock phase difference between the write clock signal and the read clock signal does not need to be determined frequently, which effectively reduces the logic depth and circuit complexity.

[0047] In a possible implementation, the cross-clock-domain sending control logic further includes a gating module configured to gate the read clock signal according to the gating signal to obtain the read enable control signal. In this way, the gating operation is implemented by the gating module, and by virtue of the optimized design of the cross-clock-domain sending control logic and the design constraint around the parameter N, the correct reading and writing of data is achieved by controlling the time when the high-speed clock reaches the cross-clock-domain sending transmission logic. That is, by virtue of the generation mechanism of the read enable control signal of the cross-clock-domain sending control logic, the write enable control signal is converted to the high-speed clock domain, and the read clock signal is gated by the gating signal converted to the high-speed clock domain by the cross-clock-domain sending control logic to obtain the read enable control signal, so that the read enable control signal can be used to control the time when the enable signal in the high-speed clock domain reaches the cross-clock-domain sending transmission logic to meet the alignment requirement of the cross-clock domain.

[0048] In one possible implementation, the apparatus further includes a digital delay chain configured to adjust a delay of the read enable control signal received by the cross clock domain send logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross clock domain send logic. In this way, an additional delay adjustment function is provided by the digital delay chain, which is configured to adjust the delay of the read enable control signal received by the cross clock domain send logic according to the delay control signal, which helps to adjust the sending delay logic to ensure correct transmission of data. With the delay adjustment function provided by the digital delay chain, the problem of delay difference between different traces on a circuit board can be effectively addressed. Specifically, there are multiple traces on a circuit board, and each input / output port corresponds to a separate trace. The delays of different traces can be different, which makes it difficult to sample the correct data when the data signals transmitted through multiple traces are sampled by the same clock signal at the receiving end, such as the DRAM side. To this end, the delay adjustment function and delay adjustment logic provided by the digital delay chain are used to indirectly adjust the data delay by adjusting the delay of the clock, so as to achieve the function of aligning the data and the clock at the DRAM side. With the digital delay chain, the correct sampling of data at the DRAM side is achieved by adjusting the delay of the data of the cross clock domain send logic. The data transmitted by the delay clock of the digital delay chain after the high-speed clock of the gate operation of the cross clock domain send control logic can ensure that the correct data is sampled at the DRAM side. If the correct data cannot be sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In some embodiments, the delay control signal is configured to adjust the delay of the output data, so as to align the middle of the data signal associated with the output data with the sampling clock edge of the data clock signal associated with the data signal. In this way, the alignment of data and clock is achieved, which helps to ensure that the written data can be correctly sampled and read for output. The middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal by the delay adjustment function, which improves the accuracy of the reading side and helps to meet the cross clock domain writing and reading requirements.

[0049] In some embodiments, the apparatus further comprises a self-checking module and a single-ended output module, the single-ended output module is configured to selectively send data out or send loopback data to the self-checking module after receiving the output data, and the self-checking module is configured to provide a data self-checking function according to the input data and the loopback data. In this way, the data self-checking function is provided by the self-checking module and the single-ended output module. Thus, the apparatus is used for high-speed input and output design, and can be used to test the availability of the input and output functions of a chip during testing by an automated test equipment. Specifically, the data sent by the cross-clock-domain transmission logic is provided to the self-checking module as loopback data after passing through the single-ended output module, i.e., back to the receiving direction, and then the adaptive checking of the sampled data is implemented by the self-checking module, such as a pseudo-random binary sequence (PRBS) checking module. Then, in combination with the delay adjustment function provided by the digital delay chain, the connectivity test of the data path can be implemented, and the scanning function of the eye diagram can be implemented. Generally, because the clock delay of the PRBS checking module is fixed, the data can be sampled from the right edge to the left edge after passing through the delay, which improves the checking efficiency. In this way, the data sent by the cross-clock-domain transmission logic is looped back to the self-checking module in the receiving direction (RX), such as a PRBS checking module, to implement the control of the clock of the cross-clock-domain transmission logic by the cross-clock-domain transmission control logic, so as to control the reading of the data, which ensures the correctness of the data looped back to the receiving direction, and the correctness of the data in the receiving direction can be checked. Moreover, the delay of the high-speed clock is adjusted by the digital delay chain, so as to implement the delay of the data, which can scan the entire data area, so as to achieve the purpose of scanning the data eye diagram.

[0050] In some examples, the delay control signal is used to adjust the delay of the output data, so as to cooperate with the self-checking module to implement the data eye diagram scanning function. In this way, the clock of the self-checking module does not pass through the delay adjustment from the output to the input, while the clock of the cross-clock-domain transmission logic passes through the delay adjustment of the digital delay chain, so that the eye diagram scanning can be performed. The eye diagram result indicates the quality of the input and output. Moreover, the control code of the digital delay chain, i.e., the delay control signal, can come from the outside in some embodiments, and is generated by external logic. With the data eye diagram scanning function, the input and output quality can be conveniently judged, and more flexibility of the control level is provided.

[0051] In a possible implementation, the cross-clock-domain transmission control logic is further configured to receive a set of control signals, wherein the set of control signals comprises a power control signal and a termination resistance control signal. In this way, a series of control signals, including a power control signal and a termination resistance control signal, are received by the cross-clock-domain transmission control logic, to provide flexibility in the control level, as long as the cross-clock-domain transmission control logic receives a write enable control signal and performs cross-clock-domain conversion to provide a read enable control signal for constructing the cycle-level timing control of data reading of the cross-clock-domain transmission logic.

[0052] In a possible implementation, the device is applied to a high-speed input / output application scenario with incorporated serialization, which includes one or more of the following: a transmission end of a serializer-deserializer, a double data rate synchronous dynamic random access memory, a low-power fifth-generation double-rate memory, a high-bandwidth memory, a die-to-die interconnection, a chip-to-chip interconnection for automotive-grade, an internal interconnection of a data center, and an internal interconnection of an artificial intelligence platform. In this way, the device can be applied to a high-speed input / output application scenario with incorporated serialization, to meet the needs of serialization in the high-speed input / output application, for example, to implement 8-to-1 operation of data on the physical layer side, and greatly simplify the control complexity of data transmission and the implementation difficulty of serialization logic, which is conducive to reducing the demand for advanced manufacturing processes and chip complexity and cost.

[0053] Figure 3 A timing control function diagram of the cross-clock-domain transmission control logic provided by the embodiments of the present application is shown. Figure 3 The original clock signal 310, the enable signal 320, and the gated clock signal 330 are shown in the figure. Figure 3 The timing control function of the cross-clock-domain transmission control logic shown in the figure corresponds to Figure 1 and Figure 2The read enable control signal of the cross-clock-domain sending control logic is generated in this way. Thus, the write enable control signal that has been written in the second FIFO is read from the second FIFO as the read enable control signal 320, which is used as a gating signal to gate the read clock signal, that is, to sample the original clock signal 310 in the high-speed clock domain, that is, the read clock signal (the frequency of the read clock signal is N times the frequency of the write clock signal), to obtain the gated clock signal 330, which is the read enable control signal and is the control signal provided by the cross-clock-domain sending control logic for the pipeline control of data reading. In this way, the read clock signal in the read clock domain is used to coordinate when the gating signal is read, and the gating signal is used to gate the read clock signal to obtain the read enable control signal, so as to construct the pipeline control of reading of the cross-clock-domain sending transmission logic, realize the cycle-level timing control of reading, and also realize the overcoming of the cross-clock-domain data transmission problem and the problem of coping with the frequency difference and phase difference between the clock signals of the two different clock domains. Further, in combination with the design constraints made on the data format of the input data, the data format of the write enable control signal, and the specific way of writing the input data into the first FIFO in the cross-clock-domain sending transmission logic, the generation mechanism of the read enable control signal of the cross-clock-domain sending control logic is used to avoid the interaction between the read and write pointers across the clock domains, avoid the loss of clock signal edge judgment and jump edge triggering, and also avoid the loss of frequent measurement and determination of the clock phase difference, so as to ensure the correctness of the data transmission control from the low-speed clock domain to the high-speed clock domain, also ensure the correctness of the parallel-to-serial logic, effectively reduce the logic depth and chip complexity, help to achieve a higher rate, and reduce the overall power consumption, which is conducive to meeting the requirements of higher and higher transmission rates and cost control requirements.

[0054] Figure 4 The schematic diagram of the delay adjustment function of the digital delay chain provided by the embodiment of the present application is shown. Figure 4 The clock A 401 before delay adjustment, the data A 403 before delay adjustment, the clock B 411 after delay adjustment, and the data B 413 after delay adjustment are shown in the figure. Figure 1 and Figure 2The device for high-speed input and output shown can include a digital delay chain for adjusting the delay of the read enable control signal received by the cross-clock-domain transmission logic according to a delay control signal, so as to adjust the delay of the output data provided by the cross-clock-domain transmission logic. In some embodiments, the delay control signal is used to adjust the delay of the output data, so as to make the middle of the data signal associated with the output data align with the sampling clock edge of the data clock signal associated with the data signal. In this way, an additional delay adjustment function is provided by the digital delay chain, which can adjust the delay of the read enable control signal received by the cross-clock-domain transmission logic according to the delay control signal, which helps to adjust the transmission delay of the logic to ensure the correct transmission of data. With the delay adjustment function provided by the digital delay chain, the problem of delay difference between different lines on the circuit board can be effectively addressed. Specifically, there are multiple lines on the circuit board, and each input and output port corresponds to a separate line. The delay of different lines can be different, which makes it difficult to sample the correct data when the data signals transmitted through multiple lines are sampled by the same clock signal on the receiving side, such as the DRAM side. Therefore, by using the delay adjustment function and delay adjustment logic provided by the digital delay chain, the delay of the data can be indirectly adjusted by adjusting the delay of the clock, and the function of aligning the data with the clock on the DRAM side can be realized. Figure 4 As shown in the middle, by using the delay adjustment function and delay adjustment logic of the digital delay chain, the alignment of data and clock is realized, which is helpful to overcome the problem of line delay difference.

[0055] Figure 5 A schematic diagram is shown for adjusting the delay of each of the multiple lines by using the delay adjustment function of the digital delay chain provided by the embodiments of the present application. As shown in the left part of the figure, Figure 5As shown, before adjustment, the case is the pre-adjustment reference clock A501, the data A503 of the pre-adjustment wire A, the data A505 of the pre-adjustment wire B, and the data A507 of the pre-adjustment wire C. It can be seen that there are multiple wires on the circuit board, and each input and output port corresponds to a separate wire. The delay between different wires can be different, which makes it difficult to sample the correct data when the same clock signal is used to sample the data signal transmitted through multiple wires on the receiving side such as the DRAM side. Therefore, by using the delay adjustment function and delay adjustment logic provided by the digital delay chain, the data delay can be indirectly adjusted by adjusting the clock delay, and the function of aligning the data on the DRAM side with the clock can be realized. By using the digital delay chain, the correct sampling of the data on the DRAM side is realized by adjusting the delay of the data transmitted by the cross-clock-domain transmission logic. After the high-speed clock controlled by the cross-clock-domain transmission control logic, the data transmitted by the delay clock of the digital delay chain can ensure that the correct data is sampled on the DRAM side. If the correct data cannot be sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the middle of the output data associated data signal aligns with the sampling clock edge of the data clock signal associated with the data signal. After adjustment, the case is the post-adjustment reference clock B511, the data B513 of the post-adjustment wire A, the data B515 of the post-adjustment wire B, and the data B517 of the post-adjustment wire C. In this way, the alignment of data and clock is realized, which helps to ensure that the written data can be correctly sampled and read for output. By using the delay adjustment function, the middle of the output data associated data signal aligns with the sampling clock edge of the data clock signal associated with the data signal, which improves the accuracy on the reading side and helps to meet the cross-clock-domain writing and reading requirements.

[0056] Figure 6 The schematic diagram for performing data eye scan by using the data self-check function of the self-check module and the delay adjustment function of the digital delay chain provided by the embodiments of the present application. Figure 6The clock 601 of the self-checking module, the delay data A 603, the delay data B 605, and the delay data C 607 are shown. Here, the device for high-speed input and output further includes a self-checking module and a single-ended output module, the single-ended output module is used to selectively send data out or send loopback data to the self-checking module after receiving the output data, and the self-checking module is used to provide a data self-checking function according to the input data and the loopback data. The delay control signal is used to adjust the delay of the output data, so as to cooperate with the self-checking module to realize a data eye scan function. In this way, the data self-checking function is provided by the self-checking module and the single-ended output module. In this way, the device is used for high-speed input and output design, and can be used to test the availability of the input and output function of the chip when tested by an automated test equipment. Specifically, the data transmitted by the cross-clock-domain transmission logic is provided with loopback data to the self-checking module, i.e., back to the receiving direction, after passing through the single-ended output module, and then the adaptive inspection of the sampled data is realized by the self-checking module, such as a pseudo-random binary sequence (PRBS) inspection module. Then, in combination with the delay adjustment function provided by the digital delay chain, the connectivity test of the data path can be realized, and the eye scan function can be realized. Generally, because the clock delay of the PRBS inspection module is fixed, the data can be sampled from the right edge to the left edge after passing through the delay, which improves the inspection efficiency. In this way, the data transmitted by the cross-clock-domain transmission logic is looped back to the self-checking module, such as the PRBS inspection module, in the receiving direction (RX), which realizes the control of the clock of the cross-clock-domain transmission logic by the cross-clock-domain transmission control logic, so as to control the reading of the data, which ensures the correctness of the data looped back to the receiving direction, and the correctness of the data can be checked in the receiving direction. Moreover, the delay of the high-speed clock is adjusted by the digital delay chain, so as to realize the delay of the data, which can scan the entire data area, so as to realize the purpose of scanning the data eye. By the self-checking module, such as the PRBS inspection module, from the output to the input, the clock of the self-checking module does not pass through the delay adjustment, while the clock of the cross-clock-domain transmission logic passes through the delay adjustment of the digital delay chain, so that the eye scan can be performed. The eye result indicates the quality of the input and output. Moreover, the control code of the digital delay chain, i.e., the delay control signal, can come from the outside in some embodiments, and is generated by external logic. With the data eye scan function, the input and output quality can be conveniently judged, and more flexibility of the control level is provided.

[0057] Figure 7 A flowchart of a method for high-speed input and output is provided for the embodiments of the present application. As shown in Figure 7 the method includes the following steps.

[0058] Step S701: by the cross-clock-domain sending transmission logic, periodically receiving N-tap input data of single-tap N-bit according to the write clock signal in the write clock domain, and respectively writing the N-tap input data bit by bit to a first first-in-first-out memory in the cross-clock-domain sending transmission logic according to the value of each bit of the N-bit write enable control signal, and reading the first first-in-first-out memory as output data according to the read enable control signal.

[0059] Step S703: by the cross-clock-domain sending control logic, writing the write enable control signal to a second first-in-first-out memory in the cross-clock-domain sending control logic, and reading the second first-in-first-out memory as a gate signal according to the read clock signal in the read clock domain, and gating the read clock signal to obtain the read enable control signal according to the gate signal, wherein the frequency of the read clock signal is N times the frequency of the write clock signal, and the N is a positive integer greater than 1 and equal to 1.

[0060] Figure 7The method for high-speed input and output shown introduces parameter N as a global parameter, and makes design aspect constraints on the data format of input data, the data format of write enable control signals, and the specific way of writing input data into the first first-in-first-out memory in cross-clock-domain sending transmission logic on the basis of the high-speed / low-speed clock frequency ratio (the frequency of the read clock signal is N times the frequency of the write clock signal). Specifically, the design aspect constraints are made: N-bit input data of N single-tick, N-bit write enable control signals, and writing the N single-tick of input data bit by bit according to the value of each bit in the N-bit write enable control signals; on the basis of the design aspect constraints made, the write clock signal in the write clock domain is used to coordinate when to receive input data for writing, thereby constructing the pipeline control of writing in cross-clock-domain sending transmission logic, and realizing the cycle-level timing control of writing; on the basis of the design aspect constraints made, the read clock signal in the read clock domain is used to coordinate when to read the gating signal, and then the gating signal is used to gate the read clock signal to obtain the read enable control signal, thereby constructing the pipeline control of reading in cross-clock-domain sending transmission logic, and realizing the cycle-level timing control of reading; in combination with the design aspect constraints made on the data format of input data, the data format of write enable control signals, and the specific way of writing input data into the first first-in-first-out memory in cross-clock-domain sending transmission logic, the generation mechanism of the read enable control signal of cross-clock-domain sending control logic is used to avoid the interaction between read-write pointers across clock domains, avoid the loss of clock signal edge judgment and jump edge triggering, and also avoid the loss of frequent measurement and determination of clock phase difference, thereby ensuring the correctness of data transmission control from the low-speed clock domain to the high-speed clock domain, also ensuring the correctness of parallel-to-serial logic, effectively reducing the logic depth and chip complexity, helping to achieve higher rates and reduce overall power consumption, and being conducive to meeting the requirements of higher and higher transmission rates and cost control requirements.

[0061] Referring to Figure 7In a possible implementation, the method further includes adjusting, by a digital delay chain, a delay of the read enable control signal received by the cross-clock-domain sending transmission logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross-clock-domain sending transmission logic. In this way, an additional delay adjustment function is provided by the digital delay chain, which can adjust the delay of the read enable control signal received by the cross-clock-domain sending transmission logic according to the delay control signal, which helps to adjust the sending delay logic to ensure correct transmission of data. With the delay adjustment function provided by the digital delay chain, the problem of delay difference between different lines on the circuit board can be effectively addressed. Specifically, there are multiple lines on the circuit board, and each input and output port corresponds to a separate line. The delays of different lines can be different, which makes it difficult to sample the correct data when the data signals transmitted through multiple lines are sampled by the same clock signal on the receiving side, such as the DRAM side. Therefore, by using the delay adjustment function and delay adjustment logic provided by the digital delay chain, the data delay can be indirectly adjusted by adjusting the delay of the clock, and the function of aligning the data and the clock on the DRAM side can be implemented. With the digital delay chain, the correct sampling of the data on the DRAM side is achieved by adjusting the delay of the data of the cross-clock-domain sending transmission logic. The data transmitted by the delay clock of the digital delay chain after the high-speed clock of the cross-clock-domain sending control logic is gated can ensure that the correct data is sampled on the DRAM side, and if the correct data cannot be sampled, the relationship between the data signal and the data clock signal can be adjusted by adjusting the delay, so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In some embodiments, the delay control signal is used to adjust the delay of the output data, so that the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal. In this way, the alignment of the data and the clock is achieved, which helps to ensure that the written data can be correctly sampled and read for output. By the delay adjustment function, the middle of the data signal associated with the output data is aligned with the sampling clock edge of the data clock signal associated with the data signal, which improves the accuracy on the reading side and helps to meet the cross-clock-domain writing and reading requirements.

[0062] The method and device provided by the embodiments of the present application are based on the same inventive concept, and the embodiments, implementation manners, examples or implementation modes of the method and device can refer to each other because the principles of the method and device for solving problems are similar, and the repeated parts will not be described herein. The embodiments of the present application further provide a system, which comprises a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0063] The embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0064] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. The present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both software and hardware aspects. Embodiments of the present application can be implemented in software, hardware, firmware or any combination thereof. Embodiments of the present application can be implemented as computer program products that comprise computer executable code, which when loaded and executed by a computer, cause the computer to perform the steps described in the embodiments of the present application. The present application can take the form of a computer program product which can be embodied in one or more computer-usable storage media having computer-usable program code embodied in said medium. The computer-usable program code can be executed by a computer to perform the steps described in the embodiments of the present application. The computer-usable program code can be stored (loaded) in a computer-usable storage medium (storage device) as computer-usable program code. The computer-usable storage medium (storage device) can be any available media that can be accessed by a computer. The computer-usable storage medium (storage device) can be a server, data center, or other data storage device that contains one or more collections of available media. The available media can be magnetic media (e.g., floppy diskette, hard disk, magnetic tape), optical media, or semiconductor media. The semiconductor media can be a solid state disk or a random access memory, a flash memory, a read only memory, a programmable read only memory, an electrically programmable read only memory, a register, or any other suitable storage medium.

[0065] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application. Each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1 The flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application. Each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1 The flowcharts and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the present application. Each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowcharts and / or block diagrams block or blocks. Figure 1one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks

[0066] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiments of the present application can be adjusted, combined or deleted in sequence according to actual needs; the modules in the system of the embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. An apparatus for high speed input / output, characterized by, The device comprises: Cross-clock-domain sending transmission logic, configured to periodically receive N-tap input data of single-tap N bits according to a write clock signal in a write clock domain, and write the N-tap input data into a first first-in-first-out memory in the cross-clock-domain sending transmission logic bit by bit according to a value of each bit of an N-bit write enable control signal, and read the first first-in-first-out memory as output data according to a read enable control signal; Cross-clock-domain sending control logic, configured to write the write enable control signal into a second first-in-first-out memory in the cross-clock-domain sending control logic, and read the second first-in-first-out memory as a gate signal according to a read clock signal in a read clock domain, and gate the read clock signal according to the gate signal to obtain the read enable control signal, wherein a frequency of the read clock signal is N times of a frequency of the write clock signal, and the N is a positive integer greater than 1 and equal to 1.

2. The apparatus of claim 1, wherein, The input data comprises parallel port data to be transmitted and parallel port enable to be transmitted, and the output data comprises serial port sending data corresponding to the parallel port data to be transmitted and serial port sending enable corresponding to the parallel port enable to be transmitted.

3. The apparatus of claim 1, wherein, The read enable control signal is used together with the write enable control signal to establish read-write pipeline control of the cross-clock-domain sending transmission logic.

4. The apparatus of claim 1, wherein, The cross-clock-domain sending control logic is configured to implement control signal conversion from the write clock domain to the read clock domain to implement period-level timing control.

5. The apparatus of claim 1, wherein, The cross-clock-domain sending transmission logic, configured to write the N-tap input data into the first first-in-first-out memory bit by bit according to a value of each bit of the N-bit write enable control signal, comprises: writing data in a bit corresponding to a position of a bit with a value of 1 in the N bits of the write enable control signal in each tap of the N-tap input data according to the position of the bit with the value of 1.

6. The apparatus of claim 1, wherein, The cross-clock-domain sending transmission logic, configured to write the N-tap input data into the first first-in-first-out memory bit by bit according to a value of each bit of the N-bit write enable control signal, comprises: writing data in a bit corresponding to a position of a bit with a value of 0 in the N bits of the write enable control signal in each tap of the N-tap input data according to the position of the bit with the value of 0.

7. The apparatus of claim 1, wherein, The cross-clock-domain sending control logic further comprises a gating module, configured to gate the read clock signal according to the gate signal to obtain the read enable control signal.

8. The apparatus of claim 1, wherein, The device further comprises a digital delay chain configured to adjust a delay of the read enable control signal received by the cross-clock-domain transmission logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross-clock-domain transmission logic.

9. The apparatus of claim 8, wherein, The delay control signal is configured to adjust the delay of the output data, so as to make a middle of a data signal associated with the output data align with a sampling clock edge of a data clock signal associated with the data signal.

10. The apparatus of claim 8, wherein, The device further comprises a self-test module and a single-ended output module configured to selectively transmit data outwards or transmit loopback data to the self-test module after receiving the output data, and the self-test module is configured to provide a data self-test function according to the input data and the loopback data.

11. The apparatus of claim 10, wherein, The delay control signal is configured to adjust the delay of the output data, so as to cooperate with the self-test module to realize a data eye scan function.

12. The apparatus of claim 1, wherein, The cross-clock-domain transmission control logic is further configured to receive a control signal set, wherein the control signal set comprises a power control signal and a termination resistance control signal.

13. The apparatus of claim 1, wherein, The device is applied to a high-speed input and output application scenario with insertions and deletions, and the high-speed input and output application scenario comprises one or more of the following: a transmitting end of a serializer-deserializer, a double data rate synchronous dynamic random access memory, a low-power fifth-generation double-rate memory, a high-bandwidth memory, a die-to-die interconnection, a chip-to-chip interconnection for a vehicle-grade chip, an internal interconnection of a data center, and an internal interconnection of an artificial intelligence platform.

14. A method for high speed input / output, characterized by, The method comprises: by the cross-clock-domain transmission logic, periodically receiving N-tap input data of a single-tap N-bit according to a write clock signal in a write clock domain, and writing the N-tap input data into a first first-in-first-out memory in the cross-clock-domain transmission logic bit by bit according to a value of each bit in an N-bit write enable control signal, and reading the first first-in-first-out memory as output data according to a read enable control signal; by the cross-clock-domain transmission control logic, writing the write enable control signal into a second first-in-first-out memory in the cross-clock-domain transmission control logic, and reading the second first-in-first-out memory as a gate signal according to a read clock signal in a read clock domain, and gating the read clock signal to obtain the read enable control signal according to the gate signal, wherein a frequency of the read clock signal is N times of a frequency of the write clock signal, and the N is a positive integer greater than 1 and equal to 1.

15. The method of claim 14, wherein, The method further comprises: by a digital delay chain, adjusting a delay of the read enable control signal received by the cross-clock-domain transmission logic according to a delay control signal, so as to adjust a delay of the output data provided by the cross-clock-domain transmission logic.

16. The method of claim 15, wherein, The delay control signal is configured to adjust the delay of the output data, so as to make a middle of a data signal associated with the output data align with a sampling clock edge of a data clock signal associated with the data signal.

Images