Read-write conversion circuit and memory

Abstract

The embodiment of the invention relates to a read-write conversion circuit and a memory, and the read-write conversion circuit comprises a first data line connected with a bit line through a column selection module, and a first complementary data line, a second data line and a second complementary data line which are connected with a complementary bit line through the column selection module, and further comprises a read-write conversion module, in response to a read-write control signal, during read-write operation, data are transmitted between the first data line and the second data line, and data are transmitted between the first complementary data line and the second complementary data line; and the amplification module is connected between the first data line and the first complementary data line and is used for amplifying the data of the first data line and the data of the first complementary data line. The embodiment of the invention can improve the data transmission speed.

Description

[0001] This application is a divisional application of the patent application with the application date of June 5, 2020, application number 202010504964.5, and invention name "Read-write conversion circuit and memory". Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a read-write conversion circuit and a memory. Background Art

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0004] DRAM can be categorized as Double Data Rate (DDR), Graphics Double Data Rate (GDDR), and Low Power Double Data Rate (LPDDR). As DRAM is increasingly used in a wide range of fields, including the mobile sector, users are demanding higher and higher DRAM speed specifications.

[0005] However, the data transfer speed of current DRAM during reading and writing still needs to be improved. Summary of the Invention

[0006] Embodiments of the present invention provide a read-write conversion circuit and a memory to solve the problem of slow data transmission speed during read and write operations.

[0007] To solve the above problems, an embodiment of the present invention provides a read-write conversion circuit, including: a first data line connected to the bit line via a column selection module and a first complementary data line, a second data line and a second complementary data line connected to the complementary bit line via the column selection module, and also including: a read-write conversion module, which responds to a read-write control signal and transmits data between the first data line and the second data line and between the first complementary data line and the second complementary data line during a read-write operation; an amplification module, connected between the first data line and the first complementary data line, and used to amplify the data of the first data line and the data of the first complementary data line.

[0008] In addition, the amplification module includes: a first inverter, an input end of the first inverter is electrically connected to the first data line, and an output end of the first inverter is electrically connected to the first complementary data line; a second inverter, an input end of the second inverter is electrically connected to the output end of the first inverter and the first complementary data line, and an output end of the second inverter is electrically connected to the input end of the first inverter and the first data line.

[0009] In addition, the first inverter includes: a first PMOS transistor and a first NMOS transistor, the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected and serve as the input of the first inverter, the source of the first PMOS transistor is connected to the working power supply, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and serve as the output of the first inverter; the second inverter includes: a second PMOS transistor and a second NMOS transistor, the gate of the second PMOS transistor and the gate of the second NMOS transistor are connected and serve as the input of the second inverter, the source of the second PMOS transistor is connected to the working power supply, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected and serve as the output of the second inverter.

[0010] In addition, the read-write conversion module includes: a first read-write unit, which transfers the data of the first data line to the second data line in response to a read control signal in the read-write control signal, or transfers the data of the second data line to the first data line in response to a write control signal in the read-write control signal; a second read-write unit, which transfers the data of the first complementary data line to the second complementary data line in response to the read control signal, or transfers the data of the second complementary data line to the first complementary data line in response to the write control signal.

[0011] In addition, the first read-write unit includes: a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; the gate of the third NMOS transistor receives the write control signal, and the third NMOS transistor is electrically connected to the first data line and the second data line in response to the write control signal; the gate of the fourth NMOS transistor is electrically connected to the first complementary data line, the drain of the fourth NMOS transistor is electrically connected to the second data line, the source of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor, and the gate of the fifth NMOS transistor receives the read control signal.

[0012] In addition, the second read-write unit includes: a seventh NMOS transistor, an eighth NMOS transistor and a ninth NMOS transistor; the gate of the seventh NMOS transistor receives the write control signal, and the seventh NMOS transistor is electrically connected to the first complementary data line and the second complementary data line in response to the write control signal; the gate of the eighth NMOS transistor is electrically connected to the first data line, the drain of the eighth NMOS transistor is electrically connected to the second complementary data line, the source of the eighth NMOS transistor is electrically connected to the drain of the ninth NMOS transistor, and the gate of the ninth NMOS transistor receives the read control signal.

[0013] In addition, the read-write conversion circuit also includes: a sixth NMOS tube, the gate of the sixth NMOS tube receives an enable signal, the drain of the sixth NMOS tube is connected to the first inverter and the second inverter, and is also electrically connected to the source of the fifth NMOS tube, and the source of the sixth NMOS tube is grounded.

[0014] In addition, the amplification module further includes: an enabling NMOS tube, the drain of which is electrically connected to the first inverter and the second inverter, the gate of which receives an enabling signal, and the source of which is grounded.

[0015] In addition, the read-write conversion module includes: a read unit, which transfers the data of the first data line to the second data line and the data of the first complementary data line to the second complementary data line in response to a read control signal in the read-write control signal; a write unit, which transfers the data of the second data line to the first data line and the data of the second complementary data line to the first complementary data line in response to a write control signal in the read-write control signal.

[0016] In addition, the write unit includes: a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor; the gate of the eighth NMOS transistor and the gate of the sixth NMOS transistor receive the write control signal, the eighth NMOS transistor is electrically connected to the first data line and the second data line in response to the write control signal, the gate of the seventh NMOS transistor is electrically connected to the second data line, the drain of the seventh NMOS transistor is electrically connected to the first complementary data line, the source of the seventh NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded.

[0017] In addition, the write unit further includes: a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; the gates of the third NMOS transistor and the fifth NMOS transistor receive the write control signal; the third NMOS transistor electrically connects the first complementary data line and the second complementary data line in response to the write control signal; the gate of the fourth NMOS transistor is electrically connected to the second complementary data line; the drain of the fourth NMOS transistor is electrically connected to the first data line; the source of the fourth NMOS transistor is electrically connected to the drain of the fifth NMOS transistor; and the source of the fifth NMOS transistor is grounded. In addition, the read unit includes: a tenth NMOS transistor and a twelfth NMOS transistor; the gate of the twelfth NMOS transistor receives the read control signal; the drain of the twelfth NMOS transistor is electrically connected to the second data line; the source of the twelfth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor; the gate of the tenth NMOS transistor is electrically connected to the first complementary data line; and the source of the tenth NMOS transistor is grounded.

[0018] In addition, the reading unit also includes: a ninth NMOS transistor and an eleventh NMOS transistor; the gate of the ninth NMOS transistor is electrically connected to the first data line, the source is grounded, and the drain is electrically connected to the source of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor receives the reading control signal, and the drain of the eleventh NMOS transistor is electrically connected to the second complementary data line.

[0019] In addition, it also includes a pre-charging module, which is connected between the first data line and the first complementary data line and is used to pre-charge the first data line and the first complementary data line in response to a pre-charging control signal.

[0020] In addition, the pre-charge module includes: a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, the gates of the third PMOS transistor, the gates of the fourth PMOS transistor and the fifth PMOS transistor receive a pre-charge control signal; the source of the third PMOS transistor and the source of the fourth PMOS transistor are connected to the working power supply, the drain of the third PMOS transistor is electrically connected to the first data line; the drain of the fourth PMOS transistor is electrically connected to the first complementary data line; and the fifth PMOS transistor is electrically connected to the first data line and the first complementary data line in response to the pre-charge control signal.

[0021] Correspondingly, an embodiment of the present invention further provides a memory including the above-mentioned read-write conversion circuit.

[0022] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0023] An embodiment of the present invention provides a read-write conversion circuit, comprising a first data line connected to a bit line via a column select module, and a first complementary data line connected to a complementary bit line via a column select module; a read-write conversion module configured to transmit data between the first data line and the first complementary data line and a second data line and the second complementary data line in response to a read control signal or a write control signal; and an amplification module connected between the first data line and the first complementary data line, configured to amplify data on the first data line and the first complementary data line. The provision of the amplification module facilitates faster differentiation between data signals on the first data line and the first complementary data line, amplifying the data signals, thereby improving the speed of data transmission in the read-write conversion circuit.

[0024] The memory provided by the present invention includes the aforementioned read-write conversion circuit with excellent structural performance, and the corresponding memory has the advantage of fast transmission speed. Furthermore, due to the provision of the amplification module, the read-write conversion circuit in the memory requires low drive capability from the memory. Specifically, the first data line and the first complementary data line require low drive capability from the first-stage amplifier in the memory. Therefore, even if the area of ​​the first-stage amplifier is reduced, sufficient drive capability can still be guaranteed, meeting the trend of device miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0026] Figure 1 A schematic diagram of the functional modules of a read-write conversion circuit provided in one embodiment of the present invention;

[0027] Figure 2 A schematic diagram of the circuit structure of a read-write conversion circuit provided in one embodiment of the present invention;

[0028] Figure 3 A circuit timing diagram of the read-write conversion circuit provided by an embodiment of the present invention during a read operation;

[0029] Figure 4 A schematic diagram of a circuit structure of a read-write conversion circuit provided by another embodiment of the present invention;

[0030] Figure 5 A schematic diagram of another circuit structure of a read-write conversion circuit provided by another embodiment of the present invention;

[0031] Figure 6 A schematic diagram of the structure of a memory provided by one embodiment of the present invention;

[0032] Figure 7 for Figure 6 Schematic diagram of the locally enlarged structure of area A in the middle. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, the current data transmission speed of DRAM still needs to be improved. In a DRAM read operation, after the selected word line is activated, the data in the corresponding storage cell will be transferred to the bit line, causing the voltage on the bit line to increase or decrease slightly. The sense amplifier connected to the bit line, usually called the first-stage amplifier (FSA, first senseamplifier), will pull the bit line signal to 0 or 1 based on this weak signal. The column select module will transmit the 0 or 1 signal on the selected bit line to the local data line based on the column select signal, and then transmit the signal in the local data line to the global data line through the read-write conversion circuit.

[0034] However, the inventors have discovered that ensuring high data transmission speeds requires high drive performance from the memory's first-stage amplifier. For example, when reading data, after the column select signal line CSL is pulled high, the first-stage amplifier directly drives the local data line. Insufficient drive capability in the first-stage amplifier significantly impacts the speed of pulling up or pulling down the local data line. However, with technological advancements and demands for reduced area, first-stage amplifiers are becoming increasingly smaller, making it difficult to increase their drive capability. Therefore, to ensure high data transmission speeds, it is necessary to consider how to reduce the drive capability requirements of the local data lines on the first-stage amplifier.

[0035] To solve the above problems, an embodiment of the present invention provides a read-write conversion circuit, wherein the first data line is connected to the bit line through a column selection module, and the first complementary data line is connected to the complementary bit line through the column selection module. An amplification module is provided between the first data line and the first complementary data line, for amplifying the data signals of the first data line and the first complementary data line, so as to accelerate the distinction between the first data line and the first complementary data line, for example, making the first data line or the first complementary data line with a lower voltage become 0 more quickly, and the first data line or the first complementary data line with a higher voltage become 1 more quickly, thereby accelerating the data transmission of the read operation or the write operation, and reducing the demand for the driving capability of the first-stage amplifier for the first data line and the first complementary data line.

[0036] To make the objectives, technical solutions, and advantages of the present invention more apparent, various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present invention to help readers better understand the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0037] Figure 1 This is a functional module diagram of a read-write conversion circuit provided by an embodiment of the present invention. Figure 2 A schematic diagram of a circuit structure provided by an embodiment of the present invention.

[0038] Combined with reference Figure 1 and Figure 2 In this embodiment, the read-write conversion circuit includes: a first data line Ldat and a first complementary data line Ldat#, the first data line Ldat is connected to the bit line BL via the column selection module 100, the first complementary data line Ldat# is electrically connected to the complementary bit line BL# via the column selection module 100, a second data line Gdat# and a second complementary data line Gdat; a read-write conversion module 101, which responds to a read-write control signal and transmits data between the first data line Ldat and the second data line Gdat, and between the first complementary data line Ldat# and the second complementary data line Gdat# during a read-write operation; and an amplification module 102, connected between the first data line Ldat and the first complementary data line Ldat#, and configured to amplify data on the first data line Ldat and the first complementary data line Ldat#.

[0039] Amplification module 102 forms a circuit for amplifying the signal of the first data line Ldat and the signal of the first complementary data line Ldat#. This helps accelerate the differentiation between the first data line Ldat and the first complementary data line Ldat#, thereby increasing the speed of data signal transmission and improving data read and write speeds. Furthermore, because the data signals of the first data line Ldat and the first complementary data line Ldat# are amplified, the driving capability requirements of the first-stage amplifier circuit in the memory are reduced. Therefore, even if the area of ​​the first-stage amplifier circuit is gradually reduced, the first-stage amplifier circuit still has sufficient driving capability for the first data line Ldat and the first complementary data line Ldat#. This ensures that the read-write conversion circuit has good electrical performance while meeting the trend of device miniaturization, thereby improving the storage performance of the memory including the read-write conversion circuit.

[0040] The read-write conversion circuit provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0041] In this embodiment, the data signals to be read or written are in pairs, with each pair of data signals including two data. During a read or write operation, one of the two data is a high-level signal, and the other is a low-level signal. Therefore, the read-write conversion circuit includes at least one pair of first data lines Ldat and first complementary data lines Ldat#, and at least one pair of second data lines Gdat and second complementary data lines Gdat#. Specifically, during a read operation, the read-write conversion circuit transmits data via the first data line Ldat and first complementary data line Ldat# to the second data line Gdat and second complementary data line Gdat#. During a write operation, the read-write conversion circuit transmits data via the second data line Gdat and second complementary data line Gdat# to the first data line Ldat and first complementary data line Ldat#.

[0042] The first data line Ldat is a local data line, and the first complementary data line Ldat# is a complementary local data line. The second data line Gdat is a global data line, and the second complementary data line Gdat# is a complementary global data line.

[0043] Specifically, the read-write conversion circuit is applied to a memory, which includes a column selection module 100. A first data line Ldat is connected to a bit line BL via the column selection module 100, and a first complementary data line Ldat# is connected to a complementary bit line BL# via the column selection module 100. A memory cell for a read or write operation is selected via the column selection module 100. Accordingly, a signal is transmitted between the bit line BL connected to the selected memory cell and the first data line Ldat, and a signal is transmitted between the complementary bit line BL# connected to the selected memory cell and the first complementary data line Ldat#.

[0044] The read and write control signals include a read control signal Rd and a write control signal Wr. During a read or write operation, in response to the read control signal Rd, the read-write conversion module 101 transfers data from the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat#. Alternatively, in response to the write control signal Wr, the read-write conversion module 101 transfers data from the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line Ldat#.

[0045] In this embodiment, the read-write conversion module 101 includes: a first read-write unit 111, which transmits the data of the first data line Ldat to the second data line Gdat in response to the read control signal Rd, or, in response to the write control signal Wr, transmits the data of the second data line Gdat to the first data line Ldat; a second read-write unit 121, which transmits the data of the first complementary data line Ldat# to the second complementary data line Gdat# in response to the read control signal Rd, or, in response to the write control signal Wr, transmits the data of the second complementary data line Gdat# to the first complementary data line Ldat#.

[0046] In an example, the first read-write unit 111 includes: a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5; the gate of the third NMOS transistor MN3 receives a write control signal Wr, and the third NMOS transistor MN3 is electrically connected to the first data line Ldat and the second data line Gdat in response to the write control signal Wr; the gate of the fourth NMOS transistor MN4 is electrically connected to the first complementary data line Ldat#, the drain of the fourth NMOS transistor MN4 is electrically connected to the second data line Gdat, the source of the fourth NMOS transistor MN4 is electrically connected to the drain of the fifth NMOS transistor MN5, and the gate of the fifth NMOS transistor MN5 receives a read control signal Rd. The second read-write unit 121 includes: a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; the gate of the seventh NMOS transistor MN7 receives a write control signal Wr, and the seventh NMOS transistor MN7 is electrically connected to the first complementary data line Ldat# and the second complementary data line Gdat# in response to the write control signal Wr; the gate of the eighth NMOS transistor MN8 is electrically connected to the first data line Ldat, the drain is electrically connected to the second complementary data line Gdat#, and the source is electrically connected to the drain of the ninth NMOS transistor MN9, and the gate of the ninth NMOS transistor MN9 receives a read control signal Rd.

[0047] In this embodiment, the circuit structure diagrams of the first read-write unit 111 and the second read-write unit 121 are the same. In other embodiments, the circuit structure diagrams of the first read-write unit and the second read-write unit may also be different, as long as data transmission can be achieved during the read-write operation.

[0048] During a read operation, data is first transferred from the selected bit line and complementary bit line to the first data line and first complementary data line via the column select module. After amplification by amplifier module 102, the first data line and first complementary data line quickly reach a low or high level. The data is then transferred from the first data line Ldat and first complementary data line Ldat# to the second data line Gdat and second complementary data line Gdat#. When the read control signal Rd is high and the write control signal Wr is low, the third NMOS transistor MN3 and the seventh NMOS transistor MN7 are turned off, and the fifth NMOS transistor MN5 and the ninth NMOS transistor MN9 are turned on. When the first data line Ldat is high, the first complementary data line Ldat# is low, and the enable signal En is high, the eighth NMOS transistor MN8 and the sixth NMOS transistor MN6 are turned on, and data is transmitted from the first complementary data line Ldat# to the second complementary data line Gdat#. The second complementary data line Gdat# becomes 0, and the second data line Gdat becomes 1. When the first data line Ldat is low and the first complementary data line Ldat# is high, the fourth NMOS transistor MN4 and the sixth NMOS transistor MN6 are turned on, and data is transmitted from the first data line Ldat to the second data line Gdat. The second data line Gdat becomes 0, and the second complementary data line Gdat# becomes 1.

[0049] During a write operation, the direction of data transfer is opposite to that during a read operation.

[0050] In this embodiment, the read-write conversion circuit further includes: a sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 receives the enable signal En, and the drain of the sixth NMOS transistor MN6 is electrically connected to the source of the fifth NMOS transistor MN5 and the source of the ninth NMOS transistor MN9, and the source of the sixth NMOS transistor MN6 is grounded.

[0051] In this embodiment, the amplification module 102 includes: a first inverter, wherein the input terminal in1 of the first inverter is electrically connected to the first data line Ldat; a second inverter, wherein the input terminal in2 of the second inverter is electrically connected to the output terminal out1 of the first inverter and the first complementary data line Ldat#, and the output terminal out2 of the second inverter is electrically connected to the input terminal in1 of the first inverter and the first data line Ldat.

[0052] During the read phase, the configuration of the amplification module 102 increases the speed of data transmission from the bit line BL to the first data line Ldat, and also increases the speed of data transmission from the complementary bit line BL# to the first complementary data line Ldat#, thereby reducing the drive requirements of the first-stage amplifier of the memory. Specifically, taking the example of data on the bit line BL being at a high level and data on the complementary bit line BL# being at a low level, since the first input terminal in1 of the first inverter is connected to the second output terminal out2 of the second inverter, and the first output terminal out1 of the first inverter is connected to the second input terminal in2 of the second inverter, during the transmission of the bit line BL and the complementary bit line BL# to the first data line Ldat and the first complementary data line Ldat#, the configuration of the amplification module 102 causes the first complementary data line Ldat#, which has a lower voltage, to be pulled down to "0" more quickly, or causes the first data line Ldat, which has a higher voltage, to be pulled up to "1" more quickly. Therefore, the speed at which the first data line Ldat is pulled up is increased, and the speed at which the first complementary data line Ldat# is pulled down is also increased, thereby reducing the driving requirements of the first data line Ldat and the first complementary data line Ldat# on the first stage amplifier.

[0053] At the same time, since the first data line Ldat and the first complementary data line Ldat# can reach a high level or a low level more quickly, the first data line Ldat and the first complementary data line Ldat# can be transmitted to the second data line Gdat and the second complementary data line Gdat# earlier. In this way, when reading data, the speed of transmitting data from the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat# is improved.

[0054] Accordingly, during the writing period, the amplifying module 102 can also amplify the first data line Ldat and the first complementary data line Ldat#, thereby increasing the speed of data transmission from the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line Ldat#.

[0055] Specifically, the first inverter includes: a first PMOS transistor MP1 and a first NMOS transistor MN1. The gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are electrically connected and serve as the input end in1 of the first inverter. The source of the first PMOS transistor MP1 is connected to the working power supply VDD. The drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1 are connected and serve as the output end out1 of the first inverter.

[0056] The second inverter includes: a second PMOS transistor MP2 and a second NMOS transistor MN2. The gate of the second PMOS transistor MP2 is connected to the gate of the second NMOS transistor MN2 and serves as the input terminal in2 of the second inverter. The source of the second PMOS transistor MP2 is connected to the working power supply VDD. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2 and serves as the output terminal out2 of the second inverter.

[0057] The first PMOS transistor MP1 , the first NMOS transistor MN1 , the second PMOS transistor MP2 , and the second NMOS transistor MN2 constitute an amplifying module 102 .

[0058] In addition, the first inverter and the second inverter are also connected to the drain of the sixth NMOS transistor. Specifically, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are connected to the drain of the sixth NMOS transistor MN6.

[0059] In this embodiment, the read-write conversion circuit may further include: a pre-charging module 103, the pre-charging module 103 is connected between the first data line Ldat and the first complementary data line Ldat#, and is used to pre-charge the first data line Ldat and the first complementary data line Ldat# in response to the pre-charging control signal Eq.

[0060] Specifically, the pre-charge module 103 includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5; the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 receive a pre-charge control signal Eq; the source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected to the working power supply VDD, the drain of the third PMOS transistor MP3 is electrically connected to the first data line Ldat; the drain of the fourth PMOS transistor MP4 is electrically connected to the first complementary data line Ldat#; and the fifth PMOS transistor MN5 is electrically connected to the first data line Ldat and the first complementary data line Ldat# in response to the pre-charge control signal Eq.

[0061] Figure 3 This is a circuit timing diagram of a read-write conversion circuit without an additional amplification module and the read-write conversion circuit provided in this embodiment during a read operation. To facilitate distinction, in the circuit timing diagram, for the same signal with a changed timing, the dotted line represents the timing corresponding to the absence of the additional amplification module, and the solid line represents the timing corresponding to this embodiment. CSL represents the column selection signal.

[0062] like Figure 3As shown, compared with the read-write conversion circuit without the additional amplification module, in this embodiment, the data of the first data line Ldat and the first complementary data line Ldat# reaches a high level or a low level t time in advance. That is, in this embodiment, the data can be transmitted t time in advance, and the rising edge time of the read control signal Rd can be advanced from time A1 to time A2, and the difference between time A2 and time A1 is t.

[0063] Another embodiment of the present invention further provides a read-write conversion circuit. The specific circuit structure of the read-write conversion module in this embodiment is different from that of the previous embodiment. The read-write conversion circuit provided by this embodiment will be described below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as the previous embodiment, please refer to the detailed description of the previous embodiment and will not be repeated below.

[0064] Figure 4 A schematic diagram of a circuit structure of a read-write conversion circuit provided in another embodiment of the present invention.

[0065] refer to Figure 4 In this embodiment, the read-write conversion circuit includes: a first data line Ldat, a first complementary data line Ldat#, a second data line Gdat, a second complementary data line Gdat#, a read-write conversion module and an amplification module.

[0066] The read-write conversion circuit provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0067] The amplifier module includes a first inverter and a second inverter. The first inverter includes a first PMOS transistor mp1 and a first NMOS transistor mn1. The second inverter includes a second PMOS transistor mp2 and a second NMOS transistor mn2. For detailed descriptions of the first and second inverters, please refer to the detailed descriptions of the above embodiments.

[0068] Different from the previous embodiment, in this embodiment, the amplification module further includes: an enable NMOS transistor mn, the drain of the enable NMOS transistor mn is electrically connected to the first inverter and the second inverter, the gate of the enable NMOS transistor mn receives the enable signal En, and the source of the enable NMOS transistor mn is grounded.

[0069] Specifically, the drain of the enabling NMOS transistor mn is electrically connected to the source of the first NMOS transistor mn1 and the source of the second NMOS transistor mn2.

[0070] The first PMOS transistor mp1 , the first NMOS transistor mn1 , the second PMOS transistor mp2 , the second NMOS transistor mn2 and the enable NMOS transistor mn constitute an amplification module for amplifying data of the first data line Ldat and the first complementary data line Ldat#.

[0071] In this embodiment, the read-write conversion module includes: a read unit, which responds to a read control signal Rd and transmits the data of the first data line Ldat and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat#, respectively; a write unit, which responds to a write control signal Wr and transmits the data of the second data line Gdat and the second complementary data line Gdat# to the first data line Ldat and the first complementary data line Ldat#, respectively.

[0072] Specifically, the writing unit includes a third NMOS transistor mn3, a fourth NMOS transistor mn4, a fifth NMOS transistor mn5, a sixth NMOS transistor mn6, a seventh NMOS transistor mn7 and an eighth NMOS transistor mn8.

[0073] The drain of the third NMOS transistor mn3 is electrically connected to the output terminal out1 of the first inverter. The gate of the third NMOS transistor mn3 and the gate of the fifth NMOS transistor mn5 receive the write control signal Wr. In response to the write control signal Wr, the third NMOS transistor mn3 is electrically connected to the first complementary data line Ldat# and the second complementary data line Gdat#. The gate of the fourth NMOS transistor mn4 is electrically connected to the second complementary data line Gdat#. The drain of the fourth NMOS transistor mn4 is electrically connected to the first data line Ldat. The source of the fourth NMOS transistor mn4 is electrically connected to the drain of the fifth NMOS transistor mn5. The fifth NMOS transistor mn 5 source is grounded; the drain of the eighth NMOS transistor mn8 is electrically connected to the output end of the second inverter, the gate of the eighth NMOS transistor mn8 and the gate of the sixth NMOS transistor mn6 receive the write control signal Wr, and the eighth NMOS transistor mn8 is electrically connected to the first data line Ldat and the second data line Gdat in response to the write control signal Wr; the gate of the seventh NMOS transistor mn7 is electrically connected to the second data line Gdat, the drain of the seventh NMOS transistor mn7 is electrically connected to the first complementary data line Ldat#, the source of the seventh NMOS transistor mn7 is electrically connected to the drain of the sixth NMOS transistor mn6, and the source of the sixth NMOS transistor mn6 is grounded.

[0074] During a write operation, the write unit is used to transfer data from the second data line Gdat to the first data line Ldat, and to transfer data from the second complementary data line Gdat# to the first complementary data line Ldat#.

[0075] Specifically, during a write operation, when the write control signal Wr is at a high level, the third NMOS transistor mn3, the fifth NMOS transistor mn5, the sixth NMOS transistor mn6, and the eighth NMOS transistor mn8 are turned on. When the second complementary data line Gdat# is at a high level, the fourth NMOS transistor mn4 is turned on and the seventh NMOS transistor mn7 is turned off. Data on the second complementary data line Gdat# is transmitted to the first complementary data line Ldat#, the first data line Ldat becomes 0, and the first complementary data line Ldat# becomes 1. Due to the configuration of the amplification module, the time required for the first data line Ldat to become 0 is shortened, thereby accelerating the speed of distinguishing between the first data line Ldat and the first complementary data line Ldat#, thereby increasing the speed of writing data from the first data line Ldat and the first complementary data line Ldat# into the corresponding storage cells.

[0076] When the second complementary data line Gdat# is at a low level, the second data line Gdat is at a high level, the fourth NMOS transistor mn4 is turned off, and the seventh NMOS transistor mn7 is turned on. The data on the second data line Gdat is transferred to the first data line Ldat, the first complementary data line Ldat# becomes 0, and the first data line Ldat becomes 1. Due to the configuration of the amplification module, the time required for the first complementary data line Ldat# to become 0 is shortened, thereby accelerating the speed of distinguishing between the first data line Ldat and the first complementary data line Ldat#, and thereby increasing the speed of writing the data on the first data line Ldat and the first complementary data line Ldat# into the corresponding storage cells.

[0077] Specifically, the reading unit includes a ninth NMOS transistor mn9 , a tenth NMOS transistor mn10 , an eleventh NMOS transistor mn11 , and a twelfth NMOS transistor mn12 .

[0078] The ninth NMOS transistor mn9 has a gate electrically connected to the first data line Ldat, a source grounded, and a drain electrically connected to the source of the eleventh NMOS transistor mn11. The gates of the eleventh NMOS transistor mn11 and the twelfth NMOS transistor mn12 receive a write control signal Rd, and the drain of the eleventh NMOS transistor mn11 is electrically connected to the second complementary data line Gdat#.

[0079] The gate of the twelfth NMOS transistor mn12 receives the read control signal Rd, the drain of the twelfth NMOS transistor mn12 is electrically connected to the second data line Gdat, the source of the twelfth NMOS transistor mn12 is electrically connected to the drain of the tenth NMOS transistor mn10, the gate of the tenth NMOS transistor mn10 is electrically connected to the first complementary data line Ldat#, and the source of the tenth NMOS transistor mn10 is grounded.

[0080] During a read operation, the read unit is used to transfer data from the first data line Ldat to the second data line Gdat, and to transfer data from the first complementary data line Ldat# to the second complementary data line Gdat#.

[0081] Specifically, during a read operation, when the read control signal Rd is high, the eleventh and twelfth NMOS transistors mn11 and mn12 are turned on. When the first data line Ldat is high, the ninth NMOS transistor mn9 is turned on and the tenth NMOS transistor mn10 is turned off. Data from the first data line Ldat is transferred to the first data line Gdat, the second complementary data line Gdat# changes to 0, and the second data line Gdat changes to 1. When the first data line Ldat is low, the ninth NMOS transistor is turned off and the tenth NMOS transistor is turned on. Data from the first complementary data line Ldat# is transferred to the second complementary data line Gdat#, the second complementary data line Gdat# changes to 1, and the second data line Gdat changes to 0. Due to the configuration of the amplification module, the response time for the first data line Ldat or the first complementary data line Ldat# to change from a high level to a low level is shortened, thereby increasing the speed at which the second data line Gdat and the second complementary data line Gdat# can follow the change, thereby improving data transmission speed.

[0082] It needs to be said that Figure 4 The circuit diagram may also have other suitable variations. For example, the gates of the ninth NMOS transistor mn9 and the tenth NMOS transistor mn10 receive the read control signal Rd, the gate of the eleventh NMOS transistor mn11 is connected to the first data line Ldat, and the gate of the twelfth NMOS transistor mn12 is connected to the first complementary data line Ldat#; or the source of the fifth NMOS transistor mn5 and the source of the sixth NMOS transistor mn6 are electrically connected to the drain of the enable NMOS transistor mn.

[0083] It is understandable that Figure 4 In the example shown, both the writing unit and the reading unit adopt a double-ended transmission mode. In other embodiments, at least one of the writing unit or the reading unit may also adopt a single-ended transmission mode. For example, Figure 5 This is another circuit structure diagram of the read-write conversion circuit provided in this embodiment.

[0084] refer to Figure 5The write unit includes: a sixth NMOS transistor mn6, a seventh NMOS transistor mn7, and an eighth NMOS transistor mn8; the gates of the eighth NMOS transistor mn8 and the sixth NMOS transistor mn6 receive a write control signal Wr, and the eighth NMOS transistor mn8 is electrically connected to the first data line Ldat and the second data line Gdat in response to the write control signal Wr. The gate of the seventh NMOS transistor mn7 is electrically connected to the second data line Gdat, the drain of the seventh NMOS transistor mn7 is electrically connected to the first complementary data line Ldat#, the source of the seventh NMOS transistor mn7 is electrically connected to the drain of the sixth NMOS transistor mn6, and the source of the sixth NMOS transistor mn6 is grounded.

[0085] Continue to refer Figure 5 The reading unit includes: a tenth NMOS transistor mn10 and a twelfth NMOS transistor mn12; the gate of the twelfth NMOS transistor mn12 receives a reading control signal Rd; the drain of the twelfth NMOS transistor mn12 is electrically connected to the second data line Gdat, the source of the twelfth NMOS transistor mn12 is electrically connected to the drain of the tenth NMOS transistor mn10, the gate of the tenth NMOS transistor mn10 is electrically connected to the first complementary data line Ldat#, and the source of the tenth NMOS transistor mn10 is grounded.

[0086] In this embodiment, the read-write conversion circuit may further include: a pre-charging module.

[0087] Specifically, the pre-charging module includes: a third PMOS tube mp3, a fourth PMOS tube mp4 and a fifth PMOS tube mp5, the gates of the third PMOS tube mp3, the gates of the fourth PMOS tube mp4 and the gates of the fifth PMOS tube mp5 receive a pre-charging control signal Eq; the source of the third PMOS tube mp3 and the source of the fourth PMOS tube mp4 are connected to the working power supply VDD, the drain of the third PMOS tube mp3 is electrically connected to the first data line Ldat; the drain of the fourth PMOS tube mp4 is electrically connected to the first complementary data line Ldat#; the fifth PMOS tube mp5 is electrically connected to the first data line Ldat and the first complementary data line Ldat# in response to the pre-charging signal Eq.

[0088] It is understandable that the read-write conversion circuit provided in this embodiment may be used for signal amplification during only one of a read operation and a write operation, or may be used for signal amplification during both a read operation and a write operation.

[0089] In addition, it should be noted that the above-mentioned "becomes 0" or becomes "1" may include the following situations: for a certain data line (such as the first data line Ldat, the first complementary data line Ldat#, the second data line Gdat or the second complementary data line Gdat#), if the state after pre-charging is pre-charged to 0, then for this data line, the "becomes 0" described in the next state should be understood as "maintained at 0"; if the state after pre-charging is pre-charged to 1, then for this data line, the "becomes 1" described in the next state should be understood as "maintained at 1".

[0090] Compared with the previous embodiment, in the read-write conversion circuit provided in this embodiment, since the second complementary data line Gdat# in the write unit simultaneously affects the first data line Ldat and the first complementary data line Ldat#, or the second data line Gdat simultaneously affects the first data line Ldat and the first complementary data line Ldat#, the write operation speed of the memory using this read-write conversion circuit is faster.

[0091] Correspondingly, an embodiment of the present invention further provides a memory, comprising the read-write conversion circuit in any of the above embodiments. Figure 6 A schematic diagram of the structure of a memory provided by an embodiment of the present invention, Figure 7 for Figure 6 Schematic diagram of the locally enlarged structure of area A in the middle.

[0092] refer to Figure 6 and Figure 7 The memory includes: a plurality of memory modules, each memory module including a memory array 301 and a sense amplifier array 302, the sense amplifier array 302 including a plurality of sense amplifiers 312, and the memory array 301 including a plurality of memory cells; a column select signal line CSL; a word line WL; a read-write conversion circuit 300, each read-write conversion circuit 300 being connected to a corresponding sense amplifier array 302, and the read-write conversion circuit 302 including a first data line Ldat, a first complementary data line Ldat#, a second data line Gdat, and a second complementary data line Gdat#; a row decoding circuit 303; a column decoding circuit 304; and a driving circuit 305.

[0093] The memory is described below in conjunction with its working mechanism.

[0094] When a word line WL is selected by the row decoding circuit 303 , the data in the memory array 301 corresponding to the word line WL is transmitted to the sense amplifier 312 . After being amplified by the sense amplifier 312 , the data is written back to the memory cell connected to the selected word line WL.

[0095] When data needs to be written, the column decoding circuit 304 selects the corresponding sense amplifier 312. The data is then transmitted from the second data line Gdat and the second complementary data line Gdat# through the read-write conversion circuit 300 to the first data line Ldat and the first complementary data line Ldat#, and then written into the corresponding sense amplifier 312 and the connected memory cell. During the write operation, the read-write conversion circuit 300 not only performs signal transmission but also amplifies the first data line Ldat and the first complementary data line Ldat#, facilitating the rapid separation of the signals on the first data line Ldat and the first complementary data line Ldat#. This not only improves data transmission speed but also reduces the drive capability requirements of the read-write conversion circuit 300 for the sense amplifier 312. This allows a smaller sense amplifier 312 to meet the required drive capability, significantly reducing the manufacturing complexity of the sense amplifier 312 and aligning with the trend of device miniaturization.

[0096] When reading data, the direction of data transmission is opposite to that when writing data. The column decoding circuit 304 selects the corresponding sense amplifier 312, and the data is transmitted to the first data line Ldat and the first complementary data line Ldat#. The data is then transmitted to the second data line Gdat and the second complementary data line Gdat# via the read-write conversion circuit 300. Similarly, when reading data, the read-write conversion circuit 300 can significantly improve the speed of distinguishing the first data line Ldat and the first complementary data line Ldat#, thereby improving the speed at which data is transmitted from the sense amplifier 312, the first data line Ldat, and the first complementary data line Ldat# to the second data line Gdat and the second complementary data line Gdat#.

[0097] It is understandable that Figure 6 and Figure 7 Only one pair of second data lines and second complementary data lines is shown. In actual use, the memory may have multiple pairs of second data lines and second complementary data lines. Similarly, in actual use, the memory may have multiple pairs of first data lines and first complementary data lines.

[0098] The memory may be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. As can be seen from the above analysis, the memory provided in this embodiment has the advantage of fast data transmission speed and low demand for the driving capability of the sense amplifier, which is conducive to meeting the development trend of device miniaturization.

[0099] Those skilled in the art will appreciate that the above-described embodiments are specific examples of the present invention, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A read-write conversion circuit, characterized in that: include: A first data line connected to the bit line via a column selection module, a first complementary data line connected to the complementary bit line via a column selection module, and a second data line, further comprising: a read / write conversion module, responsive to a read / write control signal, transmitting data between the first data line and the second data line during a read / write operation; an amplification module, connected between the first data line and the first complementary data line, and configured to amplify data on the first data line and data on the first complementary data line; The read-write conversion module includes: a read unit, which transmits data of the first data line to the second data line in response to a read control signal in the read-write control signal; and a write unit, which transmits data of the second data line to the first data line in response to a write control signal in the read-write control signal. The write unit includes: a sixth NMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor; the gate of the eighth NMOS transistor receives the write control signal, the eighth NMOS transistor is electrically connected to the first data line and the second data line in response to the write control signal, the drain of the seventh NMOS transistor is electrically connected to the first complementary data line, and the source of the seventh NMOS transistor is electrically connected to the drain of the sixth NMOS transistor.

2. The read-write conversion circuit according to claim 1, wherein: The gate of the sixth NMOS transistor receives the write control signal, and the gate of the seventh NMOS transistor is electrically connected to the second data line.

3. The read-write conversion circuit according to claim 1, wherein: The reading unit includes: a tenth NMOS transistor and a twelfth NMOS transistor; the drain of the twelfth NMOS transistor is electrically connected to the second data line, the source of the twelfth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor, and the source of the tenth NMOS transistor is grounded.

4. The read-write conversion circuit according to claim 3, wherein: The gate of the twelfth NMOS transistor receives the read control signal, and the gate of the tenth NMOS transistor is electrically connected to the first complementary data line.

5. The read-write conversion circuit according to claim 3, wherein: The gate of the tenth NMOS transistor receives the read control signal, and the gate of the twelfth NMOS transistor is electrically connected to the first complementary data line.

6. The read-write conversion circuit according to claim 1, wherein: The amplification module includes: a first inverter, wherein the input end of the first inverter is electrically connected to the first data line, and the output end of the first inverter is electrically connected to the first complementary data line; a second inverter, wherein the input end of the second inverter is electrically connected to the output end of the first inverter and the first complementary data line, and the output end of the second inverter is electrically connected to the input end of the first inverter and the first data line.

7. The read-write conversion circuit according to claim 6, wherein: The first inverter includes: a first PMOS transistor and a first NMOS transistor. The gate of the first PMOS transistor and the gate of the first NMOS transistor are connected and serve as an input end of the first inverter. The source of the first PMOS transistor is connected to an operating power supply. The drain of the first PMOS transistor and the drain of the first NMOS transistor are connected and serve as an output end of the first inverter.

8. The read-write conversion circuit according to claim 7, wherein: The second inverter includes: a second PMOS transistor and a second NMOS transistor, the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor and serves as the input end of the second inverter, the source of the second PMOS transistor is connected to the working power supply, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and serves as the output end of the second inverter.

9. The read-write conversion circuit according to claim 8, wherein: The source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is grounded.

10. The read-write conversion circuit according to claim 8, wherein: The amplification module further includes an enabling NMOS transistor, the drain of which is electrically connected to the first inverter and the second inverter, the gate of which receives an enabling signal, and the source of which is grounded.

11. The read-write conversion circuit according to claim 1, wherein: The source of the sixth NMOS transistor is grounded.

12. The read-write conversion circuit according to claim 1, wherein: The read-write conversion circuit further includes an enabling NMOS transistor, the gate of which receives an enabling signal, the drain of which is electrically connected to the source of the sixth NMOS transistor, and the source of which is grounded.

13. The read-write conversion circuit according to claim 1, wherein: Also includes: A pre-charging module is connected between the first data line and the first complementary data line, and is used to pre-charge the first data line and the first complementary data line in response to a pre-charging control signal.

14. The read-write conversion circuit according to claim 13, wherein: The pre-charging module includes: a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor, wherein the gates of the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor receive the pre-charging control signal; The source of the third PMOS transistor and the source of the fourth PMOS transistor are electrically connected to an operating power supply, the drain of the third PMOS transistor is electrically connected to the first data line; the drain of the fourth PMOS transistor is electrically connected to the first complementary data line; and the fifth PMOS transistor is electrically connected to the first data line and the first complementary data line in response to the precharge control signal.

15. A memory, characterized in that: The method comprises the read-write conversion circuit according to any one of claims 1 to 14.

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