NAND Flash data read-write method, computer equipment and storage medium

Abstract

The embodiment of the invention provides an NAND Flash data read-write method, computer equipment and a storage medium. The method comprises the steps that firstly, a write-in request of original data is received; obtaining ECC verification information according to the original data, and carrying out randomization processing on the ECC verification information to obtain target data; the target data is written into an NAND Flash page; and reading the data of the NAND Flash Page to an ECC (Error Correction Code) decoding unit, and inputting the randomized seed corresponding to the ECC verification information into the ECC decoding unit to obtain original data. According to the embodiment of the invention, by randomizing the ECC verification information, the randomization degree of reading and writing the data of the NAND Flash is improved, so that the reliability of reading and writing the data is improved, and the stability of the NAND Flash storage system is remarkably improved.

Description

Technical Field

[0001] The present application relates to the technical field of reading and writing NAND Flash data, and in particular to a method for reading and writing NAND Flash data, a computer device, and a storage medium. Background Art

[0002] In related technologies, the iterative upgrades of NAND Flash products, especially the latest QLC products, have placed higher demands on error correction capabilities. At the same time, page sizes are gradually increasing. For example, some QLC NAND Flash memories have a spare area approaching 2800 bytes (the purpose of this spare area is to accommodate more ECC information, thereby achieving higher error correction capabilities). This has the effect of significantly increasing the proportion of non-randomized data written to NAND Flash using existing application methods, making it more difficult to achieve the required randomization performance. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a NAND Flash data reading and writing method, computer equipment, and storage medium, aiming to improve the reliability of reading and writing data and enhance the stability of the NAND Flash storage system.

[0004] In a first aspect, an embodiment of the present application provides a method for reading and writing NAND Flash data, comprising: Receive a write request for raw data; Obtaining ECC check information according to the original data, and performing randomization processing on the ECC check information to obtain target data; Writing the target data into a NAND Flash page; Reading the data of the NAND Flash Page into an ECC decoding unit; The randomized seed corresponding to the ECC check information is input into the ECC decoding unit to obtain the original data.

[0005] According to some embodiments of the present application, obtaining ECC check information based on the original data, and performing randomization processing on the ECC check information to obtain target data includes: Performing randomization processing on the original data to obtain first data; Performing ECC encoding on the first data to obtain ECC check information; Randomizing the ECC check information to obtain second data; Target data is obtained according to the first data and the second data.

[0006] According to some embodiments of the present application, obtaining ECC check information according to the original data, and performing randomization processing on the ECC check information to obtain target data further includes: Performing ECC encoding on the original data to obtain ECC check information; The ECC check information and the original data are randomized to obtain target data.

[0007] According to some embodiments of the present application, inputting the randomized seed corresponding to the ECC check information into an ECC decoding unit to obtain original data includes: Inputting a randomized seed corresponding to the ECC check information into an ECC decoding unit; The original data is obtained by performing a judgment based on the LLR sign bit of the bit information of the ECC decoding unit.

[0008] According to some embodiments of the present application, inputting the randomized seed corresponding to the ECC check information into an ECC decoding unit to obtain original data includes: Inputting a randomized seed corresponding to the ECC check information into an ECC decoding unit; Obtain third data by determining the randomized seed and the LLR sign bit corresponding to the ECC check information; De-randomization is performed on the third data to obtain original data.

[0009] According to some embodiments of the present application, writing the target data into a NAND Flash page includes: Get the free page list of NAND Flash; Selecting a target page from the free page list according to a preset write strategy; Before writing the target data into the target page, performing an erasing operation on the target page; If the erasure is successful, the target data is written into the NAND Flash page according to the target page.

[0010] According to some embodiments of the present application, reading the data of the NAND Flash Page into an ECC decoding unit includes: Obtaining a read request for the original data; Acquire the corresponding NAND Flash page according to the storage address of the original data; Reading data of a target page in the NAND Flash page into an ECC decoding unit; Performing ECC decoding by the ECC decoding unit to obtain read data; The read data is verified using a CRC verification algorithm. If the verification fails, the data of the NAND Flash Page is reread.

[0011] According to some embodiments of the present application, determining by the randomization seed and the LLR sign bit corresponding to the ECC check information to obtain the third data includes: The LLR symbol whose randomization bit is the first numerical bit is flipped according to the randomization seed to obtain third data.

[0012] In a second aspect, an embodiment of the present application provides a computer device, including: at least one memory; at least one processor; at least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the NAND Flash data reading and writing method described in the first aspect.

[0013] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to enable a computer to execute the NAND Flash data reading and writing method described in the first aspect.

[0014] According to the technical solution of the embodiment of the present application, there are at least the following beneficial effects: first, a request to write original data is received; ECC check information is obtained based on the original data, and the ECC check information is randomized to obtain target data; the target data is written to a NAND Flash page; the data of the NAND Flash page is read into an ECC decoding unit, and a random seed corresponding to the ECC check information is input into the ECC decoding unit to obtain the original data. This embodiment improves the randomization level of data read and written to NAND Flash by randomizing the ECC check information, thereby improving the reliability of data read and written, and significantly enhancing the stability of the NAND Flash storage system.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0017] Figure 1 This is a flowchart of a method for reading and writing NAND Flash data provided by an embodiment of the present application; Figure 2 This is a schematic diagram of a process for obtaining target data provided by an embodiment of the present application; Figure 3 This is a schematic diagram of a process for obtaining target data provided by another embodiment of the present application; Figure 4 This is a schematic diagram of a process for obtaining original data provided by an embodiment of the present application; Figure 5 This is a schematic diagram of a process for obtaining original data provided by another embodiment of the present application; Figure 6 This is a flowchart of writing target data into a NAND Flash page according to an embodiment of the present application; Figure 7 This is a schematic diagram of a process for reading data from a NAND Flash Page provided by an embodiment of the present application; Figure 8 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0018] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0019] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0020] In the description of this application, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The terms "first" and "second" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly specifying the number or order of the technical features indicated.

[0021] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0022] First, let’s analyze some of the terms used in this application: Error Correction Code (ECC) decoding uses redundant information to detect and correct errors that occur during data transmission or storage. Redundant coding adds check bits (such as Hamming codes or Reed-Solomon codes) to the original data to create error-correctable codewords. Error detection and location calculates syndromes based on checksum relationships to locate errors. Error correction inverts or corrects erroneous bits based on the error's location and type.

[0023] LLR Sign Bit (Log-Likelihood Ratio Sign Bit): A binary flag used in communication systems to indicate the positive or negative value of the log-likelihood ratio (LLR).

[0024] NAND Flash (Non-Volatile Memory, NVM): Based on a floating-gate MOSFET structure, it stores charge for long-term data storage, eliminating the need for a continuous power supply. Its name comes from its NAND logic array circuit structure. It is widely used in solid-state drives (SSDs), USB flash drives, and mobile phone storage.

[0025] The method for reading and writing NAND Flash data provided in the embodiments of the present application is specifically described through the following embodiments.

[0026] The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Artificial Intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results.

[0027] Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interaction systems, and mechatronics. AI software technologies primarily encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0028] The method for reading and writing NAND Flash data provided in the embodiment of the present application relates to the field of data monitoring and extraction technology. The method for reading and writing NAND Flash data provided in the embodiment of the present application can be applied to a terminal, can be applied to a server side, and can also be run in software in a terminal or a server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; the server side can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers, or as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can implement the application of the method for reading and writing NAND Flash data, etc., but is not limited to the above forms.

[0029] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0030] It should be noted that in each specific embodiment of the present application, when it involves the need to perform relevant processing based on data related to the user's identity or characteristics, such as user information, user behavior data, user historical data, and user location information, the user's permission or consent will be obtained first, and the collection, use, and processing of such data will comply with relevant laws, regulations, and standards. In addition, when the embodiment of the present application needs to obtain the user's sensitive personal information, the user's separate permission or consent will be obtained through a pop-up window or by jumping to a confirmation page. After clearly obtaining the user's separate permission or consent, the necessary user-related data for the normal operation of the embodiment of the present application will be obtained.

[0031] See Figure 1 , Figure 1 This is a flow chart of a method for reading and writing NAND Flash data provided by an embodiment of the present application. The method for reading and writing NAND Flash data provided by an embodiment of the present application includes but is not limited to steps S110 to S150. Each step is introduced in turn below. Step S110: receiving a request to write original data; Step S120: Obtain ECC check information based on the original data, and perform randomization processing on the ECC check information to obtain target data; Step S130: writing the target data into the NAND Flash page; Step S140: Read the data of the NAND Flash Page into the ECC decoding unit; Step S150: Input the randomized seed corresponding to the ECC check information into the ECC decoding unit to obtain the original data.

[0032] In one embodiment, a host computer can send a request to write raw data to a storage controller via an interface such as PCIe, SATA, or USB. The request includes the raw data to be stored (such as user file data or system logs) and the data storage address. Upon receiving the request, the storage controller verifies its validity, including verifying that the data format complies with protocol specifications and that the storage address is unoccupied. Upon successful verification, the data processing flow begins.

[0033] In one embodiment, the storage controller integrates an ECC encoding unit. It first performs ECC encoding on the original data. The ECC check information is generated using internationally accepted BCH or LDPC encoding algorithms. During the encoding process, the check bit length is determined based on the length of the original data, enabling automatic correction of single-bit errors and detection of multi-bit errors. After generating the ECC check information, the storage controller invokes a randomization processing module to encrypt it. The storage controller also incorporates a built-in pseudo-random number generator that generates a unique random seed based on the original data's storage address, current timestamp, or hardware signature. The ECC check information is then bitwise XORed with the random seed to generate the randomized check information. The target data consists of the original data and the randomized check information concatenated in a "original data + randomized check information" format. The randomized check information starts at the end of the original data, facilitating quick separation during subsequent reading.

[0034] In one embodiment, NAND Flash memory uses a page as the basic write unit. Each page includes a data area and a spare area. In this embodiment, the target data is written to the data area. A storage controller sends a write command to the NAND Flash via a NAND interface (such as an ONFI protocol interface). The command includes the target page address and target data. During the write process, the storage controller performs level conversion on the target data (converting the digital signal into a voltage signal recognizable by the NAND Flash) and stores the data in the floating-gate transistor through charge injection. Simultaneously, a randomization seed is stored in the NAND Flash's OOB area or in a non-volatile register of the storage controller. This seed is mapped to the page address of the target data to ensure accurate access to the corresponding seed during subsequent reads. When the host sends a data read request, the storage controller locates the target NAND Flash page based on the address information in the request. Using a read command, the target data (including the original data and randomization check information) stored in that page is read into the storage controller's cache unit. During the read process, the storage controller performs analog-to-digital conversion on the voltage signal output by the NAND Flash to restore the target data to a digital signal. The cache unit separates the target data into original data segments and randomized check information according to a preset format, wherein the original data segments are directly temporarily stored, and the randomized check information is transmitted to the ECC decoding unit for processing. In one embodiment, the storage controller retrieves the corresponding randomization seed from the OOB area or register based on the target page address and inputs the seed into the ECC decoding unit. The decoding unit first performs derandomization on the randomized checksum information, using an exclusive-OR operation to restore the randomized checksum information and the seed to the original ECC checksum information (the inverse operation formula is "original checksum = randomized checksum ⊕ seed"). The ECC decoding unit then uses the original ECC checksum information to perform error correction on the original data segments. By comparing the redundancy between the data segments and the checksum information, errors occurring during data transmission or storage are detected and corrected. After error correction is complete, the decoding unit outputs the complete original data, which the storage controller feeds back to the host through an interface, completing the data read process. It is worth noting that this embodiment improves the randomness of data written to NAND Flash by randomizing ECC check information, improves the uniformity of charge distribution among NAND Flash cells, reduces crosstalk between cells, thereby improving the reliability of written data and significantly improving the stability of the NAND Flash storage system.

[0035] See Figure 2 , Figure 2 This is a flow chart of obtaining target data provided by an embodiment of the present application; regarding the above-mentioned step S120, ECC check information is obtained based on the original data, and the ECC check information is randomized to obtain the target data, including but not limited to steps S210 to S240. Each step is introduced in turn below. Step S210: performing randomization processing on the original data to obtain first data; Step S220: Perform ECC encoding on the first data to obtain ECC check information; Step S230: randomize the ECC check information to obtain second data; Step S240: Obtain target data according to the first data and the second data.

[0036] In one embodiment, randomization involves scrambling and transforming the original data using a preset randomization algorithm, resulting in a randomly distributed data. The randomization algorithm may employ a linear feedback shift register (LFSR) algorithm. First, the length and feedback coefficient of the LFSR are determined, and the LFSR state is initialized based on the length of the original data. Next, each bit of the original data is XORed with the bit output by the LFSR to obtain the first data after randomization. For example, if the original data is "101010" and the initial LFSR state is "110011," the first data after the XOR operation is "011001." This randomization process disrupts the regularity of the original data, reduces the likelihood of data being illegally parsed, and lays the foundation for subsequent encoding processing.

[0037] In one embodiment, the ECC encoding algorithm may be a Hamming code. Hamming code is a linear block code that can detect two errors and correct one error. For the first data, a corresponding check bit is calculated according to the encoding rules of the Hamming code. The check bit is added to the first data to form encoded data containing data bits and check bits. The check bit portion serves as the ECC check information. For example, if the first data is the 8-bit "01100101", and the 4-bit check bit "1011" is calculated according to the Hamming code encoding rules, the ECC check information is "1011". The length of the ECC check information is determined based on the length of the first data and the type of ECC encoding algorithm used to ensure effective detection and correction of errors that occur during the transmission and storage of the first data.

[0038] In one embodiment, step S230 utilizes the same LFSR algorithm as step S210, requiring the LFSR state to be reinitialized to avoid correlation with the randomization performed in step S210. The ECC check information is "1011," and the reinitialized LFSR state is "001101." After the XOR operation, the second data is "1000." Randomizing the ECC check information prevents the ECC check information from being independently stolen and exploited, thereby enhancing the security of the entire data processing process.

[0039] It should be noted that after obtaining the first data and the second data, the two are combined according to a preset combination rule to obtain the target data. The combination rule can be to splice the first data and the second data in sequence, or to mix and arrange the two using a preset mapping relationship. When splicing in sequence, the first data is "01100101" and the second data is "1000", then the target data is "011001011000". The target data combines the randomized original data and the randomized ECC check information, which not only retains the information of the original data, but also has the ability to detect and correct errors. At the same time, due to the two randomization processes, the confidentiality and anti-interference ability of the data are significantly improved.

[0040] See Figure 3 , Figure 3 This is a flowchart of obtaining target data provided by another embodiment of the present application; regarding the above-mentioned step S120, ECC check information is obtained based on the original data, and the ECC check information is randomized to obtain the target data, including but not limited to steps S310 to S320. Each step is introduced in turn below. Step S310: Perform ECC encoding on the original data to obtain ECC check information; Step S320: randomize the ECC check information and the original data to obtain target data.

[0041] In one embodiment, during the encoding process, the original data is divided into data blocks of a predetermined length. Each data block is 255 bytes long, of which 223 bytes are valid data and 32 bytes are ECC checksum information. For example, the original data block is "00101101...11001010" (223 bytes). After Reed-Solomon encoding, the 32-byte ECC checksum information "10010011...01101100" is generated. This ECC checksum information is mathematically correlated with the original data block, allowing data integrity to be verified using a checksum formula.

[0042] In one embodiment, 1024 bytes of original data are divided into four data blocks (each containing 256 bytes, including 224 bytes of valid data). A Reed-Solomon (255, 223) encoding scheme is used, generating 32 bytes of ECC check information for each data block, for a total of 128 bytes of ECC check information. The four original data blocks and the corresponding ECC check information are sequentially concatenated to form combined data with a total length of 1024 + 128 = 1152 bytes. The AES encryption module is initialized using a preset key, a random initialization vector is generated, and the combined data is encrypted using CBC mode to produce 1152 bytes of target data.

[0043] See Figure 4 , Figure 4 This is a flow chart of obtaining original data provided by an embodiment of the present application; regarding the above-mentioned step S150, the random seed corresponding to the ECC check information is input into the ECC decoding unit to obtain the original data, including but not limited to steps S410 to S420, and each step is introduced in turn below. Step S410: inputting the randomized seed corresponding to the ECC check information into the ECC decoding unit; Step S420: Determine the LLR sign bit of the bit information of the ECC decoding unit to obtain the original data.

[0044] In one embodiment, after the target data is transmitted to the receiving end or read from the storage medium, the randomization seed corresponding to the ECC check information needs to be extracted from the target data. The extraction process can be achieved by parsing the header information of the target data. The header of the target data has a dedicated field reserved for storing the randomization seed. The extracted randomization seed is input into the ECC decoding unit. The ECC decoding unit derandomizes the received randomized ECC check information based on the randomization seed to restore the original ECC check information, providing an accurate verification basis for subsequent ECC decoding.

[0045] In one embodiment, after receiving the derandomized ECC check information and the corresponding data to be decoded, the ECC decoding unit performs soft-decision decoding on the data. The LLR sign bit indicates the probability of each bit being "0" or "1" and directly reflects the decision direction of the bit information. The ECC decoding unit calculates the LLR value for each bit information. The LLR value calculation formula is LLR = ln (P (bit = 1|r) / P (bit = 0|r)), where r is the received bit information. When the LLR sign bit is positive, the bit information is "0"; when the LLR sign bit is negative, the bit information is "1". During the decoding process, the ECC decoding unit combines the ECC check information to make a comprehensive judgment on the LLR sign bit. For erroneous bits, the redundant check bits of the ECC check information are used to perform error correction adjustments, ultimately recovering the accurate original data.

[0046] See Figure 5 , Figure 5 This is a flowchart of obtaining original data provided by another embodiment of the present application; regarding the above-mentioned step S150, the random seed corresponding to the ECC check information is input into the ECC decoding unit to obtain the original data, including but not limited to steps S510 to S520, and each step is introduced in turn below. Step S510: inputting the randomized seed corresponding to the ECC check information into the ECC decoding unit; Step S520: determine the LLR sign bit corresponding to the random seed and the ECC check information to obtain third data; Step S530: De-randomize the third data to obtain original data.

[0047] In one embodiment, the LLR sign of the first numerical bit of the randomization bit is flipped according to the randomization seed to obtain the third data. The LLR sign of the bit where the XOR bit (randomization bit) is 1 is flipped, that is, positive to negative and negative to positive. Before LDPC decoding, the ECC check information is pre-processed by "de-randomization". However, within the LDPC unit, this is manifested as the logical operation of performing LLR sign bit determination and flipping using the randomization information. After completing the above-mentioned LLR sign bit processing, conventional LDPC decoding (including hard decoding and soft decoding processes) is performed to obtain the third data. Afterwards, the third data is de-randomized to ultimately obtain the original data.

[0048] In one embodiment, a decision module based on randomization information is constructed within the LDPC decoding unit. This module traverses the LLR data of the ECC parity information and examines the value of the XOR bit (randomization bit) bit by bit. When the XOR bit is detected as 1, the sign flip logic is triggered, changing the LLR sign of that bit from positive to negative or vice versa. If the XOR bit is 0, the LLR sign remains unchanged. This is integrated with the LDPC decoding process: after the LLR sign bit is processed, the processed data enters the LDPC hard and soft decoding processes. The hard decoding stage uses the processed LLR information to perform preliminary error correction decisions. The soft decoding stage uses this information to perform more refined probabilistic iterative updates, gradually approaching the correct data, and ultimately outputting the decoded third data. After obtaining the third data, the randomization information is used to perform a derandomization operation on the third data according to a pre-defined derandomization algorithm in the storage system. If randomization is achieved through a specific XOR operation during writing, de-randomization is restored through an inverse XOR operation, ultimately obtaining the original main area data for upper-layer applications or storage systems to call, completing the entire process of reading data from NAND Flash and correcting errors to restore the original data.

[0049] In one embodiment, when an abnormal situation occurs such as failure to read randomized information or a sign bit flip logic error, a default processing strategy can be set for the failure to read randomized information. For the sign bit flip logic error, a self-detection module is built into the decoding unit to verify the logical consistency of the data before and after the sign bit processing in real time. If an abnormality is found, a retry or error reporting mechanism is triggered. To ensure the effectiveness of the processing flow, a verification module is constructed in the storage system. By writing known test data, a bit flip scenario is simulated to verify the accuracy of data recovery after logical processing by the LDPC decoding unit. The data recovery results in the actual storage business are sampled and verified regularly, and the consistency of the original written data and the recovered data is compared. The processing logic is continuously optimized to ensure the long-term stable and reliable operation of the system.

[0050] It should be noted that the ECC check information is also randomized, which improves the randomness of the data written to the NAND Flash and thus improves the reliability of the written data.

[0051] Table 1 shows the bit flipping of data after it is read from NAND Flash:

[0052] Table 1 When data is read from NAND Flash without bit flipping, the data table after derandomization is shown in Table 2:

[0053] Table 2 See Figure 6 , Figure 6 This is a flowchart of writing target data into a NAND Flash page according to an embodiment of the present application. The step S130 of writing the target data into the NAND Flash page includes but is not limited to steps S610 to S640, and each step is introduced in turn below. Step S610: Obtain a list of free pages of NAND Flash; Step S620: Select a target page from the free page list according to a preset write strategy; Step S630: before writing the target data into the target page, perform an erase operation on the target page; Step S640: If the erasure is successful, write the target data into the NAND Flash page according to the target page.

[0054] In one embodiment, the page management module of a NAND flash controller monitors the status of each page in real time and generates a free page list. This list contains information on multiple free pages, including block 10-page 20 (85 erase / write cycles), block 15-page 10 (70 erase / write cycles), and block 20-page 5 (100 erase / write cycles). Using a wear-leveling strategy, the average erase / write cycles for each block are calculated. Block 15 has the lowest average erase / write cycle, at 70. Therefore, page 10 is selected as the target page among the free pages in block 15. An erase command is sent to block 15, erasing the block containing page 10. After 500 microseconds, the status register indicates that the erase is complete and error-free, indicating a successful erase. The processed target data is then transferred to the page buffer register, and a programming command and the address of page 10 are sent to write the data to page 10. After the write is complete, the controller reads the data from page 10 for an ECC check. If the check result is correct, the data write is complete. During subsequent data writes, the free page list is dynamically updated, and the write strategy is automatically adjusted based on the device's operating status.

[0055] It is worth noting that the wear leveling strategy selects the target page, making the erase and write times of each storage block more evenly distributed, avoiding premature damage of some blocks due to excessive erase and write, and significantly extending the service life of the NAND Flash. The target page is erased before data is written, and data is written only after the erase is successful, ensuring that the target page is in a clean initial state and reducing data write errors caused by incomplete erasure.

[0056] See Figure 7 , Figure 7 This is a flowchart of reading data from a NAND Flash Page provided by an embodiment of the present application; regarding the above-mentioned step S140 of reading the data from the NAND Flash Page into the ECC decoding unit, including but not limited to steps S710 to S750, each step is introduced in turn below. Step S710: Obtain a read request for original data; Step S720: Obtain the corresponding NAND Flash page according to the storage address of the original data; Step S730: Read the data of the target page in the NAND Flash page into the ECC decoding unit; Step S740: performing ECC decoding by the ECC decoding unit to obtain read data; Step S750: Use a CRC check algorithm to check the read data. If the check fails, re-read the data of the NAND Flash Page.

[0057] In one embodiment, when raw data stored in NAND Flash is needed, a read request for the raw data is sent to a data read control module. This read request includes relevant identification information of the raw data to be read, such as the data name and serial number, so that the data read control module can accurately identify the data to be read. Upon receiving the read request, the data read control module locates the storage address of the raw data in NAND Flash based on a pre-stored correspondence between raw data and storage addresses. Since NAND Flash data is stored in pages as the basic storage unit, the found storage address can be used to determine the corresponding NAND Flash page, which is the storage unit storing the target raw data. After determining the corresponding NAND Flash page, the data read control module controls the NAND Flash read circuit to read the data from the target page in the NAND Flash page. The read data is then transmitted to an ECC decoding unit, which performs subsequent error detection and correction on the data. Upon receiving the read data, the ECC decoding unit first verifies the data using a checksum algorithm. The verification algorithm performs polynomial operations on the data to generate a checksum. This checksum is then compared with the original checksum generated during data storage. If the two match, the data was read without errors, the verification succeeded, and the data can be output normally for subsequent use. If the two do not match, an error occurred during the data read and the verification failed. At this point, the data read control module instructs the read circuit to reread the data from the NAND Flash page and transmit it to the ECC decoding unit for verification. If the data still fails after multiple rereads and verifications, an error message is issued.

[0058] The present application also provides a computer device comprising: at least one memory, at least one processor, and at least one computer program, wherein the at least one computer program is stored in the at least one memory and the at least one processor executes the at least one computer program to implement any of the NAND Flash data reading and writing methods described in the above embodiments. The computer device can be any intelligent terminal, such as a tablet computer or an in-vehicle computer.

[0059] See also Figure 8 , Figure 8This is a hardware structure diagram of a computer device provided in one embodiment of the present application, which includes: The processor 810 may be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application. The memory 820 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 820 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 820, and the processor 810 calls and executes the NAND Flash data reading and writing method of the embodiments of this application; Input / output interface 830, used to implement information input and output; Communication interface 840, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.); bus 850 , which transmits information between the various components of the device (e.g., processor 810 , memory 820 , input / output interface 830 , and communication interface 840 ); The processor 810 , the memory 820 , the input / output interface 830 and the communication interface 840 are connected to each other in communication within the device via a bus 850 .

[0060] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned NAND Flash data reading and writing method is implemented.

[0061] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0062] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0063] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0064] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0065] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0066] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0067] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0069] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0070] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0071] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0072] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A method for reading and writing NAND Flash data, characterized in that: include: Receive a write request for raw data; Obtaining ECC check information according to the original data, and performing randomization processing on the ECC check information to obtain target data; Writing the target data into a NAND Flash page; Reading the data of the NAND Flash Page into an ECC decoding unit; The randomized seed corresponding to the ECC check information is input into the ECC decoding unit to obtain the original data.

2. The method according to claim 1, characterized in that The step of obtaining ECC check information according to the original data and performing random processing on the ECC check information to obtain target data includes: Performing randomization processing on the original data to obtain first data; Performing ECC encoding on the first data to obtain ECC check information; Randomizing the ECC check information to obtain second data; Target data is obtained according to the first data and the second data.

3. The method according to claim 1, characterized in that The step of obtaining ECC check information according to the original data and performing randomization processing on the ECC check information to obtain target data further includes: Performing ECC encoding on the original data to obtain ECC check information; The ECC check information and the original data are randomized to obtain target data.

4. The method according to claim 1, wherein The step of inputting the randomized seed corresponding to the ECC check information into an ECC decoding unit to obtain original data includes: Inputting a randomized seed corresponding to the ECC check information into an ECC decoding unit; The original data is obtained by performing a judgment based on the LLR sign bit of the bit information of the ECC decoding unit.

5. The method according to claim 1, characterized in that The step of inputting the randomized seed corresponding to the ECC check information into an ECC decoding unit to obtain original data includes: Inputting a randomized seed corresponding to the ECC check information into an ECC decoding unit; Obtain third data by determining the randomized seed and the LLR sign bit corresponding to the ECC check information; De-randomization is performed on the third data to obtain original data.

6. The method according to claim 1, characterized in that Writing the target data into a NAND Flashpage includes: Get the free page list of NAND Flash; Selecting a target page from the free page list according to a preset write strategy; Before writing the target data into the target page, performing an erasing operation on the target page; If the erasure is successful, the target data is written into the NAND Flash page according to the target page.

7. The method according to claim 1, characterized in that The step of reading the data of the NAND Flash Page into an ECC decoding unit includes: Obtaining a read request for the original data; Acquire the corresponding NAND Flash page according to the storage address of the original data; Reading data of a target page in the NAND Flash page into an ECC decoding unit; Performing ECC decoding by the ECC decoding unit to obtain read data; The read data is verified using a CRC verification algorithm. If the verification fails, the data of the NAND Flash Page is read again.

8. The method according to claim 5, characterized in that The determining by using the randomization seed and the LLR sign bit corresponding to the ECC check information to obtain the third data includes: The LLR symbol whose randomization bit is the first numerical bit is flipped according to the randomization seed to obtain third data.

9. A computer device, characterized in that: include: at least one memory; at least one processor; at least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is configured to cause a computer to execute the method according to any one of claims 1 to 8.

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