Data processing unit, device and method, electronic equipment and storage medium

Abstract

The invention provides a data processing unit, and relates to the technical field of artificial intelligence, in particular to the technical field of chips, the technical field of high-performance computing and the technical field of vector processors. According to the specific implementation scheme, a parameter register is configured to store parameter data; the first arithmetic logic module is configured to respond to the received calculation control signal and execute operation corresponding to the calculation control signal on the first input data and first to-be-processed data to obtain a first calculation result, and the first to-be-processed data is second input data or parameter data related to the calculation control signal; the second arithmetic logic module is configured to respond to the received calculation control signal and execute operation corresponding to the calculation control signal on second to-be-processed data and the parameter data to obtain a second calculation result, and the second to-be-processed data is the second input data or the first calculation result. The invention further provides a data processing device and method, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the fields of artificial intelligence technology, particularly to the fields of chip technology, high-performance computing technology, and vector processor technology. More specifically, the present disclosure provides a data processing unit, apparatus, method, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence and high-performance computing technologies, the demand for processor computing power is increasing. Artificial intelligence chips can include scalar computing units and vector computing units. Vector computing units can increase the degree of parallelism in calculations to improve computing power. Summary of the Invention

[0003] The present disclosure provides a data processing unit, apparatus, method, device, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing unit is provided, which includes: a parameter register configured to store parameter data; a first arithmetic logic module configured to: in response to receiving a calculation control signal, perform an operation corresponding to the calculation control signal on first input data and first data to be processed, to obtain a first calculation result, wherein the first data to be processed is second input data or parameter data related to the calculation control signal; and a second arithmetic logic module configured to: in response to receiving a calculation control signal, perform an operation corresponding to the calculation control signal on second data to be processed and parameter data, to obtain a second calculation result, wherein the second data to be processed is the second input data or the first calculation result.

[0005] According to another aspect of the present disclosure, a data processing device is provided, which includes: an instruction fetch unit configured to obtain an instruction to be processed; a decoding unit configured to decode the instruction to be processed and obtain a decoding result; a control unit configured to generate a plurality of control signals according to the decoding result, wherein the plurality of control signals include a calculation control signal; and at least one data processing unit provided by the present disclosure is configured to process first input data and second input data corresponding to the instruction to be processed based on the calculation control signal.

[0006] According to another aspect of the present disclosure, an electronic device is provided, including the data processing device provided by the present disclosure.

[0007] According to another aspect of the present disclosure, a data processing method is provided, the method comprising: in response to receiving a calculation control signal, performing an operation corresponding to the calculation control signal on first input data and first data to be processed to obtain a first calculation result, wherein the first data to be processed is second input data or parameter data related to the calculation control signal; and in response to receiving a calculation control signal, performing an operation corresponding to the calculation control signal on second data to be processed and parameter data to obtain a second calculation result, wherein the second data to be processed is second input data or the first calculation result.

[0008] According to another aspect of the present disclosure, a data processing method is provided, which includes: obtaining an instruction to be processed; decoding the instruction to be processed to obtain a decoding result; generating multiple control signals based on the decoding result, wherein the multiple control signals include a calculation control signal; based on the calculation control signal, using the method provided by the present disclosure to process first input data and second input data corresponding to the instruction to be processed.

[0009] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method provided according to the present disclosure.

[0010] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0011] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the method provided according to the present disclosure when executed by a processor.

[0012] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0014] Figure 1 is a schematic block diagram of a data processing unit according to an embodiment of the present disclosure;

[0015] Figure 2 is a schematic diagram of a data processing unit according to an embodiment of the present disclosure;

[0016] Figure 3is a schematic diagram of a data processing unit according to another embodiment of the present disclosure;

[0017] Figure 4 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure;

[0018] Figure 5 is a schematic diagram of a data processing device according to an embodiment of the present disclosure;

[0019] Figure 6 is a schematic diagram of an electronic device according to one embodiment of the present disclosure;

[0020] Figure 7 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure;

[0021] Figure 8 is a schematic flow chart of a data processing method according to an embodiment of the present disclosure; and

[0022] Figure 9 is a block diagram of an electronic device to which a data processing method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION

[0023] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] The artificial intelligence chip may be, for example, a processor chip based on an application specific integrated circuit (ASIC), which may execute dual-input vector calculation instructions and single-input vector calculation instructions.

[0025] In the disclosed embodiment, the dual input vector calculation includes performing various operations on the two input vectors and parameter data. For example, the following addition operation can be performed on the two input vectors:

[0026] F=X+Y+A (Formula 1)

[0027] X can be the first input vector. Y can be the second input vector. A can be parameter data. F can be the output vector. It will be appreciated that the parameter data can be either a parameter scalar or a parameter vector. The first input vector and the second input vector can have the same length. The elements at corresponding positions in the two input vectors are added together to produce an addition result. This addition result is then added to the parameter data to produce the output vector.

[0028] As another example, the following multiplication operation can be performed on two input vectors:

[0029] F=X×Y×A (Formula 2)

[0030] In the disclosed embodiment, single input vector calculation includes: performing various operations on the input vector and parameter data. For example, the following addition operation can be performed on the single input vector:

[0031] F=X+A (Formula 3)

[0032] X may be the first input vector. Y may be the second input vector. A may be parameter data. F may be the output vector. It will be appreciated that if the parameter data is a parameter scalar, the parameter scalar may be added to each element of the first input vector. If the parameter data is a parameter vector, the length of the parameter vector may be the same as that of the first input vector. The parameter vector is added to the elements at corresponding positions in the first input vector to generate the output vector.

[0033] As another example, the following multiplication operation can be performed on the input vector and the parameter data:

[0034] F=X×A (Formula 4)

[0035] For some high-performance vector processing units, based on the parallelism P of computing resources, P input data of length L can be processed separately. That is, for the high-performance vector processing unit, the scale of the input vector can be L×P.

[0036] In addition, the amount of data processed by artificial intelligence chips is large and the data format is regular. However, for the vector processing unit, in order to execute the instructions to be processed, P operations can be performed based on the above-mentioned parallelism P. For each operation, the source operands required by the vector processing unit can be obtained from the corresponding vector registers, and the results of the operation can also be written back to the corresponding vector registers. For example, for dual-input vector calculations, two input vectors can be read from the storage unit and stored in two sets of registers. Next, the operation can be completed based on these two sets of registers. For another example, for single-input vector calculations, an input vector can be read from the storage unit and stored in a set of registers. Next, the calculation can be completed based on this set of registers.

[0037] For high-performance vector processing units that use coarse-grained vector calculation instructions, when performing dual-input vector operations, the vector can be read in continuously multiple times, with two sub-vectors of a preset length read in each time. When performing single-input vector operations, the vector can also be read in continuously multiple times. During each read, a sub-vector of a preset length and a parameter vector can be read in, or a parameter vector of a preset length can be read in first and then multiple sub-vectors of a preset length can be read in continuously. As a result, the computational throughput of the vector processing unit is the same when performing dual-input vector calculations and single-input vector calculations respectively, resulting in insufficient bandwidth for dual-input vector calculations or wasted bandwidth for single-input vector calculations, affecting computational efficiency.

[0038] Therefore, in order to improve the computing efficiency of artificial intelligence chips, the present disclosure provides a data operation unit, which will be described below.

[0039] Figure 1 is a schematic block diagram of a data processing unit according to an embodiment of the present disclosure.

[0040] like Figure 1 As shown, the data processing unit 10 may include a parameter register 100 , a first arithmetic logic module 101 and a second arithmetic logic module 102 .

[0041] The parameter register 100 can be configured to store parameter data. For example, the parameter data can be a parameter scalar or a parameter vector. For another example, the parameter data can be the parameter data A described above.

[0042] The first arithmetic logic module 101 may be configured to: in response to receiving a calculation control signal, perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed to obtain a first calculation result.

[0043] In the embodiment of the present disclosure, the instruction to be processed corresponding to the calculation control signal may be one of a dual-input vector calculation instruction and a single-input vector calculation instruction.

[0044] In the embodiment of the present disclosure, the operation corresponding to the calculation control signal may be various operations such as addition operation, multiplication operation, multiplication-addition operation, subtraction operation, and division operation.

[0045] In the disclosed embodiments, the first data to be processed may be second input data or parameter data associated with the computation control signal. For example, if the corresponding instruction to be processed is a dual-input vector computation instruction, the first data to be processed may be the second input data. For another example, if the corresponding instruction to be processed is a single-input vector computation instruction, the first data to be processed may be parameter data.

[0046] The second arithmetic logic module 102 may be configured to, in response to receiving a calculation control signal, perform an operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain a second calculation result.

[0047] In the disclosed embodiment, the second data to be processed may be the second input data or the first calculation result. For example, if the corresponding instruction to be processed is a dual-input vector calculation instruction, the second data to be processed may be the first calculation result. For another example, if the corresponding instruction to be processed is a single-input vector calculation instruction, the second data to be processed may be parameter data.

[0048] Through the disclosed embodiments, the data processing unit can process both dual-input vector calculation instructions and single-input vector instructions. When processing a single-input vector calculation instruction, if the input data is the same size as the input data of the dual-input vector calculation instruction and the parameter data is located in the parameter register of the data processing unit, the data processing unit can efficiently process the single-input vector calculation instruction, with a calculation throughput nearly twice that of processing a dual-input vector, significantly improving calculation efficiency.

[0049] It is understood that the above description of the data processing unit of the present disclosure is based on the parameter register and the arithmetic logic module. The data processing unit of the present disclosure may also include a control module, which will be described below.

[0050] In some embodiments, the control module may be configured to send a read request to a target read port of the data storage unit in response to receiving the read control signal.

[0051] In the disclosed embodiment, the target read port can be one of at least two corresponding read ports. The corresponding read port corresponds to a data processing unit. For example, if there are M data processing units, the corresponding read ports of the data storage unit can be 2M or more. Each data processing unit corresponds to at least two corresponding read ports.

[0052] In some embodiments, the control module may be further configured to receive at least one of first input data and second input data corresponding to the read request. For example, the data storage unit may provide the input data to the control module in response to receiving the read request. The control module may receive the input data.

[0053] In some embodiments, the control module may be further configured to: in response to receiving the write control signal, send a write request to a target write port of the data storage unit.

[0054] In the disclosed embodiment, the target write port is one of at least two corresponding write ports. The corresponding write port corresponds to a data processing unit. For example, if the number of data processing units is M, the corresponding write ports of the data storage unit may be 2M or more. Each data processing unit corresponds to at least two corresponding write ports. Through the disclosed embodiment, setting corresponding read ports and corresponding write ports for the data processing units helps improve the accuracy and efficiency of data transmission, so that input data can be accurately acquired by the corresponding data processing unit.

[0055] It can be understood that the control module of the present disclosure is described above, and the data processing unit of the present disclosure will be further described below in conjunction with a single input vector calculation instruction.

[0056] Figure 2 is a schematic diagram of a data processing unit according to an embodiment of the present disclosure.

[0057] like Figure 2 As shown, the data processing unit 20 may include a parameter register 200 , a first arithmetic logic module 201 , a second arithmetic logic module 202 and a control module 203 .

[0058] In some embodiments, the read control signal may include a first read control signal and a second read control signal, the target read port may include a first target read port and a second target read port, and the read request may include a first read request and a second read request.

[0059] In some embodiments, the control module may be further configured to perform the following operations to send a read request to a target read port of the data storage unit: in response to receiving a first read control signal, send a first read request to a first target read port of the data storage unit; and in response to receiving a second read control signal, send a second read request to a second target read port of the data storage unit.

[0060] In an embodiment of the present disclosure, the first target read port may be one of the at least two corresponding read ports. The second target read port may be a read port other than the first target read port of the at least two corresponding read ports. For example, the data storage unit includes multiple read ports. The multiple read ports include two corresponding read ports corresponding to the data processing unit 20. These two corresponding read ports may serve as the first target read port and the second target read port, respectively.

[0061] In an embodiment of the present disclosure, a first read request corresponds to a first address space to be read in a data storage unit, and the first address space to be read corresponds to a first read control signal. A second read request corresponds to a second address space to be read in a data storage unit, and the second address space to be read corresponds to a second read control signal, and the second address space to be read is adjacent to the first address space to be read. For example, for a single-input vector calculation instruction, two consecutive address spaces can be determined based on a base address corresponding to a source operand and an offset of the data to be processed, respectively serving as the first address space to be read and the second address space to be read. A control unit associated with the data processing unit 20 can provide the first read control signal, the first address space to be read, the second read control signal, and the second address space to be read to the control module 203 of the data processing unit 20. Thus, the control module 203 can send a first read request to the first target read port to read the first input data from the first address space to be read. The control module 203 can also send a second read request to the second target read port to read the second input data from the second address space to be read.

[0062] In an embodiment of the present disclosure, the first input data and the second input data are from the same input data set. For example, the input data set may correspond to an input vector. The first input data and the second input data may be consecutive subvectors of the input vector, each having a predetermined length.

[0063] In some embodiments, the control module may be further configured to receive first input data corresponding to the first read request and second input data corresponding to the second read request. For example, the control module 203 may receive input data x201 and input data x202. The input data x201 may be the first input data, and the input data x202 may be the second input data.

[0064] In some embodiments, the calculation control signal may include a calculation enable signal. The control module may be configured to: in response to receiving the calculation enable signal, control the first arithmetic logic module and the second arithmetic logic module to switch to a calculation mode. Figure 2 As shown, in the case where the computing enable signal is not received, the data processing unit 20 may be in a sleep mode or a standby mode. After receiving the computing enable signal, the data processing unit 20 may enter a computing mode to process input data and output computing results.

[0065] In some embodiments, the calculation control signal may further include a first calculation type indication signal. For example, the first calculation type indication signal may indicate that the calculation type is consistent with a single-input vector calculation instruction.

[0066] In some embodiments, the control module may be further configured to provide the first input data to the first arithmetic logic module and the second input data to the second arithmetic logic module based on the first calculation type indication signal. For example, the control module 203 may provide the input data x201 to the first arithmetic logic module 201. The control module 203 may also provide the input data x202 to the second arithmetic logic module 202.

[0067] It can be understood that the control module of the present disclosure is described above in conjunction with a single-input vector calculation instruction, and the arithmetic logic module of the present disclosure will be described below in conjunction with a single-input vector calculation instruction.

[0068] In some embodiments, the first arithmetic logic module may be further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed, thereby obtaining a first calculation result: in response to receiving the first calculation type indication signal, receiving the first input data and obtaining parameter data. For example, the first arithmetic logic module 201 may receive input data x201 or read parameter data A200 from a parameter register.

[0069] In some embodiments, the first arithmetic logic module may be further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed, thereby obtaining a first calculation result: performing an operation corresponding to the first calculation type indication signal on the first input data and the parameter data, thereby obtaining a first calculation result. For example, the operation corresponding to the first calculation type indication signal may correspond to Formula 3 or Formula 4 described above. For another example, taking the single-input vector calculation instruction as a single-input vector addition instruction, the input data x201 and the parameter data A200 may be added to obtain a calculation result f201. It will be understood that the calculation result f201 may serve as the first calculation result.

[0070] In some embodiments, the second arithmetic logic module may be further configured to perform the following operations to perform the operation corresponding to the calculation control signal on the second to-be-processed data and the parameter data to obtain a second calculation result: in response to receiving the first calculation type indication signal, receive the second input data and obtain the parameter data. For example, the second arithmetic logic module 202 may receive input data x202 or read parameter data A200 from the parameter register.

[0071] In some embodiments, the second arithmetic logic module may be further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain a second calculation result: performing an operation corresponding to the first calculation type indication signal on the second input data and the parameter data to obtain a second calculation result. For example, the operation corresponding to the first calculation type indication signal may correspond to Formula 3 or Formula 4 described above. For another example, assuming that the single-input vector calculation instruction is a single-input vector add instruction, the input data x202 and the parameter data A200 may be added to obtain a calculation result f202. It will be understood that the calculation result f202 may serve as the second calculation result.

[0072] It is understood that the arithmetic logic unit of the present disclosure is described above in conjunction with single-input vector calculation instructions. The following describes some ways of writing back calculation results in conjunction with single-input vector calculation instructions.

[0073] In some embodiments, the write control signal may include a first write control signal and a second write control signal, the target write port may include a first target write port and a second target write port, and the write request may include a first write request and a second write request.

[0074] In some embodiments, the control module may be further configured to perform the following operations to send a write request to a target write port of the data storage unit: in response to receiving a first write control signal, send a first write request to a first target write port of the data storage unit; and in response to receiving a second write control signal, send a second write request to a second target write port of the data storage unit.

[0075] In an embodiment of the present disclosure, the first target write port may be one of the at least two corresponding write ports. The second target write port may be a write port other than the first target write port of the at least two corresponding write ports. For example, the data storage unit includes multiple write ports. The multiple write ports include two corresponding write ports corresponding to the data processing unit 20. These two corresponding write ports serve as the first target write port and the second target write port, respectively.

[0076] In the embodiment of the present disclosure, the first write control signal corresponds to the first address space to be written. The second write control signal corresponds to the second address space to be written, and the second address space to be written is adjacent to the first address space to be written. For example, for a single-input vector calculation instruction, two consecutive address spaces can be determined based on the base address corresponding to a destination operand and the offset of the data to be written, respectively serving as the first address space to be written and the second address space to be written. The control unit associated with the data processing unit 20 can provide the first write control signal, the first address space to be written, the second write control signal, and the second address space to be written to the control module 203 of the data processing unit 20. Thus, the control module 203 can send a first write request to the first target write port to write the calculation result f201 to the first address space to be written. The control module 203 can also send a second write request to the second target write port to write the calculation result f202 from the second address space to be written.

[0077] In the embodiment of the present disclosure, the first calculation result is written into the first address space to be written, and the second calculation result is written into the second address space to be written. For example, the control module 203 can write the first calculation result and the second calculation result into the first address space to be written and the second address space to be written, respectively. For another example, the first arithmetic logic module 201 can write the first calculation result into the first address space to be written. The second arithmetic logic module 202 can write the second calculation result into the second address space to be written. Thus, a calculation for a single input vector calculation instruction is completed. Next, under the control of the read control signal, the calculation control signal, and the write control signal, the data processing unit can read the two consecutive sub-vectors after the input data x202, perform calculations, and write back the corresponding calculation results.

[0078] It is understood that the above description of the data processing unit of the present disclosure is based on a single-input vector calculation instruction. The following description of the data processing unit of the present disclosure is based on a dual-input vector calculation instruction.

[0079] Figure 3 is a schematic diagram of a data processing unit according to another embodiment of the present disclosure.

[0080] like Figure 3 As shown, the data processing unit 30 may include a parameter register 300 , a first arithmetic logic module 301 , a second arithmetic logic module 302 and a control module 303 .

[0081] In some embodiments, a dual-input vector computation instruction may correspond to a first input vector and a second input vector. The first input vector may correspond to a first input data set. The first input data set may be stored in a first continuous address space of a data storage unit. The second input vector may correspond to a second input data set. The second input data set may be stored in a second continuous address space of the data storage unit. The first continuous address space and the second continuous address space may be adjacent or non-adjacent.

[0082] In some embodiments, the read control signal may include a third read control signal and a fourth read control signal, the target read port may include a first target read port and a second target read port, and the read request may include a third read request and a fourth read request.

[0083] In some embodiments, the control module is further configured to perform the following operations to send a read request to a target read port of the data storage unit: in response to receiving a third read control signal, send a third read request to a first target read port of the data storage unit; and in response to receiving a fourth read control signal, send a fourth read request to a second target read port of the data storage unit.

[0084] In the disclosed embodiment, the first target read port is one of the at least two corresponding read ports. The second target read port is a read port other than the first target read port of the at least two corresponding read ports. For example, the data storage unit 30 includes multiple read ports. The multiple read ports include two corresponding read ports corresponding to the data processing unit 30. These two corresponding read ports serve as the first target read port and the second target read port, respectively. It will be understood that the above description regarding the data processing unit 20 also applies to the data processing unit 30. The at least two corresponding read ports corresponding to the data processing unit 20 described above can be at least two corresponding read ports of the data processing unit 30.

[0085] In the disclosed embodiment, the third read request corresponds to a third address space to be read in the data storage unit. The third address space to be read corresponds to a third read control signal. The fourth read request corresponds to a fourth address space to be read in the data storage unit. The fourth address space to be read corresponds to a fourth read control signal. The third address space to be read is from the first continuous address space. The fourth address space to be read is from the second continuous address space. For example, for a dual-input vector computation instruction, an address space can be determined as the third address space to be read based on the base address corresponding to one source operand and the offset of the data to be processed. An address space can be determined as the fourth address space to be read based on the base address corresponding to another source operand and the offset of the data to be processed. A control unit associated with the data processing unit 30 can provide the third read control signal, the third address space to be read, the fourth read control signal, and the fourth address space to be read to the control module 303 of the data processing unit 30. Consequently, the control module 303 can send a third read request to the first target read port to read input data from the third address space to be read. The control module 303 may also send a fourth read request to the second target read port to read input data from a fourth to-be-read address space.

[0086] In an embodiment of the present disclosure, the first input data and the second input data are from a first input dataset and a second input dataset, respectively. For example, the input dataset may correspond to an input vector. The first input data may be a subvector of the first input vector. The second input data may be a subvector of the second input vector.

[0087] In some embodiments, the control module may be further configured to receive first input data corresponding to the third read request and second input data corresponding to the fourth read request. For example, the control module 303 may receive input data x300 and input data y300. Input data x300 may be the first input data, and input data y300 may be the second input data.

[0088] In some embodiments, the calculation control signal may include a calculation enable signal. The control module may be configured to: in response to receiving the calculation enable signal, control the first arithmetic logic module and the second arithmetic logic module to switch to a calculation mode. Figure 3 As shown, in the case where the computing enable signal is not received, the data processing unit 30 may be in a sleep mode or a standby mode. After receiving the computing enable signal, the data processing unit 30 may enter a computing mode to process input data and output computing results.

[0089] In some embodiments, the calculation control signal may further include a second calculation type indication signal. For example, the second calculation type indication signal may indicate that the calculation type is consistent with a dual-input vector calculation instruction.

[0090] In some embodiments, the control module may be further configured to provide the first input data and the second input data to the first arithmetic logic module based on the second calculation type control signal. For example, the control module 303 may provide the input data x300 to the first arithmetic logic module 301. The control module 303 may also provide the input data y300 to the first arithmetic logic module 301.

[0091] It can be understood that the control module of the present disclosure is described above in conjunction with the dual-input vector calculation instruction, and the arithmetic logic module of the present disclosure will be described below in conjunction with the dual-input vector calculation instruction.

[0092] In some embodiments, the first arithmetic logic module may be further configured to perform the following operations to perform the operation corresponding to the calculation control signal on the first input data and the first data to be processed, thereby obtaining a first calculation result: in response to receiving the second calculation type indication signal, receiving the first input data and the second input data. For example, the first arithmetic logic module 301 may receive input data x300 and input data y300.

[0093] In some embodiments, the first arithmetic logic module may be further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed, thereby obtaining a first calculation result: performing an operation corresponding to the second calculation type indication signal on the first input data and the second input data, thereby obtaining the first calculation result. For example, the operation corresponding to the second calculation type indication signal may correspond to Formula 1 or Formula 2 described above. For another example, taking the dual-input vector calculation instruction as a dual-input vector add instruction, the input data x300 and the input data y300 may be added to obtain a calculation result fxy. It will be understood that the calculation result fxy may serve as the first calculation result.

[0094] In some embodiments, the first arithmetic logic module may be further configured to perform the following operations to perform the operation corresponding to the calculation control signal on the first input data and the first data to be processed, thereby obtaining a first calculation result: providing the first calculation result to the second arithmetic logic unit based on the second calculation type indication signal. For example, the calculation result fxy may be provided to the second arithmetic logic module 302 based on the second calculation type indication signal.

[0095] In some embodiments, the second arithmetic logic module may be further configured to perform the following operations to perform the operation corresponding to the calculation control signal on the second to-be-processed data and the parameter data to obtain a second calculation result: in response to receiving the second calculation type indication signal, receive the first calculation result and obtain the parameter data. For example, the second arithmetic logic module 302 may receive the calculation result fxy or read the parameter data A301 from the parameter register.

[0096] In some embodiments, the second arithmetic logic module may be further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the second to-be-processed data and the parameter data to obtain a second calculation result: performing an operation corresponding to the second calculation type indication signal on the first calculation result and the parameter data to obtain the second calculation result. For example, the operation corresponding to the second calculation type indication signal may correspond to Formula 1 or Formula 2 described above. For another example, using a dual-input vector calculation instruction as a dual-input vector addition instruction, the calculation result fxy may be added to the parameter data A300 to obtain a calculation result f300. It will be understood that the calculation result f300 may serve as the second calculation result.

[0097] It is understood that the arithmetic logic unit of the present disclosure is described above in conjunction with dual-input vector calculation instructions. The following describes some ways of writing back calculation results in conjunction with dual-input vector calculation instructions.

[0098] In some embodiments, the write control signal includes a third write control signal, and the write request includes a third write request.

[0099] In some embodiments, the control module is further configured to perform the following operations to send a write request to a target write port of the data storage unit: in response to receiving the third write control signal, send a third write request to the target write port of the data storage unit.

[0100] In the disclosed embodiment, the target write port can be one of the at least two corresponding write ports. For example, the data storage unit includes multiple write ports. The multiple write ports include two corresponding write ports corresponding to the data processing unit 30. Either of these two corresponding write ports can serve as the target write port. It is understood that the at least two corresponding write ports corresponding to the data processing unit 20 described above can be the at least two corresponding write ports of the data processing unit 30.

[0101] In the embodiment of the present disclosure, the third write control signal corresponds to the third address space to be written. For example, for a dual-input vector calculation instruction, an address space can be determined based on the base address corresponding to a destination operand and the offset of the data to be written, as the third address space to be written. The control unit associated with the data processing unit 30 can provide the third write control signal and the third address space to be written to the control module 303 of the data processing unit 30. Thus, the control module 303 can send a third write request to the target write port to write the calculation result f300 to the third address space to be written. Thus, a calculation for the dual-input vector calculation instruction is completed. Next, under the control of the read control signal, the calculation control signal and the write control signal, the data processing unit can read the sub-vector after the input data x300 and the sub-vector after the input data y300, perform calculations and write back the corresponding calculation results.

[0102] Through the embodiments of the present disclosure, the data processing unit can be compatible with dual-input vector calculation instructions and single-input vector calculation instructions. When processing dual-input vector calculation instructions and single-input vector calculation instructions respectively, the same set of corresponding read ports and corresponding write ports of the data storage unit can be reused. In addition, when processing dual-input vector calculation instructions and single-input vector calculation instructions respectively, the same arithmetic logic unit can also be used, with low hardware resource overhead, and no major hardware changes need to be made to existing artificial intelligence chips to achieve higher performance improvements.

[0103] It can be understood that the above description of the present disclosure is based on the example of a control module receiving a read control signal, a write control signal, and sending a read request and a write request. However, the present disclosure is not limited to this. When the data processing unit corresponds to at least two corresponding read ports and at least two corresponding write ports, the control unit associated with the data processing unit can provide the read request corresponding to the read control signal and the address to be read to the data storage unit. Thus, the data storage unit can provide the input data to the control module of the data processing unit via the corresponding read port. Based on the calculation control signal, the control module can provide the input data to the arithmetic logic module. After obtaining the calculation result, the control unit associated with the data processing unit can also provide the write request corresponding to the write control signal and the address space to be written to the data storage unit. Next, the control module or the arithmetic logic module can write the calculation result to the address space to be written.

[0104] It can be understood that the above description of the data processing unit of the present disclosure is based on one or more input data in the input data set. The following description will describe the processing method after the input data in the input data set are processed.

[0105] In some embodiments, there are N first input data and N second input data, where N is an integer greater than or equal to 1. The parameter data, the N first input data, and the N second input data all correspond to the current instruction to be processed. The current instruction to be processed corresponds to N calculation control signals. For example, the current instruction to be processed may be the above-mentioned single-input vector calculation instruction or the dual-input vector calculation instruction. For the above-mentioned single-input vector calculation instruction, the N first input data may include the above-mentioned input data x201, the N second input data may include the above-mentioned input data x202, and the parameter data may be the above-mentioned parameter data A200. For another example, for the above-mentioned dual-input vector calculation instruction, the N first input data may include the above-mentioned input data x300, the N second input data may include the above-mentioned input data y300, and the parameter data may be the above-mentioned parameter data A301. It can be understood that the value of N may be different for different instructions.

[0106] In some embodiments, after the first arithmetic logic module and the second arithmetic logic module respectively perform N operations corresponding to N calculation control signals, the value of the parameter register is updated to the parameter data of the subsequent instruction to be processed of the current instruction to be processed. For example, if the current instruction to be processed is a single-input vector calculation instruction corresponding to the above-mentioned data processing unit 20, and the subsequent instruction to be processed is a dual-input vector calculation instruction corresponding to the above-mentioned data processing unit 30, the value of the parameter register can be updated from parameter data A200 to parameter data A301. Through the embodiment of the present disclosure, the parameter register can be configured before the instruction is executed so that the value in the parameter register can be used during the execution of the instruction, without having to read the parameter data multiple times during the execution of the instruction, thereby saving memory resources and improving data processing efficiency.

[0107] It is understood that the above description is of the data processing unit of the present disclosure. To improve the processing efficiency of vectors, multiple data processing units can be used to execute instructions in parallel. The following describes a data processing device including the data processing units.

[0108] Figure 4 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure.

[0109] like Figure 4 As shown, the apparatus 400 may include an addressing unit 410 , a decoding unit 420 , a control unit 430 and at least one data processing unit 40 .

[0110] The addressing unit 410 may be configured to obtain an instruction to be processed. For example, the instruction to be processed may be the single-input vector calculation instruction or the dual-input vector calculation instruction.

[0111] The decoding unit 420 may be configured to decode the instruction to be processed and obtain a decoding result. For example, the decoding unit 420 may parse the instruction to perform decoding.

[0112] The control unit 430 may be configured to generate a plurality of control signals according to the decoding result. For example, the plurality of control signals may include the aforementioned calculation control signal.

[0113] At least one data processing unit 40 can be configured to process first input data and second input data corresponding to the instruction to be processed based on the calculation control signal. For example, the data processing unit 40 can be any one of the above-mentioned data processing unit 10, data processing unit 20, and data processing unit 30.

[0114] It is understandable that the above Figure 4 The data processing device of the present disclosure has been described. The device of the present disclosure will be further described below.

[0115] Figure 5 is a schematic diagram of a data processing device according to an embodiment of the present disclosure.

[0116] like Figure 5 As shown, the apparatus 500 may include an instruction storage unit 540, an instruction fetch unit 510, a decoding unit 520, a control unit 530, and multiple data processing units. The multiple data processing units may include a data processing unit 50_1, a data processing unit 50_2, a data processing unit 503, and a data processing unit 50_4.

[0117] like Figure 5 As shown, the instruction storage unit 540 can be configured to store pending instructions. The pending instructions can include a first pending instruction. The first pending instruction can be, for example, the single-input vector calculation instruction described above. The instruction fetch unit 510 can retrieve the first pending instruction and provide it to the decoding unit 520. The decoding unit 520 can decode the first pending instruction to obtain a first decoding result.

[0118] In some embodiments, the control unit may be further configured to perform the following operations to generate a plurality of control signals: generating a calculation control signal, a first read control signal, a second read control signal, a first write control signal, and a second write control signal based on the first decoding result. The calculation control signal may further include a first calculation type indication signal.

[0119] In some embodiments, the apparatus 500 may further include a data storage unit 550. The data storage unit may further include: at least two read ports and at least two write ports corresponding to each data processing unit. Figure 5 As shown, data storage unit 550 includes read port 551, read port 552, write port 553, and write port 554. Read port 551 and read port 552 can serve as two corresponding read ports of data processing unit 50_1. Write port 553 and write port 554 can serve as two corresponding write ports of data processing unit 50_1.

[0120] In some embodiments, the control unit may provide a calculation control signal, a first read control signal, a second read control signal, a first write control signal, and a second write control signal to the control module of the data processing unit. For example, the control unit 530 may provide the first read control signal and the second read control signal to the control module of the data processing unit 50_1, so that the control module sends a first read request and a second read request to read port 551 and read port 552, respectively. The control module may also receive first input data and second input data corresponding to the first read request and the second read request, respectively. The control unit 530 may also provide the control module with a first calculation type indication signal, so that the control module provides the first input data to the first arithmetic logic module of the data processing unit 50_1 and the second input data to the second arithmetic logic module of the data processing unit 50_1. The first arithmetic logic module and the second arithmetic logic module respectively perform the operations corresponding to the first calculation type indication signal to obtain a first calculation result and a second calculation result, respectively. The control unit 530 may provide the first write control signal and the second write control signal to the control module of the data processing unit 50_1, so that the control module sends a first write request and a second write request to write port 553 and write port 554, respectively. Next, the first calculation result can be written back to the data storage unit 550 via the write port 553. The second calculation result can be written back to the data storage unit 550 via the write port 554. It can be understood that when processing a single-input vector calculation instruction, the manner in which the data processing unit 50_1 reads data, performs operations, and writes back results is the same or similar to the manner in which the data processing unit 20 reads data, performs operations, and writes back results, and will not be further described in this disclosure.

[0121] In other embodiments, the control unit 530 may also provide the data storage unit 550 with a first read request corresponding to the first read control signal and a signal corresponding to the first address space to be read. The control unit 530 may also provide the data storage unit 550 with a second read request corresponding to the second read control signal and a signal corresponding to the second address space to be read. The data storage unit 550 may provide the first input data and the second input data to the control module of the data processing unit 50_1 via the read port 551 and the read port 552, respectively. The control unit 530 may also provide the control module with a first calculation type indication signal, so that the control module provides the first input data to the first arithmetic logic module of the data processing unit 50_1 and the second input data to the second arithmetic logic module of the data processing unit 50_1. The first arithmetic logic module and the second arithmetic logic module respectively perform the operations corresponding to the first calculation type indication signal to obtain the first calculation result and the second calculation result, respectively. The control unit 530 may also provide the data storage unit 550 with a first write request corresponding to the first write control signal and a signal corresponding to the first address space to be written. The control unit 550 may also provide the second write request corresponding to the second write control signal and the corresponding signal of the second address space to be written to the data storage unit 550. Next, the first calculation result may be written back to the data storage unit 550 via the write port 553. The second calculation result may be written back to the data storage unit 550 via the write port 554.

[0122] It can be understood that the above description of the apparatus of the present disclosure is made in conjunction with the first calculation type indication signal, and the following description of the apparatus of the present disclosure will be made in conjunction with the second calculation type indication signal.

[0123] The pending instructions stored in the instruction storage unit 540 may further include a second pending instruction. The second pending instruction may be, for example, the aforementioned dual-input vector calculation instruction. The instruction fetch unit 510 may retrieve the second pending instruction and provide it to the decoding unit 520. The decoding unit 520 may decode the second pending instruction to obtain a second decoding result.

[0124] In some embodiments, the control unit is further configured to perform the following operations to generate a plurality of control signals: generating a calculation control signal, a third read control signal, a fourth read control signal, and a third write control signal according to the second decoding result. The calculation control signal includes a calculation enable signal and a second calculation type indication signal.

[0125] In some embodiments, the control unit may provide a calculation control signal, a third read control signal, a fourth read control signal, and a third write control signal to the control module of the data processing unit. For example, the control unit 530 may provide the third read control signal and the fourth read control signal to the control module of the data processing unit 50_1, so that the control module sends a third read request and a fourth read request to read port 551 and read port 552, respectively. The control module may also receive first input data and second input data corresponding to the third read request and the fourth read request, respectively. The control unit 530 may also provide the control module with a second calculation type indication signal, so that the control module provides the first input data and the second input data to the first arithmetic logic module of the data processing unit 50_1. The first arithmetic logic module performs an operation corresponding to the second calculation type indication signal to obtain a first calculation result. The second arithmetic logic module of the data processing unit 50_1 may perform an operation corresponding to the second calculation type indication signal on the second calculation result and parameter data to obtain a second calculation result. The control unit 530 may provide the control module of the data processing unit 50_1 with a third write control signal, so that the control module sends a third write request to write port 553. Next, the second calculation result can be written back to the data storage unit 550 via the write port 553. It can be understood that for the dual-input vector calculation instruction, the manner in which the data processing unit 50_1 reads data, performs operations, and writes back the results is the same or similar to the manner in which the data processing unit 30 reads data, performs operations, and writes back the results, and will not be further described in this disclosure.

[0126] In other embodiments, the control unit 530 may also provide the data storage unit 550 with a third read request corresponding to the third read control signal and a corresponding signal indicating the third address space to be read. The control unit 530 may also provide the data storage unit 550 with a fourth read request corresponding to the fourth read control signal and a corresponding signal indicating the fourth address space to be read. The data storage unit 550 may provide the first input data and the second input data to the control module of the data processing unit 50_1 via read port 551 and read port 552, respectively. The control unit 530 may also provide the control module with a second calculation type indication signal, so that the control module provides the first input data and the second input data to the first arithmetic logic module of the data processing unit 50_1. The first arithmetic logic module performs an operation corresponding to the second calculation type indication signal to obtain a first calculation result. The second arithmetic logic module of the data processing unit 50_1 may perform an operation corresponding to the second calculation type indication signal on the second calculation result and parameter data to obtain a second calculation result. The control unit 530 may also provide the data storage unit 550 with a first write request corresponding to the third write control signal and a corresponding signal indicating the first address space to be written via write port 553. Next, the second calculation result may be written back to the data storage unit 550 via the write port 553 .

[0127] It can be understood that the apparatus of the present disclosure is described above, and the equipment including the apparatus will be described below.

[0128] Figure 6 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0129] like Figure 6 As shown, the device 6000 may include a data processing apparatus 600. The apparatus 600 may be the apparatus 400 or the apparatus 500 described above.

[0130] It can be understood that the electronic device of the present disclosure is described above, and the method of the present disclosure will be described below.

[0131] Figure 7 is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0132] like Figure 7 As shown, the method M700 may include operations S710 to S720.

[0133] In operation S710 , in response to receiving a calculation control signal, an operation corresponding to the calculation control signal is performed on first input data and first data to be processed to obtain a first calculation result.

[0134] In operation S720 , in response to receiving the calculation control signal, an operation corresponding to the calculation control signal is performed on the second data to be processed and the parameter data to obtain a second calculation result.

[0135] In the embodiment of the present disclosure, the first data to be processed is second input data or parameter data related to the calculation control signal.

[0136] In the embodiment of the present disclosure, the second data to be processed is the second input data or the first calculation result.

[0137] It can be understood that method M700 can be executed by the above-mentioned data processing unit 10.

[0138] In some embodiments, the method further includes: in response to receiving the read control signal, sending a read request to a target read port of the data storage unit, the target read port being one of at least two corresponding read ports, the corresponding read port corresponding to the data processing unit, and receiving at least one of first input data and second input data corresponding to the read request.

[0139] In some embodiments, the method further includes: in response to receiving a write control signal, sending a write request to a target write port of the data storage unit, wherein the target write port is one of at least two corresponding write ports, the corresponding write port corresponding to the data processing unit, and at least one of the first calculation result and the second calculation result is written into an address space corresponding to the write control signal.

[0140] In some embodiments, the calculation control signal includes a first calculation type indication signal. Performing an operation corresponding to the calculation control signal on the first input data and the first data to be processed to obtain the first calculation result includes: in response to receiving the first calculation type indication signal, receiving the first input data and obtaining parameter data. Performing the operation corresponding to the first calculation type indication signal on the first input data and the parameter data to obtain the first calculation result.

[0141] In some embodiments, performing an operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain the second calculation result includes: in response to receiving the first calculation type indication signal, receiving second input data and obtaining parameter data, wherein the first input data and the second input data are from the same input data set; and performing the operation corresponding to the first calculation type indication signal on the second input data and the parameter data to obtain the second calculation result.

[0142] In some embodiments, the read control signal includes a first read control signal and a second read control signal, the target read port includes a first target read port and a second target read port, and the read request includes a first read request and a second read request. Sending the read request to the target read port of the data storage unit includes: in response to receiving the first read control signal, sending the first read request to the first target read port of the data storage unit. The first read request corresponds to a first address space to be read in the data storage unit, the first read control signal corresponds to the first address space to be read, and the first target read port is one of at least two corresponding read ports. In response to receiving the second read control signal, sending the second read request to the second target read port of the data storage unit. The second read request corresponds to a second address space to be read in the data storage unit, the second read control signal corresponds to the second address space to be read, the second address space to be read is adjacent to the first address space to be read, and the second target read port is a read port other than the first target read port of the at least two corresponding read ports.

[0143] In some embodiments, the write control signal includes a first write control signal and a second write control signal, the target write port includes a first target write port and a second target write port, and the write request includes a first write request and a second write request. Sending a write request to the target write port of the data storage unit includes: in response to receiving the first write control signal, sending the first write request to the first target write port of the data storage unit. The first write control signal corresponds to a first address space to be written, and the first target write port is one of at least two corresponding write ports. In response to receiving the second write control signal, sending a second write request to the second target write port of the data storage unit. The second write control signal corresponds to a second address space to be written, and the second address space to be written is adjacent to the first address space to be written, and the second target write port is a write port of the at least two corresponding write ports other than the first target write port. The first calculation result is written to the first address space to be written, and the second calculation result is written to the second address space to be written.

[0144] In some embodiments, the calculation control signal includes a second calculation type indication signal. Performing an operation corresponding to the calculation control signal on the first input data and the first data to be processed to obtain a first calculation result includes: in response to receiving the second calculation type indication signal, receiving the first input data and the second input data. The first input data and the second input data are from a first input data set and a second data set, respectively, the first input data set being stored in a first continuous address space of a data storage unit, and the second input data set being stored in a second continuous address space of the data storage unit. Performing the operation corresponding to the second calculation type indication signal on the first input data and the second input data to obtain the first calculation result.

[0145] In some embodiments, performing the operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain the second calculation result includes: in response to receiving the second calculation type indication signal, receiving the first calculation result and obtaining the parameter data; and performing the operation corresponding to the second calculation type indication signal on the first calculation result and the parameter data to obtain the second calculation result.

[0146] In some embodiments, the read control signal includes a third read control signal and a fourth read control signal, the target read ports include a first target read port and a second target read port, and the read request includes a third read request and a fourth read request. Sending the read request to the target read port of the data storage unit includes: in response to receiving the third read control signal, sending the third read request to the first target read port of the data storage unit. The third read request corresponds to a third address space to be read in the data storage unit, the third address space to be read corresponds to the third read control signal, and the first target read port is one of the at least two corresponding read ports. In response to receiving the fourth read control signal, sending the fourth read request to the second target read port of the data storage unit. The fourth read request corresponds to a fourth address space to be read in the data storage unit, the fourth address space to be read corresponds to the fourth read control signal, the third address space to be read is from the first continuous address space, the fourth address space to be read is from the second continuous address space, and the second target read port is a read port of the at least two corresponding read ports other than the first target read port.

[0147] In some embodiments, the write control signal includes a third write control signal, the write request includes a third write request, and sending the write request to the target write port of the data storage unit includes: sending the third write request to the target write port of the data storage unit in response to receiving the third write control signal, wherein the third write control signal corresponds to a third address space to be written, and the target write port is one of the at least two corresponding write ports.

[0148] In some embodiments, there are N first input data and N second input data, where N is an integer greater than or equal to 1. The parameter data, the N first input data, and the N second input data all correspond to a current instruction to be processed, and the current instruction to be processed corresponds to N calculation control signals. After the first arithmetic logic module and the second arithmetic logic module respectively perform N operations corresponding to the N calculation control signals, the value of the parameter register is updated with the parameter data of the instruction to be processed subsequent to the current instruction to be processed.

[0149] Figure 8 is a flowchart of a data processing method according to another embodiment of the present disclosure.

[0150] like Figure 8 As shown, the method M800 may include operations S801 to S804.

[0151] In operation S801 , a to-be-processed instruction is obtained.

[0152] In operation S802 , the instruction to be processed is decoded to obtain a decoding result.

[0153] In operation S803 , a plurality of control signals are generated according to the decoding result.

[0154] In operation S804 , first input data and second input data corresponding to the instruction to be processed are processed based on the calculation control signal.

[0155] In an embodiment of the present disclosure, the plurality of control signals includes a calculation control signal.

[0156] In the embodiment of the present disclosure, the above-mentioned method M700 may be used to process the first input data and the second input data corresponding to the instruction to be processed, and the above-mentioned device 400 may also be used to execute the method M800.

[0157] In some embodiments, the instruction to be processed includes a first instruction to be processed, and the decoding result includes a first decoding result. Decoding the instruction to be processed to obtain the decoding result includes decoding the first instruction to be processed to obtain the first decoding result. Generating multiple control signals includes generating a calculation control signal, a first read control signal, a second read control signal, a first write control signal, and a second write control signal based on the first decoding result. The calculation control signals include a calculation enable signal and a first calculation type indication signal.

[0158] In some embodiments, the pending instruction includes a second pending instruction, and the decoding result includes a second decoding result. Decoding the pending instruction to obtain the decoding result includes decoding the second pending instruction to obtain the second decoding result. Generating multiple control signals includes generating a calculation control signal, a third read control signal, a fourth read control signal, and a third write control signal based on the second decoding result. The calculation control signal includes a calculation enable signal and a second calculation type indication signal.

[0159] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0160] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0161] Figure 9A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0162] like Figure 9 As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. Various programs and data required for the operation of the device 900 can also be stored in the RAM 903. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0163] Various components in the device 900 are connected to the I / O interface 905, including an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a magnetic disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0164] The computing unit 901 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 900 via the ROM 902 and / or the communication unit 909. When the computer program is loaded into the RAM 903 and executed by the computing unit 901, one or more steps of the data processing method described above can be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to execute the data processing method in any other appropriate manner (for example, by means of firmware).

[0165] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits, application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0166] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0167] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0168] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0169] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0170] Computer systems may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The client and server relationship arises through computer programs running on the respective computers and having a client-server relationship to each other.

[0171] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0172] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A data processing unit, comprising: parameter registers configured to store parameter data; a first arithmetic logic module configured to: in response to receiving a calculation control signal, perform an operation corresponding to the calculation control signal on first input data and first data to be processed to obtain a first calculation result, wherein the first data to be processed is the second input data or the parameter data related to the calculation control signal; and The second arithmetic logic module is configured to: in response to receiving the calculation control signal, perform an operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain a second calculation result, wherein the second data to be processed is the second input data or the first calculation result.

2. The data processing unit according to claim 1, further comprising a control module configured to: In response to receiving the read control signal, a read request is sent to a target read port of the data storage unit, wherein The target read port is one of at least two corresponding read ports, and the corresponding read port corresponds to the data processing unit; as well as At least one of the first input data and the second input data corresponding to the read request is received.

3. The data processing unit according to claim 2, wherein: The control module is further configured to: In response to receiving a write control signal, a write request is sent to a target write port of the data storage unit, wherein the target write port is one of at least two corresponding write ports, the corresponding write port corresponds to the data processing unit, and at least one of the first calculation result and the second calculation result is written to the address space corresponding to the write control signal.

4. The data processing unit according to claim 1, wherein: The calculation control signal includes a first calculation type indication signal, The first arithmetic logic module is further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed, to obtain a first calculation result: In response to receiving the first calculation type indication signal, receiving the first input data and acquiring the parameter data; An operation corresponding to a first calculation type indication signal is performed on the first input data and the parameter data to obtain the first calculation result.

5. The data processing unit according to claim 4, wherein: The second arithmetic logic module is further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the second to-be-processed data and the parameter data, to obtain a second calculation result: In response to receiving the first calculation type indication signal, receiving the second input data and acquiring the parameter data, wherein the first input data and the second input data are from the same input data set; An operation corresponding to the first calculation type indication signal is performed on the second input data and the parameter data to obtain the second calculation result. The data processing unit according to claim 2 , wherein: The read control signal includes a first read control signal and a second read control signal, the target read port includes a first target read port and a second target read port, and the read request includes a first read request and a second read request; The control module is further configured to perform the following operations to send a read request to a target read port of the data storage unit: In response to receiving the first read control signal, sending the first read request to a first target read port of the data storage unit, wherein the first read request corresponds to a first to-be-read address space in the data storage unit, the first read control signal corresponds to the first to-be-read address space, and the first target read port is one of the at least two corresponding read ports; In response to receiving the second read control signal, the second read request is sent to the second target read port of the data storage unit, wherein the second read request corresponds to the second address space to be read in the data storage unit, the second read control signal corresponds to the second address space to be read, the second address space to be read is adjacent to the first address space to be read, and the second target read port is a read port other than the first target read port among at least two corresponding read ports.

7. The data processing unit according to claim 1, wherein: The calculation control signal also includes a first calculation type indication signal, The data processing unit further includes a control module, which is further configured to: Based on the first calculation type control signal, the first input data is provided to the first arithmetic logic module and the second input data is provided to the second arithmetic logic module.

8. The data processing unit according to claim 3, wherein: The write control signal includes a first write control signal and a second write control signal, the target write port includes a first target write port and a second target write port, and the write request includes a first write request and a second write request; The control module is further configured to perform the following operations to send a write request to a target write port of the data storage unit: In response to receiving the first write control signal, sending the first write request to the first target write port of the data storage unit, wherein the first write control signal corresponds to a first address space to be written, and the first target write port is one of the at least two corresponding write ports; In response to receiving the second write control signal, sending the second write request to the second target write port of the data storage unit, wherein the second write control signal corresponds to a second address space to be written, the second address space to be written is adjacent to the first address space to be written, and the second target write port is a write port other than the first target write port among the at least two corresponding write ports. The first calculation result is written into the first address space to be written, and the second calculation result is written into the second address space to be written.

9. The data processing unit according to claim 1, wherein: The calculation control signal includes a second calculation type indication signal, The first arithmetic logic module is further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the first input data and the first data to be processed, to obtain a first calculation result: In response to receiving the second computation type indication signal, receiving the first input data and the second input data, wherein the first input data and the second input data are from a first input data set and a second input data set, respectively, the first input data set is stored in a first continuous address space of the data storage unit, and the second input data set is stored in a second continuous address space of the data storage unit; performing an operation corresponding to the second calculation type indication signal on the first input data and the second input data to obtain the first calculation result; Based on the second calculation type indication signal, the first calculation result is provided to the second arithmetic logic unit.

10. The data processing unit according to claim 9, wherein: The second arithmetic logic module is further configured to perform the following operations to perform an operation corresponding to the calculation control signal on the second to-be-processed data and the parameter data, to obtain a second calculation result: In response to receiving the second calculation type indication signal, receiving the first calculation result and acquiring the parameter data; An operation corresponding to the second calculation type indication signal is performed on the first calculation result and the parameter data to obtain the second calculation result.

11. The data processing unit according to claim 2, wherein: The read control signal includes a third read control signal and a fourth read control signal, the target read port includes a first target read port and a second target read port, and the read request includes a third read request and a fourth read request; The control module is further configured to perform the following operations to send a read request to a target read port of the data storage unit: In response to receiving the third read control signal, sending the third read request to the first target read port of the data storage unit, wherein the third read request corresponds to a third to-be-read address space in the data storage unit, the third to-be-read address space corresponds to the third read control signal, and the first target read port is one of the at least two corresponding read ports; In response to receiving the fourth read control signal, the fourth read request is sent to the second target read port of the data storage unit, wherein the fourth read request corresponds to the fourth address space to be read in the data storage unit, the fourth address space to be read corresponds to the fourth read control signal, the third address space to be read comes from the first continuous address space, the fourth address space to be read comes from the second continuous address space, and the second target read port is a read port other than the first target read port among the at least two corresponding read ports.

12. The data processing unit according to claim 1, wherein: The calculation control signal also includes a second calculation type indication signal, The data processing unit further includes a control module, which is further configured to: The first input data and the second input data are provided to the first arithmetic logic module based on the second calculation type control signal.

13. The data processing unit according to claim 3, wherein: The write control signal includes a third write control signal, and the write request includes a third write request; The control module is further configured to perform the following operations to send a write request to a target write port of the data storage unit: In response to receiving the third write control signal, a third write request is sent to the target write port of the data storage unit, wherein the third write control signal corresponds to the third address space to be written, and the target write port is one of at least two corresponding write ports.

14. The data processing unit according to claim 1, wherein: The number of the first input data is N, the number of the second input data is N, and N is an integer greater than or equal to 1. The parameter data, the N first input data, and the N second input data all correspond to a current instruction to be processed, and the current instruction to be processed corresponds to the N calculation control signals. After the first arithmetic logic module and the second arithmetic logic module respectively execute N operations corresponding to the N calculation control signals, the value of the parameter register is updated to the parameter data of the subsequent instruction to be processed of the current instruction to be processed.

15. A data processing device comprising: an instruction fetch unit configured to fetch instructions to be processed; A decoding unit configured to decode the instruction to be processed and obtain a decoding result; a control unit configured to generate a plurality of control signals according to the decoding result, wherein the plurality of control signals include a calculation control signal; At least one data processing unit according to any one of claims 1 to 14, configured to process first input data and second input data corresponding to the instruction to be processed based on the calculation control signal.

16. The device according to claim 15, wherein The instruction to be processed includes a first instruction to be processed, the decoding result includes a first decoding result, The decoding unit is further configured to perform the following operations to decode the instruction to be processed and obtain a decoding result: decoding the first instruction to be processed and obtaining the first decoding result; The control unit is also configured to perform the following operations to generate multiple control signals: based on the first decoding result, generate the calculation control signal, the first read control signal, the second read control signal, the first write control signal and the second write control signal, wherein the calculation control signal includes a calculation enable signal and a first calculation type indication signal.

17. The device according to claim 15, wherein The instructions to be processed include a second instruction to be processed, and the decoding result includes a second decoding result. The decoding unit is further configured to perform the following operations to decode the pending instruction and obtain a decoding result: decode the second pending instruction and obtain a second decoding result; The control unit is further configured to perform the following operations to generate multiple control signals: based on the second decoding result, generate the calculation control signal, the third read control signal, the fourth read control signal, and the third write control signal, wherein the calculation control signal includes a calculation enable signal and a second calculation type indication signal.

18. The apparatus according to claim 15, further comprising a data storage unit, wherein the data storage unit comprises: At least two read ports and at least two write ports corresponding to each data processing unit.

19. An electronic device comprising the device according to any one of claims 15 to 18.

20. A data processing method, comprising: In response to receiving a calculation control signal, performing an operation corresponding to the calculation control signal on first input data and first data to be processed to obtain a first calculation result, wherein the first data to be processed is the second input data or the parameter data related to the calculation control signal; and In response to receiving the calculation control signal, an operation corresponding to the calculation control signal is performed on the second data to be processed and the parameter data to obtain a second calculation result, wherein the second data to be processed is the second input data or the first calculation result.

21. The method according to claim 20, further comprising: In response to receiving a read control signal, sending a read request to a target read port of a data storage unit, wherein the target read port is one of at least two corresponding read ports corresponding to the data processing unit; and At least one of the first input data and the second input data corresponding to the read request is received.

22. The method according to claim 21, further comprising: In response to receiving a write control signal, a write request is sent to a target write port of the data storage unit, wherein the target write port is at least two corresponding write ports ≥ one, the corresponding write ports correspond to the data processing unit, and at least one of the first calculation result and the second calculation result is written to the address space corresponding to the write control signal.

23. The method according to claim 20, wherein The calculation control signal includes a first calculation type indication signal, The performing the operation corresponding to the calculation control signal on the first input data and the first to-be-processed data to obtain the first calculation result includes: In response to receiving the first calculation type indication signal, receiving the first input data and acquiring the parameter data; An operation corresponding to a first calculation type indication signal is performed on the first input data and the parameter data to obtain the first calculation result.

24. The method according to claim 23, wherein The performing an operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain a second calculation result includes: In response to receiving the first calculation type indication signal, receiving the second input data and acquiring the parameter data, wherein the first input data and the second input data are from the same input data set; An operation corresponding to the first calculation type indication signal is performed on the second input data and the parameter data to obtain the second calculation result.

25. The method according to claim 21, wherein The read control signal includes a first read control signal and a second read control signal, the target read port includes a first target read port and a second target read port, and the read request includes a first read request and a second read request; The sending of a read request to a target read port of the data storage unit comprises: In response to receiving the first read control signal, sending the first read request to a first target read port of the data storage unit, wherein the first read request corresponds to a first to-be-read address space in the data storage unit, the first read control signal corresponds to the first to-be-read address space, and the first target read port is one of the at least two corresponding read ports; In response to receiving the second read control signal, the second read request is sent to the second target read port of the data storage unit, wherein the second read request corresponds to the second address space to be read in the data storage unit, the second read control signal corresponds to the second address space to be read, the second address space to be read is adjacent to the first address space to be read, and the second target read port is a read port other than the first target read port among at least two corresponding read ports.

26. The method according to claim 22, wherein The write control signal includes a first write control signal and a second write control signal, the target write port includes a first target write port and a second target write port, and the write request includes a first write request and a second write request; The sending of a write request to a target write port of the data storage unit comprises: In response to receiving the first write control signal, sending the first write request to the first target write port of the data storage unit, wherein the first write control signal corresponds to a first address space to be written, and the first target write port is one of the at least two corresponding write ports; In response to receiving the second write control signal, sending the second write request to the second target write port of the data storage unit, wherein the second write control signal corresponds to a second address space to be written, the second address space to be written is adjacent to the first address space to be written, and the second target write port is a write port other than the first target write port among the at least two corresponding write ports. The first calculation result is written into the first address space to be written, and the second calculation result is written into the second address space to be written.

27. The method according to claim 20, wherein The calculation control signal includes a second calculation type indication signal, The performing the operation corresponding to the calculation control signal on the first input data and the first to-be-processed data to obtain the first calculation result includes: In response to receiving the second computation type indication signal, receiving the first input data and the second input data, wherein the first input data and the second input data are from a first input data set and a second input data set, respectively, the first input data set is stored in a first continuous address space of the data storage unit, and the second input data set is stored in a second continuous address space of the data storage unit; An operation corresponding to the second calculation type indication signal is performed on the first input data and the second input data to obtain the first calculation result.

28. The method according to claim 27, wherein The performing the operation corresponding to the calculation control signal on the second data to be processed and the parameter data to obtain a second calculation result includes: In response to receiving the second calculation type indication signal, receiving the first calculation result and acquiring the parameter data; An operation corresponding to the second calculation type indication signal is performed on the first calculation result and the parameter data to obtain the second calculation result.

29. The method according to claim 21, wherein The read control signal includes a third read control signal and a fourth read control signal, the target read port includes a first target read port and a second target read port, and the read request includes a third read request and a fourth read request; The sending of a read request to a target read port of the data storage unit comprises: In response to receiving the third read control signal, sending the third read request to the first target read port of the data storage unit, wherein the third read request corresponds to a third to-be-read address space in the data storage unit, the third to-be-read address space corresponds to the third read control signal, and the first target read port is one of the at least two corresponding read ports; In response to receiving the fourth read control signal, the fourth read request is sent to the second target read port of the data storage unit, wherein the fourth read request corresponds to the fourth address space to be read in the data storage unit, the fourth address space to be read corresponds to the fourth read control signal, the third address space to be read comes from the first continuous address space, the fourth address space to be read comes from the second continuous address space, and the second target read port is a read port other than the first target read port among the at least two corresponding read ports.

30. The method according to claim 3, wherein The write control signal includes a third write control signal, and the write request includes a third write request; The sending of a write request to a target write port of the data storage unit comprises: In response to receiving the third write control signal, a third write request is sent to the target write port of the data storage unit, wherein the third write control signal corresponds to the third address space to be written, and the target write port is one of at least two corresponding write ports.

31. The method according to claim 1, wherein The number of the first input data is N, the number of the second input data is N, and N is an integer greater than or equal to 1. The parameter data, the N first input data, and the N second input data all correspond to a current instruction to be processed, and the current instruction to be processed corresponds to the N calculation control signals. After the first arithmetic logic module and the second arithmetic logic module respectively execute N operations corresponding to the N calculation control signals, the value of the parameter register is updated to the parameter data of the subsequent instruction to be processed of the current instruction to be processed.

32. A data processing method comprising: Get pending instructions; Decoding the instruction to be processed to obtain a decoding result; generating a plurality of control signals according to the decoding result, wherein the plurality of control signals include a calculation control signal; Based on the calculation control signal, the first input data and the second input data corresponding to the instruction to be processed are processed using the method according to any one of claims 20 to 31.

33. The method according to claim 32, wherein The instruction to be processed includes a first instruction to be processed, the decoding result includes a first decoding result, Decoding the instruction to be processed to obtain a decoding result includes: decoding the first instruction to be processed to obtain the first decoding result; Generating multiple control signals includes: generating the calculation control signal, the first read control signal, the second read control signal, the first write control signal and the second write control signal according to the first decoding result, wherein the calculation control signal includes a calculation enable signal and a first calculation type indication signal.

34. The method of claim 32, wherein: The instructions to be processed include a second instruction to be processed, and the decoding result includes a second decoding result. Decoding the instruction to be processed to obtain a decoding result includes: decoding the second instruction to be processed to obtain a second decoding result; Generating a plurality of control signals includes generating the calculation control signal, a third read control signal, a fourth read control signal, and a third write control signal according to the second decoding result, wherein the calculation control signal includes a calculation enable signal and a second calculation type indication signal.

35. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 20 to 34.

36. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to perform the method according to any one of claims 20 to 34.

37. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 20 to 34.

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