Atomic instruction execution method and device

Abstract

The invention provides an atomic instruction execution method and device, relates to the technical field of computers, and is used for improving the expandability of atomic instructions. The method comprises the steps that an atomic instruction is obtained, the atomic instruction comprises first instruction information, and the first instruction information is used for indicating at least one of an address register, a source register and a destination register; wherein the address register is used for storing an address to be operated, and the source register is used for storing an operand; respectively acquiring the address to be operated and the operand from the address register and the source register according to first instruction information; and executing an atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and storing an obtained execution result in the destination register.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for executing atomic instructions. Background Art

[0002] Due to the ever-increasing scale of application workloads and the limited processing power of individual processors, parallelizable portions of an application workload are often run on multiple processors to improve performance. However, inter-core data synchronization between multiple processors can become a performance bottleneck. Currently, atomic instructions are used to address this issue. However, the limited encoding space for instruction sets across different processor systems limits the expansion of atomic instructions. Summary of the Invention

[0003] The present application provides an atomic instruction execution method and device for improving the scalability of atomic instructions.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, an atomic instruction execution method is provided, which is applied to an instruction execution device, and the method includes: obtaining an atomic instruction, the atomic instruction including first instruction information, the first instruction information being used to indicate at least one of the following: an address register, a source register, and a destination register; wherein the address register is used to store an address to be operated (i.e., an address that requires an atomic operation), and the source register is used to store an operand; obtaining the address to be operated and the operand according to the first instruction information; executing the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and storing the obtained execution result in the destination register.

[0006] Optionally, obtaining the address to be operated and the operand according to the first instruction information includes: if the first instruction information is used to indicate the address register, obtaining the address to be operated from the address register, or, if the first instruction information includes the address to be operated, obtaining the address to be operated from the first instruction information; if the first instruction information is also used to indicate the source register, obtaining the operand from the source register, or, if the first instruction information also includes the operand, obtaining the operand from the first instruction information; wherein, if the first instruction information does not indicate the destination register, the first instruction information also includes the storage address of the execution result.

[0007] In the above technical solution, the first instruction information included in the atomic instruction obtained by the device is used to indicate at least one of the address register, source register or destination register. The address register and the source register are used to store the address to be operated and the operand of the atomic instruction. The device can obtain the address to be operated and the operand from the address register and the source register respectively according to the first instruction information and perform the atomic operation. The execution result is stored in the destination register. In this way, by storing information such as the address to be operated, the operand and the execution result in the above three registers, there is no need to carry the address to be operated and the operand directly in the atomic instruction, thereby reducing the space occupied by the above information, and the larger the register space, the more instruction information can be stored, thereby greatly improving the scalability of the atomic instruction.

[0008] In one possible implementation of the first aspect, the source register and / or the destination register includes a fixed-point register, a vector register, a register pair, or a register group. This possible implementation increases the diversity and flexibility of selection of the source register and the destination register, and further improves the scalability of the atomic instruction when the source register and the destination register are a register pair or a register group.

[0009] In a possible implementation of the first aspect, the instruction execution device includes a processor and a remote execution unit, and the remote execution unit is a last-level cache or a local agent; the first instruction information is also used to indicate an operation type, and the operation type is used to indicate: the processor executes the atomic operation, or the remote execution unit executes the atomic operation. Optionally, the operation type is stored in the source register. In the above possible implementation, the processor or the remote execution unit can execute the atomic operation according to the indication of the operation type, so that in actual applications, a suitable and efficient execution unit can be selected according to the specific atomic operation, thereby improving the execution efficiency of the atomic instruction; in addition, storing the operation type in the source register can further improve the scalability of the atomic instruction.

[0010] In a possible implementation of the first aspect, when the operation type is used to instruct the remote execution unit to perform the atomic operation, the method further includes: the processor sending second instruction information to the remote execution unit, the second instruction information including the address to be operated and the operand; and the remote execution unit sending the execution result to the processor to store the execution result in the destination register. In the above possible implementation, the remote execution unit can execute the atomic operation corresponding to the instruction of the operation type, thereby specifying the remote execution unit to execute the atomic operation corresponding to certain atomic instructions, thereby improving the execution efficiency of the atomic instructions.

[0011] In a possible implementation of the first aspect, the first instruction information is also used to indicate permission check information, and the permission check information is used to indicate: the processor performs a permission check on the atomic instruction, the remote execution unit performs a permission check on the atomic instruction, or the processor and the remote execution unit perform a permission check on the atomic instruction. Optionally, the permission check information is stored in the source register. In the above possible implementation, the processor or the remote execution unit can perform a permission check according to the indication of the permission check information, so that in actual applications, a suitable and efficient execution unit can be selected according to the specific atomic operation, thereby improving the execution efficiency of the atomic instruction; in addition, storing the permission check information in the source register can further improve the scalability of the atomic instruction.

[0012] In a possible implementation of the first aspect, the method further includes: when the remote execution unit performs a permission check on the atomic instruction and a check exception occurs, the remote execution unit sends an error message to the processor, so that the error message is stored in the destination register. In this possible implementation, the remote execution unit can perform a permission check according to the instruction of the permission check information, thereby specifying the remote execution unit to perform permission checks corresponding to certain atomic instructions, thereby improving the execution efficiency of the atomic instructions.

[0013] In a second aspect, an atomic instruction execution device is provided, which includes: a processor for obtaining an atomic instruction, the atomic instruction including first instruction information, the first instruction information being used to indicate at least one of the following: an address register, a source register, and a destination register, the address register being used to store an address to be operated, and the source register being used to store an operand; the processor is also used to obtain the address to be operated and the operand from the address register and the source register respectively according to the first instruction information; the processor or remote execution unit is used to execute the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and store the obtained execution result in the destination register.

[0014] In a possible implementation of the second aspect, the processor is further used to: if the first instruction information is used to indicate the address register, obtain the address to be operated from the address register, or, if the first instruction information includes the address to be operated, obtain the address to be operated from the first instruction information; if the first instruction information is also used to indicate the source register, obtain the operand from the source register, or, if the first instruction information also includes the operand, obtain the operand from the first instruction information; wherein, if the first instruction information does not indicate the destination register, the first instruction information also includes the storage address of the execution result.

[0015] In a possible implementation manner of the second aspect, the source register and / or the destination register includes a fixed-point register, a vector register, a register pair, or a register group.

[0016] In a possible implementation of the second aspect, the instruction execution apparatus includes a processor and a remote execution unit, and the first instruction information is further used to indicate an operation type, where the operation type is used to indicate whether the processor executes the atomic operation or the remote execution unit executes the atomic operation. Optionally, the operation type is stored in the source register.

[0017] In a possible implementation of the second aspect, when the operation type is used to instruct the remote execution unit to perform the atomic operation: the processor is further used to send second instruction information to the remote execution unit, and the second instruction information includes the address to be operated and the operand; the remote execution unit is further used to send the execution result to the processor to store the execution result in the destination register.

[0018] In a possible implementation of the second aspect, the first instruction information is further used to indicate permission check information, where the permission check information is used to instruct: the processor to perform a permission check on the atomic instruction, the remote execution unit to perform a permission check on the atomic instruction, or the processor and the remote execution unit to perform a permission check on the atomic instruction. Optionally, the permission check information is stored in the source register.

[0019] In a possible implementation of the second aspect, the remote execution unit is further configured to send error information to the processor when a permission check is performed on the atomic instruction and a check exception occurs, so that the error information is stored in the destination register.

[0020] In a possible implementation manner of the second aspect, the remote execution unit is a last-level cache or a local proxy.

[0021] In another aspect of the present application, an atomic instruction execution device is provided, which includes a processor and a memory, in which instructions are stored. When the processor runs the instruction, the device executes the atomic instruction execution method provided by the first aspect or any possible implementation of the first aspect.

[0022] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the atomic instruction execution method provided by the first aspect or any possible implementation of the first aspect is implemented.

[0023] In another aspect of the present application, a computer program product is provided, which includes a computer program or instructions. When the computer program or instructions are executed, the atomic instruction execution method provided by the first aspect or any possible implementation of the first aspect is implemented.

[0024] It can be understood that the beneficial effects that can be achieved by any of the atomic instruction execution devices, computer-readable storage media and computer program products provided above can correspond to the beneficial effects of the atomic instruction execution method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a processor system provided in an embodiment of the present application;

[0026] Figure 2 A flowchart of an atomic instruction execution method provided in an embodiment of the present application;

[0027] Figure 3 A flowchart of another atomic instruction execution method provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of an instruction encoding space provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of an atomic instruction execution device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will discuss in detail the making and use of various embodiments. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present application and technology and do not limit the scope of this application.

[0031] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0032] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0033] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0034] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0035] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0036] Due to the ever-increasing scale of application workloads and the limited processing power of a single processor, the parallelizable parts of the application workload are usually run on multiple processors to improve the execution performance of the application workload. However, inter-core data synchronization between multiple processors may become a bottleneck that restricts performance. Currently, atomic instructions are used to achieve data synchronization between multiple processors. For example, the ARM architecture provides LDEX, STEX, and other atomic instructions to facilitate programmers to complete the semantics related to atomic operations. The LDEX instruction is used to mark addresses that require exclusive access, and the STEX instruction is used to determine whether the marked address has been preempted by other processes.

[0037] In the instruction set, the operations that need to be completed by the atomic instruction, as well as the registers to be operated, are clearly defined. For example, the following instructions are proposed in ARMv8.1:

[0038] Compare and Swap instructions,CAS and CASP

[0039] Atomic memory operation instructions,LD <op>and ST <op>,where <op>is one of ADD, CLR, EOR, SET, SMAX, SMIN, UMAX, and UMIN

[0040] Swap instruction, SWP

[0041] However, the instruction encoding space of instruction sets under different processor systems is limited, usually 32 bits (bits), which imposes certain restrictions on the expansion of atomic instructions. Based on this, the embodiments of the present application provide an atomic instruction execution method and device that can be used to improve the scalability of atomic instructions.

[0042] The technical solution provided in the embodiment of the present application can be applied to a processor system, which can also be called a processor subsystem or a processing system. Figure 1 As shown, the processor system includes at least one processor cluster, a system cache, and a home agent (HA). The at least one processor cluster is coupled to the system cache, and the system cache is coupled to the home agent HA. Optionally, the system cache and the home agent can be collectively referred to as a remote execution unit.

[0043] In some embodiments, the system cache includes at least one last level cache (LLC). The at least one processor cluster can be coupled to the at least one LLC via a bus, and each LLC can be coupled to one or more processor clusters. The at least one LLC can be coupled to the HA via a bus, and the HA can serve as an agent for the at least one processor cluster. Each processor cluster in the at least one processor cluster includes one or more processors, and each processor includes a processing core (or core, also called a processor core) and a private cache. The private cache can include a first-level (level 1, L1) cache and a second-level cache (level 2, L2). The LLC can be called a shared cache, and different processors in the processor cluster coupled to the LLC can access the LL. For example, the LLC can be a third-level (level 3, L3) cache. Figure 1 The processor system including two processor clusters and two LLCs is used as an example for explanation.

[0044] Optionally, each processor cluster in the at least one processor cluster may include processors of the same type, or may include processors of different types. In practical applications, the processors may include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a digital signal processor (DSP), a network processor (NPU), an artificial intelligence (AI) processor, etc. Exemplarily, the at least one processor cluster includes a first processor cluster and a second processor cluster, and the first processor cluster and the second processor cluster both include multiple CPUs, or the first processor cluster includes multiple CPUs and the second processor cluster includes a GPU and an NPU.

[0045] Furthermore, the processor system also includes at least one memory, which may include an internal memory (referred to as memory). Optionally, the at least one memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. Exemplarily, the RAM may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0046] The processor system may be an electronic device, or a system on chip (SoC) or a chipset comprising multiple chips applied to an electronic device, or a module comprising the SoC or chipset. The electronic device may be used as a terminal device or a server. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptops, desktop computers, PDAs, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, camcorders, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electric meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as intelligent robots, hot air balloons, drones, airplanes), etc.

[0047] Figure 2 A flowchart of an atomic instruction execution method provided in an embodiment of the present application is provided. The method is applied to an atomic instruction execution device, which can be applied to the processor system provided above. The method includes the following steps.

[0048] S201: Acquire an atomic instruction, which includes first instruction information, and the first instruction information is used to indicate at least one of the following: an address register, a source register, and a destination register; the address register is used to store an address to be operated, and the source register is used to store an operand.

[0049] The atomic instruction execution device includes a processor, which is used to obtain the atomic instruction and decode the atomic instruction to obtain the first instruction information included in the atomic instruction. For example, the atomic instruction can be decoded by a decoder in the processor. The first instruction information can be the information carried in the instruction code of the atomic instruction. For example, the instruction code of the atomic instruction is 32 bits, and the first instruction information is the information carried in the 32 bits.

[0050] In one possible embodiment, the first instruction information is used to indicate the address register, the source register, and the destination register, for example, to indicate the locations of the above registers. Optionally, the first instruction information includes an identifier of the address register, an identifier of the source register, and an identifier of the destination register. Exemplarily, the identifier of the above register may be a register number or sequence number.

[0051] Among them, the address register is used to store the address to be operated, which is similar to the address of the existing atomic instruction, that is, the address that needs to perform the atomic operation, and the address can be used to generate one or more addresses, such as performing an operation on the address to generate multiple addresses through a certain operation method, so as to support the function of an atomic instruction to complete two or more atomic operations at the same time. The source register is used to store the operand, and the operand is the same as the operand type of the existing atomic instruction, that is, the operand of the atomic operation. The destination register can be used to store the execution result of the atomic instruction when it is executed normally, or to store error information when the atomic instruction is executed abnormally.

[0052] Optionally, the source register and / or the destination register include a fixed-point register (or general register), a vector register, a register pair (i.e., a pair of registers, including two registers), or a register group (i.e., a group of registers). In one example, the source register and the destination register are both fixed-point registers, vector registers, register pairs, or register groups. In another example, the destination register may be a conditional register storing NZCV, where NZVC refers to four flag bits, N, Z, C, and V, where N is a negative flag, Z is a zero flag, C is a carry flag, and V is an overflow flag.

[0053] S202: Obtain the address to be operated and the operand from the address register and the source register respectively according to the first instruction information.

[0054] In one possible embodiment, when the processor decodes the atomic instruction to obtain the first instruction information, the processor may determine the location of the address register and the location of the source register based on the first instruction information, and obtain the operation address from the address register and the operand from the source register. Exemplarily, the processor includes a decoder and a load storage unit (LSU). The decoder may send the location of the address register and the location of the source register to the LSU, and the LSU may obtain the operation address from the address register and the operand from the source register.

[0055] Optionally, obtaining the address to be operated and the operand according to the first instruction information may specifically include: if the first instruction information is used to indicate the address register, obtaining the address to be operated from the address register, or, if the first instruction information includes the address to be operated, obtaining the address to be operated from the first instruction information; if the first instruction information is also used to indicate the source register, obtaining the operand from the source register, or, if the first instruction information also includes the operand, obtaining the operand from the first instruction information; wherein, if the first instruction information does not indicate the destination register, the first instruction information also includes the storage address of the execution result.

[0056] S203: Execute the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and store the obtained execution result in the destination register.

[0057] In one possible embodiment, the processor executes the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, that is, performs an atomic operation on the address to be operated and the operand to obtain a first operation result; thereafter, the processor may store the first operation result as the execution result in the destination register. Optionally, when the address to be operated is also used to generate one or more addresses, the processor may also operate on the address to be operated in a certain operation mode to generate one or more addresses, and perform an atomic operation on the one or more addresses and the operand to obtain a second operation result; at this time, the processor may store the first operation result and the second operation result as the execution result in the destination register.

[0058] Optionally, the processor further includes an execution unit, and the decoder in the processor may further send the location of the destination register to an LSU in the processor. The LSU sends the location of the destination register to the execution unit, and the execution unit may specifically perform the aforementioned atomic operation and store the execution result in the destination register. Exemplarily, the execution unit may be a level 1 cache or a level 2 cache.

[0059] Furthermore, the first instruction information can also be used to provide other information. For example, the other information can include information about the relevant attributes of the atomic instruction. The relevant attributes can include memory model information and exception model information. The memory model information can include operation type, supported acquire / release attributes, and the exception model information can include permission check information. The embodiments of the present application do not limit the specific content of the other information.

[0060] In a possible embodiment, the first instruction information is further used to indicate an operation type, and the operation type is used to indicate that: the processor executes the atomic operation, or the remote execution unit in the instruction execution device executes the atomic operation. The operation type can be stored in the source register or carried in the first instruction information. The remote execution unit can be a last-level cache LLC or a local agent HA. In an application, when the atomic operation is executed by the processor, the operation type can also be called a near operation; when the atomic operation is executed by the remote execution unit, the operation type can also be called a far operation.

[0061] When the operation type is used to instruct the processor to perform the atomic operation, the processor may specifically perform step S203. The specific process of the processor performing step S203 can be found in the description above. When the operation type is used to instruct the remote execution unit to perform the atomic operation, the remote execution unit may specifically perform step S203. The specific process of the remote execution unit performing step S203 is described in detail below.

[0062] For example, Figure 3 As shown, when the operation type is used to instruct the remote execution unit to perform the atomic operation, the processor can send second instruction information to the remote execution unit according to the operation type after obtaining the address to be operated and the operand through step S202, and the second instruction information includes the address to be operated and the operand; when the remote execution unit receives the address to be operated and the operand, it executes the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and sends the execution result to the processor to store the execution result in the destination register. Figure 3 The processor sending the second instruction information to the remote execution unit is represented as S204.

[0063] In another possible embodiment, the first instruction information is also used to indicate permission check information, and the permission check information is used to indicate: the processor performs a permission check on the atomic instruction, the remote execution unit performs a permission check on the atomic instruction, or the processor and the remote execution unit perform a permission check on the atomic instruction (i.e., a mixed check). The permission check information can be stored in the source register or carried in the first instruction information. Optionally, the permission check can include read and write permission checks and whether the address attribute supports the atomic type, etc.

[0064] In one example, when the permission check information is used to instruct the processor to perform a permission check on the atomic instruction, after obtaining the atomic instruction, the processor can perform a permission check on the address to be operated, or on the address to be operated and one or more generated addresses according to the first instruction information, and execute the atomic operation if the check passes; if the check fails, an exception is reported. During this process, all operations of the remote execution unit will no longer generate any exceptions.

[0065] In another example, when the permission check information is used to instruct the remote execution unit to perform a permission check on the atomic instruction, the processor only performs address translation, such as translating the address to be operated from a virtual address to a physical address, and all permission checks are completed by the remote execution unit. When the remote execution unit performs a permission check on the atomic instruction and a check exception occurs, the remote execution unit sends an error message to the processor, which is stored in the destination register; or, the remote execution unit sends the error message to the processor, and the processor generates an upstream exception.

[0066] In another example, when the permission check information is used to instruct the processor and the remote execution unit to perform a permission check on the atomic instruction, the processor can complete a permission check on a certain address range (for example, performing a permission check on the address to be operated), and the remote execution unit can check whether the actual memory access address exceeds the address range (for example, checking whether one or more addresses generated by the address to be operated exceeds the address range).

[0067] It is understandable that the specific process of the processor and / or remote execution unit performing permission check on the atomic instruction can be referred to the description in the relevant technology, and the embodiments of the present application will not provide a specific description of this.

[0068] The relevant attributes of the above-mentioned atomic instruction can be partially or completely carried directly in the first instruction information, or partially or completely stored in the source register. In one example, the format of the atomic instruction is: address register + source register + destination register + at least part of the relevant attributes, and in this case, part or all of the information in the relevant attributes is carried in the first instruction information. In another example, the format of the atomic instruction is: address register + source register + destination register, and in this case, all of the information in the relevant attributes can be stored in the source register. The above-mentioned atomic instruction can also be called a general queue management (GQM) instruction.

[0069] To facilitate understanding, the atomic instructions in the embodiments of the present application and the execution process of the atomic instructions in the pipeline are illustrated below by way of examples.

[0070] Take the example of using ARM Reserved encoding space for IMPLEMENTATION DEFINEDinstructions encoding space to encode GQM instructions, such as Figure 4 As shown, the GQM instruction may include the following instruction fields:

[0071] <l>Release semantics,encoded as L

[0072] Acquire semantics,encoded as A

[0073] <rs>Status register,encoded as{s4,s3,s2,s1,s0}.Must be an even-numbered register.

[0074] <R(s+1)> Data register for pop

[0075] Command register,encoded as Rt.Must be an even-numbered register.

[0076] <R(t+1)> Data register for push

[0077] <Rn|SP> Address register,encoded as Rn

[0078] Among them, similar to CASP in the ARM instruction set, Rs and R(s+1) are the destination registers, Rt and R(t+1) are the source registers, and the corresponding instruction assembly code is as follows:

[0079] GQM operation no barrier(A==0&&L==0)

[0080] GQMOP <xs>,<X(s+1)>, <xt>,<X(t+1)>,[<Xn|SP>]

[0081] GQM operation with acquire semantic(A==1&&L==0)

[0082] GQMOPA <xs>,<X(s+1)>, <xt>,<X(t+1)>,[<Xn|SP>]

[0083] GQM operation with release semantic(A==0&&L==1)

[0084] GQMOPL <xs>,<X(s+1)>, <xt>,<X(t+1)>,[<Xn|SP>]

[0085] GQM operation with acquire and release semantics(A==1&&L==1)

[0086] GQMOPAL <xs>,<X(s+1)>, <xt>,<X(t+1)> ,[<Xn|SP> ]

[0087] For example,< / xt> < / xs> < / xt> < / xs> < / xt> < / xs> < / xt> < / xs> < / rs> Figure 5 As shown, taking the atomic instruction execution device including a processor and a remote execution unit, and the processor including a decoder, an LSU and an execution unit as an example, the execution process of the atomic instruction in the pipeline includes: 1. The decoder decodes the atomic instruction, obtains the location information of the address register, the source register and the destination register, and completes the relevant permission check; 2. The LSU receives the atomic instruction and the above-mentioned location information, and first performs a permission check on the address of the atomic instruction. The permission check may include read and write permission checks and whether the address attribute supports the atomic type, etc.; 3. When the LSU completes the relevant checks, according to the definition of the atomic instruction, the operation type and operand carried in the source register are sent to the corresponding execution unit; 4a. If the operation type supports local operation, the execution unit inside the processor receives and executes the atomic operation; 4b. If the operation type only supports remote operation, the remote execution unit receives and executes the atomic operation; 5. When the corresponding execution unit completes the atomic operation, the execution result (for example, execution status and return data) is updated to the destination register to complete all operations of the atomic instruction.

[0088] In an embodiment of the present application, the first instruction information included in the atomic instruction obtained by the device is used to indicate at least one of the address register, source register or destination register. The address register and the source register are used to store the address to be operated and the operand of the atomic instruction. The device can obtain the address to be operated and the operand from the address register and the source register respectively according to the first instruction information and perform the atomic operation. The execution result is stored in the destination register. In this way, by storing information such as the address to be operated, the operand and the execution result in the above three registers, there is no need to carry the address to be operated and the operand directly in the atomic instruction, thereby reducing the space occupied by the above information, and the larger register space can store more instruction information, thereby greatly improving the scalability of the atomic instruction.

[0089] Based on this, an embodiment of the present application also provides an atomic instruction execution device, which includes: a processor and a remote execution unit, and the remote execution unit can be a last-level cache or a local agent. The processor is used to: obtain an atomic instruction, and the atomic instruction includes first instruction information, and the first instruction information is used to indicate at least one of the following: an address register, a source register, and a destination register; according to the first instruction information, the address to be operated and the operand are respectively obtained from the address register and the source register; the processor or the remote execution unit is used to: execute the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and store the obtained execution result in the destination register. Optionally, the source register and / or the destination register include a fixed-point register, a vector register, a register pair, or a register group.

[0090] In one possible embodiment, the first instruction information is further configured to indicate an operation type, where the operation type indicates whether the processor or the remote execution unit should execute the atomic operation. The processor is further configured to, when the operation type indicates that the remote execution unit should execute the atomic operation, send second instruction information to the remote execution unit, where the second instruction information includes the address to be operated on and the operand. The remote execution unit is further configured to send the execution result to the processor, so that the execution result is stored in the destination register. Optionally, the operation type is stored in the source register.

[0091] In another possible implementation, the first instruction information is further used to indicate permission check information, and the permission check information is used to instruct: the processor to perform a permission check on the atomic instruction, the remote execution unit to perform a permission check on the atomic instruction, or the processor and the remote execution unit to perform a permission check on the atomic instruction. Optionally, the remote execution unit is further used to: when a permission check is performed on the atomic instruction and a check exception occurs, send an error message to the processor, so that the error message is stored in the destination register. Optionally, the permission check information is stored in the source register.

[0092] In another embodiment of the present application, an atomic instruction execution device is provided, comprising at least one processor and a memory, wherein the memory stores an instruction, and when the at least one processor executes the instruction, the device executes the atomic instruction execution method provided above. Optionally, the device may be a chip or an electronic device.

[0093] It can be understood that all relevant contents of each step involved in the above method embodiment can be referred to the embodiment of the device, and the embodiment of this application will not be repeated here.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0095] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0097] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, the atomic instruction execution method provided above is implemented.

[0098] In yet another aspect of the present application, a computer program product is provided. The computer program product includes a computer program or instructions. When the computer program or instructions are executed, the atomic instruction execution method provided above is implemented.

[0099] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.< / l> < / op> < / op> < / op>

Claims

1. A method for executing an atomic instruction, characterized in that: Applied to an instruction execution device, the method includes: Obtaining an atomic instruction, the atomic instruction including first instruction information, the first instruction information being used to indicate at least one of the following: an address register, a source register, and a destination register; wherein the address register is used to store an address to be operated, and the source register is used to store an operand; Acquire the address to be operated and the operand according to the first instruction information; The atomic operation corresponding to the atomic instruction is executed according to the address to be operated and the operand, and the obtained execution result is stored in the destination register.

2. The method according to claim 1, characterized in that The acquiring the address to be operated and the operand according to the first instruction information includes: If the first instruction information indicates the address register, then obtaining the address to be operated from the address register; or, if the first instruction information includes the address to be operated, then obtaining the address to be operated from the first instruction information; If the first instruction information further indicates the source register, the operand is obtained from the source register; alternatively, if the first instruction information further includes the operand, the operand is obtained from the first instruction information.

3. The method according to claim 1 or 2, characterized in that The source register and / or the destination register include a fixed-point register, a vector register, a register pair, or a register group.

4. The method according to any one of claims 1 to 3, characterized in that The instruction execution device includes a processor and a remote execution unit. The first instruction information is further used to indicate an operation type. The operation type is used to indicate: the processor executes the atomic operation, or the remote execution unit executes the atomic operation.

5. The method according to claim 4, characterized in that When the operation type is used to instruct the remote execution unit to perform the atomic operation, the method further includes: The processor sends second instruction information to the remote execution unit, where the second instruction information includes the address to be operated and the operand; The remote execution unit sends the execution result to the processor, so that the execution result is stored in the destination register.

6. The method according to claim 4 or 5, characterized in that The operation type is stored in the source register.

7. The method according to any one of claims 4 to 6, characterized in that The first instruction information is also used to indicate permission check information, and the permission check information is used to indicate: the processor performs a permission check on the atomic instruction, the remote execution unit performs a permission check on the atomic instruction, or the processor and the remote execution unit perform a permission check on the atomic instruction.

8. The method according to claim 7, characterized in that The method further comprises: When the remote execution unit performs a permission check on the atomic instruction and a check exception occurs, the remote execution unit sends error information to the processor, so that the error information is stored in the destination register.

9. The method according to claim 7 or 8, characterized in that The permission check information is stored in the source register.

10. The method according to any one of claims 4 to 9, characterized in that: The remote execution unit is a last-level cache or a local proxy.

11. An atomic instruction execution device, characterized in that: The device comprises: A processor is configured to obtain an atomic instruction, the atomic instruction including first instruction information, the first instruction information being configured to indicate at least one of the following: an address register, a source register, and a destination register; wherein the address register is configured to store an address to be operated, and the source register is configured to store an operand; The processor is further configured to obtain the address to be operated and the operand according to the first instruction information; The processor or remote execution unit is used to execute the atomic operation corresponding to the atomic instruction according to the address to be operated and the operand, and store the obtained execution result in the destination register.

12. The device according to claim 11, characterized in that The processor is further configured to: If the first instruction information is used to indicate the address register, the address to be operated is obtained from the address register; or, if the first instruction information includes the address to be operated, the address to be operated is obtained from the first instruction information; and / or, If the first instruction information is also used to indicate the source register, the operand is obtained from the source register; alternatively, if the first instruction information also includes the operand, the operand is obtained from the first instruction information.

13. The device according to claim 11 or 12, characterized in that The source register and / or the destination register include a fixed-point register, a vector register, a register pair, or a register group.

14. The device according to any one of claims 11 to 13, characterized in that The instruction execution device includes a processor and a remote execution unit. The first instruction information is further used to indicate an operation type. The operation type is used to indicate: the processor executes the atomic operation, or the remote execution unit executes the atomic operation.

15. The device according to claim 14, characterized in that When the operation type is used to instruct the remote execution unit to perform the atomic operation: The processor is further configured to send second instruction information to the remote execution unit, where the second instruction information includes the address to be operated and the operand; The remote execution unit is further configured to send the execution result to the processor so that the execution result is stored in the destination register.

16. The device according to claim 14 or 15, characterized in that The operation type is stored in the source register.

17. The device according to any one of claims 14 to 16, characterized in that The first instruction information is also used to indicate permission check information, and the permission check information is used to indicate: the processor performs a permission check on the atomic instruction, the remote execution unit performs a permission check on the atomic instruction, or the processor and the remote execution unit perform a permission check on the atomic instruction.

18. The device according to claim 17, characterized in that The remote execution unit is further configured to send error information to the processor when a permission check is performed on the atomic instruction and a check exception occurs, so as to store the error information in the destination register.

19. The device according to claim 17 or 18, characterized in that The permission check information is stored in the source register.

20. The device according to any one of claims 14 to 19, characterized in that The remote execution unit is a last-level cache or a local proxy.

21. An atomic instruction execution device, characterized in that: The device includes at least one processor and a memory, wherein instructions are stored in the memory. When the processor executes the instructions, the device executes the atomic instruction execution method according to any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program or instruction. When the computer program or instruction is executed, the atomic instruction execution method according to any one of claims 1 to 10 is implemented.

23. A computer program product, characterized in that The computer program product includes a computer program or instructions, and when the computer program or instructions are executed, the atomic instruction execution method according to any one of claims 1 to 10 is implemented.

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