Finite-state machine and data channel cooperative control method based on FPGA parallelism

Abstract

The invention discloses a finite-state machine and data channel cooperative control method based on FPGA parallel, and relates to the technical field of programming control. Comprising the following steps: S1, data transmission processing: performing transmission processing on to-be-programmed data through a set hardware architecture; s2, parallel data writing: copying the to-be-programmed data, transmitting the copied to-be-programmed data to a multi-station chip through a multi-channel IO (input / output) interface, and performing writing operation; and S3, data verification: comparing the reference data with write-in data in the FPGA parallel processing chip, and obtaining a final verification result of the FPGA parallel processing chip according to a comparison result. Through the hardware parallel characteristic of the FPGA parallel processing chip, synchronous data writing and verification of a multi-station chip are achieved, meanwhile, a linear process sequentially executed by a traditional MCU is eliminated, and through cooperative operation of a state machine and a data channel, multi-task parallel is achieved, and the effective utilization rate is improved.

Description

Technical Field

[0001] The present invention relates to the field of programming control technology, and in particular to a collaborative control method of a finite state machine and a data channel based on FPGA parallelism. Background Art

[0002] In the field of semiconductor chip programming, traditional programmers generally use a serial processing architecture based on MCU (microcontroller unit), but this technical solution is gradually unable to meet the needs of modern production. Current mainstream programmers have three fundamental flaws:

[0003] At the architectural level, the von Neumann architecture strictly follows a linear process of "data acquisition - chip writing - result verification." In traditional MCU architectures, each operation cycle can only service a single chip, resulting in 256 clock cycles (including 128 read cycles and 128 verification cycles) required to process a 128-byte data page.

[0004] At the hardware performance level, the 8 / 16-bit data bus width and the 50-100MHz clock frequency form a double bottleneck. Actual tests show that the system's effective data processing time is less than 45%, and more than 55% of the clock cycles are consumed in non-effective operations such as state switching and bus arbitration.

[0005] As chip capacity doubles every year in accordance with Moore's Law, the 15-20% annual performance improvement of traditional architecture is completely unable to match the production capacity demand. Therefore, when faced with large-capacity chips, the production capacity per unit time of traditional programmers is far from enough.

[0006] While existing multi-machine parallelization solutions can increase throughput, each additional workstation requires an additional $500-800 in hardware costs, and system complexity increases exponentially. Furthermore, clock overclocking only achieves a 50% speed increase over 100MHz, and also introduces significant power consumption and stability risks. Summary of the Invention

[0007] The purpose of the present invention is to provide a finite state machine and data channel collaborative control method based on FPGA parallelism to solve the problems of difficulty in multi-tasking parallelism and low effective utilization.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a finite state machine and data channel collaborative control method based on FPGA parallelism, comprising:

[0009] S1: Data transmission processing: The programming data is transmitted and processed through the set hardware architecture;

[0010] S2: Parallel data writing: copying the data to be programmed, and at the same time transmitting the copied data to be programmed to the multi-station chip through the multi-channel IO interface, and performing a write operation;

[0011] S3: Data verification: The reference data is compared with the written data in the FPGA parallel processing chip, and the final verification result of the FPGA parallel processing chip is obtained based on the comparison result.

[0012] Furthermore, the data to be programmed is transmitted and processed, including:

[0013] S1.1: Set up the hardware architecture: electrically connect the FPGA parallel processing chip, multi-station chip, data storage, and human-computer interaction module to the main controller;

[0014] S1.2: Data initialization: The data to be programmed is transmitted from the main controller to the FPGA parallel processing chip via a high-speed parallel bus, and the programming request signal from the main controller is detected when the FPGA parallel processing chip is in the State-Idle state.

[0015] S1.3: Data acquisition: According to the state switching of the FPGA parallel processing chip, the transmitted programming data is received, and according to the CRC check result of the programming data, the receiving time and serial number of the programming data are saved.

[0016] Furthermore, a high-frequency clock generator is provided inside the FPGA parallel processing chip, and the state cycle of each clock state machine is set according to the size of the main clock cycle.

[0017] Furthermore, according to the state cycle, the operation cycle is divided into a plurality of time segments, and the time segments are set in a one-to-one correspondence with the working states of the clock state machine.

[0018] Furthermore, the working states of the clock state machine include but are not limited to the State-Idle state, the State-GetData state and the State-WriteData state.

[0019] Furthermore, the reception time and serial number of the programming data are saved, including:

[0020] S1.3.1: CRC Check: Initialize the CRC register and obtain the CRC data of the programming data through the CRC register. Compare the CRC data with the received CRC data and determine the accuracy of the programming data based on the comparison result. Specifically:

[0021] When the CRC data is the same as the received CRC data, the programming data is correct, and the receiving time and serial number corresponding to the programming data are saved; otherwise, the programming data is incorrect and is retransmitted;

[0022] S1.3.2: Automatic retransmission: retransmit the programming data corresponding to the CRC data through the retransmission protocol, and repeat steps S1.3.1 and S1.3.2 until the programming data is correct.

[0023] Furthermore, the final verification results of the FPGA parallel processing chip are obtained, including:

[0024] S3.1: Data Reading: The reference data is transmitted to the FPGA parallel processing chip through the main controller. When the state of the FPGA parallel processing chip switches to the State-GetData state, the parallel read data of the multi-station chip is read.

[0025] S3.2: Data comparison: Compare the reference data and the parallel read data to obtain the comparison result of each station chip, and through the total verification result request, the main controller obtains the comparison results of all station chips.

[0026] Furthermore, the parallel read data in the workstation chip is compared bit by bit with the reference data to obtain the comparison result of the workstation chip. At the same time, when the state of the FPGA parallel processing chip is switched to the State-ldle state, steps S1 to S3 are repeated to obtain the comparison result of each of the workstation chips.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] First, the present invention uses the hardware parallel characteristics of the FPGA parallel processing chip to achieve synchronous data writing and verification of multi-station chips, thereby improving throughput. At the same time, it breaks away from the linear process of traditional MCU sequential execution, and realizes multi-tasking parallelism through the coordinated operation of the state machine and data channel, thereby improving effective utilization.

[0029] Second, the present invention uses FPGA parallel processing chips to support high-frequency clocks and wider data buses, thereby increasing data transmission rates. At the same time, the state machine divides the operation cycle into time segments that precisely correspond to the working state, reducing the ineffective time spent on state switching and bus arbitration, and maximizing the proportion of effective operations.

[0030] Third, the present invention utilizes internal data replication and a multi-channel IO interface within the FPGA parallel processing chip, enabling a single FPGA parallel processing chip to support multi-station parallel processing, thereby reducing hardware costs. Furthermore, the FPGA parallel processing chip integrates functional modules such as a high-frequency clock generator, CRC checksum, and automatic retransmission, thereby reducing reliance on external components.

[0031] Fourthly: The present invention can ensure the accuracy of data transmission through hardware-level CRC check and retransmission protocol, and erroneous data automatically triggers retransmission, thereby avoiding manual intervention and improving production yield. At the same time, when the current buffer receives data, the previous buffer data can be used directly, thereby realizing pipeline processing, reducing waiting time and enhancing stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a system block diagram of the hardware architecture of the present invention. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] refer to Figure 1 This embodiment provides a method for collaboratively controlling a finite state machine and a data channel based on FPGA parallelism. The method specifically includes the following steps:

[0035] Step S1: Data transmission processing. That is, the programming data is transmitted and processed through the set hardware architecture. The details are as follows:

[0036] Step S1.1: Set up the hardware architecture. Specifically, the hardware architecture is set up based on the main controller, FPGA parallel processing chip, multi-station chip, data storage, and human-computer interaction module. Specifically, the PGA parallel processing chip, multi-station chip, data storage, and human-computer interaction module are all electrically connected to the main controller, and the main controller exchanges information with the FPGA parallel processing chip, multi-station chip, data storage, and human-computer interaction module.

[0037] The main controller is an ARM processor, and the FPGA parallel processing chip uses a Xilinx Artix-7 / Kintex-7 series FPGA chip. The human-computer interaction module also includes, but is not limited to, an LCD display and buttons. Data information is visualized on the LCD, and controlled via buttons.

[0038] Specifically, the ARM processor serves as the main controller, responsible for overall task scheduling and human-computer interaction. The FPGA parallel processing chip is the parallel processing core, and a high-speed parallel bus connects the ARM processor and FPGA parallel processing chip. Furthermore, the ARM processor is equipped with a multi-channel IO interface, and each channel's IO interface is connected to a target chip station.

[0039] It is worth noting that the FPGA chip is equipped with a high-frequency clock generator inside, and the clock tree distribution network is used to ensure the synchronization between the main controller, FPGA parallel processing chip, multi-station chip, data storage and human-computer interaction module.

[0040] Furthermore, the clock cycle segments corresponding to each clock state machine are set to integer multiples of the master clock cycle, based on the master clock cycle. In other words, the FPGA chip divides the operating cycle into multiple time segments using the state cycles set by the state machines, and each time segment corresponds to an operating state, creating a one-to-one correspondence between time segments and operating states.

[0041] Step S1.2: Data initialization. That is, according to the high-speed parallel bus set in step S1.1, the data to be programmed is transmitted from the ARM processor to the FPGA chip, and the programming request signal of the ARM processor is detected in the State-Idle state of the FPGA chip.

[0042] Specifically, the programming file and target parameters are selected and set through the human-computer interaction module, and the ARM processor reads the programming data and reads the programming data from the built-in storage card into the memory buffer. At the same time, the memory buffer is transferred to the FPGA chip via a high-speed parallel bus. It is worth noting that during the data transfer between the memory buffer and the FPGA chip, the programming data is sent in batches according to the preset data packet size, and the programming data includes but is not limited to the control header frame containing the target address and data length information.

[0043] Furthermore, in the State-Idle state, the FPGA chip monitors the ARM request signal on the high-speed parallel bus in real time. Specifically, when the ARM request signal is detected, the FPGA chip's state machine engine is started and the transmitted programming data is transferred to the FPGA chip's buffer and status register.

[0044] Step S1.3: Data Acquisition. This involves receiving the transmitted programming data based on the FPGA chip's state transition. Furthermore, when the State-Idle state switches to the State-GetData state, the programming data in each buffer is saved based on the clock cycle size. Specifically, this embodiment employs a double buffering mechanism, whereby the current buffer receives the transmitted programming data in real time, while the programming data in the previous buffer can be used directly.

[0045] In this embodiment, the buffer performs a CRC check on the transmitted programming data and stores the reception time and sequence number of the programming data. The details are as follows:

[0046] Step S1.3.1: CRC check. This is to initialize the CRC register, process only one data word per clock cycle, perform data padding and byte alignment, and obtain the corresponding CRC data. Furthermore, the obtained CRC data is compared with the received CRC data, and the accuracy of the transmitted programming data is determined based on the comparison result. Specifically:

[0047] If the obtained CRC data is the same as the received CRC data, the transmitted programming data is correct, and the corresponding reception time and sequence number of the correct programming data are saved. If the obtained CRC data is different from the received CRC data, the transmitted programming data is incorrect, and the next step S1.3.2 is executed to retransmit.

[0048] Step S1.3.2: Automatic retransmission. That is, when the obtained CRC data is different from the received CRC data, the programming data corresponding to the CRC data is retransmitted using the configured retransmission protocol, and steps S1.3.1 and S1.3.2 are repeated until the transmitted programming data is correct.

[0049] Step S2: Parallel data writing. That is, according to the reception time and serial number of the programming data saved in step S1.3, the transmitted programming data is copied, and the copied programming data is simultaneously transmitted to the multi-station chip through the set multi-channel IO interface and written.

[0050] In this embodiment, when the FPGA chip switches to the State-WriteData state, the FPGA chip copies the received single programming data to obtain multiple copies of programming data. At the same time, through the multi-channel IO interface, the multiple copies of programming data are stored in the multi-station chip and written.

[0051] Step S3: Data verification. That is, the main controller compares the reference data with the written data in the FPGA chip. Based on the comparison result, the state of the FPGA chip switches to the State-Idle state, and steps S1 to S3 are repeated. The details are as follows:

[0052] Step S3.1: Data Reading. The master controller transmits the set reference data to the FPGA chip. The FPGA chip also divides the operating cycle into multiple time segments using a synchronous clock signal, with each time segment corresponding to an operating state of the finite state machine. It is worth noting that the operating states of the finite state machine include, but are not limited to, the State-Idle state, the State-GetData state, and the State-WriteData state.

[0053] Specifically, when the state of the FPGA chip switches to the State-GetData state, within the same clock cycle, the FPGA chip reads data from the multi-station chip in parallel and obtains the reference data transmitted by the main controller at the same time.

[0054] Step S3.2: Data Comparison. This involves comparing the reference data obtained in step S3.1 with the parallel read data, and obtaining the final overall verification result based on the comparison results. Specifically, the read data from the station chip is compared bit by bit with the reference data, and the corresponding comparison result for the station chip is obtained.

[0055] Furthermore, when the FPGA chip switches to the State-Idle state, steps S1 through S3 are repeated to obtain the comparison results for each station chip. It is worth noting that the main controller obtains the final verification result of the FPGA chip, i.e., the comparison results of all station chips, by reading the total verification result request.

[0056] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is limited by the accompanying embodiments and their equivalents.

Claims

1. A finite state machine and data channel collaborative control method based on FPGA parallelism, characterized in that: Includes: S1: Data transmission processing: The programming data is transmitted and processed through the set hardware architecture; S2: Parallel data writing: copying the data to be programmed, and at the same time transmitting the copied data to be programmed to the multi-station chip through the multi-channel IO interface, and performing a write operation; S3: Data verification: The reference data is compared with the written data in the FPGA parallel processing chip, and the final verification result of the FPGA parallel processing chip is obtained based on the comparison result.

2. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 1, characterized in that: Transmission processing of programming data, including: S1.1: Set up the hardware architecture: electrically connect the FPGA parallel processing chip, multi-station chip, data storage, and human-computer interaction module to the main controller; S1.2: Data initialization: The data to be programmed is transmitted from the main controller to the FPGA parallel processing chip via a high-speed parallel bus, and the programming request signal from the main controller is detected when the FPGA parallel processing chip is in the State-Idle state. S1.3: Data acquisition: According to the state switching of the FPGA parallel processing chip, the transmitted programming data is received, and according to the CRC check result of the programming data, the receiving time and serial number of the programming data are saved.

3. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 2, characterized in that: The FPGA parallel processing chip is internally provided with a high-frequency clock generator, and the state cycle of each clock state machine is set according to the size of the main clock cycle.

4. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 3, characterized in that: According to the state cycle, the operation cycle is divided into a plurality of time segments, and the time segments are set in a one-to-one correspondence with the working states of the clock state machine.

5. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 4, characterized in that: The working states of the clock state machine include but are not limited to the State-Idle state, the State-GetData state and the State-WriteData state.

6. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 2, characterized in that: Save the reception time and serial number of the programming data, including: S1.3.1: CRC Check: Initialize the CRC register and obtain the CRC data of the programming data through the CRC register. Compare the CRC data with the received CRC data and determine the accuracy of the programming data based on the comparison result. Specifically: When the CRC data is the same as the received CRC data, the programming data is correct, and the receiving time and serial number corresponding to the programming data are saved; Otherwise, the programming data is incorrect and needs to be retransmitted; S1.3.2: Automatic retransmission: retransmit the programming data corresponding to the CRC data through the retransmission protocol, and repeat steps S1.3.1 and S1.3.2 until the programming data is correct.

7. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 1, characterized in that: Obtain the final verification results of the FPGA parallel processing chip, including: S3.1: Data Reading: The reference data is transmitted to the FPGA parallel processing chip through the main controller. When the state of the FPGA parallel processing chip switches to the State-GetData state, the parallel read data of the multi-station chip is read. S3.2: Data comparison: Compare the reference data and the parallel read data to obtain the comparison result of each station chip, and through the total verification result request, the main controller obtains the comparison results of all station chips.

8. The FPGA-based parallel finite state machine and data channel collaborative control method according to claim 7, characterized in that: The parallel read data in the workstation chip is compared bit by bit with the reference data to obtain the comparison result of the workstation chip. At the same time, when the state of the FPGA parallel processing chip is switched to the State-ldle state, steps S1 to S3 are repeated to obtain the comparison result of each workstation chip.

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