Memory control device and memory

Abstract

The invention is suitable for the technical field of data storage, and provides a memory control device and a memory. The device comprises a selector and an arbiter, the selector is respectively connected with the multiple paths of HOST controllers through a PCIex4 channel, is connected with one NVMe SSD through the PCIex4 channel, and is used for selecting one path of HOST controller from the multiple paths of HOST controllers and enabling the path of HOST controller to be connected with the NVMe SSD through the PCIex4 channel; the arbiter is connected with the selector and controls the selector; and the arbiter determines a conduction path which is in PCIex4 connection with the NVMe SSD in the multi-path HOST controller through arbitration so as to obtain a conduction control signal, and sends the conduction control signal to the selector through a GPIO (General Purpose Input / Output) channel. The PCIex4 channel mapping method has the advantages that the PCIex4 channel is flexibly mapped to the required controller by arranging the selector and the arbiter which are matched with each other, the performance of the NVMe SSD is not lost, and the transmission rate is increased; through the arranged arbiter, the I2C channel is isolated, and the reliability of the system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data storage, and in particular relates to a memory control device and a memory. Background Art

[0002] NVMe solid-state drives (SSDs) are high-speed storage devices based on the NVMe (Non-Volatile Memory Express) protocol. Designed for solid-state drives (SSDs) connected via the PCIe bus, they enable high-speed data transfer via the PCIe interface. With the growing demand for data storage, NVMe SSDs are gaining widespread adoption due to their high performance and low latency.

[0003] NVMe drives connect to computer systems via the PCIe interface, enabling high-speed data transfer. However, in some application scenarios, it may be necessary to switch NVMe drives between different PCIe channels or devices to meet varying storage needs or improve system flexibility and scalability.

[0004] Currently, existing technical solutions have limitations when it comes to NVMe drive PCIe switching. For example, in a dual-controller all-flash system, a dual-port NVMe drive is connected to two controllers, and each controller can only access the NVMe drive via PCIe x2. Another example is that in a multi-controller all-flash system, data exchange is typically performed via a PCIe switch based on the dual controllers. Consequently, in some common applications, NVMe drive performance is compromised, and transmission channels are prone to hang-up failures.

[0005] Therefore, the existing control methods need to be further improved. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a memory control method, which aims to solve the problems of NVMe disk performance loss and transmission channel hang failure in the PCIe switching control of existing NVMe disks.

[0007] The embodiment of the present application is implemented by providing a memory control device, characterized in that the device includes:

[0008] Selectors and arbitrators;

[0009] The selector is connected to multiple HOST controllers through PCIex4 channels, and is connected to an NVMe SSD through PCIex4 channels. The selector is used to select one HOST controller from the multiple HOST controllers and connect it to the NVMe SSD through the PCIex4 channel;

[0010] The arbitrator is connected to the selector and controls the selector;

[0011] The arbiter determines the conduction path for PCIex4 connection with the NVMe SSD in the multi-channel HOST controller through arbitration, thereby obtaining a conduction control signal, and sends the conduction control signal to the selector through the GPIO channel.

[0012] Preferably, the arbitrator is a single chip microcomputer, and the arbitrator communicates with the upstream HOST control host through any one of Eth, UART and I2C channels.

[0013] Preferably, the selector is an ASIC or a high-speed FPGA.

[0014] Preferably, the arbitrator is also connected to the NVMe SSD, and obtains out-of-band information of the NVMe SSD through the I2C channel, and transmits the out-of-band information to the HOST control host.

[0015] Preferably, the outbound information includes at least one of the following information:

[0016] SSD manufacturer information, specifications, and operating status information.

[0017] Preferably, when the arbitrator obtains status abnormality information from the NVMe SSD, or when the HOST controller detects that the NVMe SSD is in an abnormal state, the arbitrator controls the NVMe SSD to power off or restart through the GPIO channel.

[0018] Preferably, the abnormal state includes but is not limited to temperature abnormality and / or IO abnormality.

[0019] Another object of an embodiment of the present application is to provide a memory, characterized in that the memory includes the memory control device as described above, and an NVMe SSD and several HOST controllers connected to the memory control device.

[0020] A memory control method provided by an embodiment of the present application has the following outstanding advantages: by setting a selector and an arbiter that cooperate with each other, the present application flexibly maps the PCIex4 channel to the required controller, without losing the performance of the NVMe SSD, improving the problem that the controller in the traditional dual-control environment can only obtain the PCIex2 performance of the NVMe disk and the bandwidth limitation of the shared channel of the PCIeSwitch chip, thereby improving the transmission rate; through the set arbiter, the I2C channel is isolated, so that the I2C hang of a single NVMe SSD will not affect the out-of-band access of other NVMe disks, thereby improving the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A structural block diagram of a memory control device provided in an embodiment of the present application;

[0022] Figure 2 A block diagram of a conventional memory structure provided in an embodiment of the present application;

[0023] Figure 3 This is a structural block diagram of another memory control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] It is understood that the terms "first," "second," and the like used herein may be used to describe various elements herein, but unless otherwise specified, these elements are not limited by these terms. These terms are only used to distinguish a first unit or module from another unit or module. For example, a first script may be referred to as a second script, and similarly, a second script may be referred to as a first script without departing from the scope of this application.

[0026] Figure 1 A schematic diagram of a memory control device provided in an embodiment of the present application, the device comprising:

[0027] Selectors and arbitrators;

[0028] The selector is connected to multiple HOST controllers through PCIex4 channels, and is connected to an NVMe SSD through PCIex4 channels. The selector is used to select one HOST controller from the multiple HOST controllers and connect it to the NVMe SSD through the PCIex4 channel;

[0029] The arbitrator is connected to the selector and controls the selector;

[0030] The arbiter determines the conduction path for PCIex4 connection with the NVMe SSD in the multi-channel HOST controller through arbitration, thereby obtaining a conduction control signal, and sends the conduction control signal to the selector through the GPIO channel.

[0031] Those skilled in the art will know that in the existing traditional dual-control full flash system, Figure 2As shown, with dual-port NVMe drives, each controller can only access the NVMe drive via PCIeX2. Furthermore, each NVMe SSD has only one I2C channel for out-of-band management, and simultaneous access by all controllers can easily lead to multi-master contention. Furthermore, in existing technologies, NVMe SSD I2C channels are often connected in series, often resulting in a single NVMe drive's I2C channel freezing, causing all NVMe drives in the system to freeze. Therefore, current control methods suffer from performance losses in NVMe drives and a high risk of transmission channel freezes.

[0032] In the embodiments of this application, Figure 1 As shown, the selector connects multiple host controllers and an NVMe SSD via PCIe x4 channels. Each host controller is connected to the selector via an independent PCIe x4 link, while the selector and the SSD are also connected via a PCIe x4 link. The core function of the selector is to dynamically switch the physical connection between the host controller and the NVMe SSD, ensuring that only one host is allowed to access the SSD at the full PCIe x4 bandwidth at a time. When the arbitrator issues a control signal, the selector connects the PCIe x4 channel of the selected host controller to the SSD, while the channels of other hosts are disconnected or idle. Compared to traditional dual-controller systems where each host can only access the SSD via PCIe x2, this solution allows a single host to exclusively use the PCIe x4 bandwidth, significantly improving data transfer rates.

[0033] In this embodiment of the present application, the arbiter determines the host currently granted access based on instructions from the host control console or a pre-defined control strategy, such as round-robin, load-awareness, or priority scheduling. It then sends a control signal to the selector via a general-purpose input / output (GPIO) channel, instructing it to switch physical connections. The arbiter continuously monitors access requests from each host, assesses system status in real time, and makes arbitration decisions. The arbitration results are encoded as GPIO signals, triggering the selector's channel switching action.

[0034] In this application's embodiment, the collaborative design of the selector and arbiter upgrades the NVMe SSD's PCIe access mode from static dual-port x2 allocation to dynamic single-port x4 exclusive access, significantly improving performance and resolving multi-master contention issues. Combined with potential I2C channel optimization, this enables the construction of a highly reliable, high-performance all-flash storage system suitable for demanding storage efficiency scenarios such as data centers and high-performance computing.

[0035] In a preferred embodiment, Figure 3As shown, the arbitrator is a single chip microcomputer, and the arbitrator communicates with the upstream HOST control host through any one of Eth, UART and I2C channels.

[0036] In an embodiment of the present application, a high-performance microcontroller with or supporting Eth, UART, and I2C communication interfaces can be selected, and support for GPIO high-speed control and multi-protocol communication is required. The HOST controller can send a request signal to the microcontroller through GPIO (such as pulling up the pin level) to trigger the microcontroller interrupt handler.

[0037] In a preferred embodiment, Figure 3 As shown, the selector is an ASIC or a high-speed FPGA.

[0038] In an embodiment of the present application, a PCIe Switch IP core can be set to support multiple PCIe x4 inputs from the HOST and a single PCIe x4 output to the SSD, and the switching path is configured through registers.

[0039] In a preferred embodiment, the arbitrator is also connected to the NVMe SSD, obtains out-of-band information of the NVMe SSD through an I2C channel, and transmits the out-of-band information to the HOST control host.

[0040] In this embodiment, the SSD's SMART log, health status, temperature, and other management information are acquired in real time via the I2C bus, which is independent of the PCIe data channel. The arbitrator, acting as an intermediate node, actively polls or receives I2C events from the SSD and then forwards the information to the host control host.

[0041] In this embodiment, independent I2C channels prevent congestion in the PCIe main channel from interfering with management information transmission, ensuring real-time monitoring of SSD status even under high loads. The arbiter, a dedicated management node, periodically verifies SSD health, reducing the monitoring burden on the host. In a traditional serial I2C architecture, a single drive failure can paralyze the entire channel. In this solution, the arbiter provides a direct point-to-point connection with the SSD, preventing fault propagation. Preferably, the arbiter integrates I2C master control functionality, eliminating the need for the host to directly manage the SSD's I2C interface and reducing system complexity.

[0042] In a preferred embodiment, the outbound information includes at least one of the following information:

[0043] SSD manufacturer information, specifications, and operating status information.

[0044] In this embodiment of the present application, external information may include, but is not limited to, static data such as SSD model, firmware version, capacity, and interface protocol support; and one or more dynamic indicators such as temperature, wear (P / E cycles), bad block count, and I / O error rate. The host control unit can automatically load the optimal driver or firmware based on manufacturer information, reducing manual intervention. Operational status data can provide a basis for resource scheduling.

[0045] In a preferred embodiment, when the arbitrator obtains status abnormality information from the NVMe SSD, or when the HOST controller detects that the NVMe SSD is in an abnormal state, the arbitrator controls the NVMe SSD to power off or restart through the GPIO channel.

[0046] In an embodiment of the present application, the arbitrator can make decisions based on active detection of abnormal events reported by the SSD read by I2C, or passive notifications such as when the HOST controller detects no response from the SSD or I / O timeout through the PCIe link, to control the NVMe SSD to power off or restart.

[0047] The advantage of this embodiment is that abnormal SSDs can be immediately isolated, preventing persistent errors such as overheating and data corruption from affecting other components or causing an avalanche effect. Furthermore, combined with status monitoring and arbitration logic, a fully closed-loop automation system from detection to recovery is achieved, enhancing system autonomy.

[0048] In a preferred embodiment, the abnormal state includes but is not limited to temperature abnormality and / or IO abnormality.

[0049] In this embodiment, overheating can prevent NAND flash memory lifespan degradation or controller frequency reduction, ensuring performance and reliability. Data transmission errors can be blocked promptly to avoid silent data corruption. The integrated physical and logical states provide a more comprehensive basis for fault diagnosis.

[0050] In one embodiment, a memory is provided, characterized in that the memory includes the memory control device as described above, and an NVMe SSD and several HOST controllers connected to the memory control device.

[0051] In this embodiment, independent I2C out-of-band management combined with hardware-level fault isolation significantly reduces the impact of single points of failure. Real-time monitoring and automated recovery reduce the need for manual maintenance, making it suitable for unattended scenarios. The control methods for the NVMe SSD and multiple host controllers connected to the memory control device are described above and will not be repeated here.

[0052] The advantage of this memory is that by setting up a selector and arbitrator that cooperate with each other, the PCIex4 channel is flexibly mapped to the required controller, without losing the performance of the NVMe SSD. This improves the problem that the controller in the traditional dual-control environment can only obtain the PCIex2 performance of the NVMe disk and the bandwidth limitation of the shared channel of the PCIe Switch chip, thereby increasing the transmission rate; through the set arbitrator, the I2C channel is isolated, so that the I2C hang of a single NVMe SSD will not affect the out-of-band access of other NVMe disks, thereby improving the reliability of the system.

[0053] It should be understood that, although each step in the flow chart of each embodiment of the present application is shown in sequence according to the indication of the arrow, these steps are not necessarily performed in sequence according to the order indicated by the arrow. Unless there is clear explanation in this article, the execution of these steps does not have strict order restriction, and these steps can be performed in other orders. Moreover, at least a portion of the steps in each embodiment may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these sub-steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0054] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. As an illustration and not limitation, RAM is available in many forms.

[0055] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A memory control device, characterized in that: The device comprises: Selectors and arbitrators; The selector is connected to multiple HOST controllers through PCIex4 channels, and is connected to an NVMe SSD through PCIex4 channels. The selector is used to select one HOST controller from the multiple HOST controllers and connect it to the NVMe SSD through the PCIex4 channel. The arbitrator is connected to the selector and controls the selector; The arbiter determines the conduction path for PCIex4 connection with the NVMe SSD in the multi-channel HOST controller through arbitration, thereby obtaining a conduction control signal, and sends the conduction control signal to the selector through the GPIO channel.

2. The memory control device according to claim 1, wherein: The arbitrator is a single chip microcomputer, and the arbitrator communicates with the upstream HOST control host through any one of Eth, UART and I2C channels.

3. The memory control device according to claim 1, wherein: The selector is an ASIC or a high-speed FPGA.

4. The memory control device according to claim 2, wherein: The arbitrator is also connected to the NVMe SSD, and obtains the out-of-band information of the NVMe SSD through the I2C channel, and transmits the out-of-band information to the HOST control host.

5. The memory control device according to claim 4, wherein: The outbound information includes at least one of the following information: SSD manufacturer information, specifications, and operating status information.

6. The memory control device according to claim 4, wherein: When the arbitrator obtains the abnormal status information sent by the NVMe SSD, or when the HOST controller detects that the NVMe SSD is in an abnormal state, the arbitrator controls the NVMe SSD to power off or restart through the GPIO channel.

7. The memory control device according to claim 6, wherein: The abnormal state includes but is not limited to temperature abnormality and / or IO abnormality.

8. A memory, characterized in that: The memory includes a memory control device as described in any one of claims 1 to 7, and an NVMe SSD and several HOST controllers connected to the memory control device.

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