Multi-core inter-core communication method, electronic device, readable medium and computer program product

Abstract

The invention provides a multi-core inter-core communication method which is applied to a multi-core processor, at least two of a plurality of processing cores are configured to share the same communication module, the communication module is configured with a plurality of interrupts, and each of the at least two processing cores corresponds to one interrupt and serves as a receiving party processing core of the interrupt; the communication module is configured with at least one channel; under the condition that the interrupted sender processing core sends target information to the interrupted receiver processing core, the interrupted sender processing core determines a target communication module; and the interrupted sender processing core writes the target information into a target channel in the target communication module, and triggers a universal interrupt controller to which the target communication module belongs to send an interrupt message to the interrupted receiver processing core, so that the interrupted receiver processing core reads the target information from the target channel according to the interrupt message. The invention further provides electronic equipment, a readable medium and a computer program product.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a multi-core inter-core communication method, electronic device, readable medium, and computer program product. Background Art

[0002] With the continuous advancement of advanced technologies and the increasing demands of practical applications, traditional embedded devices using single-core processors are no longer able to meet performance requirements. Currently, a variety of multi-core chips have emerged, integrating high-performance microprocessors and highly real-time microcontrollers. To achieve synchronous and coordinated multi-core operation, inter-core communication is required to achieve multi-core collaborative processing.

[0003] The basic technical requirements for multi-core inter-core communication are real-time notification and information transfer. Based on these requirements, current implementations rely on a combination of software and hardware. The hardware provides a message interrupt mechanism to achieve real-time notification, while the software implements the communication protocol to standardize the message transfer model.

[0004] In terms of hardware implementation, the relevant technology is primarily based on a one-way, point-to-point approach. Each pair of communicating processing cores requires two Mailbox hardware modules. For multi-core chips with a large number of processing cores, the number of Mailbox hardware modules increases exponentially with the number of cores, increasing chip design costs. Furthermore, the number of communication channels between different processing cores varies significantly in different business scenarios, resulting in significant waste of hardware resources. Summary of the Invention

[0005] The present disclosure provides a multi-core inter-core communication method, an electronic device, a readable medium, and a computer program product.

[0006] In a first aspect, an embodiment of the present disclosure provides a multi-core inter-core communication method, which is applied to a multi-core processor, wherein the multi-core processor includes multiple processing cores, at least two of the multiple processing cores are configured to share a common communication module, the communication module is configured with multiple interrupts, and each of the at least two processing cores corresponds to one of the interrupts, serving as a receiving processing core of the interrupts; the communication module is configured with at least one channel, and the channel is used for communication between the at least two processing cores, or between the at least two processing cores and other cores of the multiple processing cores; the method includes:

[0007] In the case where the interrupt sender processing core sends target information to the interrupt receiver processing core, the interrupt sender processing core determines a target communication module, where the target communication module is a communication module configured by the interrupt receiver processing core;

[0008] The interrupt sender processing core writes the target information into a target channel in the target communication module, triggering the universal interrupt controller to which the target communication module belongs to send an interrupt message to the interrupt receiver processing core; the target channel is one of the channels;

[0009] The interrupt receiving processing core reads the target information from the target channel according to the interrupt message.

[0010] In a second aspect, an embodiment of the present disclosure further provides an electronic device comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, the multi-core inter-core communication method as described above is implemented.

[0011] In a third aspect, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, which implements the multi-core inter-core communication method as described above when the computer program is executed by a processor.

[0012] In a fourth aspect, an embodiment of the present disclosure further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the multi-core inter-core communication method as described above.

[0013] The multi-core inter-core communication method of the embodiment of the present disclosure is applied to a multi-core processor, at least two processing cores among the multiple processing cores are configured to share the same communication module, the communication module is configured with multiple interrupts, each of the at least two processing cores corresponds to one said interrupt, and serves as the receiving processing core of the interrupt; the communication module is configured with at least one channel, and the channel is used for communication between the at least two processing cores, or between the at least two processing cores and other cores among the multiple processing cores; when the sending processing core of the interrupt sends target information to the receiving processing core of the interrupt, the sending processing core of the interrupt determines the target communication module; the sending processing core of the interrupt writes the target information to the target channel in the target communication module, triggering the general interrupt controller to which the target communication module belongs to send an interrupt message to the receiving processing core of the interrupt, so that the receiving processing core of the interrupt reads the target information from the target channel according to the interrupt message; by supporting multiple processing cores by a single communication module and determining the channel for inter-core communication based on communication requirements, the number of hardware components of the communication module can be reduced, hardware resource waste can be avoided, the cost of multi-core chips and multi-core communication can be reduced, and the efficiency of multi-core communication can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the accompanying drawings of the embodiments of the present disclosure:

[0015] Figure 1 A schematic diagram of the structure of a multi-core processor in related technology;

[0016] Figure 2 A schematic diagram of the structure of a multi-core processor provided in an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of a multi-core inter-core communication method according to an embodiment of the present disclosure;

[0018] Figure 4 A schematic diagram of the ZIPC protocol provided in an embodiment of the present disclosure;

[0019] Figure 5 A schematic diagram of a process for transmitting target information using a target channel based on the Zipc protocol provided in an embodiment of the present disclosure;

[0020] Figure 6 A schematic diagram of using a target channel to transmit target information based on the Zipc protocol provided in an embodiment of the present disclosure;

[0021] Figure 7 A schematic block diagram of the electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0023] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0024] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0025] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0026] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0027] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0029] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0030] In some related technologies, multi-core inter-core communication is based on a point-to-point unidirectional implementation mode, and each pair of communicating processing cores requires two Mailbox hardware modules to achieve communication. Figure 1 A schematic diagram of the structure of a multi-core processor of related technology is shown in FIG. Figure 1 As shown, the multi-core system is integrated into a System-on-Chip (SOC) and includes processing cores Core1-N, Mailbox1-N, a Network-on-Chip (NoC), and a Generic Interrupt Controller (GIC). Each processing core is installed with an operating system (OS), such as Linux, Baremetal, or RTOS. The Mailbox is a hardware peripheral specifically designed for inter-core communication. Each processing core is equipped with a GIC and a Mailbox. Core1-N uses the Mailbox for inter-core communication, generating interrupt messages that are sent to the GIC. The NoC is the SOC system bus, connecting various devices and responsible for transmitting data, addresses, and control information.

[0031] In areas such as smart cockpits and smart homes that use multi-core chips, the amount of Mailbox hardware will grow exponentially with the number of processing cores. In different business scenarios, the number of communication channels between different processing cores also varies significantly. Therefore, related technologies will result in a large waste of hardware resources, increase chip design costs and the cost of communication between multi-cores.

[0032] In order to solve the above technical problems, the embodiment of the present disclosure provides a multi-core inter-core communication method in which a single Mailbox supports multiple processing cores. The multi-core inter-core communication method is applied to a multi-core processor, and at least two processing cores among the multiple processing cores are configured to share the same communication module. The communication module is configured with multiple interrupts, and each of the at least two processing cores corresponds to an interrupt, serving as the receiving processing core of the corresponding interrupt. In the embodiment of the present disclosure, the communication module is described as a Mailbox as an example. The Mailbox serves as a hardware mechanism for inter-processor process synchronization and data exchange in a multi-core processor system. It carries a small block of memory and does not occupy system memory. In-band data transmission or out-of-band data transmission can be achieved through its registers.

[0033] The communication module is configured with at least one channel, which is used for communication between at least two processing cores, or between at least two processing cores and other cores in a plurality of processing cores. In Mailbox channel allocation, the number of channels between the sending and receiving processing cores is pre-agreed based on business needs. At least two processing cores are configured to share the same communication module, allowing a single Mailbox hardware unit to support communication between multiple pairs of processing cores, thereby reducing the amount of Mailbox hardware in the SOC. This reduction in the amount of Mailbox hardware can also reduce Mailbox initialization time and lower the cost of multi-core chips, thereby achieving efficient and low-cost multi-core inter-core communication.

[0034] Figure 2 A schematic diagram of the structure of a multi-core processor provided in an embodiment of the present disclosure. Figure 2The multi-core processor shown includes six processing cores, Cores 1-6. Cores 0, 1, and 2 are configured to share Mailbox 0; Cores 3 and 4 are configured to share Mailbox 1; and Cores 5 and 6 are configured to share Mailbox 2. Mailbox 0 is affiliated with GIC 0, Mailbox 1 is affiliated with GIC 1, and Mailbox 2 is affiliated with GIC 2. Mailbox 0 is configured with three interrupts whose recipient processing cores are Core 0, Core 1, and Core 2, respectively; Mailbox 1 is configured with two interrupts whose recipient processing cores are Core 3 and Core 4, respectively; and Mailbox 2 is configured with two interrupts whose recipient processing cores are Core 5 and Core 6, respectively. Mailbox 0, Mailbox 1, and Mailbox 2 are configured with at least one channel.

[0035] Figure 3 A flow chart of a multi-core inter-core communication method provided in an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the multi-core inter-core communication method includes the following steps:

[0036] Step S11 : When the interrupted sending processing core sends target information to the interrupted receiving processing core, the interrupted sending processing core determines a target communication module, where the target communication module is a communication module configured by the interrupted receiving processing core.

[0037] Since multiple processing cores share one communication module, in this step, the target communication module can be determined according to the corresponding relationship between the receiving processing core and the communication module.

[0038] Step S12 , the interrupt sender processing core writes the target information into the target channel in the target communication module, triggering the universal interrupt controller to which the target communication module belongs to send an interrupt message to the interrupt receiver processing core; the target channel is one of the channels.

[0039] The target channel is the channel configured between the interrupt's sending and receiving processing cores. It is one of the channels configured in the communication module. In the disclosed embodiment, the channel is a mailbox register. When the interrupt's sending processing core transmits data to the receiving processing core, the interrupt's sending processing core writes the target information, which is the data to be transmitted, into the interrupt's mailbox's target channel. In this case, the GIC to which the mailbox belongs sends an interrupt message to the interrupt's receiving processing core, triggering the interrupt.

[0040] Step S13: the interrupt receiving processing core reads target information from the target channel according to the interrupt message.

[0041] After receiving the interrupt message, the interrupt receiver processing core performs interrupt processing, that is, accesses the target channel of the corresponding Mailbox and reads the target information from it.

[0042] The following combination Figure 2 , the multi-core inter-core communication process of the embodiment of the present disclosure is described in detail. Figure 2 As shown in the figure, if a core (Core3, Core4, Core5, or Core6) in a multi-core processor sends an interrupt and wants to transfer data to a core (Core0, Core1, or Core2) that receives the interrupt, the sending core writes the target information to the target channel of Mailbox0 via GIC0, thereby triggering an interrupt. This interrupt is then sent to the receiving core (Core0, Core1, or Core2) via GIC0. After receiving the interrupt, the receiving core accesses the target channel of Mailbox0 to read the target information.

[0043] The multi-core inter-core communication method of the embodiment of the present disclosure is applied to a multi-core processor, at least two processing cores among the multiple processing cores are configured to share the same communication module, the communication module is configured with multiple interrupts, each of the at least two processing cores corresponds to one said interrupt, and serves as the receiving processing core of the interrupt; the communication module is configured with at least one channel, and the channel is used for communication between the at least two processing cores, or between the at least two processing cores and other cores among the multiple processing cores; when the sending processing core of the interrupt sends target information to the receiving processing core of the interrupt, the sending processing core of the interrupt determines the target communication module; the sending processing core of the interrupt writes the target information to the target channel in the target communication module, triggering the general interrupt controller to which the target communication module belongs to send an interrupt message to the receiving processing core of the interrupt, so that the receiving processing core of the interrupt reads the target information from the target channel according to the interrupt message; by supporting multiple processing cores by a single communication module and determining the channel for inter-core communication based on communication requirements, the number of hardware components of the communication module can be reduced, hardware resource waste can be avoided, the cost of multi-core chips and multi-core communication can be reduced, and the efficiency of multi-core communication can be improved.

[0044] In some embodiments, after the interrupt receiving processing core reads the target information from the target channel according to the interrupt message (i.e., step S13), the multi-core inter-core communication method may further include the following steps: clearing the target information in the target channel. In other words, after the interrupt processing is completed, the interrupt is cleared.

[0045] In the related art, the software for multi-core inter-core communication is implemented based on shared memory and inter-core interrupts. The shared memory technology mainly includes inter-core communication technology based on Remote Processor Messaging (Rpmsg). Rpmsg is a mechanism that provides communication (Inter-Process Communication, IPC) functions between the kernel driver of the main operating system (for example, Linux) and the remote processor. Inter-core interrupts are implemented using Mailbox, which realizes multi-core inter-core communication by transmitting control information. Inter-core communication is realized based on RPMsg+Mailbox. RPMsg manages shared memory in the form of queues, writes specific queue IDs into the Mailbox register and generates inter-core interrupts. However, the shared memory managed by the queue has a data volume limit, and can only realize 512 bytes of data transmission at a time. When large amounts of data communication are required, the efficiency of multi-core inter-core communication will be affected.

[0046] To address the aforementioned technical issues, the disclosed embodiment no longer utilizes Rpmsg technology, but instead directly utilizes Mailbox to implement multi-core inter-core communication. This improves inter-core communication efficiency by directly writing target information to the target channel of Mailbox, rather than managing shared memory through queues. This eliminates the need to record and manage queue IDs.

[0047] In some embodiments, the target information is first target information or second target information, the first target information at least includes information of shared memory in the multi-core processor, the second target information does not include information of shared memory in the multi-core processor, and the second target information is business data or preset indication information.

[0048] When the target information is the first target information, the interrupted sending core and the receiving core transmit the data to be transmitted through the "in-band + out-of-band" transmission method. The "in-band + out-of-band" transmission method refers to a data transmission method that uses a channel to transmit shared memory information and obtains the data to be transmitted from the shared memory according to the shared memory information.

[0049] When the target information is the second target information, the interrupted sending core and receiving core use in-band transmission to transfer the data. In-band transmission uses a channel to transmit the data, without the involvement of shared memory. There are two types of in-band transmission: one is to transmit actual business data, in which the data to be transmitted is business data; the other is to transmit indication information, in which the data to be transmitted is preset indication information, such as notification messages or special signals.

[0050] In related technologies, there are two main types of mailbox transmission protocols: the doorbell protocol, which uses virtual channels and stipulates that a service can only use one virtual channel; the data-transfer protocol, which uses physical channels and allows a service to use multiple physical channels. However, a service can only use one protocol, and once the channel and protocol are determined for a service, that channel cannot be used for other services, reducing channel utilization.

[0051] In order to solve the above problems, the embodiments of the present disclosure provide a new Mailbox communication protocol, namely the zipc protocol. The zipc protocol adopts a combination of physical channels and virtual channels to improve channel utilization and achieve conflict-free communication between multiple processing cores in multiple business scenarios.

[0052] In some embodiments, the channel may include n physical channels, where n is an integer greater than or equal to 2, the n physical channels include a designated channel and (n-1) transmission channels, the designated channel is divided into p virtual channels, where p is the number of services processed by the multi-core processor and p is an integer greater than or equal to 2, and one service corresponds to one virtual channel.

[0053] The number n of physical channels is determined according to the size of the target information. Specifically, the number n of physical channels can be calculated according to the following formula: number n of physical channels - 1 = size of target information / capacity of physical channel.

[0054] Figure 4 A schematic diagram of the zipc protocol provided in the embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the multi-core processor can handle 32 services, that is, p = 32. Accordingly, the designated channel is divided into 32 virtual channels 0-31, each of which can support the above 32 services. The capacity of the (n-1) transmission channels is the same and is the same as the capacity of the designated channel. In the embodiment of the present disclosure, the capacity of each physical channel is 32 bits.

[0055] Figure 5 The following is a flow chart of transmitting target information using a target channel based on the zipc protocol provided in the embodiment of the present disclosure, as shown in FIG. Figure 5 As shown, in some embodiments, when the target information is first target information or service data, the interrupted sender processing core writes the target information into the target channel in the target communication module (i.e., step S12), including the following steps:

[0056] Step S121, determine whether all (n-1) transmission channels are empty. If all (n-1) transmission channels are empty, execute step S122; if at least one transmission channel is not empty, wait for a preset time and then determine whether all (n-1) transmission channels are empty. Execute step S122 until all (n-1) transmission channels are empty.

[0057] Step S122: The interrupted sending processing core writes the target information into the (n-1) transmission channels in the target communication module.

[0058] In some embodiments, different services time-multiplex at least part of the (n-1) transmission channels.

[0059] Step S123 : setting a target virtual channel in the designated channel as a target tag, where the target virtual channel is a virtual channel corresponding to the service to which the target information belongs.

[0060] After step S123 is executed, an interrupt is triggered.

[0061] If the transmission mode between the interrupted sender processing core and the receiver processing core is "in-band + out-of-band" or "in-band", it means that data needs to be transmitted through the transmission channel. Therefore, the target information of the current business will be written into the (n-1) transmission channels only when there is no data to be transmitted in the (n-1) transmission channels (that is, the (n-1) transmission channels are all empty). In other words, after the data of the previous business (that is, the target information) is transmitted, the data of the next business is transmitted, which can ensure the accuracy of data transmission. In some embodiments, it is possible to determine whether the (n-1) transmission channels are empty by polling. When at least one transmission channel is not empty, it is determined whether the (n-1) transmission channels are all empty after waiting for a preset period of time. Until the (n-1) transmission channels are all empty, the interrupted sender processing core writes the target information into the (n-1) transmission channels of the corresponding Mailbox. After the target information is written into the (n-1) transmission channels of the target communication module, the bit of the virtual channel corresponding to the current service in the specified channel is set as the target mark, for example, set to 1, indicating that the in-band data of the current service has been transmitted, and the current service is the service to which the target information belongs.

[0062] The Zipc protocol uses a combination of physical and virtual channels. A physical channel is divided into p virtual channels, which can support p inter-core communication services. If in-band data is transmitted, it is written to (n-1) physical transmission channels. All p services can use these physical transmission channels for in-band data transmission, thereby improving channel utilization. Therefore, the disclosed embodiments can enable processing cores to reuse the same transmission channel to transmit data for different services, further improving channel utilization.

[0063] In some embodiments, the first target information may include information about shared memories in multiple multi-core processors. When the target information is the first target information, the interrupted sender processing core writes the target information to a target channel in the target communication module (i.e., step S12), including the following steps: the interrupted sender processing core writes the information about shared memories in the multiple multi-core processors to each (n-1) transmission channel in the target communication module, wherein the information about shared memories in each multi-core processor is written to each transmission channel. In other words, during out-of-band transmission, information about different types of shared memories can be written to different transmission channels.

[0064] In some embodiments, the first target information may include: high-order address information of the shared memory in the multi-core processor, low-order address information of the shared memory in the multi-core processor, data length information and flag information of the shared memory in the multi-core processor.

[0065] Figure 6 The schematic diagram of using a channel to transmit target information based on the zipc protocol provided in the embodiment of the present disclosure is as follows: Figure 6 and Figure 2 The process of transmitting target information through (n-1) transmission channels is described in detail.

[0066] by Figure 2 Taking Mailbox0 as an example, the channel allocation, interrupts, and the relationship between the interrupt sender processing core and the receiver processing core of Mailbox0 are shown in Table 1:

[0067] Table 1

[0068]

[0069] Table 1 shows that Mailbox0 is configured with three interrupts. The receiving cores for these three interrupts are Core 0, Core 1, and Core 2, respectively. For example, when Core 2 is the receiving core, the sending cores are multiple cores: Core 0, Core 1, and Cores 3-6. Assume that inter-core communication requires in-band transmission of 128-bit data. This 128-bit data includes: 64-bit shared memory address information (the upper 32 bits are the shared memory high address addr_high, and the lower 32 bits are the shared memory low address addr_low); 32-bit shared memory data length len; and 32-bit flag flag. Assuming that each sending core (Core 0, Core 1, Core 3-6) communicates with Core 2 using five of the Mailbox's physical channels, a total of 30 physical channels are required. Different sending cores communicate with Core 2 using one interrupt, int_to_cpu2.

[0070] For example, in the int_to_cpu2 interrupt, the sender processing core is Core 0 and the receiver processing core is Core 2. The corresponding channels include chan10-14, a total of 5 physical channels, among which chan10 is the designated channel and chan11-14 are transmission channels. Figure 6 As shown, the low-order address addr_low of the 32-bit shared memory in the 128-bit data is transferred to chan11 of Mailbox0; the high-order address addr_high of the 32-bit shared memory in the 128-bit data is transferred to chan12 of Mailbox0; the data length len of the 32-bit shared memory in the 128-bit data is transferred to chan13 of Mailbox0; and the 32-bit flag flag in the 128-bit data is transferred to chan14 of Mailbox0.

[0071] If Core 0 and Core 2 need to communicate with multiple services but only have five channels, the zipc protocol is used. The zipc protocol divides the designated channel chan10 into 32 virtual channels, each corresponding to 32 services. This allows up to 32 services to communicate between Core 0 and Core 2. In-band data for different services between Core 0 and Core 2 can be written to the four transmission channels, chan11-14, in a time-sharing manner. When a service requests a mailbox channel, it is assigned a specific virtual channel. The interrupt mechanism is triggered by setting the corresponding virtual channel to 1'b1, thus enabling inter-core communication.

[0072] In some embodiments, when the target information is preset indication information, the interrupted sender processing core and the receiving processing core transmit the indication information via an "in-band" transmission method. In this case, the target channel may include a designated channel, and the designated channel is configured as p virtual channels, where p is the number of services processed by the multi-core processor and p is an integer greater than or equal to 2, and one service corresponds to one virtual channel. That is, when the interrupted sender processing core and the receiving processing core transmit the indication information via an "in-band" transmission method, there is no need to use a transmission channel, so the channel may only include one designated channel and no transmission channel. Accordingly, the interrupted sender processing core writes the target information into the target channel in the target communication module (i.e., step S12), comprising the following steps: the interrupted sender processing core sends the target information to the target communication module and sets the target virtual channel in the designated channel of the target channel as a target flag; the target virtual channel is the virtual channel corresponding to the service to which the target information belongs. That is, the interrupted sender processing core directly sends the target information to the target communication module and sets the bit position of the virtual channel corresponding to the current service in the designated channel as the target flag, for example, to 1.

[0073] The disclosed embodiments provide a multi-core inter-core communication method. In Mailbox channel allocation, the number of channels between processing cores is pre-agreed based on business requirements. All channels are allocated according to communication needs. Each channel specifies a sending processing core and a receiving processing core, enabling the same Mailbox hardware to support multiple processing cores. This reduces the amount of Mailbox hardware in the SOC and fully utilizes Mailbox channels, reducing chip costs and space. The disclosed embodiments also provide a new Mailbox communication protocol that combines physical and virtual channels. A pair of processing cores can reuse physical channels for in-band data transmission of different services, improving channel utilization. Virtual channels are used to implement an interrupt mechanism for conflict-free inter-core communication.

[0074] The disclosed embodiments are applicable to scenarios where multi-core chips and multiple processors work together, specifically in products such as smart cockpits and smart homes. Each processing core, after determining a communication channel, uses shared memory with inter-core interrupts. The shared memory provides a channel for information exchange, while the inter-core interrupts provide an event notification mechanism based on the channel configuration, achieving efficient inter-core communication.

[0075] The present disclosure also provides an electronic device, Figure 7 A schematic block diagram of the electronic device provided in the embodiment of the present disclosure is shown in FIG. Figure 7As shown, the electronic device includes a memory 1 and a processor 2; the memory 1 stores a computer program that can be executed by the processor 2, and when the computer program is executed by the processor, any multi-core inter-core communication method of the embodiments of the present disclosure is implemented.

[0076] Among them, the processor 2 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information interaction between the memory and the processor, including but not limited to a data bus (Bus), etc.

[0077] An embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any one of the multi-core inter-core communication methods of the embodiment of the present disclosure.

[0078] An embodiment of the present disclosure further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements any multi-core inter-core communication method of the embodiment of the present disclosure.

[0079] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0080] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0081] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0082] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A multi-core inter-core communication method, applied to a multi-core processor, the multi-core processor comprising a plurality of processing cores, at least two of the plurality of processing cores being configured to share a common communication module, the communication module being configured with a plurality of interrupts, each of the at least two processing cores corresponding to one of the interrupts, serving as a receiving processing core for the corresponding interrupt; the communication module being configured with at least one channel, the channel being used for communication between the at least two processing cores, or between the at least two processing cores and other processing cores in the plurality of processing cores; the method comprising: In the case where the interrupt sender processing core sends target information to the interrupt receiver processing core, the interrupt sender processing core determines a target communication module, where the target communication module is a communication module configured by the interrupt receiver processing core; The interrupt sender processing core writes the target information into a target channel in the target communication module, triggering the universal interrupt controller to which the target communication module belongs to send an interrupt message to the interrupt receiver processing core; the target channel is one of the channels; The interrupt receiving processing core reads the target information from the target channel according to the interrupt message.

2. The method according to claim 1, wherein After the interrupt receiver processing core reads the target information from the target channel according to the interrupt message, the method further includes: Clear the target information in the target channel.

3. The method according to claim 1, wherein The target information is first target information or second target information, the first target information at least includes information about shared memory in the multi-core processor, the second target information does not include information about shared memory in the multi-core processor, and the second target information is business data or preset indication information.

4. The method according to claim 3, wherein: The target information is first target information or service data, the channel includes n physical channels, where n is an integer greater than or equal to 2, the n physical channels include a designated channel and (n-1) transmission channels, the designated channel is divided into p virtual channels, where p is the number of services processed by the multi-core processor and p is an integer greater than or equal to 2, and one service corresponds to one virtual channel; The interrupt sender processing core writes the target information into the target channel in the target communication module, including: When the (n-1) transmission channels are all empty, the interrupted sending processing core writes the target information into the (n-1) transmission channel in the target communication module; A target virtual channel in the designated channel is set as a target tag, where the target virtual channel is a virtual channel corresponding to the service to which the target information belongs.

5. The method according to claim 4, wherein The interrupted sender processing core writes the target information into the target channel in the target communication module, further comprising: When at least one of the transmission channels is not empty, it is determined whether the (n-1) transmission channels are all empty after waiting for a preset period of time, and until the (n-1) transmission channels are all empty, the interrupted sender processing core writes the target information into the (n-1) transmission channels in the target communication module.

6. The method according to claim 4 or 5, wherein: The target information is the first target information, and the first target information includes information of multiple shared memories in the multi-core processor; The interrupt sender processing core writes the target information into the target channel in the target communication module, including: The interrupt sender processing core writes the information of the shared memory in the various multi-core processors into each of the (n-1) transmission channels in the target communication module, wherein the information of the shared memory in one multi-core processor is written into one transmission channel.

7. The method according to claim 6, wherein: The first target information includes: high-order address information of the shared memory in the multi-core processor, low-order address information of the shared memory in the multi-core processor, data length information and flag information of the shared memory in the multi-core processor.

8. The method according to claim 4, wherein Different services time-division multiplex at least part of the (n-1) transmission channels.

9. The method according to claim 3, wherein: The target information is preset indication information, the target channel includes a designated channel, the designated channel is a physical channel and the designated channel is divided into p virtual channels, p is the number of services processed by the multi-core processor and p is an integer greater than or equal to 2, and one service corresponds to one virtual channel; The interrupt sender processing core writes the target information into the target channel in the target communication module, including: The interrupt sender processing core sends the target information to the target communication module and sets the target virtual channel in the designated channel as a target mark; The target virtual channel is a virtual channel corresponding to the service to which the target information belongs.

10. The method according to any one of claims 1 to 9, wherein: The communication module is a Mailbox module.

11. An electronic device comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the multi-core inter-core communication method according to any one of claims 1 to 10.

12. A computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the multi-core inter-core communication method according to any one of claims 1 to 10 is implemented.

13. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the multi-core inter-core communication method according to any one of claims 1 to 10 is implemented.

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