Direct connection between network interface and graphics processing unit in self-hosted mode in multiprocessor system

Abstract

The invention relates to a direct connection between a network interface and a graphics processing unit in a self-hosted mode in a multiprocessor system. Various embodiments include techniques for performing data transfer operations via a direct interconnect between a network interface and a graphics processor in a multiprocessor system, the multiprocessor system further including a central processing unit (CPU). A CPU communicates with a graphics processor via a dedicated high bandwidth interconnect with a memory in the graphics processor and a second interconnect with the graphics processor for various utility functions. The network interface communicates with the graphics processor via an interconnect with a memory in the graphics processor. The interconnection between the network interface and the graphics processor does not affect the throughput of the high bandwidth interconnection from the CPU to the graphics processor, thereby improving the performance of the CPU to the graphics processor. In addition, the interconnection between the CPU and the graphics processor does not affect the throughput of the interconnection from the network interface to the graphics processor, thereby improving the performance from the network interface to the graphics processor.

Description

Technical Field

[0001] Various embodiments relate generally to computer system architecture, and more particularly to a direct connection between a network interface and a graphics processing unit in a self-hosted mode in a multi-processor system. Background Art

[0002] A computing system typically includes one or more processing units (such as a central processing unit (CPU) and / or a graphics processing unit (GPU)), one or more memory systems, and one or more networks, among others. The processing unit executes a user-mode software application that submits and initiates a computing task to be executed on one or more computing engines included in the processing unit. In operation, the processing unit loads data from one or more memory systems, performs various arithmetic and logical operations on the data, and stores the data back to one or more memory systems. One way in which the processing unit can communicate with the memory system is through a network interface card (NIC). The NIC provides an interface between the processing unit and the memory system through various network interface protocols, including Ethernet, Peripheral Component Interconnect Express (PCIe), and the like.

[0003] In computing systems deployed for high-performance data centers, cloud computing, and / or other applications, a NIC can communicate with a GPU to share data, synchronize computational stages, and start new work for the GPU, the NIC, other devices in the system, and / or similar devices. In some examples, the NIC can communicate with the GPU via direct memory access (DMA) data transfers. Therefore, computing workloads in computing systems with many GPUs, CPUs, NICs, and / or other devices can benefit when the GPU and NIC communicate efficiently. In some typical self-hosted system configurations, the NIC can communicate with the GPU via the CPU. The GPU can communicate with the CPU via multiple interconnects, such as a high-bandwidth chip-to-chip (C2C) interconnect for data transfer and a lower-bandwidth interconnect, such as PCIe, for performing configuration operations, control operations, register read and / or write operations, interrupt operations, etc. The NIC can communicate with the CPU via a second, lower-bandwidth interconnect, such as PCIe. In some examples, the throughput of the high-bandwidth C2C interconnect can be up to ten times the throughput of the low-bandwidth interconnect. In one specific example, the high-bandwidth C2C interconnect can have a maximum throughput of approximately 640 gigabytes per second (GB / s) in each direction, while the low-bandwidth interconnect can have a maximum throughput of approximately 64 GB / s in each direction. The NIC can communicate with the GPU via a combination of the low-bandwidth interconnect between the NIC and the CPU and the high-bandwidth interconnect between the CPU and the GPU.

[0004] A problem with this approach to data communication between the NIC and the GPU is that throughput is limited to the lowest bandwidth interconnect. In some examples, the second lowest bandwidth interconnect between the NIC and the CPU can be a fifth generation (Gen 5) PCIe interconnect, which has a raw throughput of approximately 64 GB / s in each direction. The NIC can be upgraded to support a sixth generation (Gen 6) PCIe interconnect, which has a raw throughput of approximately 128 GB / s in each direction. However, if the CPU is not similarly upgraded, the throughput between the NIC and the CPU will be limited by the lower bandwidth 64 GB / s Gen 5 PCIe interconnect on the CPU. Since the NIC to GPU communication goes through the CPU, the throughput between the NIC and the GPU is also limited by the lower bandwidth 64 GB / s Gen 5 PCIe interconnect on the CPU.

[0005] Another problem with this approach to data communication between the NIC and GPU is that the high-bandwidth C2C interconnect between the GPU and the CPU is shared among multiple uses, including DMA communication between the NIC and GPU, input / output (I / O) communication between the CPU and GPU, and data transfer between the GPU and system memory on the CPU. Therefore, the bandwidth consumed by the NIC on the high-bandwidth C2C interconnect reduces the remaining bandwidth available for the C2C interconnect for other purposes, resulting in reduced performance.

[0006] As previously stated, what is needed in the art are more efficient techniques for communicating data in computing systems. Summary of the Invention

[0007] Various embodiments of the present disclosure describe a computer-implemented method for performing a data transfer operation in a multiprocessor system. The method includes: accessing, by a network controller, a first memory of a first processor via a first interconnect using a first address mapping. The method further includes: accessing, by a second processor, the first memory of the first processor via a second interconnect using a second address mapping. The method further includes: accessing, by the second processor, the second memory of the first processor via a third interconnect. In the method, the first interconnect is coupled to the third interconnect.

[0008] Other embodiments include, but are not limited to, systems that implement one or more aspects of the disclosed technology, one or more computer-readable media including instructions for performing one or more aspects of the disclosed technology, and methods for performing one or more aspects of the disclosed technology.

[0009] At least one technical advantage of the disclosed technology over the prior art is that, using the disclosed technology, the NIC can communicate with the GPU via a direct interconnect at a higher data transfer rate than conventional techniques that transfer data between the NIC and the GPU through the CPU. Because the NIC transfers data directly to the GPU, throughput is not limited by the lower bandwidth interconnect on the CPU. Furthermore, because the NIC does not consume bandwidth on the CPU interconnect, the CPU can perform data transfers and other data operations at a higher throughput than conventional techniques that share CPU interconnect bandwidth with NIC data transfers. These advantages represent one or more technical improvements over prior art approaches. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to understand the relevant features of the various embodiments described above in more detail, the inventive concept briefly summarized above may be described in more detail with reference to various embodiments (some of which are illustrated in the accompanying drawings). However, it should be noted that the accompanying drawings illustrate only typical embodiments of the inventive concept and are not intended to limit the scope in any way, and other equally effective embodiments may exist.

[0011] Figure 1 is a block diagram of a computing system configured to implement one or more aspects of various embodiments;

[0012] Figure 2 According to various embodiments, Figure 1 A block diagram of a parallel processing unit (PPU) in an accelerator processing subsystem;

[0013] Figure 3 According to various embodiments, Figure 2 A block diagram of a general processing cluster (GPC) in a parallel processing unit (PPU);

[0014] Figure 4 is a block diagram of a system having a single NIC module and a single PPU module, the single NIC module and the single PPU module having a direct interconnection according to various embodiments;

[0015] Figure 5 is a block diagram of a system having two NIC modules and two PPU modules with direct interconnection according to various embodiments; and

[0016] Figure 6 is a flow chart of method steps for transferring data between a NIC and a PPU, according to various embodiments. DETAILED DESCRIPTION

[0017] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of various embodiments. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0018] System Overview

[0019] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of various embodiments. As shown, computing system 100 includes, but is not limited to, a central processing unit (CPU) 102, a system memory 104, which is coupled to an accelerator processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is further coupled to an I / O (input / output) bridge 107 via a communication path 106, which is in turn coupled to a switch 116.

[0020] In operation, I / O bridge 107 is configured to receive user input information from input device 108 (such as a keyboard or mouse) and forward the input information to CPU 102 via communication path 106 and memory bridge 105 for processing. In some examples, input device 108 is used to verify the identity of one or more users so as to allow authorized users to access computing system 100 and deny unauthorized users access to computing system 100. Switch 116 is configured to provide connections between I / O bridge 107 and other components of computing system 100, such as network adapter 118 and various add-in cards 120 and 121. In some examples, network adapter 118 serves as a primary input device or a dedicated input device for receiving input data for processing by the disclosed technology.

[0021] As also shown, the I / O bridge 107 is coupled to a system disk 114, which can be configured to store content, applications, and data for use by the CPU 102 and the accelerator processing subsystem 112. Generally, the system disk 114 provides non-transitory storage for applications and data and can include fixed or removable hard drives, flash memory devices, and CD-ROMs (Compact Disc Read Only Memory), DVD-ROMs (Digital Versatile Disk-ROMs), Blu-rays, HD-DVDs (High Definition DVDs), or other magnetic, optical, or solid-state storage devices. Finally, although not explicitly shown, other components (such as a universal serial bus or other port connection, an optical disc drive, a digital versatile disk drive, a film recording device, etc.) can also be connected to the I / O bridge 107.

[0022] In various embodiments, memory bridge 105 may be a northbridge chip, and I / O bridge 107 may be a southbridge chip. Furthermore, communication paths 106 and 113, as well as other communication paths within computing system 100, may be implemented using any technically suitable protocol, including but not limited to Peripheral Component Interconnect Express (PCIe), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0023] In some embodiments, the accelerator processing subsystem 112 includes a graphics subsystem that delivers pixels to the display device 110, which can be any conventional cathode ray tube, liquid crystal display, light emitting diode display, etc. In such embodiments, the accelerator processing subsystem 112 incorporates circuits optimized for graphics and video processing, including, for example, video output circuitry. Figure 2 As described in more detail in , such circuits may be combined across one or more accelerators included in the accelerator processing subsystem 112. An accelerator includes any one or more processing units that can execute instructions, such as a central processing unit (CPU), Figures 2 to 4 Parallel processing unit (PPU), graphics processing unit (GPU), direct memory access (DMA) unit, intelligent processing unit (IPU), neural processing unit (NPU), tensor processing unit (TPU), neural network processor (NNP), data processing unit (DPU), vision processing unit (VPU), application-specific integrated circuit (ASIC), field programmable gate array (FPGA), etc.

[0024] In some embodiments, the accelerator processing subsystem 112 incorporates circuitry optimized for general-purpose and / or computational processing. Similarly, such circuitry may be combined across one or more accelerators included in the accelerator processing subsystem 112, which are configured to perform such general-purpose and / or computational operations. In other embodiments, one or more accelerators included in the accelerator processing subsystem 112 may be configured to perform graphics processing, general-purpose processing, and computational processing operations. System memory 104 includes at least one device driver 103 configured to manage processing operations of one or more accelerators in the accelerator processing subsystem 112.

[0025] In various embodiments, the accelerator processing subsystem 112 may be configured to Figure 1100. The accelerator processing subsystem 112 may be integrated with one or more other elements of the accelerator processing subsystem 112 to form a single system. For example, the accelerator processing subsystem 112 may be integrated with the CPU 102, the memory bridge 105, the I / O bridge 107, and / or other components and connecting circuits on a single chip to form a system on a chip (“SoC”). Additionally or alternatively, these various components may be integrated on multiple chips in the form of chiplets and / or dielets. As described herein, chiplets and dielets are small integrated circuits in which each performs a defined set of functions. Multiple chiplets and dielets may be combined to form multi-chip modules or hybrid integrated circuits that perform more advanced functions. For example, multiple chiplets and dielets may be combined to form the computing system 100. The interconnect circuitry on the SoC, chiplets, and / or dielets facilitates communication between various components, including the CPU, GPU, auxiliary processors, video and / or audio streaming devices, network adapters, and / or similar components.

[0026] It should be understood that the system shown herein is illustrative and that variations and modifications are possible. The connection topology (including the number and arrangement of bridges, the number of CPUs 102, and the number of accelerator processing subsystems 112) can be modified as needed. For example, in some embodiments, the system memory 104 can be directly connected to the CPU 102, rather than being connected to the CPU 102 through the memory bridge 105, and other devices will communicate with the system memory 104 via the memory bridge 105 and the CPU 102. In other alternative topologies, the accelerator processing subsystem 112 can be connected to the I / O bridge 107 or directly to the CPU 102, rather than being connected to the memory bridge 105. In still other embodiments, the I / O bridge 107 and the memory bridge 105 can be integrated into a single chip, rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more of the components shown may not be present. For example, switch 116 may be eliminated, and network adapter 118 and add-in cards 120 , 121 may be connected directly to I / O bridge 107 .

[0027] Figure 2 According to various embodiments Figure 1 A block diagram of a parallel processing unit (PPU) 202 included in the accelerator processing subsystem 112 of FIG. Figure 2 While one PPU 202 is depicted, as described above, the accelerator processing subsystem 112 may include any number of PPUs 202. Figure 2 PPU 202 is Figure 1The accelerator processing subsystem 112 is one example of an accelerator included in the accelerator. Alternative accelerators include, but are not limited to, a CPU, a GPU, a DMA unit, an IPU, an NPU, a TPU, an NNP, a DPU, a VPU, an ASIC, an FPGA, and / or the like. Figures 2 to 4 The techniques disclosed in

[15] regarding the PPU 202 are equally applicable to any type of accelerator included in the accelerator processing subsystem 112, in any combination. As shown, the PPU 202 is coupled to a local parallel processing (PP) memory 204. The PPU 202 and the PP memory 204 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a memory device, or in any other technically feasible manner.

[0028] In some embodiments, PPU 202 includes a graphics processing unit ("GPU") that can be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by CPU 102 and / or system memory 104. When processing graphics data, PP memory 204 can be used as graphics memory to store one or more conventional frame buffers (and, if desired, one or more other render targets). PP memory 204 can be used to, among other things, store and update pixel data and transmit the final pixel data, or display frame, to display device 110 for display. In some embodiments, PPU 202 can also be configured for general processing and computational operations.

[0029] In operation, CPU 102 is the main processor of computing system 100, controlling and coordinating the operations of other system components. In particular, CPU 102 issues commands that control the operation of PPU 202. In some embodiments, CPU 102 writes a command stream for PPU 202 into a data structure ( Figure 1 or Figure 2 102 and PPU 202). In some embodiments, the data structure may be located in system memory 104, PP memory 204, or another storage location accessible to both CPU 102 and PPU 202. Additionally or alternatively, a processor and / or accelerator other than CPU 102 may write one or more command streams from PPU 202 to the data structure. A pointer to the data structure is written to a push buffer to initiate processing of the command stream in the data structure. PPU 202 reads the command stream from the push buffer and then executes the commands asynchronously with respect to the operation of CPU 102. In embodiments where multiple push buffers are generated, the application may specify an execution priority for each push buffer via device driver 103 to control the scheduling of the different push buffers.

[0030] As also shown, PPU 202 includes an I / O (input / output) unit 205, which communicates with the rest of computing system 100 via communication path 113 and memory bridge 105. I / O unit 205 generates data packets (or other signals) for transmission on communication path 113, and also receives all incoming data packets (or other signals) from communication path 113, directing the incoming data packets to the corresponding components of PPU 202. For example, commands related to processing tasks may be directed to host interface 206, while commands related to memory operations (e.g., reading from or writing to PP memory 204) may be directed to crossbar unit 210. Host interface 206 reads each push buffer and sends the command stream stored in the push buffer to front end 212.

[0031] As above combined Figure 1 As described above, the connection between PPU 202 and the rest of computing system 100 can vary. In some embodiments, accelerator processing subsystem 112 (which includes at least one PPU 202) is implemented as an add-in card that can be inserted into an expansion slot of computing system 100. In other embodiments, PPU 202 can be integrated on a single chip using a bus bridge, such as memory bridge 105 or I / O bridge 107. Likewise, in other embodiments, some or all elements of PPU 202 can be included with CPU 102 in a single integrated circuit or system on a chip (SoC).

[0032] In operation, the front end 212 sends processing tasks received from the host interface 206 to a work distribution unit (not shown) within the task / work unit 207. The work distribution unit receives pointers to processing tasks, which are encoded as task metadata (TMD) and stored in memory. The pointer to the TMD is included in a command stream, which is stored as a push buffer and received by the front end 212 from the host interface 206. The processing tasks that can be encoded as TMDs include indexes associated with the data to be processed, as well as state parameters and commands that define how to process the data. For example, the state parameters and commands can define the program to be executed on the data. The task / work unit 207 receives tasks from the front end 212 and ensures that the GPC 208 is configured to a valid state before initiating the processing tasks specified by each TMD. A priority can be assigned to each TMD, which is used to schedule the execution of the processing tasks. Processing tasks can also be received from the processing cluster array 230. Optionally, the TMD may include a parameter that controls whether the TMD is added to the head or tail of a list of processing tasks (or a list of pointers to processing tasks), thereby providing another level of control over execution priority.

[0033] PPU 202 advantageously implements a highly parallel processing architecture based on a processing cluster array 230, which includes a set of C general processing clusters (GPCs) 208, where C ≥ 1. Each GPC 208 is capable of executing a large number (e.g., hundreds or thousands) of threads simultaneously, where each thread is an instance of a program. In various applications, different GPCs 208 can be assigned to process different types of programs or perform different types of computations. The assignment of GPCs 208 can vary depending on the workload generated by each type of program or computation.

[0034] The memory interface 214 includes a set of D partition units 215, where D ≥ 1. Each partition unit 215 is coupled to one or more dynamic random access memories (DRAMs) 220 residing within the PP memory 204. In one embodiment, the number of partition units 215 is equal to the number of DRAMs 220, with each partition unit 215 coupled to a different DRAM 220. In other embodiments, the number of partition units 215 may differ from the number of DRAMs 220. Those skilled in the art will recognize that the DRAMs 220 may be replaced with any other technically suitable memory device. In operation, various render targets (such as texture maps and frame buffers) may be stored across the DRAMs 220, allowing the partition units 215 to write portions of each render target in parallel, thereby efficiently utilizing the available bandwidth of the PP memory 204.

[0035] A given GPC 208 can process data to be written to any DRAM 220 in PP memory 204. The crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or any other GPC 208 for further processing. The GPCs 208 communicate with the memory interface 214 via the crossbar unit 210 to read from or write to the various DRAMs 220. In one embodiment, the crossbar unit 210 is connected to the I / O unit 205 in addition to being connected to the PP memory 204 via the memory interface 214, thereby enabling processing cores in different GPCs 208 to communicate with the system memory 104 or other memory that is not local to the PPU 202. Figure 2 In an embodiment, crossbar unit 210 is directly connected to I / O unit 205. In various embodiments, crossbar unit 210 can separate traffic flows between GPCs 208 and partition units 215 using virtual channels.

[0036] Likewise, the GPCs 208 can be programmed to perform processing tasks associated with various applications, including, but not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physical laws to determine the position, velocity, and other properties of an object), image rendering operations (e.g., tessellation shading programs, vertex shading programs, geometry shading programs, and / or pixel / fragment shading programs), general-purpose compute operations, etc. In operation, the PPU 202 is configured to transfer data from the system memory 104 and / or the PP memory 204 to one or more on-chip memory units, process the data, and write the resulting data back to the system memory 104 and / or the PP memory 204. The resulting data can then be accessed by other system components (including the CPU 102, another PPU 202 in the accelerator processing subsystem 112, or another accelerator processing subsystem 112 in the computing system 100).

[0037] As described above, any number of PPUs 202 may be included in the accelerator processing subsystem 112. For example, multiple PPUs 202 may be provided on a single add-in card, or multiple add-in cards may be connected to the communication path 113, or one or more PPUs 202 may be integrated into a bridge chip. The PPUs 202 in a multi-PPU system may be identical to or different from one another. For example, different PPUs 202 may have different numbers of processing cores and / or different amounts of PP memories 204. In implementations where multiple PPUs 202 are present, these PPUs may operate in parallel to process data at a higher throughput than would be possible with a single PPU 202. Systems including one or more PPUs 202 may be implemented in a variety of configurations and form factors, including but not limited to desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, gaming consoles, embedded systems, and the like.

[0038] Figure 3 According to various embodiments Figure 2208 . In operation, the GPC 208 can be configured to execute a large number of threads in parallel to perform graphics, general processing and / or computing operations. As used herein, a "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a general instruction unit configured to issue instructions to a group of processing engines in the GPC 208. Unlike a SIMD execution architecture (in which all processing engines generally execute the same instruction), SIMT execution allows different threads to more easily follow different execution paths through a given program. It should be appreciated by those skilled in the art that a SIMD processing architecture represents a functional subset of a SIMT processing architecture.

[0039] The operation of GPC 208 is controlled via pipeline manager 305, which distributes processing tasks received from work distribution units (not shown) within task / work units 207 to one or more streaming multiprocessors (SMs) 310. Pipeline manager 305 can also be configured to control work distribution crossbar 330 by specifying the destination of processed data output by SM 310.

[0040] In one embodiment, the GPC 208 includes a set of M SMs 310, where M ≥ 1. In addition, each SM 310 includes a set of function execution units (not shown), such as execution units and load-store units. The processing operations specific to any function execution unit can be pipelined, allowing new instructions to be issued for execution before previous instructions have completed execution. Any combination of function execution units in a given SM 310 can be provided. In various embodiments, the function execution units can be configured to support a variety of different operations, including integer and floating-point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (e.g., AND, OR, XOR), bit shifts, and calculations of various algebraic functions (e.g., planar interpolation and trigonometric functions, exponential functions, logarithmic functions, etc.). Advantageously, the same function execution unit can be configured to perform different operations.

[0041] In operation, each SM 310 is configured to process one or more thread groups. As used herein, a "thread group" or "warp" refers to a group of threads that concurrently execute the same program on different input data, with a thread in the group assigned to a different execution unit in the SM 310. A thread group may include fewer threads than the number of execution units in the SM 310, in which case some execution units may be idle during cycles while the thread group is being processed. A thread group may also include more threads than the number of execution units in the SM 310, in which case processing may occur in consecutive clock cycles. Since each SM 310 can support up to G thread groups simultaneously, up to G*M thread groups may be executing in a GPC 208 at any given time.

[0042] In addition, multiple related thread groups can be active (in different stages of execution) simultaneously in an SM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array." The size of a particular CTA is equal to m*k, where k is the number of concurrently executing threads in the thread group, which is typically an integer multiple of the number of execution units in the SM 310, and m is the number of concurrently active thread groups within the SM 310. In various embodiments, software applications written in the Compute Unified Device Architecture (CUDA) programming language describe the behavior and operations of threads executing on the GPC 208, including any of the behaviors and operations described above. A given processing task can be specified in a CUDA program so that the SM 310 can be configured to perform and / or manage general-purpose computing operations.

[0043] although Figure 3 Not shown, but each SM 310 includes a level 1 (L1) cache, or uses space in a corresponding L1 cache external to the SM 310 to support load and store operations, etc., performed by the execution units. Each SM 310 also has access to a level 2 (L2) cache (not shown) that is shared between all GPCs 208 in the PPU 202. The L2 cache can be used to transfer data between threads. Finally, the SM 310 also has access to off-chip "global" memory, which can include PP memory 204 and / or system memory 104. It should be understood that any memory external to the PPU 202 can be used as global memory. In addition, as Figure 3As shown, a level 1.5 (L1.5) cache 335 may be included in GPC 208 and is configured to receive and store data requested from memory by SM 310 via memory interface 214. Such data may include, but is not limited to, instructions, uniform data, and constant data. In embodiments having multiple SMs 310 within GPC 208, SMs 310 may advantageously share common instructions and data cached in L1.5 cache 335.

[0044] Each GPC 208 may have an associated memory management unit (MMU) 320 that is configured to map virtual addresses to physical addresses. In various embodiments, the MMU 320 may reside within the GPC 208 or the memory interface 214. The MMU 320 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles or memory pages, and optionally to cache line indices. The MMU 320 may include a translation lookaside buffer (TLB) or cache that resides within the SM 310, one or more L1 caches, or the GPC 208.

[0045] In graphics and compute applications, GPC 208 may be configured so that each SM 310 is coupled to a texture unit 315 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data.

[0046] In operation, each SM 310 sends processed tasks to the work distribution crossbar 330 so that the processed tasks can be provided to another GPC 208 for further processing, or the processed tasks can be stored in an L2 cache (not shown), parallel processing memory 204, or in system memory 104 via the crossbar unit 210. In addition, a pre-raster operation ("preROP") unit 325 is configured to receive data from the SM 310, direct the data to one or more raster operation (ROP) units in the partition unit 215, perform optimizations for color blending, organize pixel color data, and perform address translation.

[0047] It should be understood that the core architecture described herein is illustrative and that variations and modifications are possible. Among other things, any number of processing units, such as SM 310, texture unit 315, or preROP unit 325, may be included in GPC 208. Figure 2As described above, the PPU 202 may include any number of GPCs 208 that are configured to be functionally similar to one another so that execution behavior does not depend on which GPC 208 receives a particular processing task. Furthermore, each GPC 208 operates independently of the other GPCs 208 in the PPU 202 to execute tasks of one or more application programs. In view of the foregoing, it will be understood by those skilled in the art that Figure 1-Figure 3 The architecture described in this document in no way limits the scope of the various embodiments of the present disclosure.

[0048] Note that, as used herein, reference to shared memory may include any one or more technically feasible memories, including but not limited to local memory shared by one or more SMs 310 or memory accessible via memory interface 214, such as cache memory, parallel processing memory 204, or system memory 104. Note also that, as used herein, reference to cache memory may include any one or more technically feasible memories, including but not limited to L1 cache, L1.5 cache, and L2 cache.

[0049] Direct connection between network interface and graphics processing unit in self-hosted mode storage operation

[0050] Various embodiments include a method for transmitting data in a multi-processor system in a self-hosted mode via a network interface card (NIC) such as Figure 1 A technique for performing data transfer operations by directly connecting a network adapter (NIC) 118) to a graphics processor or other parallel processing unit (such as PPU 202). NIC is also referred to herein as a network controller. The disclosed system includes at least one CPU (such as Figure 1The CPU 102 includes a CPU 102, at least one PPU, and at least one NIC. The CPU includes a high-bandwidth C2C interconnect to the PPU for high-speed data transfer with memory in the PPU, and a low-bandwidth interconnect for performing configuration operations, control operations, register read and / or write operations, interrupt operations, etc. The NIC also has an interconnect to the PPU for transferring data to and from memory in the PPU. With this system configuration, the low-bandwidth interconnect from the CPU to the PPU and the interconnect from the NIC to the PPU can be coupled to the PPU via a switch. The low-bandwidth interconnect from the CPU to the PPU does not negatively impact the throughput of the interconnect from the NIC to the PPU. Furthermore, the interconnect from the NIC to the PPU does not negatively impact the throughput of the high-bandwidth interconnect from the CPU to the PPU. Through the disclosed techniques, memory in the PPU can be addressed using two different page table translations utilizing two different address mappings, a first page table translation using a first address mapping employed by the CPU, and a second page table translation using a second address mapping employed by the NIC. The disclosed techniques provide a PPU hardware-enforced consistency mechanism to address potential consistency issues caused by accessing memory in the PPU using two different page table translations utilizing two different address mappings.

[0051] Figure 4 is a block diagram of a system having a single NIC module and a single PPU module with a direct interconnection according to various embodiments. System 400 includes, but is not limited to, a CPU module 410, a PPU module 420, and a NIC module 430. CPU module 410 includes, but is not limited to, a CPU die 412. PPU module 420 includes, but is not limited to, a primary PPU die 422 and an auxiliary PPU die 424. NIC module 430 includes, but is not limited to, a NIC die 432 and a switch 434. The functions and combinations of the components included in system 400 Figures 1 to 3 Similar components as shown and described and further described herein are substantially the same.

[0052] CPU die 412 includes a central processing unit such as Figure 1 CPU 102. The CPU die 412 may also include system memory, such as Figure 1 The CPU die 412 communicates with the auxiliary PPU die 424 included in the PPU module 420 via the interconnect 452. The interconnect 452 is a high-bandwidth interconnect for high-speed data transmission between the CPU die 412 and the PP memory 204 included in the PPU module 420. The PP memory 204 ( Figure 44. The interconnect 452 (not shown) may be included in one or both of the primary PPU die 422 and the secondary PPU die 424. In some examples, the interconnect 452 is a C2C interconnect with a throughput of approximately 640 GB / s in each direction. The CPU die 412 communicates with the switch 434 via the interconnect 444. The interconnect 444 is a low-bandwidth interconnect used to perform configuration operations, control operations, register read and / or write operations, interrupt operations, etc. In some examples, the interconnect 444 is a Gen 5 PCIe interconnect with a raw throughput of approximately 64 GB / s in each direction.

[0053] The PPU module 420 includes a main PPU die 422 and an auxiliary PPU die 424. The combination of the main PPU die 422 and the auxiliary PPU die 424 constitutes one or more PPUs, such as Figure 2 The primary PPU die 422 and the secondary PPU die 424 communicate with each other via a high-speed interconnect 450. As described herein, the secondary PPU die 424 communicates with the CPU die 412 via a high-bandwidth interconnect 452 for high-speed data transfer between the CPU die 412 and the PP memory 204. The primary PPU die 422 communicates with the switch 434 via an interconnect 442. In some examples, the interconnect 442 is a Gen 6 PCIe interconnect with a raw throughput of approximately 128 GB / s in each direction. The CPU die 412 communicates with the primary PPU die 422 via interconnect 442, switch 434, and interconnect 440 to perform configuration operations, control operations, register read and / or write operations, interrupt operations, and the like. The NIC die 432 communicates with the primary PPU die 422 via interconnect 442, switch 434, and interconnect 440 to perform data transfer between the NIC die 432 and the PP memory 204.

[0054] NIC die 432 includes a network adapter such as Figure 14. The NIC die 432 communicates with one or more external systems (not shown) to facilitate data transfers between the system 400 and the external systems. The NIC die 432 is responsible for performing data transfers between the NIC die 432 and one or more other components in the system 400. In doing so, the NIC die 432 communicates with the switch 434 via the interconnect 440. In some examples, the interconnect 440 is a Gen 6 PCIe interconnect with a raw throughput of approximately 128 GB / s in each direction. The NIC die 432 communicates with the primary PPU die 422 via the interconnect 440, the switch 434, and the interconnect 442 to perform data transfers between the NIC die 432 and the PP memory 204. The NIC die 432 communicates with the CPU die 412 via the interconnect 440, the switch 434, and the interconnect 444 to perform data transfers and various other operations.

[0055] Switch 434 provides connectivity and facilitates communication between components of system 400. In some examples, switch 434 provides connectivity by bridging various PCIe interconnects, such as interconnect 440, interconnect 442, and interconnect 444. Switch 434 can support interconnects of different generations, where interconnects of different generations can have different maximum throughputs. For example, interconnect 440 and interconnect 442 can be Gen 6 PCIe interconnects, while interconnect 444 can be Gen 5 PCIe interconnects. Generally speaking, interconnects 440 and 442 can be PCIe interconnects of a generation with higher throughput than interconnect 444. Correspondingly, interconnect 444 can be a PCIe interconnect of a different generation, having lower throughput than interconnect 440 and interconnect 442. When bridging interconnects of different generations, the resulting interconnect path is limited by the interconnect with the lowest throughput. In this regard, if switch 434 is bridging Gen 5 PCIe interconnect 444 with Gen 6 PCIe interconnect 440 or Gen 6 PCIe interconnect 442, the resulting interconnect path is limited only to Gen 5 PCIe throughput. However, if switch 434 is bridging Gen 6 PCIe interconnect 440 with Gen 6 PCIe interconnect 442, the resulting interconnect path can achieve Gen 6 PCIe throughput.

[0056] In some conventional systems, when a NIC initiates a data transfer to PP memory in a PPU, the NIC may send a DMA request to the PP memory over the PCIe interconnect, where such DMA requests adhere to PCIe ordering rules. In such conventional systems, these DMA requests to the PP memory do not generate a snoop operation, also referred to herein as a probe operation or query operation. This snoop operation can determine whether the CPU has currently inspected the portion of PP memory targeted by the DMA request. By inspecting the portion of PP memory targeted by the DMA request, the CPU claims ownership or allocation rights to that portion of PP memory. In this regard, this portion of PP memory is considered owned or allocated by the CPU. Without this snoop operation, the CPU and / or NIC cannot access the PP memory consistently. Therefore, in such systems, incoming PCIe requests are typically transmitted over a specific virtual channel (VC) that does not generate a snoop operation and instead maintains PCIe write ordering to ensure consistency. This VC can also help maintain certain quality of service (QoS) guarantees by providing lower latency and higher bandwidth for certain PCIe requests, even under interference conditions caused by PCIe requests generated by other PPU clients. However, such traditional systems, such as those based on the x86 CPU architecture, lack a dedicated high-bandwidth C2C interconnect between the CPU and PP memory.

[0057] In contrast, Figure 4 The CPU die 412 in the self-hosted system 400 routes data transfer traffic to the PPU module 420 via a high-bandwidth C2C interconnect 452. The CPU die 412 routes other traffic, such as configuration operations, control operations, register read and / or write operations, interrupt operations, etc., via a low-bandwidth PCIe interconnect 444. In a dual-die configuration, where the PPU module 420 includes a primary PPU die 422 and a secondary PPU die 424, the CPU die 412 accesses the PP memory 204 via a high-bandwidth C2C interconnect 452 to the secondary PPU die 424. The NIC die 432 accesses the PP memory 204 via a PCIe interconnect 442 to the primary PPU die 422. Therefore, the PP memory 204 is accessible from the NIC die 432 via the PCIe base address register 1 (BAR1) address mapping and from the CPU die 412 via the C2C host management device memory (HDM) address mapping.

[0058] When the NIC die 432 and the CPU die 412 simultaneously access the same portion of PP memory 204, accessing PP memory 204 from two different dies using two different address mappings may result in data inconsistencies. To prevent such data inconsistencies, the hardware logic included in the PPU module 420 includes a mechanism that ensures consistency between simultaneous accesses to the same portion of PP memory 204 from both the NIC die 432 and the CPU die 412. When the NIC die 432 generates a data transfer targeting the same portion of PP memory 204, the CPU die 412 can consistently check out a specific portion of PP memory 204 containing a range of physical memory addresses. Using the coherence mechanism in the PPU module 420, if a data transfer generated by the NIC die 432 reaches the cache memory of PP memory 204 while the portion of PP memory is being checked out by the CPU die 412, the cache memory controller generates a snoop operation. The cache memory controller sends the snoop operation to a coherence point included in the CPU die 412. The CPU die 412 generates a snoop response, also known as a probe response or query response, which includes the current data in the portion of PP memory 204 targeted by the NIC die 432. To ensure data consistency, the data transfer generated by the NIC die 432 is not processed until the snoop response including the current data is returned. After receiving the snoop response from the CPU die 412, the corresponding cache slice in the cache memory of the PP memory 204 sends any write acknowledgements, read responses, atomic operation responses, etc. corresponding to the data transfer to the NIC die 432.

[0059] In contrast, if a data transfer generated by NIC die 432 reaches the cache memory of PP memory 204 when the portion of PP memory is not checked out by CPU die 412, the data transfer can proceed without generating a snoop operation. Furthermore, interconnects 440, 442, and / or 444 can preserve the "write after write" (Wr-after-Wr) ordering of write operations included in data transfers generated by NIC die 432. Interconnects 440, 442, and / or 444 can preserve this Wr-after-Wr ordering even when multiple write operations from NIC die 432 are directed to different cache slices in the cache memory of PP memory 204, even when CPU die 412 checks out corresponding memory addresses.

[0060] If the data transfer generated by the CPU die 412 is a strongly ordered write operation, indicating that strict write ordering should be enforced, the cache controller: (1) waits until a snoop response including the current data is returned before generating and sending an acknowledgment for the write operation; and (2) holds that portion of the PP memory 204 in a checked-out and interlocked state until a transaction complete acknowledgment for the write operation is received from the PCIe sequencing point. This mechanism enables the cache controller to support snooping of incoming PCIe accesses from either the NIC die 432 or the CPU die 412 memory operations in self-hosted mode.

[0061] In addition to this hardware mechanism, system 500 also includes certain software-based technologies to support direct-attached memory operations between NIC die 432 and PPU module 420 in self-hosted mode. These software-based technologies are discussed herein. In this regard, software executing on CPU die 412 can configure both NIC module 430 and PPU module 420 via Gen 5 PCIe interconnect 444 and switch 434.

[0062] Furthermore, in a self-hosted system, PP memory 204 is exposed to the CPU die 412 as a host managed device memory HDM (HDM) address mapping, allowing the CPU die 412 to access the PP memory 204 via the C2C interconnect 452. However, with the disclosed direct connect technology, PP memory 204 is also exposed to the NIC die 432 as a PCIe base address register 1 (BAR1) address mapping, allowing the NIC die 432 to access the PP memory 204 via the PCIe interconnect 440 and interconnect 442. Typically, the BAR1 page table mapping is not available in the CPU die 412. Therefore, the NIC die 432 does not use the address translation service (ATS) to obtain the BAR1 page table mapping from the CPU die 412. Instead, when the NIC die 432 accesses the PP memory 204 via the BAR1 address mapping, the PPU device driver (such as Figure 1 The device driver 103) provides the BAR1 addresses of the PP memory 204 directly to the NIC die 432. The software stack and other software applications can use these BAR1 page table mappings when performing DMA operations and / or other data transfers to access PP memory from the NIC die 432.

[0063] Note that the same physical memory address in PP memory 204 can be used by the NIC die 432 via the BAR1 address mapping and by the CPU die 412 via the HDM address mapping, such as when the NIC die 432 and the CPU die 412 share access to a semaphore at a particular memory location. For these reasons, the cache controller supports checking out memory locations by the CPU die 412 to the same memory address while maintaining PCIe write ordering for the NIC die 432.

[0064] Unlike the limitation of NIC die 432 not using ATS, PPU module 420 can operate in ATS mode, such as using ATS in conjunction with the CPU and system MMU included in CPU die 412. In some examples, PPU module 420 can use ATS to improve utilization of C2C bandwidth on interconnect 452. Generally speaking, the disclosed technology can provide increased data bandwidth from NIC die 432 to PP memory 204 via interconnect 440 and interconnect 442, better utilization of C2C bandwidth via interconnect 452, and hardware-enforced coherency mechanisms to support both BAR1 address mapping and HDM address mapping to PP memory 204.

[0065] Figure 5 5 is a block diagram of a system 500 having two NIC modules 530(0), 530(1) and two PPU modules 520(0), 520(1) with direct interconnection according to various embodiments. The system 500 includes, but is not limited to, a CPU module 510, two PPU modules 520(0), 520(1), and two NIC modules 530(0), 530(1). The CPU module 510 includes, but is not limited to, a CPU die 512. The PPU module 520(0) includes, but is not limited to, a primary PPU die 522(0) and an auxiliary PPU die 524(0). Similarly, the PPU module 520(1) includes, but is not limited to, a primary PPU die 522(1) and an auxiliary PPU die 524(1). The NIC module 530(0) includes, but is not limited to, a NIC die 532(0) and a switch 534(0). Likewise, the NIC module 530(1) includes, but is not limited to, a NIC die 532(1) and a switch 534(1). Functionality and integration of components included in the system 500 Figures 1 to 4 Similar components shown and described and further described herein function substantially the same.

[0066] With the configuration shown in system 500, a single CPU die 512 included in CPU module 510 can independently communicate with multiple PPU modules 520 and / or multiple NIC modules 530 via dedicated interconnects. In this regard, NIC die 532(0) can communicate with primary PPU die 522(0) via interconnect 540(0), switch 534(0), and interconnect 542(0). CPU die 512 can communicate with NIC die 532(0) via interconnect 544(0), switch 534(0), and interconnect 540(0). CPU die 512 can communicate with primary PPU die 522(0) via interconnect 544(0), switch 534(0), and interconnect 542(0). CPU die 512 can communicate with secondary PPU die 524(0) via high-bandwidth interconnect 552(0). The primary PPU die 522 ( 0 ) and the secondary PPU die 524 ( 0 ) may communicate with each other via a high-bandwidth interconnect 550 ( 0 ).

[0067] Similarly, the NIC die 532(1) can communicate with the primary PPU die 522(1) via interconnect 540(1), switch 534(1), and interconnect 542(1). The CPU die 512 can communicate with the NIC die 532(1) via interconnect 544(1), switch 534(1), and interconnect 540(1). The CPU die 512 can communicate with the primary PPU die 522(1) via interconnect 544(1), switch 534(1), and interconnect 542(1). The CPU die 512 can communicate with the secondary PPU die 524(1) via high-bandwidth interconnect 552(1). The primary PPU die 522(1) and the secondary PPU die 524(1) can communicate with each other via high-bandwidth interconnect 550(1).

[0068] In this manner, a system 500 having a single CPU die 512 can support multiple high-bandwidth interconnects 552 to multiple PPU modules 520. Furthermore, a system 500 having a single CPU die 512 can support multiple NIC modules 530, wherein each NIC module 530 has an independent interconnect path to a corresponding PPU module included in the multiple PPU modules 520. Furthermore, when the CPU die 512 and the NIC module 530 can access the PP memory 204 in the corresponding PPU module 530 included in the multiple PPU modules 520, the single CPU die 512 can independently resolve data consistency issues with different PPU modules 520.

[0069] It should be understood that the systems shown herein are illustrative and that variations and modifications are possible. A system employing the disclosed technology can have any number of CPU modules, PPU modules, and / or NIC modules. Each CPU module, PPU module, and / or NIC module can include any number of dies, cores, etc. in any configuration. Each CPU module can include any number of CPUs, each PPU module can include any number of PPUs, and / or each NIC module can include any number of network controllers. Switches can be included in each NIC module as shown, in one or more other modules in the system, and / or in a separate switch module.

[0070] Figure 6 is a flow chart of method steps for transferring data between a NIC and a PPU according to various embodiments. Additionally or alternatively, the method steps may be performed by one or more alternative accelerators, including but not limited to any combination of a CPU, a GPU, a DMA unit, an IPU, an NPU, a TPU, an NNP, a DPU, a VPU, an ASIC, an FPGA, and / or the like. While in combination Figures 1 to 5 Although the method steps are described with reference to a system, one of ordinary skill in the art will understand that any system configured to perform the method steps in any order is within the scope of the present disclosure.

[0071] As shown, method 600 begins at step 602, where the processor detects a memory operation directed to a memory address in the PP memory address space. The PP memory address space may include any portion or all of a memory system associated with a PPU, such as a memory address associated with a PPU. Figure 4 PPU module 420 or Figure 5 The PPU component 520 is associated with the PP memory 204 .

[0072] At step 604, the processor determines whether the CPU (such as the CPU in CPU die 412 or CPU die 512) is the source of the memory operation. If the CPU generates the memory operation and transmits the memory operation to PP memory 204 via high-bandwidth C2C interconnect 452 or high-bandwidth C2C interconnect 552 using HDM address mapping, the processor determines that the CPU is the source of the memory operation. In contrast, if the NIC generates the memory operation and transmits the memory operation to PP memory 204 via PCIe interconnect 440 and / or PCIe interconnect 442 or PCIe interconnect 540 and / or PCIe interconnect 542 using BAR1 address mapping, the processor determines that the NIC (such as the NIC in NIC die 432 or NIC die 532) is the source of the memory operation.

[0073] If the CPU is not the source of the memory operation, then the NIC is the source of the memory operation. In this case, method 600 proceeds to step 606, where the processor determines whether the memory address is owned by the CPU. In doing so, the processor determines whether the CPU has checked out the portion of PP memory 204 targeted by the memory operation.

[0074] If, at step 606, the CPU has already detected the portion of PP memory 204 targeted by the memory operation, the memory address is owned by the CPU. In this case, method 600 proceeds to step 608, where the processor retrieves the current data corresponding to the memory address. To do so, the processor generates and sends a query operation, referred to as a snoop operation or a probe operation, to a coherence point associated with the CPU. The CPU generates and returns a query response, referred to as a snoop response or a probe response, which includes the current data corresponding to the portion of PP memory targeted by the memory operation. To ensure data coherence, the NIC-generated memory operation is not processed until a query response including the current data is returned.

[0075] The NIC coherently accesses data from the memory address at step 610. Method 600 then terminates, or alternatively, returns to step 602 to process further memory operations.

[0076] Returning to step 606, if the CPU has not detected the portion of PP memory 204 targeted by the memory operation, the method 600 continues to step 610, where the NIC consistently accesses data from the memory address, as described above. The method 600 then terminates, or alternatively, returns to step 602 to process further memory operations.

[0077] Returning to step 604, if the CPU is the source of the memory operation, method 600 continues to step 612 where the processor determines whether the memory address is owned by the CPU. In doing so, the processor determines whether the CPU has checked out the portion of PP memory 204 targeted by the memory operation.

[0078] If, at step 612, the CPU does not check out the portion of PP memory 204 targeted by the memory operation, then the memory address is not owned by the CPU. In this case, method 600 proceeds to step 614 where the processor sets ownership of the memory address to the CPU.

[0079] The CPU coherently accesses the data from the memory address at step 616. The method 600 then terminates, or alternatively, returns to step 602 to process further memory operations.

[0080] Returning to step 612, if the CPU has already checked out the memory-targeted portion of PP memory 204, then the memory address is owned by the CPU. In this case, method 600 continues to step 616, where the CPU consistently accesses data from the memory address, as described above. Method 600 then terminates, or alternatively, returns to step 602 to process further memory operations.

[0081] In summary, various embodiments include techniques for performing data transfer operations in a multiprocessor system in self-hosted mode via a direct interconnect between a NIC and a PPU. The disclosed system includes at least one CPU, at least one PPU, and at least one NIC. The CPU includes a high-bandwidth C2C interconnect to the PPU for high-speed data transfers to and from memory in the PPU, and a low-bandwidth interconnect for performing configuration operations, control operations, register read and / or write operations, interrupt operations, and the like. The NIC also has an interconnect with the PPU for transfers to and from memory in the PPU. With this system configuration, the low-bandwidth interconnect from the CPU to the PPU and the interconnect from the NIC to the PPU can be coupled to the PPU via a switch. The low-bandwidth interconnect from the CPU to the PPU does not negatively impact the throughput of the interconnect from the NIC to the PPU. Furthermore, the interconnect from the NIC to the PPU does not negatively impact the throughput of the high-bandwidth interconnect from the CPU to the PPU. With the disclosed techniques, memory in the PPU can be addressed using two different page table translations using two different address mappings: a first page table translation using a first address mapping employed by the CPU, and a second page table translation using a second address mapping employed by the NIC. The disclosed technology provides a PPU hardware-enforced coherency mechanism to resolve potential coherency issues caused by accessing memory in the PPU through two different page table translations using two different address mappings.

[0082] At least one technical advantage of the disclosed technology over the prior art is that, using the disclosed technology, the NIC can communicate with the PPU via a direct interconnect at a higher data transfer rate than traditional data transfers between the NIC and the PPU that occur through the CPU. Because the NIC transmits data directly to the PPU, throughput is not limited by the lower-bandwidth interconnect on the CPU. Furthermore, because the NIC does not consume bandwidth on the CPU interconnect, the CPU can perform data transfers and other data operations at a higher throughput than traditional techniques that share CPU interconnect bandwidth with NIC data transfers. These advantages represent one or more technical improvements over prior art approaches.

[0083] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application, in any way, are within the scope of this disclosure and protection.

[0084] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0085] Aspects of the present embodiments may be embodied as systems, methods, or computer program products. Thus, aspects of the present disclosure may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects, all of which are collectively referred to herein as "modules" or "systems." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media containing computer-readable program code.

[0086] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium includes, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination thereof. More specific examples (non-exhaustive enumeration) of computer-readable storage media can include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the context of this document, a computer-readable storage medium can be any tangible medium that can include or store a program for use by or in conjunction with an instruction execution system, device or device.

[0087] Aspects of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing device enable the function / action specified in one or more boxes of the flowchart and / or block diagram to be implemented. Such processors can be, but are not limited to, general-purpose processors, special-purpose processors, application-specific processors, or field programmable gate arrays.

[0088] The flowcharts and block diagrams in the figures illustrate the possible architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, segment or portion of a code, and the code includes one or more executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative embodiments, the functions indicated in the box may not occur in the order indicated in the figure. For example, two boxes shown in succession can actually be executed roughly simultaneously, or the boxes can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented by a system based on dedicated hardware that performs a specified function or action or a combination of dedicated hardware and computer instructions.

[0089] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, as determined by the claims that follow.

Claims

1. A computer-implemented method for performing a data transfer operation in a multiprocessor system, the method comprising: accessing, by the network controller, a first memory of the first processor via the first interconnect using a first address mapping; accessing, by a second processor, the first memory of the first processor via a second interconnect using a second address mapping; as well as accessing the second memory of the first processor via a third interconnect by the second processor, Wherein the first interconnect is coupled to the third interconnect.

2. The computer-implemented method of claim 1 , wherein accessing, by the network controller, the first memory of the first processor via the first interconnect comprises: determining that at least a portion of the first memory is owned by the second processor; sending a snoop operation to the second processor; as well as A response to the snoop operation is received from the second processor, the response including data stored in the at least portion of the first memory.

3. The computer-implemented method of claim 2 , wherein accessing, by the network controller, the first memory of the first processor via the first interconnect further comprises: In response to receiving the response to the snoop operation, sending a confirmation to the network controller that the data stored in at least the portion of the first memory is available.

4. The computer-implemented method of claim 3, wherein the second processor maintains ownership of the at least portion of the first memory while awaiting receipt of a transaction completion confirmation associated with the first interconnect.

5. The computer-implemented method of claim 1 , wherein accessing, by the network controller, the first memory of the first processor via the first interconnect comprises: performing a first write operation directed to a first portion of the first memory via the first interconnect; as well as performing a second write operation directed to a second portion of the first memory via the first interconnect, Wherein a processing order via the first interconnect is maintained between the first write operation and the second write operation.

6. The computer-implemented method of claim 5, wherein: When performing at least one of the first write operation or the second write operation, at least one of the first portion of the first memory or the second portion of the first memory is owned by the second processor.

7. The computer-implemented method of claim 1 , wherein: The first processor includes a graphics processor, and The second processor includes a central processing unit.

8. The computer-implemented method of claim 1 , wherein: The first processor includes a first die coupled to the first interconnect and a second die coupled to the second interconnect, and The first die is coupled to the second die via a high-bandwidth interconnect.

9. The computer-implemented method of claim 1 , wherein: The first interconnect comprises a first Peripheral Component Interconnect Express (PCIe) interconnect having a first throughput, and The third interconnect includes a second PCIe interconnect having a second throughput.

10. The computer-implemented method of claim 9, wherein the first throughput is higher than the second throughput.

11. The computer-implemented method of claim 9, wherein the second interconnect comprises an inter-chip interconnect having a third throughput.

12. The computer-implemented method of claim 11, wherein the third throughput is higher than each of the first throughput and the second throughput.

13. The computer-implemented method of claim 11 , wherein: The first address map includes a base address register (BAR) address map associated with the first PCIe interconnect, and The second address map includes a host management device memory (HDM) address map associated with the inter-chip interconnect.

14. A system comprising: a first processor, the first processor comprising a first memory and a second memory; a network controller, the network controller being coupled to the first processor, the network controller: accessing the first memory of the first processor via a first interconnect using a first address mapping; as well as A second processor is coupled to the first processor and the network controller, wherein the second processor: accessing the first memory of the first processor via a second interconnect using a second address mapping; as well as accessing the second memory of the first processor via a third interconnect, Wherein the first interconnect is coupled to the second interconnect.

15. The system of claim 14, wherein: To access the first memory of the first processor via the first interconnect, the network controller: determining that at least a portion of the first memory is owned by the second processor; sending a snoop operation to the second processor; as well as A response to the snoop operation is received from the second processor, the response including data stored in the at least portion of the first memory.

16. The system of claim 14, wherein: The first processor includes a graphics processor, and The second processor includes a central processing unit.

17. The system of claim 14, wherein: The first processor includes a first die coupled to the first interconnect and a second die coupled to the second interconnect, and The first die is coupled to the second die via a high-bandwidth interconnect.

18. The system of claim 14, wherein: The first interconnect comprises a first Peripheral Component Interconnect Express (PCIe) interconnect having a first throughput, and The third interconnect includes a second PCIe interconnect having a second throughput. The system of claim 18 , wherein the first throughput is higher than the second throughput.

20. The system of claim 18, wherein the second interconnect comprises an inter-chip interconnect having a third throughput.

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