High-precision memristor simulation matrix equation solver and operation method

Abstract

The invention belongs to the technical field of analog circuits, and particularly discloses a high-precision memristor analog matrix equation solver and an operation method, the high-precision memristor analog matrix equation solver comprises a plurality of analog calculation cores, an analog addition module, a digital-to-analog conversion module, an analog-to-digital conversion module, a data cache module, a global controller and an I / O module; the input end of the digital-to-analog conversion module is connected with the data caching module, and the output end of the digital-to-analog conversion module is connected with the analog addition module; the input end of the analog-to-digital conversion module is connected with the analog addition module, and the output end of the analog-to-digital conversion module is connected with the data caching module; a plurality of analog calculation cores for performing residual mapping on the iteration matrix and calculating a voltage vector; and the simulation addition module determines an updated solution result based on the voltage vector and the iteration vector, and the iteration matrix and the iteration vector are an iteration matrix and an iteration vector in an iteration solution form corresponding to the matrix equation. According to the invention, high-precision solving of the matrix equation on the analog circuit can be realized.

Description

Technical Field

[0001] The present application belongs to the field of analog circuit technology, and more specifically, relates to a high-precision memristor analog matrix equation solver and an operating method. Background Art

[0002] With the explosive growth of edge AI technology, traditional Neumann computers are no longer able to meet the urgent demand for intelligent computing power and energy efficiency at the edge in the current information age. Memristive analog computing, as a storage-computing integrated technology with high energy efficiency, low computational latency, and low time complexity, is gradually demonstrating its value and showing significant energy efficiency advantages over digital computing chips in the field of edge neural network acceleration.

[0003] However, with the development of embodied intelligence technologies such as real-time positioning and mapping, edge intelligent computing urgently needs high-precision, low-latency equation-solving technologies, in addition to neural network acceleration. However, due to the influence of device non-ideal effects, the computational accuracy of memristor analog computing technology is significantly restricted. Although the current mainstream mixed-precision memristor equation solvers can achieve high-precision solutions, the introduction of digital processing systems makes it difficult for these solvers to fully utilize the performance advantages of memristor analog computing, resulting in significant performance losses in computational energy efficiency and solution latency. Therefore, to meet the key needs of emerging fields such as edge embodied intelligent computing, a new type of high-efficiency, high-precision memristor matrix equation solver is urgently needed. Summary of the Invention

[0004] In response to the defects of the existing technology, the purpose of this application is to provide a high-precision memristor analog matrix equation solver to achieve high-precision solution of matrix equations in the analog domain, so as to solve the computing power and energy efficiency challenges faced by existing memristor mixed-precision equation solvers in edge matrix equation solving tasks.

[0005] To achieve the above objectives, in a first aspect, the present application provides a high-precision memristor analog matrix equation solver, comprising: multiple analog computing cores, an analog addition module, a digital-to-analog converter (DAC) module, an analog-to-digital converter (ADC) module, a data cache module, a global controller, and an I / O module (for inputting and outputting data between the solver and external devices); The analog computing core, analog addition module and global controller are interconnected through a transmission bus; The input end of the digital-to-analog conversion module is connected to the data buffer module, and the output end of the digital-to-analog conversion module is connected to the analog addition module; The input end of the analog-to-digital conversion module is connected to the analog addition module, and the output end of the analog-to-digital conversion module is connected to the data buffer module; The data cache module is interconnected with the I / O module, and the I / O module is controlled by the global controller; Multiple simulation cores for iterating matrices Perform residual mapping and calculate voltage vector , Indicates the number of current iterations; Analog summing module for voltage vector based and iterative vector , determine the updated solution result , iterative matrix and iterative vector Iteration matrix and iteration vector in the iterative solution form corresponding to the matrix equation; The global controller is used to control the analog computing core and the analog addition module through the transmission bus to perform iterative solution until the solution converges.

[0006] It should be noted that the iteration vector The I / O module can store the result in the data buffer module, convert it to analog via the DAC module, and input it into the analog adder module, where it serves as the voltage stimulus for each analog adder. After iterative convergence, the analog adder module's output vector (the solution result) is converted to a digital value via the ADC module and stored in the data buffer module. The solution result is then transmitted to the external digital system via the I / O module.

[0007] The solver performs full simulation domain iteration of the solution formula through the simulation calculation core and simulation addition module.

[0008] It can be understood that by iterating the matrix Residual mapping can supplement the mapping error of each simulation calculation kernel to ensure the iterative matrix High-precision mapping in the analog domain, combined with iterative solution through the control of analog computing cores and analog addition modules through the transmission bus, can achieve high-precision solution of matrix equations on analog circuits, thereby resolving the computing power and energy efficiency challenges faced by existing memristor mixed-precision equation solvers in edge matrix equation solving tasks.

[0009] As a result, the simulation solver boasts high solution accuracy, low computational latency, and low power consumption, providing a viable solution for high-precision, low-latency matrix equation solving in edge scenarios such as robot positioning and map building.

[0010] In one possible implementation, the analog computing core includes: two memristor computing array modules, an inverter array, a tunable transimpedance amplifier (TIA) array, and a local controller; The two memristor computing array modules are respectively a first memristor computing array module and a second memristor computing array module; The input end of the first memristor computing array module is connected to the input end of the analog computing core, the input end of the inverter array is connected to the input end of the analog computing core, and the input end of the second memristor computing array module is connected to the output end of the inverter array; The output ends of the two memristor computing array modules are connected to the input end of the adjustable transimpedance amplifier array, and the output end of the adjustable transimpedance amplifier array is the output end of the analog computing core; The local controller is connected to the memristive computing array module, and is used to control the gating state of the array in the memristive computing array module and control the application of analog signals to the memristive computing array module.

[0011] In one possible implementation, the memristive computing array module includes: Large-scale memristor arrays, multiplexers, and driver circuits; The driving circuit is connected to the row input port of the memristor array, and the multiplexer is connected to the column output port of the memristor array.

[0012] Specifically, the memristor array is the core of the memristor computing array module, responsible for storing and computing information. Its scale is The driver circuit is responsible for providing drive signals to the row input ports of the memristor array, controlling the operating state of each row in the memristor array, while the multiplexer is connected to the column output ports of the memristor array to select and output data from a specific column. The three work together: the driver circuit activates the target memristor unit through the row input port, and the multiplexer reads the corresponding data from the column output port, realizing data selection and transmission.

[0013] In one possible implementation, the memristor array is specifically a crossbar array, which is an array formed by crossing M row lines and N column lines, and the memristors are located at the intersections of the array; The input end of the memristor array is composed of M row lines of the crossbar array, and the output end of the memristor array is composed of N column lines of the crossbar array.

[0014] In a possible implementation, the memristor medium is a resistive random access memory (ReRAM), a phase change memory (PCM), or a ferroelectric field effect transistor (FeFET).

[0015] In a possible implementation, the adjustable transimpedance amplifier array includes N adjustable transimpedance amplifiers, where N is the number of columns of the memristor calculation array module; The adjustable transimpedance amplifier includes an operational amplifier and an adjustable resistor; the adjustable resistor is connected between the input and output terminals of the operational amplifier; One adjustable transimpedance amplifier corresponds to one column in the memristive computing array module; The input of the adjustable transimpedance amplifier is the sum of the output of the corresponding column in the first memristive computing array module and the output of the corresponding column in the second memristive computing array module; The outputs of the N adjustable transimpedance amplifiers constitute the output of the analog computing core.

[0016] In one possible implementation, the analog computing kernel is used to perform differential calculations using the following formula: ; ; in, represents the output vector of the simulation kernel, represents the input vector of the simulation kernel, Indicates the resistance value of the adjustable resistor. is the mapping parameter of the first memristor computing array module, The mapping parameters of the array module are calculated for the second memristor.

[0017] In one possible implementation, the analog adding module includes N analog adders, where N is the number of columns of the memristor computing array module; The first input of the N analog adders is based on the voltage vector Determined; The second input of the N analog adders is based on the iteration vector Determined; The outputs of the N analog adders are determined by addition calculation based on the first input and the second input.

[0018] In a second aspect, the present application further provides an operating method for a high-precision memristor analog matrix equation solver, which is applied to the high-precision memristor analog matrix equation solver described in the first aspect or any possible implementation of the first aspect, the method comprising: Perform iterative solution until the solution converges; Iterative solution, including: Iteration matrix Perform residual mapping and calculate voltage vector , Indicates the number of current iterations; Based on voltage vector and iterative vector , determine the updated solution result .

[0019] In one possible implementation, the above iteration matrix Perform residual mapping and calculate voltage vector ,include: Determines the number of simulation cores enabled ; For the first analog computing core among the enabled analog computing cores, the iteration matrix is ​​written by analog programming of the memristor Go to the first simulation computing core and read the data mapping result of the first simulation computing core , and calculate the iteration matrix Mapping results with data The error matrix between ; For the second to third of the enabled simulation cores An analog computing core is used to write the error matrix through analog programming of the memristor. To A simulation computing core, read the Data mapping results of simulation computing cores ,calculate and The error matrix , , Indicates the The error matrix corresponding to the simulation calculation kernel is Indicates the The error matrix corresponding to the simulation kernel; Based on the data mapping results of each enabled simulation computing core, the iteration matrix is ​​obtained by summing the data mapping results. ; Based on iterative matrix and the current solution results , calculate the voltage vector .

[0020] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0021] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies: By iterating the matrix Residual mapping can supplement the mapping error of each simulation calculation kernel to ensure the iterative matrix High-precision mapping in the analog domain, combined with iterative solution through the transmission bus to control the analog computing core and analog addition module, can achieve high-precision solution of matrix equations on analog circuits. This analog solver has the characteristics of high solution accuracy, low computing latency, and low computing power consumption, providing a feasible solution for high-precision computing and low-latency matrix equation solving scenarios at the edge, such as robot positioning and map construction. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of a high-precision memristor analog matrix equation solver provided in an embodiment of the present application; Figure 2 is a schematic diagram of a simulation computing core provided in an embodiment of the present application; Figure 3 Schematic diagram of a memristor array and its analog multiplication-accumulation calculation performed by an embodiment of the present application; Figure 4 This is a schematic diagram of multi-bit storage using a memristor provided in an embodiment of the present application; Figure 5 Schematic diagram of the differential calculation process in the simulation calculation core provided in the embodiment of the present application; Figure 6 1 is a schematic diagram of an analog adder circuit provided in an embodiment of the present application; Figure 7 Schematic diagram of a solver provided in an embodiment of the present application for solving a matrix equation; Figure 8 This is a schematic diagram of an embodiment of the present application providing a method for implementing high-precision residual mapping of a matrix using multiple simulation computing kernels. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0024] Throughout the specification and claims of this application, the terms "first" and "second" are used to distinguish between different objects, rather than to describe a specific order of objects. For example, a first memristive computing array module and a second memristive computing array module are used to distinguish between different memristive computing array modules, rather than to describe a specific order of the modules.

[0025] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0026] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0027] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0028] Figure 1 The embodiment 1 provided in this application is a structural diagram of a high-precision memristor simulation matrix equation solver, which consists of The solver consists of an analog computing core, an analog addition module, a digital-to-analog conversion module, an analog-to-digital conversion module, a data cache module, a global controller, and an I / O module. The analog computing core, analog addition module, and global controller are interconnected via a transmission bus (which transmits analog signals). The input of the digital-to-analog converter (DAC) module in this solver is connected to the data cache module, and its output is connected to the analog addition module. The input of the analog-to-digital converter (ADC) module is connected to the analog addition module, and its output is connected to the data cache module. The data cache module is interconnected with the I / O module, and both the data cache module and the I / O module are controlled by the global controller.

[0029] Figure 2 Schematic diagram of the analog computing core provided in this application. Each analog computing core includes two memristive computing array modules, an inverter array, an adjustable transimpedance amplifier (TIA) array, and a local controller. Each memristive computing array module in the analog computing core consists of The memristor array is composed of a large-scale memristor array and an external control (mainly a multiplexer) and a driving circuit. The driving circuit is connected to the row input port of the memristor array, and the multiplexer is connected to the column output port of the memristor array. Furthermore, the input end of the memristor computing array module 1 is directly connected to the input end of the analog computing core, the input end of the memristor computing array module 2 is connected to the output end of the inverter array, and the input end of the inverter array is connected to the input end of the analog computing core. The output ends of the two memristor computing array modules are connected to the input end of the adjustable TIA array, and the output end of the adjustable TIA array is the output end of the analog computing core. The local controller (controlled by the global controller) is connected to the external control and driving circuit of the memristor computing array module to complete the selection of the array and the application of analog signals. The adjustable TIA array in the analog computing core consists of an operational amplifier (the number of operational amplifiers is equal to the number of columns N of the array) and an adjustable resistor. By adjusting the resistance value (corresponding to Figure 5 and Figure 8 The R in the TIA is used to adjust the TIA amplification factor. It should be noted that the adjustable TIA array is mainly used to assist in achieving high-precision residual mapping of the matrix on the memristor array.

[0030] It can be understood that the residual mapping method achieves high-precision mapping of the iterative matrix in the analog domain by compensating for the mapping errors of each memristor array. Combined with iterative solution calculations based on feedback circuits, it ultimately achieves high-precision solution of matrix equations in analog circuits.

[0031] Figure 3 The schematic diagram of the memristor array in the analog computing core of the present application is shown. Each memristor array includes an input port and an output port, and has a cross array structure. The input end is composed of M row lines of the cross array, and the output end is composed of N column lines of the cross array. The memristor is located at the intersection of the array, with one end of the memristor connected to the row line and the other end connected to the column line. It should be noted that the selected memristor medium can be a non-volatile memory such as resistive random access memory (ReRAM), phase change memory (PCM), ferroelectric field effect transistor (FeFET), etc. The integration method includes various types such as 1T1R (One Transistor One Resistor) and 1S1R (One Selector One Resistor). During the calculation process, the input vector is first converted into a voltage and applied to the row lines of the array. The analog quantities such as the memristor conductivity store the matrix / vector parameters, and then parallel multiplication-accumulation calculations are performed through Ohm's law and Kirchhoff's law, and the calculation results are output in the form of current. Among them, represents the memristor at the intersection between the first row line and the first column line, represents the memristor at the intersection between the first row line and the second column line, and so on. Indicates the The line and the Memristors at the intersections between column lines, represents the input voltage applied to the row line of the memristor array, represents the column line output current of the memristor array. , , .

[0032] Figure 4 Demonstrating the multi-bit storage capability of a non-volatile memory array. Memristors can typically be programmed into multiple conductance states under the control of an external voltage, with each conductance state generating a linearized readout current under voltage excitation.

[0033] Figure 5 The differential calculation process in an analog computing core of this application is shown. Considering the entire analog computing core, it is equivalent to using two memristor arrays to complete data mapping in a differential form. The mapping parameters of the memristor computing array module 1 are , mapping parameters of memristor computing array module 2 , the actual mapping parameters of the simulation kernel are Assume that the magnification factor of the adjustable TIA array in the simulation computing core is , the input vector is VI, then the output of the simulation calculation kernel is . . Indicates the output voltage of each TIA.

[0034] It should be noted that the solver The output of each analog computing core is connected to the input of the analog adding module through the transmission bus. During the calculation process, the sum of the output voltages of all enabled analog computing cores is the input voltage vector of the analog adding module. .

[0035] Figure 6 The following diagram shows the analog adders used in the solver. The analog adder module contains N analog adders. These N analog adders are independent of each other. The output of the analog adders is provided (feedback) to the analog computing core and to the analog signal port of the ADC module. The analog port of the DAC module provides voltage excitation for the analog adders. Each analog adder consists of an operational amplifier, resistors (R1, R2) and a voltage excitation. The resistance relationship between R1 and R2 is R2 / R1= . is the number of analog computing cores enabled during the solution process. Under this setting, consider the input of the analog adder to be (Input voltage vector based on analog summing module , determine the input of each analog adder in the analog addition module as ), the voltage excitation is , then the output of the analog adder is .

[0036] Figure 7 The embodiment 2 provided in this application shows a schematic diagram of the memristor simulation equation solver provided in this application to solve the matrix equation. The entire solution process includes the following steps: (1) For the matrix equation Ax=b, convert it into The iterative solution form is represents the iteration matrix, represents the iteration vector, Indicates the The solution obtained by the iterative solution is Indicates the The solution is obtained by iterative solution. And the iteration matrix B and iteration vector f are input into the solver; (2) the iteration matrix B is mapped in the simulation calculation core, Represents the matrix obtained by residual mapping for each simulation computing core ( ), represents the amplification factor of the TIA array in each simulation computing core, Represents the conductivity matrix of each simulation kernel mapping; (3) The iteration vector f is converted into a voltage quantity through DAC (as the voltage excitation is ), input the simulation addition module and start the iterative solution process; in each round of iterative calculation, the input of the simulation calculation kernel is , the output of the simulation calculation core (the matrix obtained by residual mapping of each simulation calculation core ) are added to obtain the iterative matrix , and transport To the analog adding module, the analog adding module will With vector Add together to get . The iterative calculation is performed through the analog domain feedback process. It can be seen that the analog iterative calculation does not provide intermediate calculation results, and provides the final calculation results after the calculation converges. (4) After the iteration converges, the output vector of the analog addition module is converted into a digital quantity through the ADC and stored in the data cache module; (5) The final solution result is transmitted to the external digital system through the I / O module to complete other calculation / storage operations. The above operation step (1) is performed by the external calculator, and the above operation steps (2)-(5) are performed by the solver provided by this application.

[0037] Here we will expand on the operation step (2) of the above solution process. Figure 8 The high-precision memristor analog matrix equation solver designed in this application is demonstrated by The high-precision mapping of matrix B is realized by using the residual mapping method. The residual mapping method includes the following steps: (1) Set the number of enabled simulation computing cores to ( ), by programming the memristor with multiple values, write the matrix B into the first analog computing core; (2) read the mapping result of the first analog computing core , calculate the iteration matrix Mapping results with data The error matrix between (or called calculated residual) ; (3) For the An analog computing core is used to write the error matrix through analog programming of the memristor. To A simulation computing core, read the Data mapping results of simulation computing cores ,calculate and The error matrix (or calculated residual) , , Indicates the The error matrix corresponding to the simulation calculation kernel is Indicates the The error matrix corresponding to the simulation kernel. (4) Repeat step (3) until Each simulation core is programmed. When the mapping operation is completed, the actual matrix B mapped is expressed as It should be noted that the residual mapping method can select the number of computing cores to be enabled according to the accuracy requirements of the solution task. , in order to meet the requirements of different computing tasks for solution accuracy and energy consumption.

[0038] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0039] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A high-precision memristor analog matrix equation solver, characterized in that: include: Multiple analog computing cores, analog addition modules, digital-to-analog conversion modules, analog-to-digital conversion modules, data cache modules, global controllers, and I / O modules; The analog computing core, analog addition module and global controller are interconnected through a transmission bus; The input end of the digital-to-analog conversion module is connected to the data buffer module, and the output end of the digital-to-analog conversion module is connected to the analog addition module; The input end of the analog-to-digital conversion module is connected to the analog addition module, and the output end of the analog-to-digital conversion module is connected to the data buffer module; The data cache module is interconnected with the I / O module, and the I / O module is controlled by the global controller; Multiple simulation cores for iterating matrices Perform residual mapping and calculate voltage vector , Indicates the number of current iterations; Analog summing module for voltage vector based and iterative vector , determine the updated solution result , iterative matrix and iterative vector Iteration matrix and iteration vector in the iterative solution form corresponding to the matrix equation; The global controller is used to control the analog computing core and the analog addition module through the transmission bus to perform iterative solution until the solution converges.

2. The high-precision memristor analog matrix equation solver according to claim 1, characterized in that: The analog computing core includes: two memristor computing array modules, an inverter array, an adjustable transimpedance amplifier array, and a local controller; The two memristor computing array modules are respectively a first memristor computing array module and a second memristor computing array module; The input end of the first memristor computing array module is connected to the input end of the analog computing core, the input end of the inverter array is connected to the input end of the analog computing core, and the input end of the second memristor computing array module is connected to the output end of the inverter array; The output ends of the two memristor computing array modules are connected to the input end of the adjustable transimpedance amplifier array, and the output end of the adjustable transimpedance amplifier array is the output end of the analog computing core; The local controller is connected to the memristive computing array module, and is used to control the gating state of the array in the memristive computing array module and control the application of analog signals to the memristive computing array module.

3. The high-precision memristor analog matrix equation solver according to claim 2, characterized in that: The memristive computing array module includes: Large-scale memristor arrays, multiplexers, and driver circuits; The driving circuit is connected to the row input port of the memristor array, and the multiplexer is connected to the column output port of the memristor array.

4. The high-precision memristor analog matrix equation solver according to claim 3, characterized in that: The memristor array is specifically a crossbar array, which is an array composed of M row lines and N column lines crossing each other, and the memristors are located at the intersections of the array; The input end of the memristor array is composed of M row lines of the crossbar array, and the output end of the memristor array is composed of N column lines of the crossbar array.

5. The high-precision memristor analog matrix equation solver according to claim 4, characterized in that: The memristor medium is resistive random access memory (ReRAM), phase change memory (PCM), or ferroelectric field effect transistor (FeFET).

6. The high-precision memristor analog matrix equation solver according to claim 2, characterized in that: The adjustable transimpedance amplifier array includes N adjustable transimpedance amplifiers, where N is the number of columns of the memristor calculation array module; The adjustable transimpedance amplifier includes an operational amplifier and an adjustable resistor; the adjustable resistor is connected between the input and output terminals of the operational amplifier; One adjustable transimpedance amplifier corresponds to one column in the memristive computing array module; The input of the adjustable transimpedance amplifier is the sum of the output of the corresponding column in the first memristive computing array module and the output of the corresponding column in the second memristive computing array module; The outputs of the N adjustable transimpedance amplifiers constitute the output of the analog computing core.

7. The high-precision memristor analog matrix equation solver according to claim 6, characterized in that: The analog calculation kernel is used to perform differential calculations using the following formula: ； ； in, represents the output vector of the simulation kernel, represents the input vector of the simulation kernel, Indicates the resistance value of the adjustable resistor. is the mapping parameter of the first memristor computing array module, The mapping parameters of the array module are calculated for the second memristor.

8. The high-precision memristor analog matrix equation solver according to claim 2, characterized in that: The analog adding module includes N analog adders, where N is the number of columns of the memristor computing array module; The first input of the N analog adders is based on the voltage vector Determined; The second input of the N analog adders is based on the iteration vector Determined; The outputs of the N analog adders are determined by addition calculation based on the first input and the second input.

9. A method for operating a high-precision memristor analog matrix equation solver, characterized in that: Applied to the high-precision memristor analog matrix equation solver according to any one of claims 1 to 8, the operating method includes: Perform iterative solution until the solution converges; Iterative solution, including: Iteration matrix Perform residual mapping and calculate voltage vector , Indicates the number of current iterations; Based on voltage vector and iterative vector , determine the updated solution result .

10. The method for operating the high-precision memristor analog matrix equation solver according to claim 9, characterized in that: The iteration matrix Perform residual mapping and calculate voltage vector ,include: Determines the number of simulation cores enabled ; For the first analog computing core among the enabled analog computing cores, the iteration matrix is ​​written by analog programming of the memristor Go to the first simulation computing core and read the data mapping result of the first simulation computing core , and calculate the iteration matrix Mapping results with data The error matrix between ; For the second to third of the enabled simulation cores An analog computing core is used to write the error matrix through analog programming of the memristor. To A simulation computing core, read the Data mapping results of simulation computing cores ,calculate and The error matrix , , Indicates the The error matrix corresponding to the simulation calculation kernel is Indicates the The error matrix corresponding to the simulation kernel; Based on the data mapping results of each enabled simulation computing core, the iteration matrix is ​​obtained by summing the data mapping results. ; Based on iterative matrix and the current solution results , calculate the voltage vector .

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