Hierarchical circuit repairing method based on netlist learning

Abstract

The invention provides a method for repairing a Hierarchical circuit based on netlist learning, and aims to solve the technical problems that in a traditional repairing scheme, logic resource consumption is high, a circuit hierarchical structure is prone to being damaged, and time delay power consumption is increased. The method comprises the steps that information of the Hierarchical circuit is obtained in a netlist learning mode, the connection state of a clock pin of a scanning unit is recognized according to the information, and therefore the Hierarchical circuit is repaired. According to the method, an optimal repair point is positioned by combining hierarchical structure analysis, a clock signal repair strategy based on minimum MUX module insertion is provided for a multi-clock scene, time delay accumulation and power consumption rise caused by excessive deployment of logic units in a deep module are avoided, and experimental results show that the method can significantly improve the test coverage rate and improve the test efficiency. And the occupation of logic resources for repairing the violation points is reduced, so that the technical bottleneck of repairing the multi-clock Hierarchical circuit is effectively broken through, and an efficient solution is provided for the testability design of a super-large-scale integrated circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and manufacturing, specifically to the field of integrated circuit testability design, and more specifically to a hierarchical circuit repair method based on netlist learning. Background Art

[0002] With the continued growth of chip sizes and the rapid advancement of integrated circuit processes, the use of Electronic Design Automation (EDA) tools has become an indispensable part of chip design. However, as design complexity increases, the probability of Design Rule Check (DRC) violations during chip manufacturing increases significantly. This is especially true in multi-clock hierarchical circuits, where DRC issues are even more prominent.

[0003] Traditional design rule repair methods mostly focus on flat circuit structures. This type of circuit layout is relatively simple, the component connection relationship is intuitive, and the rule checking and repair logic is relatively clear. However, in hierarchical circuits, circuits are constructed through modular and hierarchical design, with nesting and interaction between levels. The complex hierarchical relationship causes the clock signal propagation path to present a complex multi-branch, cross-level form, involving not only signal transmission within the same level, but also across multiple sub-module levels. This makes it difficult for traditional methods to efficiently handle the complex relationships between multiple levels when parsing circuit netlists (files that systematically describe the resistors, capacitors, transistors and other components and electrical connection relationships in the circuit in text form), resulting in problems such as significantly reduced scanning efficiency and time-consuming error location.

[0004] Furthermore, traditional DRC repair solutions typically employ a simple strategy of directly inserting a large amount of MUX logic (a digital logic circuit that selects a single output from multiple input signals based on a select signal) when addressing violations. While this "stacking" repair approach is simple to implement, it inevitably significantly increases chip area, leading to more crowded circuit routing space. Signal transmission paths become longer, increasing latency and impacting chip speed. Furthermore, the additional logic cells increase power consumption, reducing chip energy efficiency. Furthermore, this repair approach lacks a holistic view of the hierarchical circuit structure, making it difficult to achieve efficient and accurate DRC repair, severely restricting improvements in hierarchical circuit design efficiency and quality.

[0005] In summary, traditional design rule checking (DRC) repair methods exhibit multiple shortcomings when working with hierarchical circuits. First, the efficiency of circuit netlist parsing is significantly reduced due to the complex clock signal paths introduced by the hierarchical structure, making it difficult to quickly locate faulty nodes. Second, the simple repair strategy of inserting a large amount of MUX logic, while simple to implement, can lead to increased chip area, increased latency, and increased power consumption. Therefore, a new DRC repair solution tailored to hierarchical circuits is urgently needed to overcome the technical bottlenecks of traditional methods and effectively improve the efficiency of hierarchical circuit repair.

[0006] It should be noted that this background information is provided solely to introduce relevant information of the present invention to facilitate understanding of the technical solution of the present invention. It does not necessarily constitute prior art. In the absence of evidence demonstrating that the relevant information was disclosed prior to the filing date of the present invention, the relevant information should not be considered prior art. Summary of the Invention

[0007] Therefore, the purpose of the present invention is to overcome the above-mentioned defects of the prior art and provide a hierarchical circuit repair method based on netlist learning.

[0008] The purpose of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, a hierarchical circuit repair method based on netlist learning is proposed, which is used to detect whether there is a problem with the clock pin connection of a scan unit in a hierarchical circuit inserted with a scan chain and repair the problematic circuit, wherein the hierarchical circuit includes one or more module instances and scan units, each module instance is an instance of a user module, and each user module includes one or more logic units. The method comprises: step S1, obtaining a gate-level netlist, a selection signal, and a system clock signal of the hierarchical circuit to be detected; step S2, parsing the gate-level netlist obtained in step S1 to obtain the hierarchical structure and connection relationship between the module instances and the logic units in the hierarchical circuit to be detected, and constructing a netlist database based on this; step S 3. Based on the constructed netlist database, a module instance containing a scanning unit is obtained, and a unique operation is performed on the user module corresponding to each obtained module instance to ensure that a one-to-one correspondence is formed between each module instance containing a scanning unit and the user module; step S4, based on the constructed netlist database and the preset clock pin connection rules, each scanning unit in the hierarchical circuit to be detected is checked to determine whether the scanning unit in the hierarchical circuit to be detected has a clock pin connection problem, wherein the clock pin includes a CLK pin, a SET pin, and a RESET pin; step S5, according to a preset repair method, the module instance of the hierarchical circuit to be detected that has a clock pin connection problem is repaired, and the same repair operation is performed on the user module corresponding to the module instance.

[0010] Preferably, in step S1, the signal set of the hierarchical circuit to be detected is obtained in the following manner: by parsing a configuration file constructed by the user according to requirements to obtain a selection signal and a system clock signal of the hierarchical circuit to be repaired.

[0011] Preferably, the hierarchical structure and connection relationship between module instances and logic units include: the hierarchical structure in each module instance; the hierarchical path of each module instance in the hierarchical circuit to be tested; the input signal and output signal of each module instance; the complete transmission path of each signal in the hierarchical circuit to be tested; and the fan-in relationship, fan-out relationship of each module instance and the type of logic unit contained in each module instance.

[0012] Preferably, in step S5, the preset repair method includes: when multiple scanning units have the same clock pin connection problem and share the same clock signal, obtaining the common path of the multiple scanning units with the same clock pin connection problem based on the netlist database, and inserting a MUX module in the common path to simultaneously repair multiple clock pin connection problems.

[0013] Preferably, in step S5, the preset method includes: when a scanning unit with a clock pin connection problem is located in a bottom module instance, obtaining the hierarchical path of the module instance based on the netlist database, and preferentially inserting a MUX module into the top module instance or the middle module instance in the module instance hierarchical path to repair the clock pin connection problem of the scanning unit.

[0014] Preferably, in step S5, the preset repair method includes: when there is a connection problem with the RESET pin or the SET pin, repairing the connection problem with the RESET pin or the SET pin by inserting a minimum of MUX modules, on the premise of ensuring that the repaired scanning unit can correctly respond to the reset signal.

[0015] Preferably, the MUX module includes a mode selection input port, a first signal input port, a second signal input port, and an output signal port, wherein the MUX module is inserted in the following manner: the insertion position of the MUX module is determined based on a preset position constraint, the MUX module is inserted into the determined insertion position, and the ports of the MUX module are connected in the following manner: the selection signal is connected to the mode selection input port of the MUX module; the original signal connected to the clock pin is connected to the first signal input port of the MUX module; the system clock signal is connected to the second signal input port of the MUX module; and the output signal port of the MUX module is connected to the clock pin of the scanning unit where there is a connection problem.

[0016] Preferably, the preset position constraints include: preferentially inserting a MUX module at the source of the propagation path of the input signal of the clock pin with connection problems to reduce the noise accumulated by the signal in the propagation path; inserting the MUX module at the boundary position of the module instance to avoid destroying the hierarchical structure of the Hierarchical circuit to be repaired.

[0017] Preferably, in step S5, the preset repair method includes: when the hierarchical circuit to be repaired is a multi-clock domain circuit, repairing the clock pin connection problem in the following manner: if the scan chain where the scanning unit with the clock pin connection problem is located belongs to one clock domain, obtaining the system clock signal of the clock domain where the scanning unit is located, and connecting the obtained system clock signal to the clock signal pin of the scanning unit to ensure that the scan chain where the repaired scanning unit is located does not cross clock domains; if the scan chain where the scanning unit with the clock pin connection problem is located belongs to multiple clock domains, inserting a DLAT module in front of the scanning unit, obtaining the system clock signal of the clock domain where the scanning unit is located, and connecting the obtained system clock signal to the inserted DLAT module to avoid timing disorder problems in the scanning unit.

[0018] According to a second aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. The computer program can be executed by a processor to implement the steps of any method described in the first aspect of the present invention.

[0019] Compared with the prior art, the advantages of the present invention are:

[0020] This invention uses a netlist learning mechanism to analyze the hierarchical structure and connection relationships of hierarchical circuits, accurately locates connection issues with scan unit clock pins, and combines hierarchical analysis to select the optimal repair point. It adopts a strategy of minimizing MUX module insertion for multi-clock scenarios, avoiding latency and power consumption issues caused by excessive deployment of deep-level module logic. It also ensures circuit hierarchy integrity through unique operations and boundary insertion rules. This effectively overcomes the technical bottlenecks of traditional repair solutions in terms of logic resource consumption, hierarchical structure protection, and latency and power consumption control, providing an efficient and reliable testability design solution for very large-scale integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of steps of a hierarchical circuit repair method based on netlist learning according to an embodiment of the present invention;

[0023] Figure 2 A pseudo code diagram of a configuration file according to an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a hierarchical structure of a module instance according to an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of unique operations according to an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of repairing a clock pin connection problem according to an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of repairing a clock pin connection problem in a multi-clock domain circuit according to an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of a clock pin connection problem that does not require repair according to an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of a clock pin connection problem that does not require repair according to an embodiment of the present invention;

[0030] Figure 9 A schematic diagram of a clock pin connection problem that does not require repair according to an embodiment of the present invention;

[0031] Figure 10 Schematic diagram of comparative experimental data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] As mentioned in the background technology section, traditional design rule repair methods expose multiple deficiencies when dealing with hierarchical circuits. On the one hand, the efficiency of parsing the circuit netlist is significantly reduced due to the complex clock signal paths brought about by the hierarchical structure, making it difficult to quickly locate the faulty nodes. On the other hand, the repair strategy of simply inserting a large amount of MUX logic, although easy to operate, will lead to problems such as increased chip area, increased latency, and increased power consumption. Therefore, there is an urgent need for a DRC repair solution that breaks through the technical bottlenecks of traditional methods, effectively improves the efficiency of hierarchical circuit repair, and is suitable for multi-clock domain hierarchical circuits.

[0034] Through careful research, the inventors discovered that the design rule check for multi-clock hierarchical circuits primarily focuses on the connection relationship of the clock pins (CLK, SET, RESET) of the scan cells. When the clock pins are not correctly connected to the system clock signal, it may cause chip timing disorder and test vector generation failure, thereby affecting the circuit fault coverage. Therefore, to solve the above problems, the present invention proposes a hierarchical circuit repair method based on netlist learning. This method learns the netlist during the circuit analysis phase, identifies the connection status of each scan cell, and combines hierarchical structure analysis to select the optimal repair point, thereby minimizing the use of logic resources and the impact on circuit performance. The steps of this method are shown in [1]. Figure 1 In summary, the method includes steps S1 to S4, wherein, in step S1, a gate-level netlist, a selection signal, and a system clock signal of a hierarchical circuit to be tested are obtained; in step S2, the gate-level netlist obtained in step S1 is parsed to obtain the hierarchical structure and connection relationship between module instances and logic units in the hierarchical circuit to be tested, and a netlist database is constructed based on the obtained gate-level netlist; in step S3, a module instance including a scan unit is obtained based on the constructed netlist database, and a unique operation is performed on the user module corresponding to each obtained module instance to ensure that a one-to-one correspondence is formed between each module instance including a scan unit and the user module; in step S4, each scan unit in the hierarchical circuit to be tested is checked based on the constructed netlist database and a preset clock pin connection rule to determine whether the scan unit in the hierarchical circuit to be tested has a clock pin connection problem, wherein the clock pin includes a CLK pin, a SET pin, and a RESET pin; in step S5, the module instance of the hierarchical circuit to be tested that has a clock pin connection problem is repaired according to a preset repair method, and the same repair operation is performed on the user module corresponding to the module instance.

[0035] In order to better understand the present invention, each step will be described in detail below with reference to specific embodiments and drawings.

[0036] According to one embodiment of the present invention, in step S1 of the present invention, the test selection signal and the system clock signal of the hierarchical circuit to be detected are obtained in the following manner: by parsing a configuration file constructed by the user according to the requirements, the selection signal and the system clock signal of the hierarchical circuit to be repaired are obtained. In order to facilitate understanding of how the present invention obtains the selection signal and the system clock signal of the hierarchical circuit to be detected, the following will be described with reference to the accompanying drawings. Figure 2The pseudo code in the figure describes the information of the user-configured selection signal and the system clock signal. MultiClkInfo represents the information of the CLK signal in the system clock signal, MultiRstInfo represents the information of the Reset signal in the system clock signal, Reset represents the information of the Reset signal in the system clock signal, Test Mode represents the selection signal in the test mode, ScanDataIn represents the input signal of the scan unit, ScanDef represents the information related to the insertion chain in the netlist, Reset represents the reset signal, ScanDataIn represents the input signal of the scan unit, ScanDataOut represents the output signal of the scan unit, ScanEnable represents the enable signal connected to the scan unit, and ScanChainCount represents the number of scan chains.

[0037] According to one embodiment of the present invention, in step S2 of the present invention, the hierarchical structure and connection relationship of the example modules and logic units obtained include: the hierarchical structure in each module instance; the hierarchical path of each module instance in the hierarchical circuit to be tested; the input and output signals of each module instance; the complete transmission path of each signal in the hierarchical circuit to be tested; and the fan-in relationship and fan-out relationship of each module instance, as well as the type of logic units contained in each module instance. The present invention constructs a netlist database based on this information. Subsequently, during the design rule checking and violation point repair stages, this data can be directly called from the netlist database to quickly analyze and locate the hierarchical circuit.

[0038] According to one embodiment of the present invention, the hierarchical structure of each module instance and the hierarchical path of each module instance in the hierarchical circuit to be detected need to analyze the structural relationship between the logic units (such as AND, OR, MUX, etc.) of each module instance and the module instance. Each instance has a unique hierarchical path to identify its position in the circuit. See Appendix. Figure 3 Taking "In2==U1==M1" as an example, "==" represents a hierarchical relationship, where: In2 represents the top-level module, U1 represents a sub-module instance in In2, and M1 represents a deeper sub-module instance in U1.

[0039] According to one embodiment of the present invention, the hierarchical structure of each module instance and the hierarchical path of each module instance in the hierarchical circuit to be inspected are stored hierarchically in the following manner. Each instance's hierarchical path is stored in a hierarchical data structure, specifically including: a top-level module (such as In2), which identifies the module's global scope; a sub-module (such as U1), which records the module's local scope; and a signal path (such as I1 or Y), which records the signal propagation path at each level. This hierarchical storage method effectively supports subsequent hierarchical structure analysis and repair operations, avoiding misoperations caused by confusion about hierarchical relationships.

[0040] According to one embodiment of the present invention, the complete transmission path of each module instance's input signal and output signal and each signal in the hierarchical circuit to be detected is obtained by gradually traversing each instance's input port (pins) and tracing back to its previous connection point. Figure 3 Taking "In2==U1==M1" as an example: the signal of input port Pin I1 of Instance U1==M1 comes from Pin I1 of its upper-layer module In2. Continuing to trace forward, the signal of I1 ultimately comes from Pin Y of the top-level module In1==U1. During the tracing process, the connection relationship of each level (including signal name, hierarchical path and port information) is saved in the data structure, for example, In1==U1.Y->In1==O1->In2.I1->In2==U1.I1->In2==U1==M1.I1. This is a complete signal transmission path. According to the complete signal transmission path, the input and output signals of each module instance can also be obtained. The present invention uses a recursive tracing method to quickly determine the relationship between any module and the top-level input of the system.

[0041] According to one embodiment of the present invention, in the present invention, the fan-in relationship, fan-out relationship of each module instance and the type signal fan-in / fan-out analysis of the logic unit contained in each module instance are shown in the attached FIG. Figure 3 For In2==U1==M1, the fan-in of its input signal I1 comes from In2==U1.I1. For M1's output signal O1, its fan-out target is the next-level logic unit or module. Obtaining fan-in / fan-out information can help quickly analyze the signal propagation path and determine whether the pins of the scan unit are correctly connected to the system clock signal (CLK, SET, RESET) or other key signals.

[0042] It should be noted that the same user module can be instantiated multiple times, thereby generating multiple corresponding module instances. The circuit structure of the user module and all its corresponding module instances remains consistent. However, during the repair process, if differentiated repair operations are performed on different instances (for example, only some instances are repaired, or different repair strategies are used for each instance), due to the structural synchronization mechanism between modules and instances, these operations may be forcibly synchronized to all associated entities, thereby causing unintended global impacts. To address the above problem, according to one embodiment of the present invention, a unique operation (uniqueness operation) is performed on the user module corresponding to each module instance containing a scanning unit. The unique operation uniquely processes the user module that has been instantiated multiple times, thereby establishing a one-to-one correspondence between the user module and the module instance.

[0043] In order to more clearly illustrate the unique operation of the present invention, the following description will be made with reference to the accompanying drawings. Since the inspection of the circuit of the present invention is mainly focused on the connection relationship of the clock pins (CLK, SET, RESET) of the scanning unit (Scan Cell), in other words, only the module instance containing the scanning unit will be detected with a connection problem, that is, the repair operation is also concentrated in the module instance containing the scanning unit. Therefore, the present invention only performs the unique operation on the user module corresponding to the module instance containing the scanning unit. See the accompanying drawings. Figure 4 The left side of the figure is a schematic diagram of the correspondence between user modules and module instances before the unique operation, that is, one user module corresponds to multiple module instances. The right side of the figure is a schematic diagram of the correspondence between user modules and module instances after the unique operation, each module instance corresponds to a user module, so that after any module instance is repaired, the same repair operation will only be performed on the user module corresponding to it, without affecting the internal structure of other user modules and module instances.

[0044] According to one embodiment of the present invention, in step S4, a design rule check is performed on each scan cell (Scan Cell) in the circuit one by one based on the preset clock pin connection rule, focusing on analyzing the connection between its clock pin (CLK, SET, RESET) and the system clock. The purpose of the design rule check is to ensure the correctness of the clock signal and the stability of its propagation, and to avoid affecting the function and test coverage of the circuit due to clock connection errors. The preset clock pin connection rules include Rule 1, Rule 2 and Rule 3. In order to facilitate understanding of each preset clock pin connection rule, each rule will be described in detail below.

[0045] Rule 1

[0046] According to one embodiment of the present invention, in the present invention, the clock pin of the scanning unit needs to be correctly connected to the system clock signal and meet the trigger state of the trigger. If the clock pin (such as CLK, SET, RESET) of the scanning unit is correctly connected to the global clock signal of the system and the trigger edge (Rising Edge or Falling Edge) of the clock signal is consistent with the design requirements of the trigger, then it is considered that the scanning unit does not need to be repaired. At the same time, it is necessary to further verify whether the "off-state" state (i.e., the inactive state) of the clock signal meets the requirements of low power consumption and test mode to ensure that the clock signal does not interfere with the circuit operation when it is not working.

[0047] Rule 2

[0048] According to one embodiment of the present invention, in the present invention, the clock pin of the scanning unit needs to be connected to the system clock signal and ensure that the trigger state of the trigger is correct. If the clock pin of the scanning unit has been connected to the system clock signal, but the edge (Edge Trigger) of the clock signal does not meet the design requirements of the trigger (for example, the trigger requires a rising edge trigger, but the connected clock is a falling edge), it needs to be repaired.

[0049] Rule 3

[0050] According to one embodiment of the present invention, in the present invention, if the clock pin of the scanning unit is not directly connected to the system clock signal, but is indirectly connected through other logic gates (such as AND, OR, MUX, etc.), it is necessary to determine whether these logic gates will affect the correct propagation of the clock signal. The basis for determining whether the clock pin of the scanning unit is not directly connected to the system clock signal includes: (1) whether the function of the logic gate destroys the periodicity of the clock signal. For example, if the logic gate may introduce additional delays, glitches or irregular waveforms, it should be considered as a violation point; (2) whether the logic gate correctly responds to the test signal (Test Mode). For example, in the test mode, the output of the logic gate must be able to correctly propagate the system clock signal to the clock pin of the scanning unit; (3) timing analysis of the logic path, that is, through static timing analysis (STA), determine whether the logic path meets the setup time (Setup Time) and hold time (Hold Time) of the clock signal. If not, it needs to be repaired.

[0051] It should be noted that the clock pin connection rules listed above are only illustrative and non-exhaustive. Implementers can add other clock pin connection rules according to specific needs, or select some of the above rules for application.

[0052] According to one embodiment of the present invention, in step S5 of the present invention, the module instance of the Hierarchical circuit to be detected with the clock pin connection problem is repaired according to a preset repair method, and the same repair operation is performed on the user module corresponding to the module instance. In summary, the preset repair method includes method 1, method 2, method 3 and method 4. The four repair methods will be described in detail below.

[0053] Method 1

[0054] According to one embodiment of the present invention, when multiple scan units have the same clock pin connection problem and share the same clock signal, the common path of the multiple scan units with the same clock pin connection problem is obtained based on the netlist database, and a MUX module is inserted into the common path to simultaneously repair multiple clock pin connection problems, so that the repair range of one MUX logic covers as many illegal connection points as possible, thereby minimizing hardware resource consumption. Figure 5 , (a) in the figure is a schematic diagram of the result of repairing the situation where multiple scanning units have the same clock pin connection problem and share the same clock signal using the existing repair method. Specifically, a MUX module is inserted into each of the two scanning units that have the same clock pin connection problem and share the same clock signal, and (b) in the figure is a schematic diagram of the result of repair using the repair method proposed in the present invention. The CLK ports of the two scanning units are controlled by the signal NET_1 (instead of the CLK signal), so only one MUX logic unit needs to be added, with its Sel-0 end connected to the NET_1 signal, its Sel-1 end connected to the CLK signal, its S0 end connected to the TEST_MODE signal, and its Y end connected to the CLK of the two scanning units respectively.

[0055] Method 2 is to obtain the hierarchical path of the module instance from the netlist database when a scan unit with a clock pin connection problem is located in a bottom-level module instance. Based on the obtained hierarchical path, a MUX module is preferentially inserted into the top-level module instance or the middle-level module instance in the module instance hierarchical path to fix the clock pin connection problem of the scan unit. Specifically, to avoid excessive insertion of MUX modules in deep-level modules and prevent delay accumulation and power consumption increase due to logic nesting, the MUX module is preferentially inserted into shallow-level modules (such as top-level or middle-level modules) by analyzing the logic hierarchy relationship. Figure 3 In the module instance In2, if there is a connection problem with the scanning unit in M1, the present invention gives priority to inserting MUX modules in In2 and I1 to avoid excessive insertion of MUX modules in deep-level modules, effectively suppressing the signal delay accumulation and power consumption increase caused by logic level nesting.

[0056] Method 3 is to repair the connection problem of the RESET pin or SET pin by inserting a minimum of MUX modules, while ensuring that the repaired scanning unit can correctly respond to the reset signal when there is a connection problem with the RESET pin or SET pin.

[0057] Method 4 is that when the hierarchical circuit to be repaired is a multi-clock domain circuit, if the scan chain where the scan unit with the clock pin connection problem is located belongs to one clock domain, obtain the system clock signal of the clock domain where the scan unit is located, and connect the obtained system clock signal to the clock signal pin of the scan unit to ensure that the scan chain where the repaired scan unit is located does not cross the clock domain; if the scan chain where the scan unit with the clock pin connection problem is located belongs to multiple clock domains, insert a DLAT module (DLAT module refers to D-Latch module, i.e. D-Latch is a basic digital storage device used to capture and hold data signals under specific conditions) in front of the scan unit, obtain the system clock signal of the clock domain where the scan unit is located, and connect the obtained system clock signal to the inserted DLAT module to avoid timing disorder problems in the scan unit. See Appendix. Figure 6 ,The two scan units (SDFF1 and SDFF2) in the figure do not belong to the same clock ,domain. Therefore, when repairing SDFF2, a DLAT module is inserted before SDFF2 to avoid ,timing issues.

[0058] According to one embodiment of the present invention, in the present invention, the MUX module includes a mode selection input port, a first signal input port, a second signal input port, and an output signal port, wherein each MUX module is inserted in the following manner: the insertion position of the MUX module is determined based on a preset position constraint, the MUX module is inserted into the determined insertion position, and the ports of the MUX module are connected in the following manner: the selection signal is connected to the mode selection input port of the MUX module; the original signal connected to the clock pin is connected to the first signal input port of the MUX module; the system clock signal is connected to the second signal input port of the MUX module; and the output signal port of the MUX module is connected to the clock pin of the scanning unit where there is a connection problem.

[0059] According to an embodiment of the present invention, the present invention does not repair three situations where the clock pins are incorrectly connected. The three situations will be described below in conjunction with Example 1, Example 2 and Example 3.

[0060] Example 1

[0061] See also Figure 7,In the figure, before the scanning unit is repaired, that is, before the MUX module is inserted, the CLK end of the scanning unit is directly connected to the AND logic gate. One end of the AND logic gate is connected to the CLK signal and the other end is connected to the Tie-1 signal. Therefore, the AND logic gate is solely controlled by the CLK signal and therefore does not need to be repaired.

[0062] Example 2

[0063] See also Figure 8 ,In the figure, before the scanning unit is repaired, that is, before the MUX module is inserted, the CLK end of the scanning unit is directly connected to the OR logic gate. One end of the OR logic gate is connected to the CLK signal and the other end is connected to the Tie-0 signal. Therefore, the OR logic gate is solely controlled by the CLK signal, so there is no need for excessive repair.

[0064] Example 3

[0065] See also Figure 9 ,In the figure, before the scanning unit is repaired, that is, before the MUX module is inserted, the CLK end of the scanning unit is directly connected to the clock unit, so the clock unit is solely controlled by the CLK signal, so there is no need for excessive repair.

[0066] According to one embodiment of the present invention, in the present invention, the preset location constraints include preferentially inserting a MUX module at the source of the propagation path of the input signal of the clock pin with connection problems to reduce the noise accumulated by the signal in the propagation path; and inserting the MUX module at the boundary position of the module instance to avoid destroying the hierarchical structure of the Hierarchical circuit to be repaired.

[0067] In order to prove the beneficial effects of the present invention, the inventors designed a comparative experiment to compare the number of MUX insertions before and after applying the repair method proposed by the present invention. The experimental results are as follows: Figure 10As shown in the figure, the difference ("Diff.") is used to show the number of MUX modules inserted by the present invention. For designs such as picorv32 and openC906, most clock and set / reset fixes are greatly reduced after applying the repair method proposed by the present invention. For example, openC906 cut 1,134 MUX modules inserted into clock ports and 821 MUX modules added before set / reset pins. openE902 saw a greater relative impact, with the number of added MUX modules going from 481 to 0. In contrast, the sv_nyuzi and gpu_unit circuit designs had MUX differences, which indicates that the clock signals of these circuit designs have largely met the test requirements, or that the gating logic of these circuit designs is minimal. Overall, these results demonstrate that the repair method proposed by the present invention can combine the netlist analysis results to select the optimal MUX insertion point and minimize the use of logic resources and the impact on circuit performance.

[0068] The present invention analyzes the hierarchical structure and connection relationship of the hierarchical circuit through the netlist learning mechanism, accurately locates the connection problem of the scan unit clock pin, combines hierarchical analysis to realize the optimal repair point selection, and adopts the minimized MUX module insertion strategy for multi-clock scenarios to avoid the delay and power consumption problems caused by excessive deployment of deep-level module logic. At the same time, the circuit hierarchy integrity is guaranteed through unique operations and boundary insertion rules, effectively breaking through the technical bottlenecks of traditional repair solutions in logic resource consumption, hierarchical structure protection and delay power consumption control, and providing an efficient and reliable testability design solution for very large-scale integrated circuits.

[0069] It should be noted that although the above describes the various steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0070] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0071] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove having instructions stored thereon, and any suitable combination thereof.

[0072] While various embodiments of the present invention have been described above, the above descriptions are intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A hierarchical circuit repair method based on netlist learning, for detecting whether there are problems with the clock pin connection of a scan unit in a hierarchical circuit inserted into a scan chain and repairing the problematic circuit. The hierarchical circuit includes one or more module instances and scan units, each module instance is an instance of a user module, and each user module includes one or more logic units. The method is characterized in that: The method comprises: Step S1, obtaining a gate-level netlist, a selection signal, and a system clock signal of a hierarchical circuit to be tested; Step S2: parsing the gate-level netlist obtained in step S1 to obtain the hierarchical structure and connection relationship of module instances and logic units in the hierarchical circuit to be tested, and constructing a netlist database based on this; Step S3: obtaining module instances including scanning units based on the constructed netlist database, and performing a unique operation on the user modules corresponding to each obtained module instance to ensure a one-to-one correspondence between each module instance including the scanning unit and the user module; Step S4: checking each scan unit in the hierarchical circuit to be tested based on the constructed netlist database and the preset clock pin connection rules to determine whether the scan unit in the hierarchical circuit to be tested has a clock pin connection problem, wherein the clock pins include a CLK pin, a SET pin, and a RESET pin; Step S5: Repair the module instance of the to-be-detected hierarchical circuit with the clock pin connection problem according to a preset repair method, and perform the same repair operation on the user module corresponding to the module instance.

2. The method according to claim 1, characterized in that In step S1, a signal set of the hierarchical circuit to be detected is obtained in the following manner: By parsing the configuration file built by the user according to the requirements, the selection signal and system clock signal of the hierarchical circuit to be repaired are obtained.

3. The method according to claim 1, characterized in that The hierarchical structure and connection relationship between module instances and logic units include: The hierarchy within each module instance; The hierarchical path of each module instance in the Hierarchical circuit to be detected; Input and output signals for each module instance; The complete transmission path of each signal in the hierarchical circuit to be tested; and The fan-in relationship and fan-out relationship of each module instance and the type of logic units contained in each module instance.

4. The method according to claim 1, wherein In step S5, the preset repair method includes: When multiple scan units have the same clock pin connection problem and share the same clock signal, the common path of the multiple scan units with the same clock pin connection problem is obtained based on the netlist database, and a MUX module is inserted into the common path to simultaneously repair multiple clock pin connection problems.

5. The method according to claim 1, characterized in that In step S5, the preset method includes: When a scan unit with a clock pin connection problem is located in a bottom-level module instance, the hierarchical path of the module instance is obtained based on the netlist database, and a MUX module is preferably inserted into the top-level module instance or the middle-level module instance in the module instance hierarchical path to fix the clock pin connection problem of the scan unit.

6. The method according to claim 1, wherein In step S5, the preset repair method includes: When there is a connection problem with the RESET pin or the SET pin, the connection problem with the RESET pin or the SET pin is repaired by inserting a minimum of MUX modules, while ensuring that the repaired scanning unit can correctly respond to the reset signal.

7. The method according to any one of claims 4 to 6, characterized in that: The MUX module includes a mode selection input port, a first signal input port, a second signal input port, and an output signal port, wherein the MUX module is inserted in the following manner: Determine the insertion position of the MUX module based on the preset position constraints, insert the MUX module into the determined insertion position, and connect the ports of the MUX module as follows: Connect the selection signal to the mode selection input port of the MUX module; Connect the original signal connected to the clock pin to the first signal input port of the MUX module; Connect the system clock signal to the second signal input port of the MUX module; Connect the output signal port of the MUX module to the clock pin of the scanning unit where the connection problem occurs.

8. The method according to claim 7, characterized in that The preset position constraints include: It is recommended to insert a MUX module at the source of the propagation path of the input signal of the clock pin with connection problems to reduce the noise accumulated in the signal propagation path; Insert the MUX module at the boundary of the module instance to avoid destroying the hierarchical structure of the hierarchical circuit to be repaired.

9. The method according to claim 1, characterized in that In step S5, the preset repair method includes: When the hierarchical circuit to be repaired is a multi-clock domain circuit, repair the clock pin connection problem in the following ways: If the scan chain where the scan unit with the clock pin connection problem is located belongs to the same clock domain, obtain the system clock signal of the clock domain where the scan unit is located, and connect the obtained system clock signal to the clock signal pin of the scan unit to ensure that the scan chain where the repaired scan unit is located does not cross clock domains; If the scan chain where the scan unit with clock pin connection problem is located belongs to multiple clock domains, insert a DLAT module in front of the scan unit to obtain the system clock signal of the clock domain where the scan unit is located, and connect the obtained system clock signal to the inserted DLAT module to avoid timing disorder problems in the scan unit.

10. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 9.

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