Impedance adaptive packaging design method

Abstract

The invention discloses an impedance adaptive packaging design method. The method comprises the following steps: S1, selecting a packaging substrate for bearing and fixing a chip; s2, optimizing wiring by adding a signal complete reference plane and signal left and right accompanying ground, and designing wiring impedance matching; s3, a plurality of ground accompanying drill holes are additionally formed in the periphery of each signal drill hole in a circle, and design of drill hole impedance matching is carried out; and S4, under the condition that the size of the bonding pad cannot be adjusted, removing the reference layers above and below the bonding pad by using a reference layer principle, and improving the impedance of the bonding pad by adding an anti-bonding pad. The packaging structure is suitable for a substrate type packaging structure, for a chip with a high-speed or high-frequency characteristic, impedance matching is mainly achieved for a whole packaging link, from chip signal access to signal wiring, wiring is connected with a bonding pad through a drill hole, the impedance of the bonding pad is reduced, and the packaging structure is more compact. Therefore, impedance matching of single-ended or differential signals on the whole link from signal input to final solder ball output is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to an impedance-adaptive packaging design method. Background Art

[0002] Currently, impedance matching is not usually considered in the design between traditional chips and packaging substrates because the speed is low and the impact is negligible. However, as the chip application speed increases, impedance mismatch will cause signal distortion, seriously affecting chip performance. Therefore, impedance matching is required in the packaging design.

[0003] A packaging method is currently available, which includes: obtaining a substrate to be packaged, the substrate to be packaged including a high-resistance silicon substrate, the high-resistance silicon substrate having a packaging surface, solder joints being provided on the packaging surface, and a surface of the solder joints away from the high-resistance silicon substrate having a surface oxide layer; forming an impedance adjustment layer on the packaging surface, the impedance adjustment layer being used to reduce the surface resistivity of the high-resistance silicon substrate; and etching to remove the surface oxide layer to obtain a packaging structure.

[0004] However, this existing packaging method, first of all, increases the complexity of the process. When performing the impedance adjustment layer production and oxide layer removal operations, additional deposition and etching steps are required, which may reduce production efficiency and increase time and cost. Secondly, it increases the dependence on the impedance adjustment layer material. If the adjustment layer material is not selected appropriately, such as if it does not match the thermal expansion coefficient of high-resistance silicon, it may cause stress problems and affect the long-term reliability of the packaging structure. It also increases the accuracy requirements for surface oxide layer removal. Precise control is required when etching the surface oxide layer. Excessive etching may damage the solder joints or the substrate, while insufficient etching will leave a residual oxide layer, both of which affect the electrical performance. Summary of the Invention

[0005] In response to the above problems, the purpose of the present invention is to propose an impedance-adaptive packaging design method, which ensures impedance matching through multiple links such as wiring, drilling and pads on the entire packaging substrate, thereby achieving impedance matching on the entire packaging substrate, thereby ensuring impedance matching of single-ended or differential signals on the entire link from signal input to final solder ball output.

[0006] This is achieved through the following technical solutions: An impedance-adaptive packaging design method includes: S1. Selecting a packaging substrate for carrying and fixing a chip, wherein the basic structure for signal or power transmission on the packaging substrate includes wiring, drilling holes, and pads; S2. Optimizing wiring by adding a complete signal reference plane and left and right signal accompanying grounds, thereby designing wiring impedance matching; S3. Adding multiple accompanying ground holes around each signal drilling hole to achieve a ground reference plane for the signal drilling hole, thereby designing drilling impedance matching; S4. Fixing the size of the pad by attaching specified solder balls to the packaging substrate. When the pad size cannot be adjusted, utilizing the reference layer principle, removing the reference layers above and below the pad, and improving the pad impedance by adding anti-pads.

[0007] The present invention is applicable to substrate-type packaging structures. For chips with high-speed or high-frequency characteristics, the main method is to achieve impedance matching in the entire packaging link, from chip signal access to signal wiring. The wiring is connected to the pads through drilling, and the impedance of the pads themselves is reduced, thereby ensuring impedance matching of single-ended or differential signals in the entire link from signal input to final solder ball output.

[0008] Preferably, in step S1, the signals and power supply on the chip are led out to the outside through the wiring, drilling and pads in the package substrate. Impedance matching is ensured through multiple links of wiring, drilling and pads on the entire package substrate, so that impedance matching can be achieved on the entire package substrate.

[0009] Preferably, in step S1, the wiring, drilling holes, and pads are all made of copper material to carry the transmission of signals and power. Copper has good electrical conductivity, which can ensure smooth flow of current in the circuit, reduce signal loss and interference, and ensure stable signal transmission.

[0010] Preferably, in step S1, routing by signal type includes at least signal routing, power routing, and RF routing; and drilling by function includes at least signal drilling, power drilling, and ground via drilling. The present invention further achieves impedance matching across the entire package substrate by designing routing impedance matching and drilling impedance matching.

[0011] Preferably, in step S2, after adding the signal integrity reference plane and left and right signal ground planes, the signal reference plane is controlled to be intact and undivided, and the left and right reference paths of the signal wiring are controlled to be intact and undivided by setting a specific line width and controlling the dielectric properties. By adding the signal integrity reference plane and signal ground plane, the electric field distribution of the signal line can be uniform, avoiding sudden changes in capacitance or inductance caused by crossing divisions or gaps, and ensuring impedance matching for single-ended or differential signals.

[0012] Preferably, in step S3, after adding multiple companion ground holes around each signal hole, the multiple companion ground holes directly connect the signal hole to the nearest ground plane, achieving uniform electric field distribution for the signal line. By adding multiple companion ground holes, uniform electric field distribution for the signal line is achieved, and sudden changes in capacitance or inductance caused by crossing splits or gaps can be avoided, thereby achieving impedance matching in the drilling process.

[0013] Preferably, in step S4, after attaching the designated solder balls, the solder balls are used to lead out the signal or power supply on the package substrate. Leading out the signal or power supply on the package substrate through the solder balls can ensure stable signal transmission and stable power supply.

[0014] Preferably, in step S4, after adding the anti-pad, the anti-pad is used to reduce the overlapping area between the signal line and the reference layer. By adding the anti-pad, the coupling area can be reduced, which directly reduces the distributed capacitance, thereby achieving the pad impedance matching effect.

[0015] Preferably, in step S4, when the reference layers above and below the pad are removed, the capacitive coupling between the signal line and the reference plane is reduced, thereby changing the distributed parameters of the transmission line and ultimately improving the characteristic impedance Z0. Increasing the characteristic impedance Z0 by removing the reference layers above and below the pad can achieve pad impedance matching and avoid signal distortion caused by impedance mismatch.

[0016] Preferably, the characteristic impedance Z0 is determined by the distributed parameters of the transmission line, which include capacitance C and inductance L. By balancing capacitance C and inductance L, pad impedance matching can be achieved, thereby improving the stability of high-speed signal transmission.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention ensures impedance matching on the entire packaging substrate through multiple links such as wiring, drilling and pads, thereby achieving impedance matching on the entire packaging substrate; the present invention is applicable to substrate-type packaging structures, and for chips with high-speed or high-frequency characteristics, the main method is to achieve impedance matching on the entire packaging link, from chip signal access to signal wiring, and the wiring is connected to the pads through drilling, and the impedance of the pads themselves is reduced, thereby ensuring impedance matching of single-ended or differential signals on the entire link from signal input to final solder ball output, which can improve chip performance and avoid signal distortion due to impedance mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a flow chart of an impedance-adapted package design method. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] like Figure 1 As shown, it is a flow chart of an impedance-adaptive packaging design method, which includes: selecting a substrate, designing wiring impedance matching, designing drilling impedance matching and designing pad impedance matching; wherein, selecting a substrate is selecting a packaging substrate for carrying and fixing a chip; designing wiring impedance matching is by optimizing wiring from two aspects: adding a complete signal reference plane and left and right accompanying grounds of the signal; designing drilling impedance matching is by adding multiple accompanying ground holes around each signal drill hole; designing pad impedance matching is by using the reference layer principle to remove the reference layers above and below the pad when the pad size cannot be adjusted, and improving the pad impedance by adding anti-pads; an impedance-adaptive packaging design method of the present invention is applicable to substrate-type packaging structures, and for chips with high-speed or high-frequency characteristics, the main method is to achieve impedance matching for the entire packaging link, from chip signal access to signal wiring, and the wiring is connected to the pad through drilling, and the impedance of the pad itself is reduced, thereby ensuring impedance matching of single-ended or differential signals on the entire link from signal input to final solder ball output.

[0021] The method specifically comprises the following steps: S1. Select a packaging substrate for carrying and fixing the chip. The basic structures on the packaging substrate for signal or power transmission include: wiring, drilling and pads; among them, wiring is classified by signal type to include at least: signal wiring, power wiring and RF wiring; drilling is classified by function to include at least: signal drilling, power drilling and ground drilling.

[0022] In this embodiment, in step S1, the chip's signals and power are externally led through the wiring, drilled holes, and pads in the package substrate, achieving impedance matching across the entire package substrate. Furthermore, the wiring, drilled holes, and pads are all made of copper, which is used to carry the signal and power transmission. Copper has excellent electrical conductivity, and copper wiring, drilled holes, and pads ensure smooth current flow in the circuit, reducing signal loss and interference, and ensuring stable signal transmission.

[0023] S2. Optimize the wiring by adding a complete signal reference plane and left and right signal accompanying grounds, and design wiring impedance matching. Specifically, after adding a complete signal reference plane, by setting a specific line width and controlling the dielectric properties to be consistent, the signal reference plane is complete and undivided, which can make the electric field distribution of the signal line uniform, avoid the capacitance or inductance mutation caused by crossing the division or gap, and ensure the impedance matching of single-ended or differential signals; after adding signal accompanying grounds on both sides of the signal wiring, by setting a specific line width and controlling the dielectric properties to be consistent, the left and right reference paths of the signal wiring are complete and undivided, which can make the electric field distribution of the signal line uniform, avoid the capacitance or inductance mutation caused by crossing the division or gap, and ensure the impedance matching of single-ended or differential signals and reduce the crosstalk coupling between adjacent signals. Among them, the signal reference plane is a copper material plane, and the left and right reference paths are metal copper wires. By using copper material for the signal reference plane and reference path, the wiring impedance matching can be improved and the integrity of the signal transmission can be ensured.

[0024] S3. By adding multiple ground drill holes around each signal drill hole, the signal drill hole reference plane is set as the ground, and the drill hole impedance matching design is performed.

[0025] In this embodiment, in step S3, after adding multiple companion ground holes in a circle around each signal drill hole, the multiple companion ground holes directly connect the signal drill hole to the nearest ground plane, thereby achieving uniform electric field distribution of the signal line, avoiding sudden changes in capacitance or inductance caused by crossing divisions or gaps, and achieving an impedance matching effect in the drilling link.

[0026] S4. Fix the size of the pad by attaching specified solder balls on the package substrate. If the pad size cannot be adjusted, use the reference layer principle to remove the reference layers above and below the pad, and increase the pad impedance by adding anti-pads.

[0027] The reference layer principle refers to using the adjacent copper layer as a reference plane for the signal layer to control the impedance of the transmission line, reduce electromagnetic interference and improve signal integrity.

[0028] Secondly, the principle of increasing the pad impedance in step S4 is: the pad area where the solder ball is attached on the package substrate is very large, which will greatly reduce the impedance here, making it impossible to achieve impedance matching; at the same time, in the case of a specified solder ball, the size of the pad is fixed and the impedance is relatively small, so the pad impedance must be increased at this time, where the solder ball is a spherical metal solder used to lead the signal or power supply on the package substrate to the outside. Leading the signal or power supply on the package substrate to the outside through the solder ball can ensure stable signal transmission and stable power supply.

[0029] In this embodiment, in step S4, when the reference layers above and below the pad are removed, the capacitive coupling between the signal line and the reference plane is reduced, thereby changing the distributed parameters of the transmission line and ultimately improving the characteristic impedance Z0, thereby achieving pad impedance matching and avoiding signal distortion caused by impedance mismatch.

[0030] Among them, the anti-pad is a hole opened on the reference layer above and below the pad. The anti-pad is added to reduce the overlapping area of ​​the signal line and the reference layer. It directly reduces the distributed capacitance by reducing the coupling area by adding the anti-pad, that is, the capacitance C is reduced. At the same time, by reducing the reference plane, the current return path becomes longer and the local inductance increases, that is, the inductance L increases, thereby achieving the effect of pad impedance matching.

[0031] Secondly, the characteristic impedance Z0 is determined by the distributed parameters of the transmission line, which include capacitance C and inductance L. According to the formula Z0= , reducing the capacitance C or increasing the inductance L can increase the characteristic impedance Z0, so by balancing the capacitance C and the inductance L, the pad impedance can be matched and the stability of high-speed signal transmission can be improved.

[0032] To sum up, the present invention ensures impedance matching on the entire packaging substrate through multiple links such as wiring, drilling and pads, thereby realizing impedance matching on the entire packaging substrate; the present invention is applicable to substrate-type packaging structures, and for chips with high-speed or high-frequency characteristics, the main method is to realize impedance matching on the entire packaging link, from chip signal access to signal wiring, and the wiring is connected to the pads through drilling, and the impedance of the pads themselves is reduced, thereby ensuring impedance matching of single-ended or differential signals on the entire link from signal input to final solder ball output, which can improve chip performance and avoid signal distortion due to impedance mismatch, and has significant progress.

[0033] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A package design method for impedance adaptation, characterized in that: include: S1. Select a package substrate for carrying and fixing the chip. The basic structures on the package substrate for signal or power transmission include: wiring, drilling and pads; S2. Optimize the wiring by adding a complete signal reference plane and two aspects of the signal's left and right accompanying grounds, and design the wiring impedance matching; S3. By adding multiple ground holes around each signal hole, the signal hole reference plane is set as ground, and the hole impedance matching design is performed. S4. Fix the size of the pad by attaching the specified solder ball on the package substrate. If the pad size cannot be adjusted, use the reference layer principle to add an anti-pad by removing the reference layers above and below the pad.

2. The impedance-adapted packaging design method according to claim 1, wherein: In step S1, the signals and power on the chip are led out to the outside through the wiring, drilling and pads in the packaging substrate.

3. The impedance-adaptive packaging design method according to claim 1, wherein: In step S1 , the wiring, drilling holes and pads are all made of copper materials and are used to carry the transmission of signals and power.

4. The impedance-adaptive packaging design method according to claim 1, wherein: In step S1, the wiring is classified by signal type to include at least: signal wiring, power wiring and radio frequency wiring; the drilling is classified by function to include at least: signal drilling, power drilling and ground drilling.

5. The impedance-adaptive packaging design method according to claim 1, wherein: In step S2, after adding the signal complete reference plane and the signal left and right accompanying grounds, the signal reference plane is controlled to be complete and undivided and the signal wiring left and right reference paths are controlled to be complete and undivided by setting a specific line width and controlling the medium characteristics to be consistent.

6. The impedance-adaptive packaging design method according to claim 1, characterized in that: In step S3, after adding multiple companion ground holes around each signal borehole, the multiple companion ground holes directly connect the signal borehole to the nearest ground plane, thereby achieving uniform electric field distribution of the signal line.

7. The impedance-adaptive packaging design method according to claim 1, wherein: In step S4, after the designated solder balls are attached, the signals or power on the package substrate are led outwards using the solder balls.

8. The impedance-adaptive packaging design method according to claim 1, characterized in that: In step S4, after adding the anti-pad, the anti-pad is used to reduce the overlapping area between the signal line and the reference layer.

9. The impedance-adaptive packaging design method according to claim 1, wherein: In step S4, when the reference layers above and below the pad are removed, the capacitive coupling between the signal line and the reference plane is reduced, thereby changing the distributed parameters of the transmission line and ultimately improving the characteristic impedance Z0.

10. The impedance-adapted packaging design method according to claim 9, characterized in that: The characteristic impedance Z0 is determined by the distributed parameters of the transmission line, which include capacitance C and inductance L.

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