Display substrate, display panel and display device

Abstract

The invention relates to a display substrate, a display panel and a display device. The display substrate comprises a plurality of pixel circuits which are arranged in a plurality of rows and a plurality of columns; the data lines extend in the second direction, and the data lines are electrically connected with the pixel circuits in the corresponding pixel circuit columns respectively; the at least one gate driving circuit is configured to drive a plurality of pixel circuit rows at the same time each time; the source electrode driving circuit is located in the non-display area, and the source electrode driving circuit is provided with a plurality of data signal output ends; the data gating circuits are in one-to-one correspondence with the data lines, first ends of the data gating circuits are electrically connected with the corresponding data lines, the data gating circuits comprise a plurality of data gating circuit groups, and each data gating circuit group comprises a plurality of data gating circuits; the data gating circuit groups are in one-to-one correspondence with the data signal output ends, and the second ends of the data gating circuits in the same data gating circuit group are electrically connected with the corresponding data signal output ends.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] With the development of technology, display products are increasingly being used in people's daily lives and work, bringing tremendous convenience and enriching and diversifying their daily lives and work. Furthermore, with economic development, people are demanding higher and higher specifications for display products, such as higher resolution and higher refresh rate. As a result, competition in the display product market is becoming increasingly fierce. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate, a display panel, and a display device.

[0004] In order to achieve the above-mentioned object, the present disclosure provides a display substrate having a display area and a non-display area surrounding the display area, the display substrate comprising:

[0005] a plurality of pixel circuits located in the display area, the plurality of pixel circuits being arranged in a plurality of rows and columns, and the plurality of pixel circuits including a plurality of pixel circuit columns arranged along a first direction;

[0006] a plurality of data lines extending along a second direction, located in the display area, wherein the second direction intersects the first direction, the data lines corresponding to the pixel circuit columns one by one, and the data lines are electrically connected to each pixel circuit in the corresponding pixel circuit column;

[0007] At least one gate driving circuit is located in the non-display area, and the gate driving circuit is configured to drive multiple rows of pixel circuits simultaneously each time;

[0008] A source driving circuit is located in the non-display area, and the source driving circuit has a plurality of data signal output terminals;

[0009] A plurality of data strobe circuits, each corresponding one-to-one to the data lines and having a first end electrically connected to the corresponding data line, the plurality of data strobe circuits comprising a plurality of data strobe circuit groups, each of the data strobe circuit groups comprising a plurality of data strobe circuits, the data strobe circuit groups corresponding one-to-one to the data signal output ends, and the second end of the data strobe circuit in the same data strobe circuit group electrically connected to the corresponding data signal output end.

[0010] In some embodiments, the display substrate further includes a plurality of data strobe signal lines located in the non-display area;

[0011] The control terminal of the data strobe circuit is electrically connected to the data strobe signal line, wherein the control terminals of at least two data strobe circuits in the same data strobe circuit group are electrically connected to different data strobe signal lines;

[0012] The data strobe signal line is connected to the gate driving circuit, and the gate driving circuit is further configured to output a data strobe signal to the data strobe signal line so that the data strobe signal line transmits the data strobe signal to the control terminal of the data strobe circuit;

[0013] The data strobe circuit is configured to be disconnected under the control of the data strobe signal to disconnect the data signal output terminal from the corresponding data line, or to be turned on under the control of the data strobe signal to electrically connect the data signal output terminal to the corresponding data line.

[0014] In some embodiments, the multiple data lines include multiple data line groups arranged along the first direction, the data line group includes multiple data lines arranged along the first direction, the control end of the data selection circuit corresponding to each data line in the same data line group is electrically connected to the same data selection signal line, and the control end of the data selection circuit corresponding to the data lines in at least two data line groups is electrically connected to different data selection signal lines.

[0015] In some embodiments, there are q data lines in the data line group, and there are r data selection signal lines. Along the first direction, each q*r data lines includes r groups of data line groups arranged in sequence, and the data selection circuits corresponding to the q*r data lines include r groups of data selection circuit groups, wherein at least two data selection circuits in each data selection circuit group are electrically connected to data lines belonging to different data line groups in the r groups of data line groups, i is an integer greater than or equal to 1 and less than or equal to r, r is an integer greater than or equal to 2 and less than or equal to m / q, and m is the total number of data lines.

[0016] In some embodiments, in every r data line groups, the data line groups correspond to the data strobe signal lines one by one, and the control terminals of the data strobe circuits electrically connected to the data lines in the same data line group are all electrically connected to the corresponding data strobe signal lines.

[0017] In some embodiments, r is 2 or 3.

[0018] In some embodiments, the multiple data lines include multiple data line groups arranged along the first direction, and the data line group includes multiple data lines arranged along the first direction, which are different from the data selection signal lines electrically connected to the control ends of the data selection circuits electrically connected to different data lines in the same data line group.

[0019] In some embodiments, there are q data lines in the data line group, and the multiple data selection signal lines include at least one group of data selection signal line groups. The data selection signal line group includes q data selection signal lines, and each group of data selection signal line groups corresponds to multiple groups of data line groups. The control end of the data selection circuit corresponding to the j-th data line in each data line group is electrically connected to the j-th data selection signal line in the corresponding data selection signal line group, and j is an integer greater than or equal to 1 and less than or equal to q.

[0020] In some embodiments, among the data lines corresponding to each group of data selection signal line groups, along the first direction, the data selection circuits electrically connected to each q*k data lines include k groups of data selection circuit groups, k is an integer greater than or equal to 2 and less than or equal to m' / q, and m' is the total number of data lines in the multiple data line groups corresponding to each group of data selection signal line groups, wherein the data selection circuits connected to the j-th data line in different data line groups belong to different data selection circuit groups.

[0021] In some embodiments, k is 2 or 3.

[0022] In some embodiments, the plurality of pixel circuits include a plurality of pixel circuit rows arranged along the second direction;

[0023] The display substrate further includes a plurality of gate lines extending along a first direction, the gate lines being located in a display area, the plurality of gate lines including a plurality of gate line groups arranged along a second direction, the gate line groups including a plurality of gate lines arranged along the second direction, the gate lines corresponding one-to-one to the pixel circuit rows, and the gate lines being electrically connected to each pixel circuit in the corresponding pixel circuit row;

[0024] The gate drive circuit includes a plurality of shift registers that are cascaded and arranged along the second direction, the plurality of shift registers include a plurality of shift register groups, the shift register groups correspond one-to-one to the gate line groups, and the shift registers in the shift register groups correspond one-to-one to the gate lines in the corresponding gate line groups and are electrically connected along the second direction, and the shift registers in the same shift register group have the same timing.

[0025] The present disclosure also provides a display panel, comprising the display substrate as described above.

[0026] In some embodiments, the display panel further includes a cell substrate disposed opposite to the display substrate, the cell substrate including a plurality of color filter portions, the color filter portions corresponding to the pixel circuits one by one and disposed opposite to each other;

[0027] There are q data lines in the data line group, and the color filter portion corresponding to the pixel circuit electrically connected to the j-th data line in each data line group can transmit the same color of light, j is an integer greater than or equal to 1 and less than or equal to q, and the color filter portion corresponding to the pixel circuit electrically connected to different data lines in the same data line group can transmit different colors of light.

[0028] The present disclosure also provides a display device, comprising the display panel as described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0030] Figure 1 is a schematic diagram of a planar structure of a display substrate in some embodiments of the present disclosure;

[0031] Figure 2 This is a schematic diagram of a structure of a portion of a data strobe module in some embodiments of the present disclosure;

[0032] Figure 3 is a schematic diagram of another component structure of the data strobe module in some embodiments of the present disclosure;

[0033] Figure 4 is a schematic diagram of the composition structure of the data strobe module in other embodiments of the present disclosure;

[0034] Figure 5 is a schematic diagram of the composition structure of the data strobe module in other embodiments of the present disclosure;

[0035] Figure 6 is a schematic diagram of the composition structure of the data strobe module in other embodiments of the present disclosure;

[0036] Figure 7A is a schematic structural diagram of a shift register in some embodiments of the present disclosure;

[0037] Figure 7B is a timing waveform diagram of a shift register in some embodiments of the present disclosure;

[0038] Figure 8 is a data flow diagram in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0043] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0044] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0045] Display products include, for example, liquid crystal display devices, which include liquid crystal display panels. These are currently commonly used flat panel displays. The display panel includes an array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate. Pixel circuits arranged in an array are provided on the array substrate. Some products use GOA (Gateon Array) technology, which integrates the gate driver circuit on the array substrate to form a scan driver for the pixel circuit. This design not only saves costs but also enables a narrow-frame design.

[0046] For example, in some display devices, the gate drive circuit includes multiple shift registers GOA, each of which can drive a row of pixel circuits. Generally, the shift register GOA includes multiple transistors and at least one capacitor. For example, in one embodiment, the shift register GOA includes 10 transistors and 1 capacitor. If one shift register GOA can only drive one row of pixel circuits, 10 transistors are required to drive each row of pixel circuits. It is very challenging to further achieve high resolution of the display device at a high pixel density (PPI, Pixel Per Inch, pixels per inch) while meeting the spatial deployment requirements of 10 transistors. The process preparation difficulty will increase, and the preparation cost will also increase.

[0047] Furthermore, a timing controller is also provided on the display substrate, which is electrically connected to the shift register GOA and is used to control the shift register GOA so that each shift register GOA drives each row of pixel circuits.

[0048] In addition, a SOC chip and a source driver circuit are also provided on the display substrate, wherein the SOC chip is configured to provide data signals such as source video and image to the source driver circuit. The source driver circuit is used to provide data signals to each pixel circuit so that the display panel displays the corresponding picture. Under the requirements of high-resolution and high-refresh rate display, the hardware specifications of the SOC chip and the timing controller, such as transmission rate and bandwidth, are extremely high. This situation limits the development of high-resolution / high-refresh rate display products. At a high refresh rate, the charging time of the data signal input to each pixel circuit may be relatively short, which will also affect the display effect of the display panel.

[0049] In order to alleviate or solve at least one of the above-mentioned technical problems, the present disclosure provides a display substrate, a display panel and a display device.

[0050] Figure 1 Schematic diagram of the planar structure of the display substrate in some embodiments of the present disclosure. Figure 2 This is a schematic diagram of the structure of a portion of the data selection module in some embodiments of the present disclosure. Figure 3 This is a schematic diagram of another component structure of the data strobe module in some embodiments of the present disclosure. Figure 2 and Figure 3 The structure of the data strobe module 30 is a schematic diagram of the structure of the data strobe module 30 in some embodiments. Figure 4 Schematic diagram of the composition structure of the data strobe module in other embodiments.

[0051] like Figure 1 As shown, the present disclosure provides a display substrate having a display area AA and a non-display area NA surrounding the display area AA. The display substrate of the present disclosure includes: a plurality of pixel circuits 10, a plurality of data lines S1, S2, ..., S(m), a plurality of gate lines G1, G2, ..., G(n), at least one gate driver circuit 20, a source driver circuit 40, and a data strobe module 30.

[0052] The pixel circuit 10, data lines, and gate lines are located in the display area AA. The gate lines extend along a first direction, and multiple gate lines are arranged along a second direction. The second direction intersects the first direction, and for example, the second direction and the first direction may be perpendicular. The data lines extend along the second direction, and multiple data lines are arranged along the first direction. The intersection of the multiple data lines and the multiple gate lines defines multiple pixel regions, and the pixel circuit 10 is located within the pixel regions.

[0053] The plurality of pixel circuits 10 are arranged in a plurality of rows and columns. Specifically, the plurality of pixel circuits 10 include a plurality of pixel circuit columns arranged along a first direction, and the plurality of pixel circuits 10 include a plurality of pixel circuit rows arranged along a second direction.

[0054] The gate lines correspond to pixel circuit rows one by one and are electrically connected to each pixel circuit 10 in the corresponding pixel circuit row. The data lines correspond to pixel circuit columns one by one and are electrically connected to each pixel circuit 10 in the corresponding pixel circuit column.

[0055] The gate driving circuit 20 , the source driving circuit 40 and the data strobe module 30 are located in the non-display area NA.

[0056] Specifically, for example, the gate driving circuit 20 is located on at least one side of the display area AA in the first direction. Figure 1 In the illustrated embodiment, two gate driver circuits 20 are provided, one located on opposite sides of the display area AA in a first direction. A source driver circuit 40 is located on one side of the display area AA in a second direction. The data strobe module 30 is located between the display area AA and the source driver circuit 40.

[0057] The gate driving circuit 20 is configured to drive multiple rows of pixel circuits simultaneously each time.

[0058] The source driving circuit 40 has a plurality of data signal output terminals, for example, Figure 2 and Figure 3 In the embodiment shown, or in the Figure 4 In the embodiment shown, the plurality of data signal output terminals include a data signal output terminal Y1, a data signal output terminal Y2, ..., a data signal output terminal Y(m-1), and a data signal output terminal Y(m). Optionally, the source driver circuit 40 may be a driver chip.

[0059] The data strobe module 30 includes a plurality of data strobe circuits. Each data strobe circuit corresponds to a data line one by one, and a first end of each data strobe circuit is electrically connected to the corresponding data line.

[0060] The plurality of data strobe circuits include a plurality of data strobe circuit groups, each of which includes a plurality of data strobe circuits. The data strobe circuit groups correspond one to one with the data signal output terminals, and the second terminal of each data strobe circuit in the same data strobe circuit group is electrically connected to the corresponding data signal output terminal.

[0061] Optionally, the data strobe circuit includes a transistor. The first electrode of the transistor can serve as the first terminal of the data strobe circuit, the second electrode of the transistor can serve as the second terminal of the data strobe circuit, and the gate of the transistor can serve as the control terminal of the data strobe circuit. The embodiments of the present disclosure are described using a transistor as an example.

[0062] For example, in Figure 2 and Figure 3In the illustrated embodiment, data strobe circuit T1, data strobe circuit T4, and data strobe circuit T7 form a data strobe circuit group, wherein a first end of data strobe circuit T1 is electrically connected to data line S1. A first end of data strobe circuit T4 is electrically connected to data line S4. A first end of data strobe circuit T7 is electrically connected to data line S7. Furthermore, a second end of data strobe circuit T1, a second end of data strobe circuit T4, and a second end of data strobe circuit T7 are all electrically connected to data signal output terminal Y1.

[0063] Data strobe circuit T2, data strobe circuit T5, and data strobe circuit T8 form a data strobe circuit group, wherein a first end of data strobe circuit T2 is electrically connected to data line S2. A first end of data strobe circuit T5 is electrically connected to data line S5. A first end of data strobe circuit T8 is electrically connected to data line S8. Furthermore, a second end of data strobe circuit T2, a second end of data strobe circuit T5, and a second end of data strobe circuit T8 are all electrically connected to data signal output terminal Y2.

[0064] Data strobe circuit T3, data strobe circuit T6, and data strobe circuit T9 form a data strobe circuit group. A first end of data strobe circuit T3 is electrically connected to data line S3. A first end of data strobe circuit T6 is electrically connected to data line S6. A first end of data strobe circuit T9 is electrically connected to data line S9. Furthermore, a second end of data strobe circuit T3, a second end of data strobe circuit T6, and a second end of data strobe circuit T9 are all electrically connected to data signal output terminal Y3.

[0065] And so on. Data strobe circuit T(m-8), data strobe circuit T(m-5), and data strobe circuit T(m-2) constitute a data strobe circuit group, wherein the first end of data strobe circuit T(m-8) is electrically connected to data line S(m-8). The first end of data strobe circuit T(m-5) is electrically connected to data line S(m-5). The first end of data strobe circuit T(m-2) is electrically connected to data line S(m-2). Furthermore, the second end of data strobe circuit T(m-8), the second end of data strobe circuit T(m-5), and the second end of data strobe circuit T(m-2) are all electrically connected to data signal output terminal Y(S / 3-2).

[0066] Data strobe circuit T(m-7), data strobe circuit T(m-4), and data strobe circuit T(m-1) form a data strobe circuit group, wherein a first end of data strobe circuit T(m-7) is electrically connected to data line S(m-7). A first end of data strobe circuit T(m-4) is electrically connected to data line S(m-4). A first end of data strobe circuit T(m-1) is electrically connected to data line S(m-1). Furthermore, a second end of data strobe circuit T(m-7), a second end of data strobe circuit T(m-4), and a second end of data strobe circuit T(m-1) are all electrically connected to data signal output terminal Y(S / 3-1).

[0067] Data strobe circuit T(m-6), data strobe circuit T(m-3), and data strobe circuit T(m) form a data strobe circuit group. A first end of data strobe circuit T(m-6) is electrically connected to data line S(m-6). A first end of data strobe circuit T(m-3) is electrically connected to data line S(m-3). A first end of data strobe circuit T(m) is electrically connected to data line S(m-). Furthermore, a second end of data strobe circuit T(m-6), a second end of data strobe circuit T(m-3), and a second end of data strobe circuit T(m) are all electrically connected to data signal output terminal Y(m / 3).

[0068] For example, in Figure 4 In the illustrated embodiment, data strobe circuit T1, data strobe circuit T3, and data strobe circuit T5 form a data strobe circuit group, wherein a first end of data strobe circuit T1 is electrically connected to data line S1. A first end of data strobe circuit T3 is electrically connected to data line S3. A first end of data strobe circuit T5 is electrically connected to data line S5. Furthermore, a second end of data strobe circuit T1, a second end of data strobe circuit T3, and a second end of data strobe circuit T5 are all electrically connected to data signal output terminal Y1.

[0069] Data strobe circuit T2, data strobe circuit T4, and data strobe circuit T6 form a data strobe circuit group, wherein a first end of data strobe circuit T2 is electrically connected to data line S2. A first end of data strobe circuit T4 is electrically connected to data line S4. A first end of data strobe circuit T6 is electrically connected to data line S6. Furthermore, a second end of data strobe circuit T2, a second end of data strobe circuit T4, and a second end of data strobe circuit T6 are all electrically connected to data signal output terminal Y2.

[0070] And so on. Data strobe circuit T(m-5), data strobe circuit T(m-3), and data strobe circuit T(m-1) constitute a data strobe circuit group, wherein the first end of data strobe circuit T(m-5) is electrically connected to data line S(m-5). The first end of data strobe circuit T(m-3) is electrically connected to data line S(m-3). The first end of data strobe circuit T(m-1) is electrically connected to data line S(m-1). Furthermore, the second end of data strobe circuit T(m-5), the second end of data strobe circuit T(m-3), and the second end of data strobe circuit T(m-1) are all electrically connected to data signal output terminal Y(S / 3-1).

[0071] Data strobe circuit T(m-4), data strobe circuit T(m-2), and data strobe circuit T(m) form a data strobe circuit group, wherein a first end of data strobe circuit T(m-4) is electrically connected to data line S(m-4). A first end of data strobe circuit T(m-2) is electrically connected to data line S(m-2). A first end of data strobe circuit T(m) is electrically connected to data line S(m). Furthermore, a second end of data strobe circuit T(m-4), a second end of data strobe circuit T(m-2), and a second end of data strobe circuit T(m) are all electrically connected to data signal output terminal Y(S / 3).

[0072] In the disclosed embodiment, multiple rows of pixel circuits 10 are driven simultaneously. In this case, data signals are written into the multiple rows of pixel circuits 10 through the data signal output terminals. That is, the primary data of the source driver circuit 40 is written into two rows of pixel circuits 10 simultaneously. Therefore, high refresh rate display can be achieved without changing the hardware specifications of the existing SOC chip, timing controller, etc. For example, after charging image data with a resolution of 4K×1K and a refresh rate of 120Hz into the pixel circuit 10, the display panel will display image data with a resolution of 4K×2K and a refresh rate of 120Hz.

[0073] That is, the embodiment of the present disclosure can achieve a display effect with a resolution of 4K×2K and a refresh rate of 120Hz at the hardware cost and specifications of transmitting image data with a resolution of 4K×1K and a refresh rate of 120Hz, thereby reducing the hardware specification requirements of the SOC chip, timing controller, etc., reducing costs, and at the same time improving the display effect.

[0074] Specifically, in one example, two rows of pixel circuits 10 are driven simultaneously each time, for example, the first and second rows of pixel circuits 10 are driven simultaneously, the third and fourth rows of pixel circuits 10 are driven simultaneously, and so on. In this case, the two rows of pixel circuits 10 are turned on at the same time so that the number of row-by-row scans is halved, so that the time for each row is doubled, and the pixel data charging time of the high-refresh green is doubled, which can solve the problem of insufficient pixel charging time of the display substrate with high resolution and high refresh rate.

[0075] In some embodiments, as Figure 2 and Figure 3 As shown, or as Figure 4 As shown, the data strobe module 30 further includes a plurality of data strobe signal lines MUX. Specifically, the plurality of data strobe signal lines MUX include a data strobe signal line MUX1, a data strobe signal line MUX2, and a data strobe signal line MUX3.

[0076] The control end of the data strobe circuit is electrically connected to the data strobe signal line, wherein the control ends of at least two data strobe circuits in the same data strobe circuit group are electrically connected to different data strobe signal lines.

[0077] Accordingly, the plurality of data strobe circuits include a data strobe circuit T1 , a data strobe circuit T2 , a data strobe circuit T3 , . . . , a data strobe circuit T(m−1), and a data strobe circuit T(m).

[0078] exist Figure 2 and Figure 3 In the illustrated embodiment, in the data strobe circuit group consisting of data strobe circuit T1, data strobe circuit T4, and data strobe circuit T7, the control terminal of data strobe circuit T1 is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T4 is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T3 is electrically connected to data strobe signal line MUX3.

[0079] In the data strobe circuit group consisting of data strobe circuit T2, data strobe circuit T5, and data strobe circuit T8, the control terminal of data strobe circuit T2 is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T5 is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T8 is electrically connected to data strobe signal line MUX3.

[0080] In the data strobe circuit group consisting of data strobe circuit T3, data strobe circuit T6, and data strobe circuit T9, the control terminal of data strobe circuit T3 is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T6 is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T9 is electrically connected to data strobe signal line MUX3.

[0081] Similarly, in the data strobe circuit group consisting of data strobe circuit T(m-8), data strobe circuit T(m-5), and data strobe circuit T(m-2), the control terminal of data strobe circuit T(m-8) is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T(m-5) is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T(m-2) is electrically connected to data strobe signal line MUX3.

[0082] In the data strobe circuit group consisting of data strobe circuit T(m-7), data strobe circuit T(m-4), and data strobe circuit T(m-1), the control terminal of data strobe circuit T(m-7) is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T(m-4) is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T(m-1) is electrically connected to data strobe signal line MUX3.

[0083] In the data strobe circuit group consisting of data strobe circuit T(m-6), data strobe circuit T(m-3), and data strobe circuit T(m), the control terminal of data strobe circuit T(m-6) is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T(m-3) is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T(m) is electrically connected to data strobe signal line MUX3.

[0084] exist Figure 4 In the illustrated embodiment, in the data strobe circuit group consisting of data strobe circuit T1, data strobe circuit T3, and data strobe circuit T5, the control terminal of data strobe circuit T1 is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T3 is electrically connected to data strobe signal line MUX3. The control terminal of data strobe circuit T5 is electrically connected to data strobe signal line MUX2.

[0085] In the data strobe circuit group consisting of data strobe circuit T2, data strobe circuit T4, and data strobe circuit T6, the control terminal of data strobe circuit T2 is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T4 is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T6 is electrically connected to data strobe signal line MUX3.

[0086] Similarly, in the data strobe circuit group consisting of data strobe circuit T(m-5), data strobe circuit T(m-3), and data strobe circuit T(m-1), the control terminal of data strobe circuit T(m-5) is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T(m-3) is electrically connected to data strobe signal line MUX3. The control terminal of data strobe circuit T(m-1) is electrically connected to data strobe signal line MUX2.

[0087] In the data strobe circuit group consisting of data strobe circuit T(m-4), data strobe circuit T(m-2), and data strobe circuit T(m), the control terminal of data strobe circuit T(m-4) is electrically connected to data strobe signal line MUX2. The control terminal of data strobe circuit T(m-2) is electrically connected to data strobe signal line MUX1. The control terminal of data strobe circuit T(m) is electrically connected to data strobe signal line MUX3.

[0088] The data strobe signal line is connected to the gate driving circuit 20 , and the gate driving circuit 20 is further configured to output a data strobe signal to the data strobe signal line so that the data strobe signal line is transmitted to the control end of the data strobe circuit.

[0089] The data strobe circuit is configured to be turned off under the control of a data strobe signal to disconnect the data signal output terminal from the corresponding data line, or to be turned on under the control of a data strobe signal to electrically connect the data signal output terminal to the corresponding data line.

[0090] Specifically, in Figure 2 and Figure 3In the illustrated embodiment, for example, when the gate drive circuit 20 drives the pixel circuits 10 in the first and second rows, data strobe signals are output to the data strobe signal line MUX1, the data strobe signal line MUX2, and the data strobe signal line MUX3, respectively. The data strobe signal in the data strobe signal line MUX1 controls the data strobe circuits T1, T2, and T3 to be turned on. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuits T4, T5, and T6 to be turned off. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuits T7, T8, and T9 to be turned off. At this point, the data signal output by the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the first column of pixel circuits. At the same time, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T(m-8), the data strobe circuit T(m-7) and the data strobe circuit T(m-6) to be turned on. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T(m-5), the data strobe circuit T(m-4) and the data strobe circuit T(m-3) to be turned off. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T(m-2), the data strobe circuit T(m-1) and the data strobe circuit T(m) to be turned off. At this time, the data signal output by the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the (m-8)th column of pixel circuits. Of course, it can be understood that the data signal is also charged into the first two pixel circuits 10 in other pixel circuit columns, for example, the first two pixel circuits 10 in the tenth column of pixel circuits, which will not be listed one by one in this disclosure.

[0091] In one example, the data strobe signal that controls the data strobe circuit T to be turned on may be a high-level signal, and the data strobe signal that controls the data strobe circuit T to be turned off may be a low-level signal.

[0092] Furthermore, the data strobe signal on the data strobe signal line MUX2 turns on the data strobe circuits T4, T5, and T6. The data strobe signal on the data strobe signal line MUX1 turns off the data strobe circuits T1, T2, and T3. The data strobe signal on the data strobe signal line MUX3 turns off the data strobe circuits T7, T8, and T9. At this point, the data signal output by the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the fourth column of pixel circuits. Simultaneously, the data strobe signal on the data strobe signal line MUX2 turns on the data strobe circuits T(m-5), T(m-4), and T(m-3). The data strobe signal on the data strobe signal line MUX1 turns off the data strobe circuits T(m-8), T(m-7), and T(m-6). The data strobe signal on the data strobe signal line MUX3 controls the data strobe circuits T(m-2), T(m-1), and T(m) to be disconnected. At this point, the data signal output from the data signal output terminal Y1 is fed into the first two pixel circuits 10 in the (m-5)th pixel circuit column.

[0093] The process is deduced in this way until the first two pixel circuits 10 in all pixel circuit columns receive the data signal.

[0094] Then, the third and fourth pixel circuit rows are driven again, and the above data signal charging process is repeated, so that the third and fourth pixel circuits 10 in all pixel circuit columns receive the data signal. This process is repeated until all pixel circuits 10 in all rows receive the data signal.

[0095] exist Figure 4In the illustrated embodiment, when the gate drive circuit 20 drives the pixel circuits 10 in the first and second rows, it outputs data strobe signals to the data strobe signal line MUX1, the data strobe signal line MUX2, and the data strobe signal line MUX3, respectively. The data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T1 and the data strobe circuit T4 to be turned on. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T2 and the data strobe circuit T5 to be turned off. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T3 and the data strobe circuit T6 to be turned off. At this point, the data signal output by the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the first column of pixel circuits. At the same time, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T(m-5) and the data strobe circuit T(m-2) to be turned on. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T(m-4) and the data strobe circuit T(m-1) to be disconnected. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T(m-3) and the data strobe circuit T(m) to be disconnected. At this time, the data signal output by the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the (m-5)th column of pixel circuits. Of course, it can be understood that the data signal is also charged into the first two pixel circuits 10 in other pixel circuit columns, such as the first two pixel circuits 10 in the seventh column of pixel circuits, which will not be listed one by one in this disclosure.

[0096] Furthermore, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T1 and the data strobe circuit T4 to be disconnected. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T2 and the data strobe circuit T5 to be turned on. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T3 and the data strobe circuit T6 to be disconnected. At this point, the data signal output by the data signal output terminal Y2 can be charged into the first two pixel circuits 10 in the second column of pixel circuits. At the same time, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T(m-5) and the data strobe circuit T(m-2) to be disconnected. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T(m-4) and the data strobe circuit T(m-1) to be turned on. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T(m-3) and the data strobe circuit T(m) to be disconnected. At this time, the data signal outputted by the data signal output terminal Y2 can be charged into the first two pixel circuits 10 in the (m-4)th pixel circuit column.

[0097] Furthermore, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T1 and the data strobe circuit T4 to be disconnected. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T2 and the data strobe circuit T5 to be disconnected. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T3 and the data strobe circuit T6 to be connected. At this point, the data signal output by the data signal output terminal Y2 can be charged into the first two pixel circuits 10 in the third column of pixel circuits. At the same time, the data strobe signal in the data strobe signal line MUX1 controls the data strobe circuit T(m-5) and the data strobe circuit T(m-2) to be disconnected. The data strobe signal in the data strobe signal line MUX2 controls the data strobe circuit T(m-4) and the data strobe circuit T(m-1) to be disconnected. The data strobe signal in the data strobe signal line MUX3 controls the data strobe circuit T(m-3) and the data strobe circuit T(m) to be connected. At this time, the data signal outputted from the data signal output terminal Y1 can be charged into the first two pixel circuits 10 in the (m-3)th pixel circuit column.

[0098] The process is deduced in this way until the first two pixel circuits 10 in all pixel circuit columns receive the data signal.

[0099] Then, the third and fourth pixel circuit rows are driven again, and the above data signal charging process is repeated, so that the third and fourth pixel circuits 10 in all pixel circuit columns receive the data signal. This process is repeated until all pixel circuits 10 in all rows receive the data signal.

[0100] Of course, those skilled in the art will appreciate that there is no single method for inputting data signals, and any method can be freely selected based on the connection relationship, as long as it can complete the input of data signals to each pixel circuit 10. The similarity is that each time the data signal is input to two rows of pixel circuits 10 simultaneously.

[0101] In the disclosed embodiment, the data strobe circuit MUX can function as a switch, that is, the gate driver circuit 20 controls the data strobe circuit to achieve conduction between the data line and the data signal output terminal. In this case, the disclosed embodiment can simultaneously turn on and off multiple rows of pixel circuits 10. In combination with the switching function of the data strobe circuit MUX, it can simultaneously write a row of original data to multiple rows of pixel circuits 10, ultimately doubling the display effect of the display panel.

[0102] In some embodiments, as Figure 2 and Figure 3As shown, the multiple data lines include multiple data line groups arranged along a first direction, the data line groups include multiple data lines arranged along the first direction, the control ends of the data selection circuits corresponding to the data lines in the same data line group are electrically connected to the same data selection signal line, and the control ends of the data selection circuits corresponding to the data lines in at least two data line groups are electrically connected to different data selection signal lines.

[0103] Specifically, in Figure 2 and Figure 3 In the illustrated embodiment, along a first direction, every three data lines form a data line group. The data line groups can be arranged one at a time along the first direction. The control terminals of the data strobe circuits T1, T2, and T3 corresponding to the data lines S1, S2, and S3 in the first data line group are electrically connected to a data strobe signal line MUX1. The control terminals of the data strobe circuits T4, T5, and T6 corresponding to the data lines S4, S5, and S6 in the second data line group are electrically connected to a data strobe signal line MUX2. The control terminals of the data strobe circuits T7, T8, and T9 corresponding to the data lines S7, S8, and S9 in the third data line group are electrically connected to a data strobe signal line MUX3.

[0104] In the disclosed embodiments, the control terminals of the data strobe circuits corresponding to the data lines in the same data line group are electrically connected to the same data strobe signal line, facilitating control of the data lines in the same data line group via the data strobe signal line. Furthermore, the control terminals of the data strobe circuits corresponding to the data lines in at least two data line groups are electrically connected to different data strobe signal lines. This means that the disclosed embodiments can connect and disconnect the data lines in different data line groups from the data signal input terminals via different data strobe signal lines. This improves the controllability of the data strobe signal line MUX in connecting and disconnecting the data lines from the data signal input terminals, thereby adapting to different product requirements.

[0105] In some embodiments, there are q data lines in a data line group and r data selection signal lines. Along the first direction, each q*r data lines includes r groups of data line groups arranged in sequence, and the data selection circuits corresponding to the q*r data lines include r groups of data selection circuit groups, wherein at least two data selection circuits in each data selection circuit group are electrically connected to data lines belonging to different data line groups in the r groups of data line groups, i is an integer greater than or equal to 1 and less than or equal to r, r is an integer greater than or equal to 2 and less than or equal to m / q, and m is the total number of data lines.

[0106] Specifically, in Figure 2 and Figure 3 In the embodiment shown, each data line group includes three data lines and three data strobe signal lines MUX. Along the first direction, each 3*3=9 data lines includes three data line groups arranged in sequence.

[0107] For example, data lines S1, S2, S3, S4, S5, S6, S7, S8, and S9 comprise three data line groups, wherein data lines S1, S2, and S3 form a first data line group, data lines S4, S5, and S6 form a second data line group, and data lines S7, S8, and S9 form a third data line group. Furthermore, data strobe circuits T1, T2, T3, T4, T5, T6, T7, T8, and T9 corresponding to these nine data lines S1, S2, S3, S4, S5, S6, S7, S8, and S9 comprise three data strobe circuit groups. Specifically, data strobe circuits T1, T4, and T7 form a first data strobe circuit group, data strobe circuits T2, T5, and T8 form a second data strobe circuit group, and data strobe circuits T3, T6, and T9 form a third data strobe circuit group.

[0108] Obviously, in the first group of data selection circuits, the data selection circuit T1 is electrically connected to the first data line S1 in the first data line group, the data selection circuit T4 is electrically connected to the first data line S4 in the second data line group, and the data selection circuit T7 is electrically connected to the first data line S7 in the third data line group.

[0109] In the second group of data selection circuits, the data selection circuit T2 is electrically connected to the second data line S2 in the first data line group, the data selection circuit T5 is electrically connected to the second data line S5 in the second data line group, and the data selection circuit T8 is electrically connected to the second data line S8 in the third data line group.

[0110] In the third group of data selection circuits, the data selection circuit T3 is electrically connected to the third data line S3 in the first data line group, the data selection circuit T6 is electrically connected to the third data line S6 in the second data line group, and the data selection circuit T9 is electrically connected to the third data line S9 in the third data line group.

[0111] Similarly, the data lines S(m-8), S(m-7), S(m-6), S(m-5), S(m-4), S(m-3), S(m-2), S(m-1), and S(m) include three data line groups, among which the data lines S(m-8), S(m-7), and S(m-6) are the first data line group, the data lines S(m-5), S(m-4), and S(m-3) are the second data line group, and the data lines S(m-2), S(m-1), and S(m) are the third data line group. The data strobe circuits T(m-8), T(m-7), T(m-6), T(m-5), T(m-4), T(m-3), T(m-2), T(m-1), and T(m) corresponding to the nine data lines S(m-8), S(m-7), S(m-6), S(m-5), S(m-4), S(m-3), S(m-2), S(m-1), and S(m) include three data strobe circuit groups. Specifically, the data strobe circuits T(m-8), T(m-5), and T(m-2) form a first data strobe circuit group, the data strobe circuits T(m-7), T(m-4), and T(m-1) form a second data strobe circuit group, and the data strobe circuits T(m-6), T(m-3), and T(m) form a third data strobe circuit group.

[0112] Obviously, in the first group of data selection circuits, the data selection circuit T(m-8) is electrically connected to the first data line S(m-8) in the first data line group, the data selection circuit T(m-5) is electrically connected to the first data line S(m-5) in the second data line group, and the data selection circuit T(m-2) is electrically connected to the first data line S(m-2) in the third data line group.

[0113] In the second group of data selection circuits, the data selection circuit T(m-7) is electrically connected to the second data line S(m-7) in the first group of data line groups, the data selection circuit T(m-4) is electrically connected to the second data line S(m-4) in the second group of data line groups, and the data selection circuit T(m-1) is electrically connected to the second data line S(m-1) in the third group of data line groups.

[0114] In the third group of data selection circuits, the data selection circuit T(m-6) is electrically connected to the third data line S(m-6) in the first group of data line groups, the data selection circuit T(m-3) is electrically connected to the third data line S(m-3) in the second group of data line groups, and the data selection circuit T(m) is electrically connected to the third data line S(m) in the third group of data line groups.

[0115] In general display products, the areas corresponding to the pixel circuits 10 connected to different data lines in different data line groups have different light-emitting colors. Therefore, in the embodiment of the present disclosure, the data lines electrically connected to at least two data selection circuits in each data selection circuit group belong to different data line groups in the r groups of data line groups, which can avoid simultaneous driving of the pixel circuits 10 corresponding to areas with different light-emitting colors in the same data line group, resulting in the overall display effect being affected.

[0116] In some embodiments, as Figure 2 and Figure 3 As shown, in each r data line groups, the data line groups correspond to the data strobe signal lines one by one, and the control ends of the data strobe circuits electrically connected to the data lines in the same data line group are all electrically connected to the corresponding data strobe signal lines.

[0117] Specifically, in Figure 2 and Figure 3 In the illustrated embodiment, every nine data lines include three data line groups. In the three data line groups, each data line group corresponds to a data selection signal.

[0118] For example, in the three data line groups consisting of data lines S1, S2, S3, S4, S5, S6, S7, S8, and S9, the first data line group includes data lines S1, S2, and S3, and corresponds to the data strobe signal line MUX1. That is, the control ends of the data strobe circuits T1, T2, and T3 electrically connected to the data lines S1, S2, and S3 are all electrically connected to the data strobe signal line MUX1. The second data line group includes data lines S4, S5, and S6, and corresponds to the data strobe signal line MUX2. That is, the control ends of the data strobe circuits T4, T5, and T6 electrically connected to the data lines S4, S5, and S6 are all electrically connected to the data strobe signal line MUX2. The third data line group includes data lines S7, S8 and S9, and corresponds to the data selection signal line MUX3, that is, the control ends of the data selection circuits T7, T8, T9 electrically connected to the data lines S7, S8, S9 are all electrically connected to the data selection signal line MUX3.

[0119] In the three data line groups consisting of data lines S(m-8), S(m-7), S(m-6), S(m-5), S(m-4), S(m-3), S(m-2), S(m-1) and S(m), the first data line group includes data lines S(m-8), S(m-7) and S(m-6), and corresponds to the data selection signal line MUX1, that is, the control ends of the data selection circuits T(m-8), T(m-7) and T(m-6) electrically connected to the data lines S(m-8), S(m-7) and S(m-6) are all electrically connected to the data selection signal line MUX1. The second data line group includes data lines S(m-5), S(m-4), and S(m-3), and corresponds to the data strobe signal line MUX2. That is, the control terminals of the data strobe circuits T(m-5), T(m-4), and T(m-3) electrically connected to the data lines S(m-5), S(m-4), and S(m-3) are all electrically connected to the data strobe signal line MUX2. The third data line group includes data lines S(m-2), S(m-1), and S(m), and corresponds to the data strobe signal line MUX3. That is, the control terminals of the data strobe circuits T(m-2), T(m-1), and T(m) electrically connected to the data lines S(m-2), S(m-1), and S(m) are all electrically connected to the data strobe signal line MUX3.

[0120] It should be noted that the value range of the number of data strobe signal lines r is 2 to m / q. Figure 2 and Figure 3 In the embodiment shown, r=3.

[0121] Figure 5 Schematic diagram of the structure of the data strobe module 30 in other embodiments.

[0122] like Figure 5 As shown, there are two data strobe signal lines, ie, r=2, which are data strobe signal lines MUX1 and MUX2 respectively.

[0123] Accordingly, every 2*3=6 data lines include two data line groups, the first data line group includes data lines S1, S2 and S3, and the second data line group includes data lines S4, S5 and S6.

[0124] The control ends of the data strobe circuits T1, T2, and T3 electrically connected to the data lines S1, S2, and S3 in the first data line group are all electrically connected to the data strobe signal line MUX1. The control ends of the data strobe circuits T4, T5, and T6 electrically connected to the data lines S4, S5, and S6 in the second data line group are all electrically connected to the data strobe signal line MUX2.

[0125] The data strobe circuits T1, T2, T3, T4, T5, and T6 electrically connected to these six data lines include two groups of data strobe circuit groups. The first group of data strobe circuit groups includes data strobe circuits T1, T4, and T5, and the second group of data strobe circuit groups includes data strobe circuits T2, T3, and T6.

[0126] In the first data strobe circuit group, the control terminal of data strobe circuit T1 is electrically connected to the data strobe signal line MUX1, and the control terminals of data strobe circuits T4 and T5 are electrically connected to the data strobe signal line MUX2. In the second data strobe circuit group, the control terminals of data strobe circuits T2 and T3 are electrically connected to the data strobe signal line MUX2, and the control terminal of data strobe circuit T6 is electrically connected to the data strobe signal line MUX1.

[0127] In another embodiment, the number r of data strobe signal lines can be m / q. In this case, the data line groups correspond to the data strobe signal lines one-to-one, that is, the control terminal of the data strobe circuit electrically connected to each data line group is electrically connected to one data strobe signal line, and the control terminals of the data strobe circuits electrically connected to different data line groups are electrically connected to different data strobe signal lines. For example, the control terminal of the data strobe circuit electrically connected to the xth data line group is electrically connected to the xth data strobe signal line, where x is an integer greater than or equal to 1 and less than or equal to m / q.

[0128] Of course, the number r of data strobe signal lines can also take other values, which are not listed one by one in this disclosure. When r is greater than or equal to q, the data lines electrically connected to different data strobe circuits in each data strobe circuit group belong to different data line groups. For example, in 3A and Figure 3 In the embodiment shown, r=q, and the data lines S1, S4, and S7 electrically connected to the data selection circuits T1, T4, and T7 in the data selection circuit group belong to the first data line group, the second data line group, and the third data line group, respectively. This design is conducive to realizing the input control of the data signal of each column of data lines through the data signal output end.

[0129] On the basis that the data line control ends of the data selection circuits corresponding to the data lines in at least two of all the data line groups are electrically connected to different data selection signal lines, the embodiment of the present disclosure corresponds the data line groups to the data selection signal lines one-to-one in every r groups of data line groups, thereby enabling further precise control of the data lines and the data signal output ends.

[0130] In some embodiments, as Figure 4 As shown, the multiple data lines include multiple data line groups arranged along the first direction, and the data line groups include multiple data lines arranged along the first direction. The data selection signal lines electrically connected to the control ends of the data selection circuits electrically connected to different data lines in the same data line group are different.

[0131] Specifically, in Figure 4 In the embodiment shown, the data line group includes three data lines, for example, data lines S1, S2, and S3 constitute a data line group, wherein the data selection circuit T1 electrically connected to the data line S1 is electrically connected to the data selection signal point MUX1, the data selection circuit T2 electrically connected to the data line S2 is electrically connected to the data selection signal point MUX2, and the data selection circuit T3 electrically connected to the data line S3 is electrically connected to the data selection signal point MUX3.

[0132] Data lines S4, S5, and S6 constitute a data line group, wherein the data selection circuit T4 electrically connected to the data line S4 is electrically connected to the data selection signal point MUX1, the data selection circuit T5 electrically connected to the data line S5 is electrically connected to the data selection signal point MUX2, and the data selection circuit T6 electrically connected to the data line S6 is electrically connected to the data selection signal point MUX3.

[0133] And so on. Data lines S(m-2), S(m-1), and S(m) constitute a data line group, wherein the data strobe circuit T(m-2) electrically connected to data line S(m-2) is electrically connected to data strobe signal point MUX1, the data strobe circuit T(m-1) electrically connected to data line S(m-1) is electrically connected to data strobe signal point MUX2, and the data strobe circuit T(m) electrically connected to data line S(m) is electrically connected to data strobe signal point MUX3.

[0134] The disclosed embodiments can enable different data selection signal lines to control different data lines in the same data line group, which is beneficial for controlling data writing to different data lines in the same data line group.

[0135] In the embodiment of the present disclosure, r is set to 2 or 3, which can minimize circuit complexity. For example, when r is set to a large value, since the data strobe module is set in the non-display area NA, it is not conducive to narrowing the frame.

[0136] In some embodiments, there are q data lines in a data line group, the multiple data selection signal lines include at least one group of data selection signal line groups, the data selection signal line group includes q data selection signal lines, each group of data selection signal line groups corresponds to multiple groups of data lines, and the control end of the data selection circuit corresponding to the j-th data line in different data line groups is electrically connected to the j-th data selection signal line in the corresponding data selection signal line group, where j is an integer greater than or equal to 1 and less than or equal to q.

[0137] Specifically, the plurality of data strobe signals include a data strobe signal line group, which includes data strobe signal lines MUX1, MUX2, and MUX3. This data strobe signal line group corresponds to multiple data line groups, for example, m / q data line groups, which may include a first data line group, a second data line group, ..., and m / q data line groups.

[0138] The control end of the data strobe circuit electrically connected to the first data line in the first data line group, the second data line group, ..., and the m / qth data line group is electrically connected to the first data strobe signal line MUX. Specifically, the control end of the data strobe circuit T1 electrically connected to the first data line S1 in the first data line group, the control end of the data strobe circuit T4 electrically connected to the first data line S4 in the second data line group, ..., and the control end of the data strobe circuit T(m-2) electrically connected to the first data line S(m-2) in the m / qth data line group are all electrically connected to the data strobe signal line MUX1.

[0139] The control ends of the data strobe circuits electrically connected to the second data line in the first data line group, the second data line group, ..., and the m / qth data line group are all electrically connected to the second data strobe signal line MUX. Specifically, the control end of the data strobe circuit T2 electrically connected to the second data line S2 in the first data line group, the control end of the data strobe circuit T5 electrically connected to the second data line S5 in the second data line group, ..., and the control end of the data strobe circuit T(m-1) electrically connected to the second data line S(m-1) in the m / qth data line group are all electrically connected to the data strobe signal line MUX2.

[0140] The control terminals of the data strobe circuits electrically connected to the third data line in the first data line group, the second data line group, ..., and the m / qth data line group are all electrically connected to the third data strobe signal line MUX. Specifically, the control terminal of the data strobe circuit T3 electrically connected to the third data line S3 in the first data line group, the control terminal of the data strobe circuit T6 electrically connected to the third data line S6 in the second data line group, ..., the control terminal of the data strobe circuit T(m) electrically connected to the third data line S(m) in the m / qth data line group are all electrically connected to the data strobe signal line MUX3.

[0141] On the basis that the data selection signal lines electrically connected to the control ends of the data selection circuits electrically connected to different data lines in the same data line group are different, in the embodiment of the present disclosure, the data selection signal lines in the data selection signal line group are corresponded one-to-one with the data lines in the data line group, thereby achieving precise control of the conduction and disconnection of the data lines of each data line group and the data signal output end.

[0142] In some embodiments, among the data lines corresponding to each group of data selection signal line groups, along the first direction, the data selection circuits electrically connected to each q*k data lines include k groups of data selection circuit groups, k is an integer greater than or equal to 2 and less than or equal to m' / q, and m' is the total number of data lines in the multiple data line groups corresponding to each group of data selection signal line groups, wherein the data selection circuits connected to the j-th data line in different data line groups belong to different data selection circuit groups.

[0143] like Figure 4 As shown, among the data lines corresponding to this group of data line strobe signal lines, that is, among all the data lines, along the first direction, the data strobe circuits electrically connected to every 3*2=6 data lines include two data strobe circuit groups.

[0144] That is, the data strobe circuits T1, T2, T3, T4, T5, and T6 electrically connected to the data lines S1, S2, S3, S4, S5, and S6 include two groups of data strobe circuits.

[0145] The first data line group includes data lines S1, S2, and S3, the second data line group includes data lines S4, S5, and S6, the first data strobe circuit group includes data strobe circuits T1, T3, and T5, and the second data strobe circuit group includes data strobe circuits T2, T4, and T6.

[0146] The data strobe circuit T1 electrically connected to the first data line S1 in the first data line group and the data strobe circuit T4 electrically connected to the first data line S4 in the second data line group belong to different data strobe circuit groups.

[0147] The data strobe circuit T2 electrically connected to the second data line S2 in the first data line group and the data strobe circuit T5 electrically connected to the second data line S5 in the second data line group belong to different data strobe circuit groups.

[0148] The data strobe circuit T3 electrically connected to the third data line S3 in the first data line group and the data strobe circuit T6 electrically connected to the third data line S6 in the second data line group belong to different data strobe circuit groups.

[0149] It should be noted that the value range of k is 2 to m' / q. In the embodiment of the present disclosure, the data strobe signal line group is a group, so m'=m. Figure 4 In the embodiment shown, k=2.

[0150] Figure 6 Schematic diagram of the structure of the data strobe module 30 in other embodiments.

[0151] exist Figure 6In the embodiment shown, k=3. That is, each data strobe signal line group includes three data strobe signal lines MUX1, MUX2, and MUX3. Figure 6 The following description still takes a group of data strobe signal groups as an example.

[0152] Each of the nine data lines includes three data line groups, and the data strobe circuits connected to the nine data lines include three data strobe circuit groups.

[0153] Specifically, if Figure 6 As shown, the first data line group includes data lines S1, S2, and S3, the second data line group includes data lines S4, S5, and S6, and the third data line group includes data lines S7, S8, and S9.

[0154] Among them, the control ends of the data strobe circuits T1, T2, and T3 electrically connected to the data lines S1, S2, and S3 in the first data line group are all electrically connected to the data strobe signal line MUX1, the control ends of the data strobe circuits T4, T5, and T6 electrically connected to the data lines S4, S5, and S6 in the second data line group are all electrically connected to the data strobe signal line MUX2, and the control ends of the data strobe circuits T4, T5, and T6 electrically connected to the data lines S4, S5, and S6 in the third data line group are all electrically connected to the data strobe signal line MUX3.

[0155] The first data strobe circuit group includes data strobe circuits T1, T4, and T7, the second data strobe circuit group includes data strobe circuits T2, T5, and T8, and the third data strobe circuit group includes data strobe circuits T3, T6, and T9.

[0156] Obviously, the data selection circuit T1 electrically connected to the first data line S1 in the first data line group, the data selection circuit T4 electrically connected to the first data line S4 in the second data line group, and the data selection circuit T7 electrically connected to the first data line S7 in the third data line group belong to different data selection circuit groups.

[0157] The data selection circuit T2 electrically connected to the second data line S2 in the first data line group, the data selection circuit T5 electrically connected to the second data line S5 in the second data line group, and the data selection circuit T8 electrically connected to the third data line S8 in the third data line group belong to different data selection circuit groups.

[0158] The data selection circuit T3 electrically connected to the third data line S3 in the first data line group, the data selection circuit T6 electrically connected to the third data line S6 in the second data line group, and the data selection circuit T9 electrically connected to the third data line S9 in the third data line group belong to different data selection circuit groups.

[0159] In the disclosed embodiment, since the same data selection circuit group is electrically connected to the same data signal output terminal, the data selection circuits corresponding to the j-th data lines in different data line groups belong to different data selection circuit groups. This can prevent the j-th data lines in different data line groups from writing data signals of the same data signal input terminal, thereby preventing the display effect from being affected.

[0160] In the embodiment of the present disclosure, k takes a value of 2 or 3, and the circuit connection relationship is relatively simpler, which can further reduce costs while ensuring the realization of high refresh rate and high resolution effects.

[0161] In some embodiments, as Figure 1 As shown, the plurality of gate lines include a plurality of gate line groups arranged along the second direction, the gate line groups include a plurality of gate lines arranged along the second direction, the gate lines correspond one-to-one to the pixel circuit rows, and the gate lines are electrically connected to each pixel circuit 10 in the corresponding pixel circuit row.

[0162] The gate drive circuit 20 includes a plurality of shift registers that are cascaded and arranged along the second direction. The plurality of shift registers include a plurality of shift register groups. The shift register groups correspond one-to-one to the gate line groups, and the shift registers in the shift register groups correspond one-to-one to the gate lines in the corresponding gate line groups and are electrically connected. The shift registers in the same shift register group have the same timing.

[0163] Specifically, the shift registers in the same shift register group are configured to simultaneously drive corresponding pixel circuit rows through gate lines in corresponding gate line groups.

[0164] Figure 7A is a schematic structural diagram of a shift register in some embodiments of the present disclosure, Figure 7B 1 is a timing waveform diagram of a shift register in some embodiments of the present disclosure.

[0165] Specifically, in one example, there is a column of cascaded shift registers on each of the left and right sides of the display area AA.

[0166] like Figure 7A As shown, each shift register has an input signal terminal INPUT, a reset signal input terminal RESET, a low level terminal VSS, a first clock signal input terminal CLK, a second clock signal input terminal CLKB, and a gate drive signal output terminal OUT. The signal input terminal INPUT of the first row is electrically connected to the first control signal terminal STV1, and the signal input terminal INPUT of the second row is electrically connected to the second control signal terminal STV2.

[0167] Figure 7B In the example, STV1L, STV2L, CLK1L, CLK2L, CLK3L, and CLK4L represent Figure 7AThe timing waveform of the shift register on the left side of the middle diagram, STV1R, STV2R, CLK1R, CLK2R, CLK3R, CLK4R represent Figure 7A The timing waveform of the shift register on the right side of the figure.

[0168] like Figure 7B As shown, during the data writing process from time T1 to time T2, the left and right shift registers, under the control of the corresponding signals STV1, STV2, CLK1, CLK2, CLK3, and CLK4, output gate drive signals to the first and second rows, thereby driving the pixel units in the first and second rows. Simultaneously, during this process, the high levels of the data selection signal lines MUX1, MUX2, and MUX3 sequentially connect the corresponding data lines to the data signal input terminals, ultimately completing the data writing process for the first and second rows.

[0169] The embodiment of the present disclosure can realize simultaneous driving of multiple rows of pixel circuits 10 through a group of shift registers, thereby achieving a high-resolution and high-refresh-rate display effect of the display panel.

[0170] The present disclosure also provides a display panel, comprising the display substrate as described in any embodiment of the present disclosure.

[0171] In some embodiments, the display panel further includes a cell-matching substrate disposed opposite to the display substrate. The cell-matching substrate includes a plurality of color filter portions. The color filter portions correspond to the pixel circuits 10 one by one and are disposed opposite to each other.

[0172] There are q data lines in the data line group, and the color filter portion corresponding to the pixel circuit 10 electrically connected to the j-th data line in each data line group can transmit the same color of light, j is an integer greater than or equal to 1 and less than or equal to q, and the color filter portion corresponding to the pixel circuit 10 electrically connected to different data lines in the same data line group can transmit different colors of light.

[0173] For example, in Figure 1 In the embodiment shown, each data line group includes three data lines, each data line is electrically connected to a column of pixel circuits. The color filters corresponding to the three columns of pixel circuits 10 electrically connected to each data line group can transmit red light, green light, and blue light respectively.

[0174] That is, it can be understood that the display panel includes a plurality of pixel units arranged in an array. The pixel units include a plurality of pixel unit columns along a first direction, the plurality of pixel unit columns include a plurality of pixel unit column groups, each pixel unit column group includes three pixel unit columns, and among the three pixel unit columns, all pixel units in the first pixel unit column are red pixel units, all pixel units in the second pixel unit column are green pixel units, and all pixel units in the third pixel unit column are blue pixel units.

[0175] Specifically, if Figure 1 The pixel circuit 10 includes a first pixel circuit 11, a second pixel circuit 12, and a third pixel circuit 13. The pixel unit corresponding to the first pixel circuit 11 is a red pixel unit, the pixel unit corresponding to the second pixel circuit 12 is a green pixel unit, and the pixel unit corresponding to the third pixel circuit 13 is a blue pixel unit.

[0176] In this case, Figure 2 and Figure 3 In the embodiment shown, different data signal output terminals Y1, Y2, and Y3 can be respectively connected to pixel unit columns of the same color in different pixel unit column groups. Data selection circuits MUX1, MUX2, and MUX3 act as switches to respectively connect pixel unit columns of different colors in the same pixel unit column group to control the writing of data signals.

[0177] exist Figure 4 In the embodiment shown, different data signal output terminals Y1 and Y2 are connected to pixel unit columns of different colors, respectively. Data selection circuits MUX1, MUX2, and MUX3 act as switches to connect pixel unit columns of the same color in different pixel unit column groups, respectively, to control the writing of data signals.

[0178] The present disclosure also provides a display device, comprising the display panel as described in any embodiment of the present disclosure.

[0179] exist Figure 2 and Figure 3 In the embodiment shown, the conduction between the pixel units of different colors electrically connected to the data lines in the same data line group and the data signal output terminal is controlled by the same data selection circuit, but the writing of the data signal is not done to the same data signal output terminal. Figure 4 In the illustrated embodiment, pixel units of different colors electrically connected to data lines in the same data line group are controlled by different data selection circuits, but the writing of data signals is controlled by the same data signal output terminal. Therefore, the disclosed embodiment can prevent the same data signal from being written into data units of different colors.

[0180] The following are respectively Figure 1The specific driving process of the display substrate shown is described below.

[0181] like Figure 1 As shown, the pixel circuits 10 are arranged into n rows and m columns, that is, m×n pixel circuits 10 are arranged into m pixel circuit columns along the first direction and into n pixel circuit rows along the second direction.

[0182] Correspondingly, the plurality of gate lines are specifically n gate lines, and specifically include gate line G1, gate line G2, ..., gate line G(n-1), and gate line G(n). The number of data lines is m, and specifically includes data line S1, data line S2, data line S3, ..., data line S(m-2), data line S(m-1), and data line S(m). Accordingly, in the first direction, each data line group includes three data lines, and there are m / 3 data line groups for the m data lines. Specifically, data line S1, data line S2, and data line S3 constitute a data line group, data line S4, data line S5, and data line S6 constitute a data line group, and data line S7, data line S8, and data line S9 constitute a data line group. And so on, finally, data line S(m-2), data line S(m-1), and data line S(m) constitute a data line group.

[0183] The data strobe circuits correspond one-to-one to the data lines, i.e., there are m data strobe circuits in total. Three data strobe circuits constitute a data strobe circuit group, i.e., the m data strobe circuits comprise S / 3 data strobe circuit groups. Accordingly, the source driver circuit 40 has p = S / 3 data signal output terminals.

[0184] exist Figure 2 and Figure 3 In the display substrate shown, there are three data strobe signal lines, specifically, a data strobe signal line MUX1 , a data strobe signal line MUX2 , and a data strobe signal line MUX3 .

[0185] In the first direction, each of three consecutive data line groups includes a first data line group, a second data line group and a third data line group.

[0186] The control ends of the data selection circuits electrically connected to the data lines in the first data line group are all electrically connected to the data selection signal line MUX1, the control ends of the data selection circuits electrically connected to the data lines in the second data line group are all electrically connected to the data selection signal line MUX2, and the control ends of the data selection circuits electrically connected to the data lines in the third data line group are all electrically connected to the data selection signal line MUX1.

[0187] Furthermore, the data selection circuits electrically connected to the data lines in each of the three data line groups include three data selection circuit groups, wherein the first data selection circuit group includes a data selection circuit electrically connected to the first data line in the first data line group, a data selection circuit electrically connected to the first data line in the second data line group, and a data selection circuit electrically connected to the first data line in the third data line group.

[0188] The second group of data selection circuits includes a data selection circuit electrically connected to the second data line in the first group of data line groups, a data selection circuit electrically connected to the second data line in the second group of data line groups, and a data selection circuit electrically connected to the second data line in the third group of data line groups.

[0189] The third group of data selection circuits includes a data selection circuit electrically connected to the third data line in the first group of data line groups, a data selection circuit electrically connected to the third data line in the second group of data line groups, and a data selection circuit electrically connected to the third data line in the third group of data line groups.

[0190] Accordingly, each of the three pixel circuit columns includes a first pixel circuit column, a second pixel circuit column, and a third pixel circuit column. The color filter portion corresponding to the pixel circuit 10 in the first pixel circuit column can transmit red light; the color filter portion corresponding to the pixel circuit 10 in the first pixel circuit column can transmit red light; and the color filter portion corresponding to the pixel circuit 10 in the first pixel circuit column can transmit red light.

[0191] like Figure 1 As shown, there are two gate drive circuits 20, which are located on opposite sides of the display area AA in the first direction, and the two gate drive circuits 20 are electrically connected to each row of gate lines. The driving process of the display substrate includes:

[0192] Step S1 : under the modulation of the driving timing, the gate driving circuit 20 drives the pixel circuits 10 in the first row and the pixel circuits 10 in the second row simultaneously through the gate lines in the first row and the gate lines in the second row.

[0193] Step S2: The data selection circuits T1, T2, T3, ..., T(m-8), T(m-7), and T(m-6) electrically connected to the data lines S1, S2, S3, ..., S(m-8), S(m-7), and S(m-6) in each first group of data line groups are turned on through the data selection signal line MUX1, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S1 electrically connected to the data selection circuit T1 through the first data signal output terminal Y1, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S1 electrically connected to the data selection circuit T10 through the fourth data signal output terminal Y4, and so on, the data signal is written into the first two pixel circuits 10 electrically connected to the data line S(m-8) electrically connected to the data selection circuit T(m-8) through the (m / 3-2)th data signal output terminal Y(m / 3-2).

[0194] Then, the data selection circuits T4, T5, T6, ..., T(m-5), T(m-4), and T(m-3) electrically connected to the data lines S4, S5, S6, ..., S(m-5), S(m-4), and S(m-3) in each second group of data line groups are turned on through the data selection signal line MUX2, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S4 electrically connected to the data selection circuit T4 through the second data signal output terminal Y2. And so on, the data signal is written into the first two pixel circuits 10 electrically connected to the data line S(m-7) electrically connected to the data selection circuit T(m-7) through the (m / 3-1)th data signal output terminal Y(m / 3-1).

[0195] Finally, the data selection circuits T7, T8, T9, ..., T(m-2), T(m-1), and T(m) electrically connected to the data lines S7, S8, S9, ..., S(m-2), S(m-1), and S(m) in each third group of data line groups are turned on through the data selection signal line MUX3, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S7 electrically connected to the data selection circuit T7 through the third data signal output terminal Y3. And so on, the data signal is written into the first two pixel circuits 10 electrically connected to the data line S(m / 3) electrically connected to the data selection circuit T(m-2) through the (m / 3)th data signal output terminal Y(m / 3).

[0196] By analogy, the data signals are written into the first two pixel circuits 10 in other columns of pixel circuits through the data selection signal lines MUX1, MUX2, MUX3 and the data signal output terminals Y1, Y2..., that is, the source driver circuit 40 completes the data writing to the first row of pixel circuits 10 and the second row of pixel circuits 10.

[0197] Step S3: The gate driving circuit 20 drives the third row of pixel circuits 10 and the fourth row of pixel circuits 10 through the third row of gate lines and the fourth row of gate lines respectively. Step S2 is repeated to complete the writing of data into the third row of pixel circuits 10 and the fourth row of pixel circuits 10.

[0198] This process is repeated in this way until the data writing into the pixel circuits 10 in the n-1th row and the pixel circuits 10 in the nth row is completed. For example, n may be 2160, and the driving process of the pixel circuits 10 in the 2159th row and the pixel circuits 10 in the 2160th row includes: the gate driving circuit 20 simultaneously drives the pixel circuits 10 in the 2159th row and the pixel circuits 10 in the 2160th row via the gate line in the 2159th row and the gate line in the 2160th row, respectively, and repeats step S2 to complete the data writing into the pixel circuits 10 in the 2159th row and the pixel circuits 10 in the 2160th row.

[0199] In the embodiment of the present disclosure, the data signal can be sequentially charged into the corresponding pixel circuits 10 according to the opening sequence of the data selection signal line MUX1 and the data signal output terminal Y1. Obviously, in this process, a data signal can be written into two rows of pixel circuits 10 at the same time.

[0200] Figure 8 is a data flow diagram in some embodiments of the present disclosure.

[0201] Among them, such as Figure 8 As shown, the SOC chip sends image data with a resolution of 3840*1080 and a refresh rate of 120Hz, and the timing controller TCON receives image data with a resolution of 3840*1080 and a refresh rate of 120Hz. That is, the data signal in this process is image data with a resolution of 3840*1080 and a refresh rate of 120Hz. The timing controller controls the timing of the shift register and cooperates with the data signal selection circuit MUX switch to achieve simultaneous driving of two rows of pixel circuits 10 and write a data signal into the two rows of pixel circuits 10. Finally, the display panel panel displays image information with a resolution of 3840*2160 and a refresh rate of 120Hz.

[0202] exist Figure 4 In the display substrate shown, the control end of the data selection circuit electrically connected to the first data line in each data line group is electrically connected to the data selection signal line MUX1, the control end of the data selection circuit electrically connected to the second data line in each data line group is electrically connected to the data selection signal line MUX2, and the control end of the data selection circuit electrically connected to the third data line in each data line group is electrically connected to the data selection signal line MUX3.

[0203] In addition, the first group of data selection circuits includes a data selection circuit electrically connected to the first data line in the first group of data line groups, a data selection circuit electrically connected to the third data line in the first group of data line groups, and a data selection circuit electrically connected to the second data line in the second group of data line groups.

[0204] The second group of data selection circuits includes a data selection circuit electrically connected to the second data line in the first group of data line groups, a data selection circuit electrically connected to the first data line in the second group of data line groups, and a data selection circuit electrically connected to the third data line in the second group of data line groups.

[0205] The driving process of the display substrate includes:

[0206] Step S1 : under the modulation of the driving timing, the gate driving circuit 20 drives the pixel circuits 10 in the first row and the pixel circuits 10 in the second row simultaneously through the gate lines in the first row and the gate lines in the second row.

[0207] Step S2: The data selection circuits T1, T4, ..., T(m-5), T(m-2) electrically connected to the first data lines S1, S4, ..., S(m-5), S(m-2) in each data line group are turned on through the first data selection signal line MUX1, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S1 electrically connected to the data selection circuit T1 through the first data signal output terminal Y1. And so on, the data signal is written into the first two pixel circuits 10 electrically connected to the data line S(m-5) electrically connected to the data selection circuit T(m-5) through the (m / 3-1)th data signal output terminal Y(m / 3-1).

[0208] Then, the data selection circuits T2, T5, ..., T(m-4), T(m-1) electrically connected to the second data lines S2, S5, ..., S(m-4), S(m-1) in each data line group are turned on through the second data selection signal line MUX2, and the data signal is written into the first two pixel circuits 10 electrically connected to the data line S4 electrically connected to the data selection circuit T4 through the second data signal output terminal Y2. And so on, the data signal is written into the first two pixel circuits 10 electrically connected to the data line S(m-1) electrically connected to the data selection circuit T(m-1) through the (m / 3)th data signal output terminal Y(m / 3).

[0209] By analogy, the data signals are written into the first two pixel circuits 10 in other columns of pixel circuits through the data selection signal lines MUX1, MUX2, MUX3 and the data signal output terminals Y1, Y2..., that is, the source driver circuit 40 completes the data writing to the first row of pixel circuits 10 and the second row of pixel circuits 10.

[0210] Step S3: The gate driving circuit 20 drives the third row of pixel circuits 10 and the fourth row of pixel circuits 10 through the third row of gate lines and the fourth row of gate lines respectively. Step S2 is repeated to complete the writing of data into the third row of pixel circuits 10 and the fourth row of pixel circuits 10.

[0211] The same process is repeated until the data writing to the pixel circuits 10 in the (n-1)th row and the pixel circuits 10 in the nth row is completed.

[0212] Similarly, in the embodiment of the present disclosure, data signals can also be written simultaneously into two rows of pixel circuits 10. Therefore, when receiving image data with a resolution of 3840*1080 and a refresh rate of 10Hz, the display panel can display images with a resolution of 3840*2160 and a refresh rate of 120Hz. In other words, the embodiment of the present disclosure can achieve high refresh rate display without changing the hardware specifications.

[0213] At the same time, turning on two rows of pixel circuits 10 simultaneously reduces the number of pixel circuit rows scanned row by half. In this case, the data writing time for each pixel circuit row is correspondingly doubled. For example, doubling the data charging time for pixel circuits 10 with a refresh rate of 120 Hz can solve the problem of insufficient charging time for pixel circuits 10 in high-resolution and high-refresh rate display substrates.

[0214] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate comprising a display area and a non-display area surrounding the display area, characterized in that: The display substrate comprises: a plurality of pixel circuits located in the display area, the plurality of pixel circuits being arranged in a plurality of rows and columns, and the plurality of pixel circuits including a plurality of pixel circuit columns arranged along a first direction; a plurality of data lines extending along a second direction, located in the display area, wherein the second direction intersects the first direction, the data lines corresponding to the pixel circuit columns one by one, and the data lines are electrically connected to each pixel circuit in the corresponding pixel circuit column; At least one gate driving circuit is located in the non-display area, and the gate driving circuit is configured to drive multiple rows of pixel circuits simultaneously each time; A source driving circuit is located in the non-display area, and the source driving circuit has a plurality of data signal output terminals; A plurality of data strobe circuits, each corresponding one-to-one to the data lines and having a first end electrically connected to the corresponding data line, the plurality of data strobe circuits comprising a plurality of data strobe circuit groups, each of the data strobe circuit groups comprising a plurality of data strobe circuits, the data strobe circuit groups corresponding one-to-one to the data signal output ends, and the second end of the data strobe circuit in the same data strobe circuit group electrically connected to the corresponding data signal output end.

2. The display substrate according to claim 1, wherein: The display substrate further includes a plurality of data strobe signal lines located in the non-display area; The control terminal of the data strobe circuit is electrically connected to the data strobe signal line, wherein the control terminals of at least two data strobe circuits in the same data strobe circuit group are electrically connected to different data strobe signal lines; The data strobe signal line is connected to the gate driving circuit, and the gate driving circuit is further configured to output a data strobe signal to the data strobe signal line so that the data strobe signal line transmits the data strobe signal to the control terminal of the data strobe circuit; The data strobe circuit is configured to be disconnected under the control of the data strobe signal to disconnect the data signal output terminal from the corresponding data line, or to be turned on under the control of the data strobe signal to electrically connect the data signal output terminal to the corresponding data line.

3. The display substrate according to claim 2, wherein: The multiple data lines include multiple data line groups arranged along the first direction, the data line group includes multiple data lines arranged along the first direction, the control end of the data selection circuit corresponding to each data line in the same data line group is electrically connected to the same data selection signal line, and the control end of the data selection circuit corresponding to the data lines in at least two data line groups is electrically connected to different data selection signal lines.

4. The display substrate according to claim 3, wherein: There are q data lines in the data line group, and there are r data selection signal lines. Along the first direction, each q*r data lines includes r groups of data line groups arranged in sequence, and the data selection circuits corresponding to the q*r data lines include r groups of data selection circuit groups, wherein at least two data selection circuits in each data selection circuit group are electrically connected to data lines belonging to different data line groups among the r groups of data line groups, i is an integer greater than or equal to 1 and less than or equal to r, r is an integer greater than or equal to 2 and less than or equal to m / q, and m is the total number of data lines.

5. The display substrate according to claim 4, wherein: In each r data line groups, the data line groups correspond to the data strobe signal lines one by one, and the control terminals of the data strobe circuits electrically connected to the data lines in the same data line group are all electrically connected to the corresponding data strobe signal lines.

6. The display substrate according to claim 4, wherein: The value of r is 2 or 3.

7. The display substrate according to claim 2, wherein: The multiple data lines include multiple data line groups arranged along the first direction, and the data line group includes multiple data lines arranged along the first direction, and the data selection signal lines electrically connected to the control ends of the data selection circuits electrically connected to different data lines in the same data line group are different.

8. The display substrate according to claim 7, wherein: There are q data lines in the data line group, and the multiple data selection signal lines include at least one group of data selection signal line groups. The data selection signal line group includes q data selection signal lines, and each group of data selection signal line groups corresponds to multiple groups of data line groups. The control end of the data selection circuit corresponding to the j-th data line in each data line group is electrically connected to the j-th data selection signal line in the corresponding data selection signal line group, where j is an integer greater than or equal to 1 and less than or equal to q.

9. The display substrate according to claim 8, wherein: In the data lines corresponding to each group of data selection signal line groups, along the first direction, the data selection circuits electrically connected to each q*k data lines include k groups of data selection circuit groups, k is an integer greater than or equal to 2 and less than or equal to m' / q, m' is the total number of data lines in the multiple data line groups corresponding to each group of data selection signal line groups, wherein the data selection circuits corresponding to the j-th data line in different data line groups belong to different data selection circuit groups.

10. The display substrate according to claim 9, wherein: The value of k is 2 or 3.

11. The display substrate according to any one of claims 1 to 10, characterized in that: The plurality of pixel circuits include a plurality of pixel circuit rows arranged along a second direction; The display substrate further includes a plurality of gate lines extending along a first direction, the gate lines being located in a display area, the plurality of gate lines including a plurality of gate line groups arranged along a second direction, the gate line groups including a plurality of gate lines arranged along the second direction, the gate lines corresponding one-to-one to the pixel circuit rows, and the gate lines being electrically connected to each pixel circuit in the corresponding pixel circuit row; The gate drive circuit includes a plurality of shift registers that are cascaded and arranged along the second direction, the plurality of shift registers include a plurality of shift register groups, the shift register groups correspond one-to-one to the gate line groups, and the shift registers in the shift register groups correspond one-to-one to the gate lines in the corresponding gate line groups and are electrically connected along the second direction, and the shift registers in the same shift register group have the same timing.

12. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 11.

13. The display panel according to claim 12, wherein: The display panel further includes a cell-matching substrate disposed opposite to the display substrate, the cell-matching substrate including a plurality of color filter portions, the color filter portions corresponding to the pixel circuits one by one and disposed opposite to each other; There are q data lines in the data line group, and the color filter portion corresponding to the pixel circuit electrically connected to the j-th data line in each data line group can transmit the same color of light, j is an integer greater than or equal to 1 and less than or equal to q, and the color filter portion corresponding to the pixel circuit electrically connected to different data lines in the same data line group can transmit different colors of light.

14. A display device, characterized in that: Comprising the display panel according to claim 12 or 13.

Images