Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The memory includes a first data line and a first control line for writing, and a second data line and a second control line for reading. The memory cell includes: a first transistor having a gate connected to a first control line and one end connected to a first data line; a second transistor having a gate connected to the second control line and one end connected to the second data line; and a third transistor having a gate connected to the other end of the first transistor and having one end connected to the other end of the second transistor. The detection circuit is connected to the first and second data lines. When writing or reading data, the control unit activates the second control line, the detection circuit detects the first data on the basis of the voltage of the second data line, and then the control unit activates the first control line. After receiving the write command, the detection circuit transfers second data to the gate of the third transistor when latching the second data from the outside.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Art

[0002] A gain cell memory reads data by amplifying accumulated charge at a sense node using a transistor. In such a gain cell memory, it is desirable to reduce power consumption. Summary of the Invention

[0003] Provided is a semiconductor memory device capable of reducing power consumption.

[0004] The semiconductor memory device of this embodiment includes a first data line and a first control line for writing data, and a second data line and a second control line for reading data. Multiple memory cells include: a first transistor having a gate connected to the first control line and one end connected to the first data line; a second transistor having a gate connected to the second control line and one end connected to the second data line; and a third transistor having a gate connected to the other end of the first transistor to hold data from the first data line, and one end connected to the other end of the second transistor, with a conductive state corresponding to the data. A detection circuit is connected to the first and second data lines, latches external data, applies a voltage corresponding to the latched data to the first data line, or detects data based on the voltage of the second data line. A control unit controls the first and second control lines. When writing or reading data, the control unit activates the second control line, and the detection circuit detects the first data based on the voltage of the second data line. The control unit then activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor. After receiving a write command instructing writing, the detection circuit transmits the second data to the gate of the third transistor while latching the second data from the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 This is a circuit diagram showing a configuration example of a memory cell of a gain cell memory according to the first embodiment.

[0006] Figure 2 This is a block diagram showing a configuration example of a gain unit memory according to the first embodiment.

[0007] Figure 3 This is a state transition diagram showing an example of a case where the gain cell memory is operated in the DRAM mode.

[0008] Figure 4 This is a timing chart showing an example of operating the gain cell memory in the DRAM mode.

[0009] Figure 5 FIG. 1 is a diagram showing the state of the sense amplifier in the DRAM mode.

[0010] Figure 6 FIG. 1 is a diagram showing the state of the sense amplifier in the DRAM mode.

[0011] Figure 7 FIG. 1 is a diagram showing the state of the sense amplifier in the DRAM mode.

[0012] Figure 8 FIG. 1 is a diagram showing the state of the sense amplifier in the DRAM mode.

[0013] Figure 9 This is a state transition diagram showing an example of a case where the gain block memory is operated in the first gain block mode.

[0014] Figure 10 This is a timing chart showing an example of a case where the gain block memory is operated in the first gain block mode.

[0015] Figure 11 3 is a diagram showing the state of the sense amplifier in the first gain unit mode.

[0016] Figure 12 3 is a diagram showing the state of the sense amplifier in the first gain unit mode.

[0017] Figure 13 3 is a diagram showing the state of the sense amplifier in the first gain unit mode.

[0018] Figure 14 This is a timing chart showing an example of a case where the gain block memory is operated in the second gain block mode.

[0019] Figure 15 3 is a diagram showing the state of the sense amplifier in the second gain unit mode.

[0020] Figure 16 3 is a diagram showing the state of the sense amplifier in the second gain unit mode.

[0021] Figure 17 This is a timing chart showing an example of random access in the first gain unit mode.

[0022] Figure 18 This is a timing diagram showing an example of page access in the first gain unit mode.

[0023] Figure 19 This is a timing chart showing an example of random access in the second gain unit mode.

[0024] Figure 20 This is a timing diagram showing an example of page access in the second gain unit mode.

[0025] Figure 21This is a state transition diagram showing the operation of the gain cell memory according to the second embodiment.

[0026] Figure 22 This is a timing chart showing the operation of the gain cell memory according to the third embodiment.

[0027] Figure 23 This is a timing chart showing the operation of the gain cell memory according to the third embodiment.

[0028] Figure 24 This is a timing chart showing the operation of the gain cell memory according to the fourth embodiment.

[0029] Figure 25 This is a timing chart showing the operation of the gain cell memory according to the fourth embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual. In the specification and the drawings, the same elements are marked with the same symbols.

[0031] (First embodiment)

[0032] Figure 1 This circuit diagram shows an example configuration of a memory cell of a gain cell memory according to the first embodiment. A memory cell MC of the gain cell memory is composed of three transistors: MW1, MR1, and MR2. Transistors MW1, MR1, and MR2 are, for example, n-type oxide semiconductor field effect transistors (OSFETs).

[0033] The gate of transistor MW1, serving as the first transistor, is connected to write word line WWL, serving as the first control line. One electrode of transistor MW1 is connected to write bit line WBL, serving as the first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. One and the other electrodes of transistor MW1 function as a source electrode or a drain electrode, depending on the voltage supplied to transistor MW1. Transistor MW1 is controlled by write word line WWL and connects write bit line WBL to the gate of transistor MR1, serving as sense node SN (hereinafter also referred to as sense node SN). When transistor MW1 is in the on state, it transfers the voltage of write bit line WBL to sense node SN. When transistor MW1 is in the off state, it maintains the voltage of sense node SN. In this way, transistor MW1 can write the voltage (data) from write bit line WBL to sense node SN, or maintain the voltage (data) written to sense node SN.

[0034] The gate of transistor MR1, the third transistor, is connected to the other electrode of transistor MW1 and functions as a sensing node SN. One electrode (source) of transistor MR1 is connected to a low voltage source VSS. The other electrode (drain) of transistor MR1 is connected to one electrode of transistor MR2. Transistor MR1 is turned on in accordance with the voltage (i.e., data) of sensing node SN. For example, when sensing node SN is maintained at a high voltage level (e.g., data "1"), transistor MR1 is turned on. When sensing node SN is maintained at a low voltage level (e.g., data "0"), transistor MR1 is turned off.

[0035] The gate of transistor MR2, serving as the second transistor, is connected to read word line RWL, serving as the second control line. One electrode of transistor MR2 is connected to the drain of transistor MR1. The other electrode of transistor MR2 is connected to read bit line RBL, serving as the second data line. One and the other electrodes of transistor MR2 can function as either a source electrode or a drain electrode depending on the voltage supplied to transistor MR2. Transistor MR2 is controlled by read word line RWL and connects read bit line RBL to the drain of transistor MR1. Transistor MR1 assumes a state (conductive or non-conductive) corresponding to the voltage (data) held at sense node SN. When transistor MR2 is conductive, connecting read bit line RBL to transistor MR1, charge from read bit line RBL flows to low voltage source VSS depending on the state of transistor MR1. When transistor MR1 is conductive, charge from read bit line RBL flows to low voltage source VSS, lowering the voltage of read bit line RBL. When transistor MR1 is non-conductive, almost no charge flows from read bit line RBL to low voltage source VSS, and the voltage of read bit line RBL is maintained high. As a result, a voltage based on data stored in sense node SN is transferred to read bit line RBL.

[0036] A sense amplifier SA, serving as a detection circuit, is connected to the write bit line WBL and the read bit line RBL. The sense amplifier SA latches externally supplied write data and applies a voltage corresponding to the write data to the write bit line WBL. Furthermore, the sense amplifier SA detects read data based on the voltage of the read bit line RBL and latches the read data. The read data latched by the sense amplifier SA is transmitted externally. The sense amplifier SA also precharges the write bit line WBL and the read bit line RBL.

[0037] The control unit CTL is connected to the write word line WWL and the read word line RWL, and controls the voltages of the write word line WWL and the read word line RWL.

[0038] The write word line WWL and write bit line WBL are used for writing data. The read word line RWL and read bit line RBL are used for reading data. Thus, the gain cell memory uses different word lines and bit lines for writing and reading data. This allows the gain cell memory to read data while maintaining the data on the sense node SN (non-destructive read). Furthermore, a single memory cell MC consists of three transistors MW1, MR1, and MR2, eliminating the need for capacitors, which are difficult to miniaturize in DRAM (Dynamic Random Access Memory). Consequently, the gain cell memory is highly adaptable to miniaturization.

[0039] Figure 2 This is a block diagram showing an example of the configuration of a gain cell memory according to the first embodiment. The gain cell memory of this embodiment includes a three-dimensional memory cell array in which a plurality of memory cells MC are arranged in three dimensions. The plurality of memory cells MC are arranged in a matrix including a plurality of rows and a plurality of columns. A row is an arrangement of the memory cells MC in the X direction. A column is an arrangement of the memory cells MC in the Z direction. In addition, the memory cells MC arrange the rows and columns of the memory cells MC in the Y direction. Thus, the memory cell array MCA becomes a three-dimensional array in which a plurality of memory cells MC are arranged in three dimensions. In addition, the number of rows, columns, and matrices of the memory cells MC is not particularly limited.

[0040] A plurality of write word lines WWL are provided corresponding to each of the plurality of rows of memory cells MC, and a plurality of read word lines RWL are also provided corresponding to each of the plurality of rows of memory cells MC.

[0041] Multiple write bit lines WBL are provided for each of the multiple columns of memory cells MC. Multiple read bit lines RBL are also provided for each of the multiple columns of memory cells MC. Multiple sense amplifiers SA are also provided for each of the multiple columns of memory cells MC. Furthermore, source lines SL are also provided for each of the multiple columns of memory cells MC.

[0042] Next, the operation of the gain cell memory according to this embodiment will be described.

[0043] (DRAM mode: Mode 1)

[0044] Figure 3 This is a state transition diagram showing an example of operating the gain cell memory in DRAM mode. Figure 3 In the , the horizontal arrow of each instruction indicates the active or inactive state. The upward arrow indicates active, and the downward arrow indicates inactive. Figure 9 、 Figure 13 and Figure 21 Same here. Figure 4This is a timing diagram showing an example of operating the gain unit memory in DRAM mode. Figure 4 , a specific example is shown in which data “1” is stored in a memory cell MC and data “0” is written to the memory cell MC.

[0045] Each memory cell MC of the gain cell memory holds data in an idle state. The gain cell memory periodically performs a data recovery operation (refresh) on each memory cell MC. The recovery operation will be described later.

[0046] The memory cell array MCA is divided into multiple memory banks, each of which operates in an active state (Bank active). Figure 4 At t1, when the gain cell memory receives an active command ACT, a bank is selectively placed in the active state. In the active state, the read bit lines RBL of the multiple columns in the selected bank are charged. Next, at t2, the read word line RWL corresponding to the selected row among the multiple rows in the bank is activated. Consequently, from t3 to t4, data from the multiple memory cells MC corresponding to the selected row is detected and latched by the sense amplifier SA in each of the multiple columns.

[0047] At t4, the read word line RWL of the selected row is deactivated, and the write word line WWL of the selected row is activated. This enables data to be written to the multiple memory cells MC in the selected row. From t4 to t5, the data latched by the sense amplifier SA (the data originally stored in the memory cells MC in the selected row) is returned to the sense nodes SN of the multiple memory cells MC in the selected row via the write bit lines WBL of each column.

[0048] Next, at t5, when the gain unit memory receives a write instruction WRITE or a read instruction READ, the gain unit memory is Figure 3 The active state (Bank active) changes to the writing state (Writing) or the reading state (Reading). Figure 4 As shown, a write command WRITE is issued at t5. In this case, the gain unit memory changes from the active state to the write state.

[0049] At t6, when the column selection line CSL is enabled, the write data is transferred and latched to the sense amplifier SA corresponding to the selected column selected from the plurality of columns. Figure 4 In the example, data "0" is transferred as write data to the sense amplifier SA of the selected column. At this time, since the write word line WWL is activated, the write data is written to the memory cell MC corresponding to the selected column in the selected row via the write bit line WBL. Figure 4In the example shown in Figure 2, data "0" is written to the memory cell MC in the selected column within the selected row via write bit line WBL. Consequently, the data on sense node SN is inverted from "1" to "0." Furthermore, the original data stored in the memory cell MC corresponding to the unselected column within the selected row is written back. Furthermore, even in the selected column, if the written data and the original data stored in the memory cell MC have the same logic, the original data stored in the memory cell MC is written without undergoing a logic inversion.

[0050] At t7, the column select line CSL is deactivated, and at t8, a precharge command PRE is issued. Figure 3 The write state transitions to the precharging state. At this point, at t9, the write word line WWL is deactivated. This electrically disconnects the multiple memory cells MC in the selected row from the write bit line WBL, leaving the write data stored in the sense node SN. Furthermore, at t10, the multi-column sense amplifier SA precharges the write bit line WBL to, for example, VDD / 2. The write bit line WBL is then disconnected from the sense amplifier SA. VDD is, for example, the voltage of a high-voltage source. Precharging is thus completed, and the gain cell memory returns to the standby state.

[0051] On the other hand, at t5, when the gain unit memory receives the read command READ, the gain unit memory is Figure 3 The active state (Bank active) transitions to the read state (Reading). In this case, although not shown, at t6, when the column select line CSL is enabled, the sense amplifier SA transmits the latched data to the external device as read data. The data latched in the sense amplifier SA is not inverted and is directly written back to the multiple memory cells MC in the selected row via the write bit line WBL. Therefore, during the precharge operation, the data on the sense nodes SN of the multiple memory cells MC in the selected row is not inverted and remains unchanged. The remaining read operations (t1-t5, t8-t10) can be identical to the corresponding write operations.

[0052] Thus, in DRAM mode, when writing or reading data, the read word line RWL is activated, and the sense amplifier SA detects data based on the voltage of the read bit line RBL. Subsequently, during a write operation, the write word line WWL is activated, and the sense amplifier SA transfers the write data to the sense node SN of the memory cell MC at the timing when the column select line CSL is activated to latch the external write data. The memory cell MC retains the data written to the sense node SN. Conversely, during a read operation, the write word line WWL is activated, and the sense amplifier SA returns the read data to the sense node SN of the memory cell MC at the timing when the column select line CSL is activated to output the read data externally. The memory cell MC retains the data returned to the sense node SN.

[0053] Therefore, in DRAM mode, when reading data, read word line RWL is activated, and sense amplifier SA detects the read data based on the voltage of read bit line RBL. Write word line WWL is then activated, and sense amplifier SA outputs the read data externally by activating column select line CSL. The same data is also returned to sense node SN of memory cell MC. Memory cell MC retains the read data returned to sense node SN.

[0054] In the recovery operation, the gain cell memory temporarily reads out the data stored in each memory cell MC and then writes back the same data. Figure 3 After the standby state is changed to the active state, when the precharge command PRE is issued, it directly changes to the precharge state and returns to the standby state. At this time, the column select line CSL cannot be enabled. The sense amplifier SA does not output data from the memory cell MC to the outside, nor does it extract data from the outside. Therefore, writing data to the sense amplifier SA and reading data from the sense amplifier SA are not performed. In the active state, the data detected by the sense amplifier SA is directly written back to the original memory cell MC. In other words, the control unit CTL activates the write word line WWL, and the sense amplifier SA transfers the latched data from the memory cell MC to the sense node SN of the original memory cell MC, thereby restoring (refreshing) the data of the memory cell MC. The recovery operation can be performed by selecting multiple rows in sequence.

[0055] In addition, if Figure 3 As shown in FIG. 1 , when a read command READ is received after a write command WRITE is received, the gain cell memory may transition from the write state (Writing) to the read state (Reading). Conversely, when a write command WRITE is received after a read command READ is received, the gain cell memory may transition from the read state (Reading) to the write state (Writing).

[0056] Figures 5 to 8 This is a diagram showing the state of the sense amplifier in DRAM mode. The sense amplifier SA has a latch circuit composed of two n-type MOSFETs and two p-type MOSFETs. The latch circuit maintains either the high voltage source VDD or the low voltage source VSS at the node N1 according to the latched data. For example, when the read bit line RBL is a low-level voltage (data "1"), the node N1 maintains a low-level voltage based on the low voltage source VSS. For example, when the read bit line RBL is a high-level voltage (data "0"), the node N1 maintains a high-level voltage based on the high voltage source VDD. Node N1_b maintains an inversion signal for node N1. In addition, RBL_b represents the inversion signal of the read bit line RBL. WBL_b represents the inversion signal of the write bit line WBL. LIO_b represents the inversion signal of the input / output line LIO.

[0057] First, in the active state from t1 to t2, if Figure 5 As shown, read bit lines RBL and RBL_b are connected to sense amplifier SA and charged based on the precharge potential. In addition, write bit lines WBL and WBL_b are not connected to sense amplifier SA.

[0058] At t2~t4, if Figure 6 As shown, data from the memory cell MC is detected and latched by the sense amplifier SA via the read bit line RBL.

[0059] At t4-t6, if Figure 7 As shown, the write state is established, and write bit lines WBL and WBL_b are connected to sense amplifier SA. As a result, data latched in sense amplifier SA is written into memory cell MC. Furthermore, after read word line RWL is deactivated, read bit lines RBL and RBL_b are disconnected from sense amplifier SA.

[0060] At t6~t7, if Figure 8 As shown, column select line CSL is activated, and input / output lines LIO and LIO_b are connected to nodes N1 and N1_b, respectively. External write data (data "0") is thus latched into nodes N1 and N1_b and transferred to sense node SN of memory cell MC via write bit line WBL.

[0061] In this way, the sense amplifier SA can detect data stored in the memory cell MC and output the data to the outside as read data, or latch write data from the outside and write the write data to the memory cell MC.

[0062] In DRAM mode, when the gain cell memory becomes active, the read word line RWL is temporarily activated, the sense amplifier SA detects data based on the voltage of the read bit line RBL, and before receiving a write command WRITE or a read command READ, the write word line WWL is activated.

[0063] After the gain cell memory becomes active, upon receiving a write command WRITE, the sense amplifier SA transfers the write data to the sense node SN of the memory cell MC at a timing to latch the write data from the outside.

[0064] When receiving the read command READ, the sense amplifier SA outputs the latched data to the outside.

[0065] In DRAM mode, the gain cell memory can perform high-speed random access to any memory cell MC within a block of the memory cell array MCA. Because the gain cell memory divides the word lines and bit lines into write and read, it can operate in the same manner as DRAM. On the other hand, in DRAM mode, each time the gain cell memory becomes active, it activates the write word line WWL regardless of the issuance of the write command WRITE. Therefore, in the case of repeated read operations, power consumption increases. In addition, in DRAM mode, because the write word line WWL is activated each time the gain cell memory becomes active, precharging is required even for read operations. Therefore, in the case of repeated read operations, power consumption also increases.

[0066] (1st gain unit mode: 1st sub-mode of 2nd mode)

[0067] Figure 9 This is a state transition diagram showing an example of a case where the gain block memory is operated in the first gain block mode. Figure 10 This is a timing diagram showing an example of operating the gain unit memory in the first gain unit mode. Figure 10 , a specific example is shown in which data “1” is stored in a memory cell MC and data “0” is written to the memory cell MC.

[0068] In the first gain unit mode, when the standby state is changed to the active state, the write word line WWL is not activated. The write word line WWL is activated after the write command WRITE is issued. For example, Figure 10 As shown, the write word line WWL is activated at the same timing as the column select line CSL is activated.

[0069] In addition, in the first gain unit mode, if Figure 9As shown, path P1 is set, which allows the device to transition directly from the read state (Reading) to the idle state (Idle) without precharging. As mentioned above, the gain cell memory is capable of non-destructive reading, and the original data does not necessarily need to be written back to the memory cell MC during the read operation. Therefore, if recovery is not required, the gain cell memory can transition directly to the idle state after the read operation, as shown by path P1.

[0070] exist Figure 10 In the example, the actions of t1 to t4 can be Figure 4 The operations from t1 to t4 are the same. However, in the first gain cell mode, at t4, the write word line WWL is not activated. In addition, the data latched in the sense amplifier SA is not transferred to the write bit line WBL.

[0071] At t6, the control unit CTL activates the column selection line CSL. As a result, the write data is transferred and latched to the sense amplifier SA corresponding to the selected column selected from the plurality of columns. Figure 10 In the example, data "0" is transmitted as write data to the sense amplifier SA of the selected column. At the same timing, the control unit CTL activates the write word line WWL of the selected row. In addition, the write bit lines WBL and WBL_b are connected to the sense amplifier SA. As a result, the write data is written to the memory cell MC corresponding to the selected column in the selected row via the write bit line WBL. Figure 10 In the example shown in Figure 2, data "0" is written to the memory cell MC in the selected column within the selected row via write bit line WBL. Consequently, the data on sense node SN is inverted from "1" to "0." Furthermore, the original data stored in the memory cell MC corresponding to the unselected column within the selected row is written back. Furthermore, even in the selected column, if the written data and the original data stored in the memory cell MC have the same logic, the original data stored in the memory cell MC is written without undergoing a logic inversion.

[0072] after, Figure 10 The actions of t7 to t10 can be Figure 4 The actions from t7 to t10 are the same.

[0073] Figure 11 and Figure 12 The state of the sense amplifier SA at t1 to t4 is shown in FIG. Figure 5 and Figure 6 The status of the description is the same.

[0074] At t4-t6, Figure 11 The sense amplifier SA shown holds data read out from the memory cell MC.

[0075] At t6~t7, if Figure 12 As shown, column select line CSL is activated, and input / output lines LIO and LIO_b are connected to nodes N1 and N1_b, respectively. This latches external write data (data "0") into nodes N1 and N1_b. At the same timing as the activation of column select line CSL, write word line WWL is activated. This transfers the external write data to nodes N1 and N1_b and, via write bit line WBL, to sense node SN of memory cell MC.

[0076] In this manner, the sense amplifier SA can detect data stored in the memory cell MC and output the data to the outside as read data, or can latch write data from the outside and write the write data to the memory cell MC.

[0077] Thus, in the first gain cell mode, when the gain cell memory is in the active state, read word line RWL is temporarily activated, and sense amplifier SA detects read data based on the voltage of read bit line RBL. At this time, write word line WWL remains inactive.

[0078] After the gain cell memory enters the active state, upon receiving a write command (WRITE), it activates the write word line WWL. The sense amplifier SA latches external write data by activating the column select line CSL and transfers the latched data to the sense node SN of the memory cell MC at the same time as the write word line WWL is activated. Furthermore, in the first gain cell mode, since the column select line CSL and the write word line WWL are activated at approximately the same time, the sense amplifier SA transfers the external write data to the sense node SN of the memory cell MC at the same time as the latched data.

[0079] When a read command READ is received, the write word line WWL remains inactive, and the sense amplifier SA outputs the read data externally at the timing when the column select line CSL becomes active. As described above, the gain cell memory is capable of non-destructive readout, so in the first gain cell mode, it transitions directly to the standby state after the read operation.

[0080] (Second gain unit mode: second sub-mode of the second mode)

[0081] Figure 13 This is a state transition diagram showing an example of a case where the gain block memory is operated in the second gain block mode. Figure 14 This is a timing diagram showing an example of operating the gain unit memory in the second gain unit mode. Figure 14 , a specific example is shown in which data “1” is stored in a memory cell MC and data “0” is written to the memory cell MC.

[0082] The second gain unit mode is similar to the first gain unit mode in that the write word line WWL is activated after the write command WRITE is issued. Figure 14 As shown, the write word line WWL is activated at the timing of receiving the precharge command PRE after the column select line CSL is activated.

[0083] In addition, in the second gain unit mode, as Figure 13 As shown, a path P1 is also set that directly transitions from the read state to the standby state without precharging. This is because the gain cell memory can be read non-destructively.

[0084] exist Figure 14 In the example, the actions of t1 to t5 can be Figure 10 The actions from t1 to t5 are the same.

[0085] From t6 to t7, the control unit CTL activates the column select line CSL. As a result, the write data is transmitted and latched to the sense amplifier SA corresponding to the selected column selected from the multiple columns. However, at this time, in the second gain unit mode, the write word line WWL has not yet been activated. After the write command WRITE is issued, the write word line WWL is activated at the timing of receiving the precharge command PRE at t8. In addition, the write bit lines WBL and WBL_b are connected to the sense amplifier SA. Therefore, in Figure 14 In the example of , when the precharge command PRE is issued, the write word line WWL is activated, and the write data latched in the sense amplifier SA is written to the memory cell MC corresponding to the selected column in the selected row via the write bit line WBL. Figure 14 In the example shown in FIG. 1 , data “0” is written to the memory cell MC of the selected column in the selected row via the write bit line WBL. Therefore, the data of the sense node SN is inverted from “1” to “0”.

[0086] Thereafter, at t9, write word line WWL is deactivated, and at t10, write bit line WBL is set to a precharge state. Write bit lines WBL and WBL_b are disconnected from sense amplifier SA.

[0087] The other operations of the second gain block mode may be the same as those of the first gain block mode.

[0088] Figure 15 and Figure 16 The state of the sense amplifier SA at t1 to t4 is shown in FIG. Figure 5 and Figure 6 The state of the sense amplifier SA from t4 to t6 is the same as that of the reference Figure 11 The status of the description is the same.

[0089] At t6~t7, if Figure 15 As shown, column select line CSL is activated, and input / output lines LIO and LIO_b are connected to nodes N1 and N1_b, respectively. External write data (data "0") is latched into nodes N1 and N1_b. At this point, write word line WWL is not yet activated.

[0090] At t8-t9, if Figure 16 As shown, when the precharge command PRE is issued, the write word line WWL is activated. In addition, the write bit lines WBL and WBL_b are connected to the sense amplifier SA. As a result, the sense amplifier SA writes the latched write data into the memory cell MC.

[0091] Thus, in the second gain cell mode, after the gain cell memory enters the active state, the write word line WWL remains inactive even when a write command WRITE is received. Furthermore, the sense amplifier SA latches external write data by activating the column select line CSL, but the write word line WWL also remains inactive at this time. Subsequently, when a precharge command PRE is issued, the sense amplifier SA transfers the write data to the sense node SN of the memory cell MC.

[0092] When a read command (READ) is received, the write word line WWL remains inactive, and the sense amplifier SA outputs the read data externally at the same time as the column select line CSL becomes active. As mentioned above, the gain cell memory is capable of non-destructive readout, so it transitions directly to standby mode after the read operation.

[0093] The gain cell memory of this embodiment can selectively execute any one of the DRAM mode, the first gain cell mode, and the second gain cell mode. A mode selection signal indicating which of the DRAM mode, the first gain cell mode, and the second gain cell mode to execute can be pre-set in a program executed by the control unit CTL. In this case, the gain cell memory repeatedly executes the same mode specified by the mode selection signal. Alternatively, the control unit CTL can receive the mode selection signal from an external source when the control unit CTL is operating. In this case, each time the active command ACT is received, the gain cell memory receives the mode selection signal from an external source and selects or switches modes according to the mode selection signal.

[0094] In the first and second gain unit modes, the gain unit memory can also perform random access to any memory cell of the memory cell array MCA, or can also access a selected block of the memory cell array MCA in page units (row units, write word line WWL or read word line RWL units) (page access).

[0095] (Random access in the first gain unit mode)

[0096] For example, Figure 17 This is a timing diagram showing an example of random access in the first gain cell mode. When writing using random access, the gain cell memory activates read word line RWL[i] in selected row [i] in response to the selected row address (RA), setting it to the active state (t2-t4). Sense amplifier SA detects and latches data from a selected memory cell MC in a selected column among multiple memory cells MC in the selected row.

[0097] Next, control unit CTL activates column select line CSL of the selected column and enables write word line WWL[i] of the selected row. Sense amplifier SA of the selected column latches external write data and applies the write data to sense node SN[i] of the selected memory cell via write bit line WBL (t6).

[0098] Thereafter, after a precharge command PRE is issued, the write word line WWL[i] is deactivated ( t9 ), and the write bit line WBL is precharged ( t10 ).

[0099] The write cycle CYCL can be selectively executed on any of the rows [j] to [l].

[0100] In this case, before the precharge command PRE is issued, the write word line WWL is activated, and writing to the memory cell MC is performed. Therefore, high-speed random access is maintained. Since the read operation is easily understood from the write operation described above, its description is omitted here.

[0101] (Page access in the first gain unit mode)

[0102] For example, Figure 18 This is a timing diagram showing an example of page access in the first gain cell mode. When writing using page access, the gain cell memory charges read bit lines RBL[a]-RBL[d] for multiple columns [a]-[d] within the row address (RA), then enables read word line RWL for the selected row and sets it to the active state (t1-t4). Multiple sense amplifiers SA[a]-SA[d] detect and latch data from multiple memory cells MC in the selected row.

[0103] Next, when a write command WRITE is received, the control unit CTL enables the write word line WWL[i] of the selected row and activates the column select lines CSL[a] to CSL[d] of each column according to the column address (CA) received during the write command. For example, when the column select line CSL[a] is activated, the sense amplifier SA[a] of the selected column latches the corresponding write data from the external source and applies the write data to the sense node SN[a] of the selected memory cell via the write bit line WBL (t6a to t7a). Similarly, when the column select lines CSL[b] to CSL[d] are sequentially activated, the sense amplifiers SA[b] to SA[d] of the corresponding selected columns latch the corresponding write data from the external source and apply the write data to the sense nodes SN[b] to SN[d] of the selected memory cell via the write bit line WBL (t6b to t7d).

[0104] Thereafter, after a precharge command PRE is issued, the write word line WWL is deactivated ( t9 ), and the write bit line WBL is precharged ( t10 ).

[0105] The write cycle CYCL can be selectively executed on any row.

[0106] In page access, although random access cannot be performed on any memory cell MC, all data (one page of data) in the selected row can be written by driving one write word line WWL once. Therefore, page access can be performed with low power consumption. In addition, during the read operation, since non-destructive reading is possible, the write instruction WRITE is not issued. Therefore, since the write bit line WBL is in a precharged state, no precharge operation is required. Therefore, the gain unit memory directly transitions to the standby state after the read operation. This can further reduce power consumption. In particular, the power consumption reduction effect is higher when the read operation is repeated frequently.

[0107] (Random access in the second gain unit mode)

[0108] For example, Figure 19 This is a timing diagram illustrating an example of random access in the second gain cell mode. During random access write operations in the second gain cell mode, the activation timing of the write word lines WWL[i]-WWL[l] in the selected row differs from that in the first gain cell mode. In the second gain cell mode, the write word lines WWL[i]-WWL[l] in the selected row are activated upon receiving the precharge command PRE. The remaining random access operations in the second gain cell mode are similar to those in the first gain cell mode.

[0109] In the second gain cell mode, the write cycle CYCL is relatively long because data is written from the sense amplifier SA to the sense node after the precharge command PRE is issued. Therefore, for high-speed random access, the DRAM mode or the first gain cell mode is more preferable.

[0110] (Page access in the second gain unit mode)

[0111] For example, Figure 20 This is a timing diagram showing an example of page access in the second gain cell mode. When writing using page access, the gain cell memory charges read bit lines RBL[a]-RBL[d] for multiple columns [a]-[d] within the row address (RA), then enables read word line RWL for the selected row and sets it to the active state (t1-t4). Multiple sense amplifiers SA[a]-SA[d] each detect and latch data from multiple memory cells MC in the selected row.

[0112] In the second gain block mode, the write word line WWL of the selected row is activated upon receiving the precharge command PRE. Therefore, in a page access in the second gain block mode, when the precharge command PRE is issued and the write word line WWL of the selected row is activated, the data latched in the sense amplifiers SA[a] to SA[d] is written to the sense nodes SN[a] to SN[d] via the write bit lines WBL[a] to WBL[d], respectively (t8). The rest of the page access operation in the second gain block mode can be the same as that in the first gain block mode.

[0113] The write cycle CYCL can also be selectively executed on any row.

[0114] Page access in the second gain cell mode achieves the same effect as page access in the first gain cell mode. Furthermore, in the second gain cell mode, the time during which the write word line WWL is activated is relatively short, resulting in a greater reduction in power consumption.

[0115] Furthermore, in the first or second gain cell mode, the write word line WWL may be activated at any timing between the activation of the column select line CSL and the reception of the precharge command PRE.

[0116] (Second embodiment)

[0117] Figure 21This is a state transition diagram illustrating the operation of the gain cell memory according to the second embodiment. The gain cell memory according to the second embodiment can also receive a write command WRITE from the active state and, after the write operation, receive a read command READ (Reading after Writing) for the same page. In this case, precharging is performed only after the page is read.

[0118] It is also possible to receive a read command READ from the active state, and after the read operation, receive a write command WRITE for the same page. In this case, it is sufficient to perform precharging after the write operation on the page.

[0119] (Third embodiment)

[0120] Figure 22 and Figure 23 This is a timing chart showing the operation of the gain cell memory according to the third embodiment. Figure 22 Indicates that the read data is "1" and the written data is "0". Figure 23 Indicates that the read data is "0" and the written data is "1".

[0121] In the third embodiment, after control unit CTL activates read word line RWL at t2, it maintains the active state until it deactivates write word line WWL at t8 (ending the write operation). Consequently, drain voltage MR1_d of transistor MR1 does not float during the write phase but is fixed to the voltage of read bit line RBL. This increases the voltage difference (sensing margin) between data "0" and data "1" due to the parasitic capacitance between the drain of transistor MR1 and sense node SN.

[0122] The remaining operations of the third embodiment are similar to those of the second gain cell mode of the first embodiment. Furthermore, the third embodiment can be applied to the DRAM mode or the first gain cell mode. This also increases the voltage difference (sensing margin) between data "0" and data "1" in the DRAM mode or the first gain cell mode.

[0123] (Fourth embodiment)

[0124] Figure 24 and Figure 25 This is a timing chart showing the operation of the gain cell memory according to the fourth embodiment. Figure 24 Indicates that the read data is "1" and the written data is "0". Figure 25 Indicates that the read data is "0" and the written data is "1".

[0125] In the fourth embodiment, between the activation of the write word line WWL at t8 (the start of the write operation) and the deactivation of the write word line WWL at t9 (the end of the write operation), the voltage of the source line SL is reduced from VSS to the negative side (e.g., VSS-ΔVsl). In the standby state after precharging, the voltage of the source line SL returns to VSS. Even in the write operation of data "0" or data "1," the voltage of the source line SL is reduced from VSS to the negative side during the activation period of the write word line WWL (during the write operation). This prevents changes in the sensing margin and slightly increases the voltage of the sense node SN in the standby state after precharging. This mitigates the source-drain voltage difference Vgs of the transistor MW1 in the standby state, improving the data retention characteristics of the memory cell MC. This prolongs the recovery operation cycle, thereby reducing power consumption.

[0126] When memory cell MC holds data "0," the source-drain voltage difference Vgs of transistor MW1 is the voltage difference between sense node SN and the gate of transistor MW1. When memory cell MC holds data "1," the source-drain voltage difference Vgs of transistor MW1 is the voltage difference between write bit line WBL and the gate of transistor MW1.

[0127] The remaining operations of the fourth embodiment are the same as those of the second gain cell mode of the first embodiment. Furthermore, the fourth embodiment can be applied to the DRAM mode or the first gain cell mode. This can also improve the data retention characteristics of the DRAM mode or the first gain cell mode.

[0128] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments described may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are also intended to be within the scope of the invention set forth in the claims and their equivalents.

[0129] [Explanation of Symbols]

[0130] MC: Storage Unit

[0131] MW1, MR1, MR2: transistors

[0132] WWL: Write Word Line

[0133] RWL: Read word line

[0134] WBL: Write bit line

[0135] RBL: Read bit line

[0136] SA: Sense Amplifier

[0137] SL: Source line

[0138] CTL: Control Department.

Claims

1. A semiconductor memory device comprising: The first data line and the first control line are used for writing data; A second data line and a second control line for reading data; A plurality of memory cells, comprising: a first transistor having a gate connected to the first control line and one end connected to the first data line; a second transistor having a gate connected to the second control line and one end connected to the second data line; and a third transistor having a gate connected to the other end of the first transistor, holding data from the first data line, one end connected to the other end of the second transistor, and having a conduction state corresponding to the data; a detection circuit connected to the first and second data lines, latching data from the outside and applying a voltage corresponding to the latched data to the first data line, or detecting data based on the voltage of the second data line; and a control unit that controls the first control line and the second control line; and When writing or reading data, the control unit activates the second control line, and the detection circuit detects first data based on the voltage of the second data line. Thereafter, the control unit activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor. After receiving a write command instructing writing, the detection circuit transmits the second data to the gate of the third transistor while latching the second data from the outside.

2. The semiconductor memory device according to claim 1, wherein the plurality of memory cells are arranged in a plurality of rows and a plurality of columns, The plurality of first control lines and the plurality of second control lines are provided corresponding to each of the plurality of rows. The plurality of first data lines, the plurality of second data lines and the plurality of detection circuits are arranged corresponding to each of the plurality of columns. When writing or reading data, the control unit activates the second control line corresponding to a selected row selected from the plurality of rows, and the plurality of detection circuits corresponding to the plurality of columns detect the first data based on the voltages of the plurality of second data lines respectively corresponding to the plurality of columns. Thereafter, the control unit activates the first control line corresponding to the selected row, and the detection circuit transmits the first data to the gate of the third transistor. After receiving the write command, the detection circuit corresponding to the selected column selected from the plurality of columns transmits the second data to the gate of the third transistor of the memory cell corresponding to the selected row and the selected column when latching the second data from the outside. 3 . The semiconductor memory device according to claim 2 , wherein after the control unit inactivates the first control line corresponding to the selected row, the detection circuit performs precharge to set the first data line to a predetermined voltage.

4. The semiconductor memory device according to claim 3, wherein when a precharge command instructing the precharge is issued instead of the write command and the read command, the detection circuit transfers the first data to the gate of the third transistor.

5. A semiconductor memory device comprising: The first data line and the first control line are used for writing data; A second data line and a second control line for reading data; A plurality of memory cells, comprising: a first transistor having a gate connected to the first control line and one end connected to the first data line; a second transistor having a gate connected to the second control line and one end connected to the second data line; and a third transistor having a gate connected to the other end of the first transistor to hold data from the first data line, one end connected to the other end of the second transistor and having a conductive state corresponding to the data; a detection circuit connected to the first and second data lines, latching data from the outside and applying a voltage corresponding to the latched data to the first data line, or detecting data based on the voltage of the second data line; and a control unit that controls the first control line and the second control line; and When writing or reading data, the control unit activates the second control line, and the detection circuit detects the first data based on the voltage of the second data line; The control unit selectively executes any one of the following modes: In a first mode, after detecting the first data, the control unit activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor. Furthermore, after receiving a write command instructing writing, the detection circuit transmits the second data to the gate of the third transistor while latching the second data from the outside. and In the second mode, after detecting the first data, the detection circuit outputs the first data to the outside or latches the second data from the outside, and when the control unit activates the first control line, the detection circuit transmits the first or second data to the gate of the third transistor. 6 . The semiconductor memory device according to claim 5 , wherein the control unit selects the first mode or the second mode based on a mode selection signal for selecting the first mode or the second mode.

7. The semiconductor memory device according to claim 6, wherein the second mode includes at least one of the following modes: In a first sub-mode, the control unit activates the first control line at a timing when the detection circuit outputs the first data to the outside or latches the second data from the outside; and In the second sub-mode, after the detection circuit outputs the first data to the outside or latches the second data from the outside, the control unit activates the first control line at the timing of issuing a precharge command to set the first data line to a predetermined voltage. 8 . The semiconductor memory device according to claim 7 , wherein the control section selects the first sub-mode or the second sub-mode based on a mode selection signal for selecting the first sub-mode or the second sub-mode. 9 . The semiconductor memory device according to claim 1 , wherein the control unit activates the second control line while the control unit activates the first control line.

10. The semiconductor memory device according to claim 1 or 5, further comprising a source line connected to the other end of the third transistor, and The control unit changes the voltage of the source line while activating the first control line.

11. A semiconductor memory device comprising: The first data line and the first control line are used for writing data; A second data line and a second control line for reading data; A plurality of memory cells, comprising: a first transistor having a gate connected to the first control line and one end connected to the first data line; a second transistor having a gate connected to the second control line and one end connected to the second data line; and a third transistor having a gate connected to the other end of the first transistor to hold data from the first data line, one end connected to the other end of the second transistor and having a conductive state corresponding to the data; a detection circuit connected to the first and second data lines, latching data from the outside and applying a voltage corresponding to the latched data to the first data line, or detecting data based on the voltage of the second data line; and a control unit that controls the first control line and the second control line; and When writing or reading data, the control unit activates the second control line, and the detection circuit detects the first data based on the voltage of the second data line; When receiving a read command instructing reading, the control unit does not activate the first control line but causes the detection circuit to output the first data to the outside; When receiving a write command instructing writing, the detection circuit latches the second data from the outside, and when the control unit activates the first control line, the detection circuit transmits the second data to the gate of the third transistor.

12. The semiconductor memory device according to claim 11, wherein the plurality of memory cells are arranged in a plurality of rows and a plurality of columns, The plurality of first control lines and the plurality of second control lines are provided corresponding to each of the plurality of rows. The plurality of first data lines, the plurality of second data lines and the plurality of detection circuits are arranged corresponding to each of the plurality of columns. When writing or reading data, the second control line corresponding to the selected row selected from the plurality of rows is activated, and the plurality of detection circuits corresponding to the plurality of columns detect the first data based on the voltages of the plurality of second data lines corresponding to the respective ones. When receiving the write instruction, the multiple detection circuits latch the second data from the outside, and when the control unit activates the first control line corresponding to the selected row, the multiple detection circuits transmit the second data to the gates of the third transistors of the multiple storage cells corresponding to the selected row and the multiple columns.

13. The semiconductor memory device according to claim 12, wherein, when receiving the write command, after transmitting the second data and after the control unit inactivates the first control line corresponding to the selected row, the detection circuit performs precharging to set the first data line to a specified voltage.

14. The semiconductor memory device according to claim 13, wherein when a precharge command instructing precharging is issued instead of the write command and the read command, the control unit activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor.

15. The semiconductor memory device according to claim 11 or 12, comprising at least one of the following modes: In a first sub-mode, the control unit activates the first control line at a timing when the detection circuit outputs the first data to the outside or latches the second data from the outside; and In the second sub-mode, after the detection circuit outputs the first data to the outside or latches the second data from the outside, the control unit activates the first control line at the timing of issuing a precharge command to set the first data line to a predetermined voltage. 16 . The semiconductor memory device according to claim 15 , wherein the control section selects the first sub-mode or the second sub-mode based on a mode selection signal for selecting the first sub-mode or the second sub-mode.

17. A semiconductor storage device according to claim 11, wherein the control unit activates the first control line at any timing between the timing when the detection circuit outputs the first data to the outside or latches the second data from the outside and the timing when a precharge instruction is issued to set the first data line to a specified voltage. 18 . The semiconductor memory device according to claim 11 , wherein the control unit activates the second control line while the control unit activates the first control line.

19. The semiconductor memory device according to claim 11, further comprising: a source line connected to the other end of the third transistor, and The control unit changes the voltage of the source line while activating the first control line.

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