Memory device and operating method thereof

Abstract

In certain aspects, a memory device includes a memory cell and a peripheral circuit coupled to the memory cell. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first word line and the second word line. The peripheral circuit is configured to: program the target memory cell; executing first sample reading on the first storage unit to obtain a first sample value of the first storage unit; configuring one or more verification parameters of the target storage unit based on the first sample value; executing second sample reading on the second storage unit to obtain a second sample value of the second storage unit; and configuring one or more read parameters of the target memory cell based on the second sample value.

Description

Background Art

[0001] The present disclosure relates to a storage device and an operating method thereof.

[0002] Non-volatile storage devices, such as solid-state drives (SSDs), non-volatile memory express (NVMe), embedded multimedia cards (eMMCs), and universal flash storage (UFS) devices, have gained widespread popularity in recent years due to their numerous advantages over traditional hard disk drives (HDDs), such as faster read and write speeds, durability and reliability, lower power consumption, silent operation, and smaller form factors. For example, non-volatile storage devices such as SSDs can use NAND flash memory for non-volatile storage. NAND flash memory can perform various operations such as reading, programming (writing), and erasing. For NAND flash memory, erase operations can be performed at the block level, and program operations or read operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a method for operating a memory device including a memory cell is disclosed. The method includes programming a target memory cell coupled to a select word line. The method includes performing a first sample read on a first memory cell coupled to a first word line adjacent to the select word line to obtain a first sample value of the first memory cell; the method includes configuring one or more verification parameters of the target memory cell based on the first sample value. The method also includes performing a second sample read on a second memory cell coupled to a second word line adjacent to the select word line to obtain a second sample value of the second memory cell. The method also includes configuring one or more read parameters of the target memory cell based on the second sample value.

[0004] In some embodiments, the first word line includes a word line WL(n-1), the selection word line includes a word line WL(n), and the second word line includes a word line WL(n+1), where n is an integer of n≥1.

[0005] In some implementations, the first sample read is associated with a first set of threshold voltage (Vth) ranges, and the second sample read is associated with a second set of Vth ranges.

[0006] In some embodiments, the one or more verification parameters include at least one of: a set of verification voltages, a first set of sense node (SO) development times, a first set of pass voltages, or a first set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

[0007] In some embodiments, configuring the one or more verification parameters of the target memory cell based on the first sample value includes: determining a first verification voltage for the target memory cell based on a target program state of the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determining a second verification voltage for the target memory cell based on the target program state of the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and a first offset of the first verification voltage from a default verification voltage associated with the target program state is greater than a second offset of the second verification voltage from the default verification voltage.

[0008] In some embodiments, configuring the one or more verification parameters of the target memory cell based on the first sample value further comprises: determining a first SO development time for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determining a second SO development time for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and the first SO development time is greater than the second SO development time.

[0009] In some embodiments, configuring the one or more verification parameters of the target memory cell based on the first sample value further comprises: determining a first pass voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determining a second pass voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and the first pass voltage is greater than the second pass voltage.

[0010] In some embodiments, configuring the one or more verification parameters of the target memory cell based on the first sample value further includes: determining a first bias level voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determining a second bias level voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges. A first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and the first bias level voltage is greater than the second bias level voltage.

[0011] In some embodiments, the one or more read parameters include at least one of: a set of read voltages, a second set of SO development times, a second set of pass voltages, or a second set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

[0012] In some embodiments, configuring the one or more read parameters of the target memory cell based on the second sample value includes: determining a first subset of read voltages for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a second subset of read voltages for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges. A third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range. For each read voltage in the first subset of read voltages, a shift of the read voltage relative to a corresponding default read voltage is less than a shift of a corresponding one of the read voltages in the second subset of read voltages relative to the corresponding default read voltage.

[0013] In some embodiments, configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third SO development time for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth SO development time for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third SO development time is less than the fourth SO development time.

[0014] In some embodiments, configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third pass voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth pass voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third pass voltage is less than the fourth pass voltage.

[0015] In some embodiments, configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third bias level voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth bias level voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third bias level voltage is less than the fourth bias level voltage.

[0016] In some embodiments, the storage device includes a NAND flash memory device.

[0017] In some implementations, the target memory cell, the first memory cell, and the second memory cell are coupled to a same bit line of the memory device.

[0018] In another aspect, a memory device includes memory cells and peripheral circuitry coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuitry is configured to: program the target memory cell; perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell; configure one or more verification parameters of the target memory cell based on the first sample value; perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell; and configure one or more read parameters of the target memory cell based on the second sample value.

[0019] In some embodiments, the first word line includes word line WL(n-1), the third word line includes word line WL(n), and the second word line includes word line WL(n+1), where n is an integer of n≥1.

[0020] In some implementations, the first sample read is associated with a first set of Vth ranges, and the second sample read is associated with a second set of Vth ranges.

[0021] In some embodiments, the one or more verification parameters include at least one of: a set of verification voltages, a first set of SO development times, a first set of pass voltages, or a first set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

[0022] In some embodiments, to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determine a first verification voltage for the target memory cell based on a target program state of the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determine a second verification voltage for the target memory cell based on the target program state of the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges. A first Vth value in the first Vth range is less than a second Vth value in the second Vth range. A first offset of the first verification voltage relative to a default verification voltage associated with the target program state is greater than a second offset of the second verification voltage relative to the default verification voltage.

[0023] In some embodiments, to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determine a first SO development time for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determine a second SO development time for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is smaller than a second Vth value in the second Vth range, and the first SO development time is greater than the second SO development time.

[0024] In some embodiments, to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determine a first pass voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determine a second pass voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and the first pass voltage is greater than the second pass voltage.

[0025] In some embodiments, to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determine a first bias level voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determine a second bias level voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges. A first Vth value in the first Vth range is smaller than a second Vth value in the second Vth range, and the first bias level voltage is greater than the second bias level voltage.

[0026] In some embodiments, the one or more read parameters include at least one of: a set of read voltages, a second set of SO development times, a second set of pass voltages, or a second set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

[0027] In some embodiments, to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determine a first subset of read voltages for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determine a second subset of read voltages for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges. A third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range. For each read voltage in the first subset of read voltages, an offset of the read voltage relative to a corresponding default read voltage is less than an offset of a corresponding one of the read voltages in the second subset of read voltages relative to the corresponding default read voltage.

[0028] In some embodiments, to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determine a third SO development time for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determine a fourth SO development time for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third SO development time is less than the fourth SO development time.

[0029] In some embodiments, to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determine a third pass voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determine a fourth pass voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third pass voltage is less than the fourth pass voltage.

[0030] In some embodiments, to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determine a third bias level voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determine a fourth bias level voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is less than a fourth Vth value in the fourth Vth range, and the third bias level voltage is less than the fourth bias level voltage.

[0031] In some embodiments, the storage device includes a NAND flash memory device.

[0032] In some implementations, the target memory cell, the first memory cell, and the second memory cell are coupled to a same bit line of the memory device.

[0033] In another aspect, a system includes a memory device configured to store data, and a memory controller coupled to the memory device and configured to control operations of the memory device. The memory device includes memory cells and peripheral circuitry coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuitry is configured to: program the target memory cell; perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell; configure one or more verification parameters of the target memory cell based on the first sample value; perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell; and configure one or more read parameters of the target memory cell based on the second sample value. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate several aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0035] Figure 1 A block diagram of a system having a storage device according to some aspects of the present disclosure is shown.

[0036] Figure 2A A diagram illustrating a memory card having storage devices according to some aspects of the present disclosure is shown.

[0037] Figure 2B A diagram of a solid-state drive (SSD) having a storage device is shown, according to some aspects of the present disclosure.

[0038] Figure 3 A block diagram of a memory controller according to some aspects of the present disclosure is shown.

[0039] Figure 4 A schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0040] Figure 5A A block diagram of a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0041] Figure 5B Vth distribution of memory cells in a programming operation according to some aspects of the present disclosure is shown.

[0042] Figures 6A-6C A read operation on a target memory cell according to some examples is shown.

[0043] Figure 7A A process for performing multiple rounds of programming operations in a memory device according to some examples is shown.

[0044] Figure 7B-7C Waveforms of word line voltages applied to selected word lines in a coarse programming round according to some examples of the present disclosure are shown.

[0045] Figure 7D-7E Waveforms of word line voltages applied to selected word lines in a fine programming round according to some examples of the present disclosure are shown.

[0046] Figure 8 A flowchart of a method for operating a storage device according to some aspects of the present disclosure is shown.

[0047] Figures 9A-9G An example implementation of an assisted authentication scheme according to some aspects of the present disclosure is shown.

[0048] Figures 10A-10G An example implementation of an assisted read scheme according to aspects of the present disclosure is shown.

[0049] Figure 11A and Figure 11B A page buffer circuit according to some aspects of the present disclosure is shown.

[0050] Figure 12A Shown is a change in Vth distribution of memory cells after data retention according to some examples.

[0051] Figure 12B Shown is a change in Vth distribution of memory cells after data retention when an auxiliary verification scheme is applied, according to some aspects of the present disclosure.

[0052] Figure 12C Shown is a change in Vth distribution of memory cells when an assist read scheme is applied, according to some aspects of the present disclosure.

[0053] Figure 12D Shown is a change in Vth distribution of memory cells when a combination of an assisted verification scheme and an assisted read scheme is applied according to some aspects of the present disclosure.

[0054] Figure 13 According to some aspects of the present disclosure, an application Figures 9A-9G Auxiliary verification scheme and Figures 10A-10G An example box of a storage unit with an assisted read scheme.

[0055] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0056] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the present disclosure may be used in a variety of other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with each other in ways not specifically described in the accompanying drawings, so that such combinations, adjustments, and modifications are within the scope of this disclosure.

[0057] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey the singular or to convey the plural, depending at least in part on the context. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can, depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0058] Memory cells in a non-volatile (NV) memory device (e.g., a NAND flash memory device) can be programmed to corresponding target programming states at the page / word line level. After retention, lateral charge migration may occur in the memory cells due to the Vth difference between memory cells on adjacent word lines. Lateral charge migration may cause severe margin loss in the Vth distribution of the memory cells. Taking the memory cells on a specific word line as an example, the different programming states of adjacent memory cells on adjacent word lines may affect the margin loss of the memory cells on the specific word line after retention. Consistent with the scope of the present disclosure, for a specific memory cell coupled to a specific word line, the adjacent memory cell may be a first memory cell that is (a) coupled to the same bit line as the specific memory cell and also (b) coupled to a first word line adjacent to the specific word line. Alternatively, the adjacent memory cell may be a second memory cell that is (a) coupled to the same bit line as the specific memory cell and also (b) coupled to a second word line adjacent to the specific word line. The specific word line is located between the first word line and the second word line.

[0059] For example, a NAND flash memory device may include a quad-level cell (QLC) having an erased state (P0) or any one of programmed states P1-P15. Assume that a memory cell X on a word line WL(n) n can be programmed to a specific target program state Pt (for example, Pt can be any one of P0-P15, and n can be a positive integer). Memory cell X on word line WL(n) n , the first adjacent memory cell X on the adjacent word line WL(n-1) n-1 , and the second adjacent memory cell X on the adjacent word line WL(n+1)n+1 can be coupled to the same bit line. If the memory cell X n has a low programmed state, for example, P1, while the first and second adjacent memory cells X n-1 and X n+1 With a high programming state, such as P15, the memory cell X n There can be a charge gain due to lateral charge migration after retention. However, if the memory cell X n has a high programming state, such as P15, and the first and second adjacent memory cells X n-1 and X n+1 With a low programming state, for example P1, the memory cell X n There may be charge loss due to lateral charge migration. In either case, the memory cell X n The threshold voltage (Vth) can be changed after holding.

[0060] In another example, reference Figure 12A The memory device may be a NAND flash memory device including a QLC having an erased state (P0) or any one of the programming states P1-P15. First, for memory cells having a specific target programming state, if their neighboring memory cells have a low threshold voltage (Vth) corresponding to a low programming state (e.g., P0-P7), the first Vth distribution of the memory cells may be illustrated using curve 1204, as shown in FIG. Figure 12A If the adjacent memory cell has a high Vth corresponding to a high programmed state (e.g., P8-P15), the second Vth distribution of the memory cell can be illustrated using curve 1206, as shown in FIG. Figure 12A As shown in part (a) of FIG. 1204 and FIG. 1206 are consistent with each other, indicating that the first Vth distribution of the memory cell is the same as the second Vth distribution. Charge migration has not yet occurred, and the different programming states of adjacent memory cells have not yet affected the margin loss of the memory cell. The third Vth distribution of the memory cell is the sum of the first and second distributions, which can be illustrated using curve 1202, as shown in FIG. Figure 12A shown in part (a).

[0061] After holding, curves 1202, 1204, and 1206 are shifted and changed to curves 1208, 1210, and 1212, respectively. Figure 12A As shown in part (b) of FIG. 1208, 1210 and 1212 are wider than curves 1202, 1204 and 1206 respectively due to lateral charge migration. Figure 12A Compared with part (a), Figure 12APart (b) shows that each of the first, second, and third Vth distributions of the memory cell is shifted and widened. The first Vth distribution is inconsistent with the second Vth distribution (for example, the first Vth distribution only partially overlaps with the second Vth distribution and is located to the left of the second Vth distribution). In addition, the first, second, and third Vth distributions become wider. As a result, the Vth distribution of the memory cell suffers from margin loss.

[0062] To address one or more of the above-mentioned issues, the present disclosure introduces a margin improvement scheme to enhance the margin of the Vth distribution of memory cells after retention, thereby improving the performance of NAND flash memory devices. The margin improvement scheme may include an auxiliary verification scheme for program operations, an auxiliary read scheme for read operations, or a combination of the auxiliary verification scheme and the auxiliary read scheme.

[0063] Specifically, a programming operation may include cycles of applying programming / verification pulses, and each cycle may include (a) a programming phase in which programming pulses are applied to a selected word line (e.g., word line WL(n)) and (b) a verification phase in which one or more verification pulses are applied to the selected word line. During the programming phase, programming pulses may be applied to a target memory cell coupled to at least the selected word line. During the verification phase, an auxiliary verification scheme may be applied to a first adjacent word line (e.g., word line WL(n-1) or WL(n+1)) and configured to determine one or more verification parameters to be applied in the verification phase of the target memory cell on the selected word line. Margin loss caused by lateral charge migration caused by different programming states of the memory cells on the first adjacent word line may then be recovered. Additionally or alternatively, during a read operation on the target memory cell, an auxiliary read scheme may be applied to a second adjacent word line (e.g., word line WL(n+1) or WL(n-1)) and configured to determine one or more read parameters to be applied in the read operation. Then, the margin loss caused by lateral charge migration due to the different programming states of the memory cells on the second adjacent word line can be recovered. In some embodiments, the first adjacent word line can be word line WL(n-1), and the second adjacent word line can be word line WL(n+1). In this case, the margin loss caused by word line coupling can also be recovered.

[0064] Therefore, by applying the auxiliary verification scheme and the auxiliary read scheme disclosed herein, the margin of the Vth distribution can be improved after the maintenance because the margin loss caused by lateral charge migration can be recovered. The margin improvement of the auxiliary verification scheme and the margin improvement of the auxiliary read scheme can be combined to enhance the performance of the NAND flash memory device.

[0065] Figure 1FIG1 shows a block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102 having one or more storage devices 104 and a memory controller 106. Host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 may be configured to send data to or receive data (also referred to as user data or host data) from memory system 102. Memory system 102 may be a storage product, such as an SSD, that integrates memory controller 106 and one or more storage devices 104.

[0066] The storage device 104 may be any storage device disclosed in this disclosure, including a non-volatile storage device, such as a NAND flash memory device. In some embodiments, the storage device 104 further includes one or more volatile storage devices, such as a DRAM device or a static random-access memory (SRAM) device.

[0067] According to some embodiments, memory controller 106 is operably coupled to storage device 104 and host 108 and is configured to control storage device 104. Memory controller 106 can manage data stored in storage device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices, such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 106 is designed to operate in high-duty-cycle environments, such as with SSDs or embedded Multimedia Cards (eMMC) for data storage in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 106 can be configured to control operations of storage device 104, such as read, program / write, and / or erase operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical (L2P) address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes (ECC) for data read from or written to the storage device 104. Any other suitable functions may also be performed by the memory controller 106, such as formatting the storage device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a high-speed non-volatile memory express (NVMe) protocol, an NVMe-oF protocol, a high-speed PCI (PCI-express, PCI-E) protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0068] The memory controller 106 and the one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2A In one example shown, the memory controller 106 and the single storage device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the memory card. Figure 2B In another example shown, the memory controller 106 and the plurality of storage devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 11 and 2. In some embodiments, the memory system 102 is implemented as an SSD 206 that includes a non-volatile storage device and a volatile storage device as the storage device 104, such as an enterprise SSD.

[0069] Figure 3 1 shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 may be Figure 1 An example of a memory controller 106 in FIG. Figure 3 As shown, the memory controller 300 may include a processor 308, an accelerator 307 (e.g., a hardware accelerator), a cache 310, and a read-only memory (ROM) 311. In some embodiments, the processor 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or a microcontroller (also known as a microcontroller unit (MCU)), which executes firmware and / or software modules to perform the various functions described herein. The various firmware modules in the memory controller 300 described herein can be implemented as firmware code or instructions stored in ROM 311 and executed by the processor 308. In some embodiments, the processor 308 includes one or more hardware circuits, such as fixed logic units, such as logic gates, multiplexers, flip-flops, state machines, field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs). For example, the hardware circuits may include dedicated circuits that perform given logic functions known at the time of device manufacture, such as application-specific integrated circuits (ASICs).

[0070] like Figure 3As shown, the memory controller 300 may also include various input / output (I / O) interfaces (I / Fs), such as a non-volatile memory interface 312, a DRAM interface 314, and a host interface 316, which are operatively coupled to the non-volatile memory device 302 (e.g., a flash memory), the DRAM 304 (e.g., an example of a volatile memory device), and the host 306 (e.g., an example of the host 108), respectively. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 may be configured to transmit data, commands, clocks, or any suitable signals between the processor 308 and the non-volatile memory device 302, the DRAM 304, and the host 306, respectively. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 may implement any suitable communication protocol that facilitates data transmission, communication, and management, such as the NVMe protocol, the PCI-E protocol, and the Double Data Rate (DDR) protocol, to name a few.

[0071] As described above, cache 310 and DRAM 304 can both be considered as volatile storage devices that can be controlled and accessed by the memory controller 300 in the memory system. In some embodiments, cache can be implemented as part of the volatile storage device, for example, by SRAM and / or DRAM 304. It should be understood that although Figure 3 Cache 310 is shown within memory controller 300 and DRAM 304 is shown external to memory controller 300 , but in some examples, both cache 310 and DRAM 304 may be within or external to memory controller 300 .

[0072] Figure 4 Schematic diagram of a memory device 400 including peripheral circuitry 402 according to some aspects of the present disclosure is shown. The memory device 400 may be Figure 1 4. An example of a memory device 104 in FIG. Memory device 400 may include a memory cell array 401 and a peripheral circuit 402 coupled to memory cell array 401. Memory cell array 401 may be a NAND flash memory cell array in which memory cells 406 are provided in the form of an array of NAND memory strings 408, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell having a floating gate transistor or a charge trap type memory cell having a charge trap transistor.

[0073] In some embodiments, each memory cell 406 is a single-level cell (SLC), which can have two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 406 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as TLC), or four bits per cell (also known as QLC). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​into the cell. The fourth nominal storage value can be used for an erased state.

[0074] like Figure 4 As shown, each NAND memory string 408 may also include a source select gate (SSG) transistor 410 at its source terminal and a drain select gate (DSG) transistor 412 at its drain terminal. The SSG transistor 410 and the DSG transistor 412 may be configured to activate the selection of the NAND memory string 408 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a DSG select voltage or a DSG deselect voltage to the gate of a corresponding DSG transistor 412 via one or more DSG lines 413 and / or applying an SSG select voltage or an SSG deselect voltage to the gate of a corresponding SSG transistor 410 via one or more SSG lines 415.

[0075] like Figure 4As shown, the NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414, for example, coupled to an ACS. In some embodiments, each block 404 is a basic data unit for an erase operation, that is, all memory cells 406 on the same block 404 are erased at the same time. In order to erase the memory cells 406 in the selected block 404, the source lines 414 coupled to the selected block 404 and the unselected blocks 404 in the same plane as the selected block 404 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 is affected by the read and program operations. Each word line 418 can include multiple control gates (gate electrodes) at each memory cell 406 coupled to the word line 418 and a gate line coupling the control gates. Reference Figure 4 , showing a plurality of word lines WL(0), WL(1), WL(2), ..., WL(n-1), WL(n), WL(n+1) and WL(n+2), where n is a positive integer.

[0076] The peripheral circuit 402 may be coupled to the memory cell array 401 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for applying and sensing voltage signals and / or current signals to each target memory cell 406 and from each target memory cell 306 via the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413 to facilitate operation of the memory cell array 401. The peripheral circuit 402 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology. For example, Figure 5A Some peripheral circuits 601 are shown, including page buffers / sense amplifiers 504, column decoders / bit line drivers 506, row decoders / word line drivers 508, voltage generators 510, control logic 512, registers 514, interfaces 516, and data buses 518. It should be understood that in some examples, Figure 5A Additional peripheral circuits not shown.

[0077] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of programming data (write data) to be programmed into a page of the memory cell array 401. In another example, the page buffer / sense amplifier 504 can verify the programmed target memory cell 406 in each program / verify cycle (cycle) in a programming operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 416 representing a data bit stored in the memory cell 406 and amplify the small voltage swing to a recognizable logic level in a read operation. During a programming operation, the page buffer / sense amplifier 504 may include a storage module (e.g., a latch, a cache, a register, etc.) for temporarily storing a set of N-bit data received from the data bus 518 (e.g., in the form of Gray code) and providing the set of N-bit data to the corresponding target memory cell 406 through the corresponding bit line 416 in each programming round of multiple programming operations.

[0078] The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and to select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 510. The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and to select / deselect a block 404 of the memory cell array 401 and select / deselect a word line 418 of the block 404. The row decoder / word line driver 508 can also be configured to drive the word line 418 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the SSG line 415 and the DSG line 413. The voltage generator 510 can be configured to be controlled by the control logic 512 and to generate word line voltages (e.g., read voltage, program voltage, pass-through voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 401.

[0079] The control logic 512 may be coupled to each of the above-mentioned peripheral circuits and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to control the operation of the peripheral circuit from the host (e.g., Figure 1The interface 516 receives control commands from the control logic 512 and status information from the host computer 108 for buffering and relaying. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data input / output (I / O) interface and data buffer to buffer and relay data entering and exiting the memory cell array 401.

[0080] Figure 5B 4 shows the Vth distribution of memory cells in a programming operation according to some aspects of the present disclosure. As described above, each memory cell 406 can be configured to N A set of N bits of data is stored in one of the 2 levels, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level may correspond to 2 bits of memory cell 406. N One of the Vth ranges. Considering multiple rounds of programming operations, where the memory cell 406 may first be programmed to an intermediate level in a coarse programming round, the "level" referred to herein may be considered to be the final level after the fine programming round of the multiple rounds of programming operations, as opposed to the intermediate level. Taking QLC as an example, where N=4, as Figure 4 As shown, the memory cell 406 can be programmed to one of 16 levels, including one level of the erased state (P0) and 15 levels of programmed states (programmed states P1-P15). Each level can correspond to a corresponding Vth range of the memory cell 406. For example, the level corresponding to the lowest threshold voltage range ( Figure 5B The leftmost threshold voltage distribution in the distribution) can be regarded as level 0, and the level corresponding to the second lowest threshold voltage range ( Figure 5B The second threshold voltage distribution from the left in the distribution) can be considered as level 1, and so on, up to the level corresponding to the highest threshold voltage range ( Figure 5B rightmost threshold voltage distribution in ).

[0081] Figures 6A-6C The read operation of the target memory cell according to some examples is shown. Figures 6A-6C . refer to Figure 6A , shows a block 600 of memory cells (e.g., block 404) including a memory string 602 (e.g., NAND memory string 408). As an example, referring to Figures 6A-6C The process of reading data stored in the target memory cell 603 in the memory string 602 is shown. The target memory cell 603 can be coupled to the select word line WL(n) and the bit line 605. The bit line 605 can be coupled to the sense node (SO) of the corresponding page buffer circuit in the page buffer 504. Figure 11A or Figure 11BAn example implementation of a page buffer circuit is shown.

[0082] To sense the state of the target memory cell 603, a DSG select voltage (e.g., Von) can be applied to the gate of the DSG transistor 612 via the DSG line 613, and an SSG select voltage (e.g., Von) can be applied to the gate of the SSG transistor 610 via the SSG line 615. The word line WL(n) can be selected by applying a read voltage Vread to the word line WL(n). Other word lines (e.g., WL(n-1), WL(n+1), etc.) can be deselected by applying a pass voltage Vpass to the other word lines to ensure that the other memory cells on the memory string 602 are turned on (e.g., in the "ON" state). Figure 6B As shown, the SO node of the corresponding page buffer circuit can be precharged. The bit line 605 can also be precharged based on a bias level voltage. For example, the bias level voltage can be used to bias the voltage of the bit line 605. The SO node can be discharged at a discharge rate based on the state of the target memory cell 603. When the SO development time "t" elapses, the voltage of the SO node can be compared with a reference voltage "Vtrip" to determine the state of the target memory cell 603. For example, when the voltage of the SO node is greater than the reference voltage Vtrip at the SO development time "t", the target memory cell 603 is determined to be in the "OFF" state, indicating that the Vth of the target memory cell 603 is greater than the read voltage Vread. When the voltage of the SO node is less than the reference voltage Vtrip at the SO development time "t", the target memory cell 603 is determined to be in the "ON" state, indicating that the Vth of the target memory cell 603 is less than the read voltage Vread. Consistent with some aspects of the present disclosure, the SO development time can include a time window for the discharge of the SO node.

[0083] Figure 7A 1 shows a process 700 for performing multiple rounds of programming operations in a memory device according to some examples. The process 700 may be performed by peripheral circuits of the memory device (e.g., Figure 4 The peripheral circuit 402 of FIG. 4 is executed. Multiple rounds of programming operations may be performed for multiple word lines (e.g., WL(n-1), WL(n), WL(n+1)). Taking xLC (e.g., TLC, QLC, etc.) as an example, a coarse programming round and a fine programming round may be performed for each word line. For example, a coarse programming round 702 associated with word line WL(n) may be performed. Prior to the coarse programming round 702, a coarse programming round associated with word line WL(n-1) may be performed. Figure 7AAfter the coarse programming pass 702, a fine programming pass 704 associated with word line WL(n-1) may be performed. Subsequently, a coarse programming pass 706 associated with word line WL(n+1), a fine programming pass 708 associated with word line WL(n), a coarse programming pass 710 associated with word line WL(n+2), a fine programming pass 712 associated with word line WL(n+1), and so on may be sequentially performed.

[0084] Figure 7B-7C The waveforms of word line voltages applied to selected word lines in a coarse programming round according to some examples of the present disclosure are shown. For xLC, a multi-round programming operation may involve a coarse programming round for programming the xLC to a corresponding level among intermediate levels, and a fine programming round for programming the xLC from the intermediate level to a final level.

[0085] like Figure 7B As shown, the multi-round programming operation includes at least a coarse programming round 722. The coarse programming round 722 includes one or more program / verify loops (or program / verify cycles). In each program / verify loop, a program voltage is applied to a selected word line during a programming phase, followed by a plurality of verification voltages with incremental changes in voltage levels during a verification phase. For example, Figure 7B-7C 7. An initial program / verify cycle 724 of a coarse programming run 722 is shown in FIG. In the initial program / verify cycle 724, a program voltage (Vpgm_init) is applied to a selected word line, followed by application of a plurality of verify voltages (Vvf_1, Vvf_2, ..., Vvf_i), where i is a positive integer (i ≥ 1). Vvf_1 may indicate the verify voltage for programmed state P1 in the coarse programming run 722. Vvf_2 may indicate the verify voltage for programmed state P2 in the coarse programming run 722. Similarly, Vvf_i may indicate the verify voltage for programmed state Pi in the coarse programming run 722. In some embodiments, incremental step pulse programming (ISPP) may be applied in the coarse programming run 722.

[0086] Figure 7D-7E 7 shows waveforms of word line voltages applied to selected word lines in a fine programming round according to some examples of the present disclosure. In some embodiments, the multi-round programming operation further includes a fine programming round 728. The fine programming round 728 can be performed after the coarse programming round 722. The fine programming round 728 can also include one or more program / verify cycles. In each program / verify cycle, a program voltage is applied to the selected word line in a programming phase, followed by application of multiple verification voltages with incremental changes in voltage levels in a verification phase. For example, Figure 7D-7E7. An initial program / verify cycle 730 of a fine programming run 728 is shown in FIG. In the initial program / verify cycle 730, a program voltage (V'pgm_init) is applied to a selected word line, followed by a plurality of verify voltages (V'vf_1, V'vf_2, ..., V'vf_j), where j is a positive integer (j ≥ 1). V'vf_1 may indicate a verify voltage for program state P1 in the fine programming run 728. V'vf_2 may indicate a verify voltage for program state P2 in the fine programming run 728. V'vf_j may indicate a verify voltage for program state Pj in the fine programming run 728. In some embodiments, ISPP may be applied in the fine programming run 728.

[0087] According to some aspects of the present disclosure, an auxiliary verification scheme for a programming operation, an auxiliary read scheme for a read operation, or a combination of an auxiliary verification scheme and an auxiliary read scheme can be applied in a memory device to improve the margin of the Vth distribution after maintenance. As a result, the performance of the memory device can be improved. Figure 8 Operations 804 and 806 and Figures 9A-9G To provide example implementations of the auxiliary authentication scheme, these example implementations will be described in more detail below. Figure 8 Operations 808 and 810 and Figures 10A-10G Example implementations of the assisted read scheme are provided, which are described in more detail below.

[0088] Figure 8 800 for operating a memory device according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 104, 302, or 400. Method 800 may be implemented by peripheral circuitry 402, such as control logic 512, row decoder / word line driver 508, and page buffer / sense amplifier 504. It should be understood that the operations illustrated in method 800 may not be exhaustive, and other operations may be performed before, after, or between any illustrated operations. Furthermore, some of these operations may be performed simultaneously or in parallel. Figure 8 The execution order is different as shown in .

[0089] Without loss of generality, method 800 is described herein with reference to peripheral circuit 402. Operations 802, 804, and 806 may involve performing a program operation on a target memory cell coupled to at least a selected word line. Operations 808 and 810 may involve performing a read operation on the target memory cell.

[0090] refer to Figure 8Method 800 begins at operation 802, where at least a target memory cell coupled to a selected word line may be programmed. For example, peripheral circuit 402 may apply a program voltage to the selected word line to program at least the target memory cell. The target memory cell may be configured to be programmed to a specific target program state.

[0091] Method 800 proceeds to operation 804, as shown in FIG. Figure 8 As shown, a first sample read can be performed on a first memory cell to obtain a first sample value of the first memory cell. The first memory cell can be coupled to a first word line adjacent to a select word line and can also be coupled to the same bit line as a target memory cell. For example, the first memory cell and the target memory cell are located in the same memory string coupled to the same bit line and are adjacent to each other. In some embodiments, the select word line can be word line WL(n), and the first adjacent word line can be word line WL(n-1) or WL(n+1).

[0092] The peripheral circuit 402 may perform a first sample read on the first memory cell to obtain a first sample value. The first sample read may be associated with a first set of Vth ranges. Specifically, the entire range of all possible Vth distributions of the memory cell may be divided into a first set of Vth ranges. A read operation may be performed on the first memory cell according to the first set of Vth ranges, so that a first sample value of the Vth of the first memory cell may be obtained from the read operation. For example, the first set of Vth ranges may include two Vth ranges. In this case, the first sample read on the first memory cell may be an SLC read on the first memory cell (for example, the first memory cell is regarded as an SLC, regardless of whether the first memory cell is actually an MLC, QLC, or any other type of memory cell). If the Vth of the first memory cell falls into the first of the two Vth ranges, a first sample value "S0" corresponding to the first of the two Vth ranges may be obtained (for example, S0=0). If the Vth of the first memory cell falls into the second of the two Vth ranges, a first sample value "S1" corresponding to the second of the two Vth ranges may be obtained (for example, S1=1). Reference is made below. Figure 9A An example implementation of a first sample read is described.

[0093] In another example, the first set of Vth ranges may include four Vth ranges. In this case, the first sample read of the first memory cell may be an MLC read of the first memory cell (e.g., treating the first memory cell as an MLC, regardless of whether the first memory cell is actually an SLC, QLC, or any other type of memory cell). If the Vth of the first memory cell falls within a first range of the four Vth ranges, a first sample value “00” corresponding to the first range of the four Vth ranges may be obtained. If the Vth of the first memory cell falls within a second range of these Vth ranges, a first sample value “01” corresponding to the second range of these Vth ranges may be obtained. If the Vth of the first memory cell falls within a third range of these Vth ranges, a first sample value “11” corresponding to the third range of these Vth ranges may be obtained. If the Vth of the first memory cell falls within a fourth range of these Vth ranges, a first sample value “10” corresponding to the fourth range of these Vth ranges may be obtained.

[0094] Method 800 proceeds to operation 806, as shown in FIG. Figure 8 As shown, one or more verification parameters of the target memory cell can be configured based on the first sample value of the first memory cell. In the following description of operation 806, it is assumed that the first set of Vth ranges can include at least a first Vth range and a second Vth range. The Vth value in the first Vth range can be smaller than the Vth value in the second Vth range (for example, the first Vth value in the first Vth range is smaller than the second Vth value in the second Vth range).

[0095] In some embodiments, the one or more verification parameters may include a set of verification voltages for target memory cells associated with a target programming state. The peripheral circuit 402 may determine a default verification voltage for the target programming state. For example, Figure 7C or Figure 7E As shown, if the target programming state is P1, the default verification voltage may be the verification voltage Vvf_1 for the coarse programming round (or the verification voltage V'vf_1 for the fine programming round). In another example, if the target programming state is P2, the default verification voltage for the target programming state P2 may be the verification voltage Vvf_2 for the coarse programming round (or the verification voltage V'vf_2 for the fine programming round).

[0096] Specifically, in response to a first sample value of a first memory cell corresponding to a first Vth range from the first set of Vth ranges, the peripheral circuit 402 may determine a first verification voltage for the target memory cell based on a target program state of the target memory cell. Alternatively, in response to a first sample value of a first memory cell corresponding to a second Vth range from the first set of Vth ranges, the peripheral circuit 402 may determine a second verification voltage for the target memory cell based on the target program state of the target memory cell. A first verification offset of the first verification voltage relative to a default verification voltage may be greater than a second verification offset of the second verification voltage relative to the default verification voltage.

[0097] For example, the peripheral circuit 402 may determine a set of verify offsets based on the first sample value, and then determine the set of verify voltages based on the default verify voltage for the target programming state and the set of verify offsets. Each verify voltage may be equal to the sum of the default verify voltage and the corresponding verify offset. For example, if the first sample value corresponds to a first Vth range, the peripheral circuit 402 may determine a first verify offset, and then determine that the first verify voltage is equal to the sum of the first verify offset and the default verify voltage (e.g., first verify voltage = default verify voltage + first verify offset). When the first sample value corresponds to the first Vth range, the first verify voltage may be a first corrected version of the default verify voltage for the target programming state. If the first sample value corresponds to a second Vth range, the peripheral circuit 402 may determine a second verify offset, and then determine that the second verify voltage is equal to the sum of the second verify offset and the default verify voltage (e.g., second verify voltage = default verify voltage + second verify offset). When the first sample value corresponds to the second Vth range, the second verify voltage may be a second corrected version of the default verify voltage for the target programming state. The first verify offset and the second verify offset can have any suitable voltage values, where the first verify offset is greater than the second verify offset (eg, first verify offset > second verify offset).

[0098] Next, the peripheral circuit 402 can verify the programming of the target memory cell based on the set of verification voltages and the first sample value of the first memory cell. For example, if the first sample value corresponds to a first Vth range, the peripheral circuit 402 can apply the first verification voltage to verify the programming of the target memory cell (e.g., to determine whether the Vth of the target memory cell has reached the first verification voltage). In response to the Vth of the target memory cell reaching the first verification voltage, it is determined that the target memory cell is programmed to the target programming state. Alternatively, if the first sample value corresponds to a second Vth range, the peripheral circuit 402 can apply the second verification voltage to verify the programming of the target memory cell (e.g., to determine whether the Vth of the target memory cell has reached the second verification voltage). In response to the Vth of the target memory cell reaching the second verification voltage, it is determined that the target memory cell is programmed to the target programming state.

[0099] In some examples, as long as the first verification offset is greater than the second verification offset, the first verification voltage and the second verification voltage may be greater than, equal to, or less than the default verification voltage, without limitation. Since the first verification offset is greater than the second verification offset, the Vth of the target memory cell verified by the first verification voltage may be right-shifted compared to the Vth of the target memory cell verified by the second verification voltage. If the first verification voltage and the second verification voltage are greater than the default verification voltage, (1) the Vth of the target memory cell verified by the first verification voltage and (2) the Vth of the target memory cell verified by the second verification voltage may be right-shifted compared to the Vth of the target memory cell verified by the default verification voltage.

[0100] In some embodiments, the one or more verification parameters may include a first set of SO development times. Specifically, the peripheral circuit 402 may determine a default SO development time for a target program state. In response to a first sample value corresponding to a first Vth range, the peripheral circuit 402 may determine a first SO development time for the target memory cell. Alternatively, in response to a first sample value corresponding to a second Vth range, the peripheral circuit 402 may determine a second SO development time for the target memory cell. The first SO development time may be greater than the second SO development time.

[0101] Next, the peripheral circuit 402 may verify programming of the target memory cell based on the first set of SO development times and the first sample value of the first memory cell. For example, if the first sample value corresponds to a first Vth range, the peripheral circuit 402 may apply the first SO development time instead of the default development time when verifying programming of the target memory cell. Alternatively, if the first sample value corresponds to a second Vth range, the peripheral circuit 402 may apply the second SO development time instead of the default development time when verifying programming of the target memory cell.

[0102] In some examples, as long as the first SO development time is greater than the second SO development time, the first SO development time and the second SO development time may be greater than, equal to, or less than the default SO development time, without limitation. Because the first SO development time is greater than the second SO development time, the Vth of the target memory cell when the first SO development time is applied may be right-shifted compared to the Vth of the target memory cell when the second SO development time is applied. If the first SO development time and the second SO development time are greater than the default SO development time, (1) the Vth of the target memory cell when the first SO development time is applied and (2) the Vth of the target memory cell when the second SO development time is applied may be right-shifted compared to the Vth of the target memory cell when the default SO development time is applied.

[0103] In some embodiments, the one or more verification parameters may include a first set of pass voltages. Specifically, the peripheral circuit 402 may determine a default pass voltage for the target programming state. In response to a first sample value corresponding to a first Vth range, the peripheral circuit 402 may determine a first pass voltage to be applied to one or more unselected word lines. Alternatively, in response to a first sample value corresponding to a second Vth range, the peripheral circuit 402 may determine a second pass voltage to be applied to one or more unselected word lines. The first pass voltage may be greater than the second pass voltage.

[0104] Next, the peripheral circuit 402 may verify programming of the target memory cell based on the first set of pass voltages and the first sample value of the first memory cell. For example, if the first sample value corresponds to a first Vth range, the peripheral circuit 402 may apply the first pass voltage to one or more unselected word lines when verifying programming of the target memory cell. For example, the first pass voltage may replace the default pass voltage and be applied to one or more unselected word lines, such as word line WL(n-1) or word line WL(n+1), while the default pass voltage may still be applied to any remaining unselected word lines. Alternatively, if the first sample value corresponds to a second Vth range, the peripheral circuit 402 may apply a second pass voltage to one or more unselected word lines when verifying programming of the target memory cell. For example, the second pass voltage may replace the default pass voltage and be applied to one or more unselected word lines, such as word line WL(n-1) or word line WL(n+1), while the default pass voltage may still be applied to any remaining unselected word lines.

[0105] In some examples, as long as the first pass voltage is greater than the second pass voltage, the first pass voltage and the second pass voltage may be greater than, equal to, or less than the default pass voltage, without limitation. Because the first pass voltage is greater than the second pass voltage, the Vth of the target memory cell when the first pass voltage is applied may be shifted to the right compared to the Vth of the target memory cell when the second pass voltage is applied. If the first pass voltage and the second pass voltage are greater than the default pass voltage, then (1) the Vth of the target memory cell when the first pass voltage is applied and (2) the Vth of the target memory cell when the second pass voltage is applied may be shifted to the right compared to the Vth of the target memory cell when the default pass voltage is applied.

[0106] In some embodiments, the one or more verification parameters may include a first set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell. Specifically, the peripheral circuit 402 may determine a default bias level voltage for a target program state. In response to a first sample value corresponding to a first Vth range, the peripheral circuit 402 may determine a first bias level voltage for the target memory cell. Alternatively, in response to a first sample value corresponding to a second Vth range, the peripheral circuit 402 may determine a second bias level voltage for the target memory cell. The first bias level voltage may be greater than the second bias level voltage.

[0107] Next, the peripheral circuit 402 may verify programming of the target memory cell based on the first set of bias level voltages and the first sample value of the first memory cell. For example, if the first sample value corresponds to a first Vth range, the peripheral circuit 402 may apply the first bias level voltage to the bit line coupled to the target memory cell when verifying programming of the target memory cell. Alternatively, if the first sample value corresponds to a second Vth range, the peripheral circuit 402 may apply the second bias level voltage to the bit line coupled to the target memory cell when verifying programming of the target memory cell.

[0108] In some examples, as long as the first bias level voltage is greater than the second bias level voltage, the first bias level voltage and the second bias level voltage may be greater than, equal to, or less than the default bias level voltage, and there is no limitation thereto. Since the first bias level voltage is greater than the second bias level voltage, the Vth of the target memory cell when the first bias level voltage is applied may be shifted to the right compared to the Vth of the target memory cell when the second bias level voltage is applied. If the first bias level voltage and the second bias level voltage are greater than the default bias level voltage, (1) the Vth of the target memory cell when the first bias level voltage is applied and (2) the Vth of the target memory cell when the second bias level voltage is applied may be shifted to the right compared to the Vth of the target memory cell when the default bias level voltage is applied.

[0109] Method 800 proceeds to operation 808, as shown in FIG. Figure 8 As shown, a second sample read can be performed on the second memory cell to obtain a second sample value of the second memory cell. The second memory cell can be coupled to a second word line adjacent to the selection word line and can also be coupled to the same bit line as the target memory cell. For example, the second memory cell and the target memory cell are located in the same memory string coupled to the same bit line and are adjacent to each other. In some embodiments, the selection word line can be word line WL(n). The second adjacent word line can be word line WL(n-1) or WL(n+1).

[0110] The peripheral circuit 402 may perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell. The second sample read may be associated with a second set of Vth ranges. Specifically, the entire Vth range of all possible Vths of the memory cell may be divided into a second set of Vth ranges. A read operation may be performed on the second memory cell according to the second set of Vth ranges, so that a second sample value of the Vth of the second memory cell may be obtained from the read operation. For example, the second set of Vth ranges may include two Vth ranges. In this case, the second sample read on the second memory cell may be an SLC read on the second memory cell. Reference Figure 10A An example implementation of the second sample read as an SLC read is shown. In another example, the second set of Vth ranges may include four Vth ranges, and in this case, the second sample read of the second memory cell may be an MLC read of the second memory cell.

[0111] The second sample read may include similar operations to the first sample read, except that the second sample read is associated with a second set of Vth ranges, while the first sample read is associated with a first set of Vth ranges. For example, the first sample read may be an SLC read, while the second sample read may be an MLC read. In some embodiments, the first set of Vth ranges may be the same as the second set of Vth ranges, and the first sample read may be the same as the second sample read. For example, each of the first sample read and the second sample read may be an SLC read. In another example, each of the first sample read and the second sample read may be an MLC read.

[0112] Method 800 proceeds to operation 810, as shown in FIG. Figure 8As shown, one or more read parameters of the target memory cell may be configured based on the second sample value. In the following description of operation 810, it is assumed that the second set of Vth ranges may include at least a third Vth range and a fourth Vth range. The Vth value in the third Vth range may be smaller than the Vth value in the fourth Vth range (e.g., the third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range).

[0113] In some embodiments, one or more read parameters may include a set of read voltages. Specifically, the peripheral circuit 402 may determine a set of default read voltages for the target memory cell. For example, if the target memory cell is an SLC, the peripheral circuit 402 may determine a default read voltage for the target memory cell. The default read voltage may be used to distinguish the Vth of a memory cell with an erased state P0 from the Vth of a memory cell with a programmed state P1. The default read voltage may be applied to a select word line to sense the state of the target memory cell (e.g., to determine whether the Vth of the target memory cell is greater than or less than the default read voltage). In another example, if the target memory cell is an MLC, the peripheral circuit 402 may determine three default read voltages for the target memory cell. The three default read voltages may be used to distinguish the Vth of a memory cell with an erased state P0, the Vth of a memory cell with a programmed state P1, the Vth of a memory cell with a programmed state P2, and the Vth of a memory cell with a programmed state P3. Three default read voltages may be applied to the selection word lines, respectively, to sense the states of the target memory cells (eg, to determine whether the Vth of the target memory cells is greater than or less than the three default read voltages, respectively).

[0114] In response to the second sample value corresponding to a third Vth range from the second set of Vth ranges, the peripheral circuit 402 may determine a first subset of read voltages for the target memory cell. The first subset of read voltages may have a one-to-one correspondence with the set of default read voltages and may be a first corrected version of the set of default read voltages when the second sample value corresponds to the third Vth range. Alternatively, in response to the second sample value corresponding to a fourth Vth range from the second set of Vth ranges, the peripheral circuit 402 may determine a second subset of read voltages for the target memory cell. The second subset of read voltages may have a one-to-one correspondence with the set of default read voltages and may be a second corrected version of the set of default read voltages when the second sample value corresponds to the fourth Vth range.

[0115] For each read voltage in the first subset of read voltages, a first read offset of the read voltage relative to the corresponding default read voltage can be less than a second read offset of a corresponding one of the read voltages in the second subset of read voltages relative to the corresponding default read voltage. For example, a first read voltage from the first subset and a second read voltage from the second subset each correspond to a default read voltage. The first read voltage is equal to the sum of the default read voltage and the first read offset, and the second read voltage is equal to the sum of the default read voltage and the second read offset (for example, first read voltage = default read voltage + first read offset, second read voltage = default read voltage + second read offset, and first read offset < second read offset).

[0116] Next, the peripheral circuit 402 can apply the set of read voltages during a read operation on the target memory cell to read the target memory cell. For example, if the second sample value corresponds to a third Vth range, the peripheral circuit 402 can apply a first subset of read voltages to read the target memory cell. Alternatively, if the second sample value corresponds to a fourth Vth range, the peripheral circuit 402 can apply a second subset of read voltages to read the target memory cell. Because the first read offset of each read voltage from the first subset relative to the corresponding default read voltage is less than the second read offset of the corresponding read voltage from the second subset relative to the corresponding default read voltage, the Vth of the target memory cell sensed by the first subset of read voltages can be right-shifted compared to the Vth of the target memory cell sensed by the second subset of read voltages.

[0117] In some embodiments, the one or more read parameters may include a second set of SO development times. Specifically, the peripheral circuit 402 may determine a default SO development time for the target memory cell. In response to the second sample value corresponding to the third Vth range, the peripheral circuit 402 may determine a third SO development time that is a corrected version of the default SO development time. Alternatively, in response to the second sample value corresponding to the fourth Vth range, the peripheral circuit 402 may determine a fourth SO development time that is another corrected version of the default SO development time. The third SO development time may be less than the fourth SO development time.

[0118] Next, the peripheral circuit 402 may apply the second set of SO development times to read the target memory cell during a read operation on the target memory cell. For example, if the second sample value corresponds to a third Vth range, the peripheral circuit 402 may apply the third SO development time to read the target memory cell. Alternatively, if the second sample value corresponds to a fourth Vth range, the peripheral circuit 402 may apply the fourth SO development time to read the target memory cell. Because the third SO development time is less than the fourth SO development time, the Vth of the target memory cell when the third SO development time is applied in the read operation may be right-shifted compared to the Vth of the target memory cell when the fourth SO development time is applied in the read operation.

[0119] In some embodiments, the one or more read parameters may include a second set of pass voltages. Specifically, the peripheral circuit 402 may determine a default pass voltage for the target memory cell. In response to the second sample value corresponding to a third Vth range, the peripheral circuit 402 may determine a third pass voltage that is a corrected version of the default pass voltage. Alternatively, in response to the second sample value corresponding to a fourth Vth range, the peripheral circuit 402 may determine a fourth pass voltage that is another corrected version of the default pass voltage. The third pass voltage may be less than the fourth pass voltage.

[0120] Next, the peripheral circuit 402 may apply a second set of pass voltages to read the target memory cell during a read operation on the target memory cell. For example, if the second sample value corresponds to a third Vth range, the peripheral circuit 402 may apply a third pass voltage to read the target memory cell. For example, the third pass voltage may be applied to one or more unselected word lines, such as WL(n-1), WL(n+1), while the default pass voltage may still be applied to any remaining unselected word lines. Alternatively, if the second sample value corresponds to a fourth Vth range, the peripheral circuit 402 may apply a fourth pass voltage to read the target memory cell. For example, the fourth pass voltage may be applied to one or more unselected word lines, such as word lines WL(n-1), WL(n+1), while the default pass voltage may still be applied to any remaining unselected word lines. Since the third pass voltage is less than the fourth pass voltage, the Vth of the target memory cell when the third pass voltage is applied may be right-shifted compared to the Vth of the target memory cell when the fourth pass voltage is applied.

[0121] In some embodiments, the one or more read parameters may include a second set of bias level voltages for biasing the voltage of the bit line coupled to the target memory cell. Specifically, the peripheral circuit 402 may determine a default bias level voltage for biasing the voltage of the bit line coupled to the target memory cell. In response to the second sample value corresponding to the third Vth range, the peripheral circuit 402 may determine a third bias level voltage that is a corrected version of the default bias level voltage. Alternatively, in response to the second sample value corresponding to the fourth Vth range, the peripheral circuit 402 may determine a fourth bias level voltage that is another corrected version of the default bias level voltage. The third bias level voltage may be less than the fourth bias level voltage.

[0122] Next, the peripheral circuit 402 may apply a second set of bias level voltages to read the target memory cell during a read operation on the target memory cell. For example, if the second sample value corresponds to a third Vth range, the peripheral circuit 402 may apply a third bias level voltage to read the target memory cell. For example, the third bias level voltage may be applied to bias the bit line during the read operation. Alternatively, if the second sample value corresponds to a fourth Vth range, the peripheral circuit 402 may apply a fourth bias level voltage to read the target memory cell. For example, the fourth bias level voltage may be applied to bias the bit line during the read operation. Because the third bias level voltage is less than the fourth bias level voltage, the Vth of the target memory cell when the third bias level voltage is applied may be right-shifted compared to the Vth of the target memory cell when the fourth bias level voltage is applied.

[0123] According to some aspects of the present disclosure, a single-round programming operation can be applied to program target memory cells coupled to a selected word line WL(n) in one round. In this case, the first word line in the first sample read of reference operation 804 (e.g., the first adjacent word line in the auxiliary verification scheme disclosed herein) can be word line WL(n-1). The second word line in the second sample read of reference operation 808 (e.g., the second adjacent word line in the auxiliary read scheme disclosed herein) can be word line WL(n+1).

[0124] According to some aspects of the present disclosure, a multi-round programming operation can be applied to program target memory cells coupled to a selection word line WL(n) in multiple rounds, which can include a coarse programming round and a fine programming round. In this case, the auxiliary verification scheme and the auxiliary read scheme disclosed herein can be applied during the fine programming round of the selection word line WL(n). The first adjacent word line in the first sample read of the auxiliary verification scheme can be word line WL(n-1). The second adjacent word line in the second sample read of the auxiliary read scheme can be word line WL(n+1). Alternatively, the first adjacent word line in the first sample read can be word line WL(n+1). The second adjacent word line in the second sample read can be word line WL(n-1).

[0125] Figures 9A-9G An example implementation of an auxiliary verification scheme applied in a programming operation according to some aspects of the present disclosure is shown. Figures 9A-9G In the embodiment of the present invention, a program operation can be configured to program a target memory cell coupled to a selection word line. A first memory cell can be coupled to a first word line adjacent to the selection word line and can also be coupled to the same bit line as the target memory cell. As an example, the target memory cell and the first memory cell are MLCs. The target memory cell can be programmed to a target program state, which can be one of P0-P3. The first memory cell can also be programmed to one of the program states P0-P3.

[0126] refer to Figure 9A, a first sample read on a first memory cell may be an SLC read and may be associated with a first set of Vth ranges including a first Vth range 902 and a second Vth range 904. The Vth distribution of memory cells having a target programming state P0 and the Vth distribution of memory cells having a target programming state P1 are within the first Vth range 902. The Vth distribution of memory cells having a target programming state P2 and the Vth distribution of memory cells having a target programming state P3 are within the second Vth range 904. The first Vth range 902 and the second Vth range 904 are separated by a read voltage Vsample_read for the first sample read. For example, during a first sample read of a first memory cell, the read voltage Vsample_read may be applied to a first word line coupled to the first memory cell to select the first word line. If the Vth of the first memory cell falls within the first Vth range 902 (e.g., the Vth of the first memory cell is less than the read voltage Vsample_read), this indicates that the first memory cell has a P0 state or a P1 state, and a first sample value "S0" (e.g., S0=0) corresponding to the first Vth range 902 can be obtained. If the Vth of the first memory cell falls within the second Vth range 904 (e.g., the Vth of the first memory cell is greater than the read voltage Vsample_read), this indicates that the first memory cell has a P2 state or a P3 state, and a first sample value "S1" (e.g., S0=1) corresponding to the second Vth range 904 can be obtained.

[0127] refer to Figure 9B , shows one or more verification parameters of the target memory cell. For example, if the target programming state of the target memory cell is P1, the verification voltage parameter Vverify(1) can be used to verify the programming of the target memory cell. If the target programming state of the target memory cell is P2, the verification voltage parameter Vverify(2) can be used to verify the programming of the target memory cell. If the target programming state of the target memory cell is P3, the verification voltage parameter Vverify(3) can be used to verify the programming of the target memory cell. Figure 9B Also shown in FIG. 5 is a pass voltage parameter Vpass.

[0128] Figure 9CA table (Table 1) is shown that lists different configurations of verification voltage parameters Vverify(1), Vverify(2), and Vverify(3) associated with target programming states P1-P3, respectively. By default (when the auxiliary verification scheme disclosed herein is not applied), the verification voltage parameters Vverify(1), Vverify(2), and Vverify(3) can be configured as default verification voltages Vverify(1)_d, Vverify(2)_d, and Vverify(3)_d, respectively.

[0129] When the auxiliary verification scheme disclosed herein is applied, the verification voltage parameters Vverify(1), Vverify(2), and Vverify(3) may be configured as follows. For example, when the target programming state of the target memory cell is P1, the verification voltage parameter Vverify(1) is configured to include a first set of verification voltages Vverify(1)_1, Vverify(1)_2 for the target memory cell. Specifically, if the first sample value of the first memory cell corresponds to the first Vth range 902, the verification voltage parameter Vverify(1) may be configured as the first verification voltage Vverify(1)_1. Then, the first verification voltage Vverify(1)_1 may be applied to verify programming of the target memory cell. Alternatively, if the first sample value of the first memory cell corresponds to the second Vth range 904, the verification voltage parameter Vverify(1) may be configured as the second verification voltage Vverify(1)_2. Then, the second verification voltage Vverify(1)_2 may be applied to verify programming of the target memory cell. A first verification offset of the first verification voltage Vverify(1)_1 relative to the default verification voltage Vverify(1)_d may be greater than a second verification offset of the second verification voltage Vverify(1)_2 relative to the default verification voltage Vverify(1)_d.

[0130] Similarly, when the target programming state of the target memory cell is P2, the verification voltage parameter Vverify(2) is configured to include a second set of verification voltages Vverify(2)_1 and Vverify(2)_2 for the target memory cell. When the target programming state of the target memory cell is P3, the verification voltage parameter Vverify(3) is configured to include a third set of verification voltages Vverify(3)_1 and Vverify(3)_2 for the target memory cell. Similar descriptions are not repeated herein.

[0131] Figure 9DA table (Table 2) listing different configurations of the SO evolution time parameter is shown.By default (when the auxiliary verification scheme disclosed herein is not applied), the SO evolution time parameter may be configured to a default SO evolution time Tso_d.

[0132] When applying the auxiliary verification scheme disclosed herein, the SO development time parameter can be configured as follows. For example, the SO development time parameter is configured to include a first set of SO development times for the target memory cell. Specifically, if the first sample value of the first memory cell corresponds to the first Vth range 902, the SO development time parameter can be configured as a first SO development time Tso_1. Then, when verifying the programming of the target memory cell, the first SO development time Tso_1 can be applied. Alternatively, if the first sample value of the first memory cell corresponds to the second Vth range 904, the SO development time parameter can be configured as a second SO development time Tso_2, so that the second SO development time Tso_2 can be applied when verifying the programming of the target memory cell. The first SO development time Tso_1 can be greater than the second SO development time Tso_2.

[0133] Figure 9D A table (Table 3) listing different configurations for the bias level voltage parameter is shown. By default (when the assisted verification scheme disclosed herein is not applied), the bias level voltage parameter may be configured to a default bias level voltage Vbl_d.

[0134] When applying the auxiliary verification scheme disclosed herein, the bias level voltage parameters can be configured as follows. For example, the bias level voltage parameters are configured to include a first set of bias level voltages for the target memory cell. Specifically, if the first sample value of the first memory cell corresponds to the first Vth range 902, the bias level voltage parameters can be configured to be a first bias level voltage Vbl_1. Then, when verifying programming of the target memory cell, the first bias level voltage Vbl_1 can be applied to the bit line. Alternatively, if the first sample value of the first memory cell corresponds to the second Vth range 904, the bias level voltage parameters can be configured to be a second bias level voltage Vbl_2. Then, when verifying programming of the target memory cell, the second bias level voltage Vbl_2 can be applied to the bit line. The first bias level voltage Vbl_1 can be greater than the second bias level voltage Vbl_2.

[0135] Figure 9F A table (Table 4) listing different configurations for the pass voltage parameter is shown.By default (when the assisted verification scheme disclosed herein is not applied), the pass voltage parameter Vpass may be configured to a default pass voltage Vpass_d.

[0136] When applying the auxiliary verification scheme disclosed herein, the pass voltage parameter Vpass can be configured as follows. For example, the pass voltage parameter Vpass is configured to include a first set of pass voltages for the target memory cell. Specifically, if the first sample value of the first memory cell corresponds to the first Vth range 902, the pass voltage parameter Vpass can be configured as a first pass voltage Vpass_1. Then, when verifying programming of the target memory cell, the first pass voltage Vpass_1 can be applied to one or more unselected word lines. Alternatively, if the first sample value of the first memory cell corresponds to the second Vth range 904, the pass voltage parameter Vpass can be configured as a second pass voltage Vpass_2. Then, when verifying programming of the target memory cell, the second pass voltage Vpass_2 can be applied to one or more unselected word lines. The first pass voltage Vpass_1 can be greater than the second pass voltage Vpass_2.

[0137] Figure 9G A table (Table 5) is shown that provides a comparison of verification parameters when the first sample value corresponds to the first Vth range 902 and the second Vth range 904, respectively. For example, the first row of Table 5 indicates that the first bias level voltage Vbl_1 (when the first sample value corresponds to the first Vth range 902) can be greater than the second bias level voltage Vbl_2 (when the first sample value corresponds to the second Vth range 904), as described above with reference to Figure 9E The second row of Table 5 indicates that the first SO development time Tso_1 (when the first sample value corresponds to the first Vth range 902) can be greater than the second SO development time Tso_2 (when the first sample value corresponds to the second Vth range 904), as described above with reference to Figure 9D The third row of Table 5 indicates that the first pass voltage Vpass_1 (when the first sample value corresponds to the first Vth range 902) can be greater than the second pass voltage Vpass_2 (when the first sample value corresponds to the second Vth range 904), as described above with reference to Figure 9F described.

[0138] The fourth row of Table 5 indicates that for the target programmed state P1, the first verification offset of the first verification voltage Vverify(1)_1 (when the first sample value corresponds to the first Vth range 902) can be greater than the second verification offset of the second verification voltage Vverify(1)_2 (when the first sample value corresponds to the second Vth range 904), as described above with reference to Figure 9CSimilarly, for the target programming state P2, the first verification offset of the first verification voltage Vverify(2)_1 may be greater than the second verification offset of the second verification voltage Vverify(2)_2. For the target programming state P3, the first verification offset of the first verification voltage Vverify(3)_1 may be greater than the second verification offset of the second verification voltage Vverify(3)_2.

[0139] Figures 10A-10G An example implementation of an assist read scheme applied in a read operation according to some aspects of the present disclosure is shown. Figures 10A-10G In the embodiment of the present invention, a read operation can be configured to read a target memory cell coupled to a selected word line. A second memory cell can be coupled to a second word line adjacent to the selected word line and can also be coupled to the same bit line as the target memory cell. As an example, the target memory cell and the second memory cell are MLCs. The target memory cell can have one of the programmed states P0-P3. The second memory cell can also have one of the programmed states P0-P3.

[0140] refer to Figure 10A , a second sample read on the second memory cell can be an SLC read and can be associated with a second set of Vth ranges including a third Vth range 1002 and a fourth Vth range 1004. The Vth distribution of the memory cells having the target program state P0 and the Vth distribution of the memory cells having the target program state P1 are within the third Vth range 1002. The Vth distribution of the memory cells having the target program state P2 and the Vth distribution of the memory cells having the target program state P3 are within the fourth Vth range 1004. The third Vth range 1002 and the fourth Vth range 1004 are separated by a read voltage Vsample_read. For example, during the second sample read of the second memory cell, the read voltage Vsample_read can be applied to a second word line coupled to the second memory cell. If the Vth of the second memory cell falls within the third Vth range 1002 (e.g., the Vth of the second memory cell is less than the read voltage Vsample_read), this indicates that the second memory cell has a P0 state or a P1 state (or the Vth of the second memory cell is less than the read voltage Vsample_read), and a second sample value "S0" (e.g., S0=0) corresponding to the third Vth range 1002 can be obtained. If the Vth of the second memory cell falls within the fourth Vth range 1004 (e.g., the Vth of the second memory cell is greater than the read voltage Vsample_read), this indicates that the second memory cell has a P2 state or a P3 state, and a second sample value "S1" (e.g., S1=1) corresponding to the fourth Vth range 1004 can be obtained.

[0141] refer to Figure 10B , showing one or more read parameters of the target memory cell. For example, read voltage parameters Vread(1), Vread(2), and Vread(3) can be applied to the selected word lines to sense the state of the target memory cell. Figure 10B Also shown in FIG. 5 is a pass voltage parameter Vpass.

[0142] Figure 10C A table (Table 6) lists different configurations of the read voltage parameters Vread(1), Vread(2), and Vread(3). By default (when the assisted read scheme disclosed herein is not applied), the read voltage parameters Vread(1), Vread(2), and Vread(3) can be configured as default read voltages Vread(1)_d, Vread(2)_d, and Vread(3)_d, respectively.

[0143] When the assisted read scheme disclosed herein is applied, the read voltage parameters Vread(1), Vread(2), and Vread(3) may be configured as follows. For example, if the second sample value corresponds to the third Vth range 1002, the read voltage parameters Vread(1), Vread(2), and Vread(3) may be configured as a first subset of read voltages (e.g., Vread(1)_1, Vread(2)_1, and Vread(3)_1), respectively. If the second sample value corresponds to the fourth Vth range 1004, the read voltage parameters Vread(1), Vread(2), and Vread(3) may be configured as a second subset of read voltages (e.g., Vread(1)_2, Vread(2)_2, and Vread(3)_2), respectively.

[0144] A first read offset of each read voltage in the first subset relative to the corresponding default read voltage may be smaller than a second read offset of a corresponding read voltage in the second subset relative to the corresponding default read voltage. For example, a read offset of Vread(1)_1 relative to Vread(1)_d may be smaller than a read offset of Vread(1)_2 relative to Vread(1)_d. A read offset of Vread(2)_1 relative to Vread(2)_d may be smaller than a read offset of Vread(2)_2 relative to Vread(2)_d. A read offset of Vread(3)_1 relative to Vread(3)_d may be smaller than a read offset of Vread(3)_2 relative to Vread(3)_d.

[0145] Figure 10DA table (Table 7) listing different configurations of the SO development time parameter is shown. By default (when the assisted reading scheme disclosed herein is not applied), the SO development time parameter may be configured to a default SO development time Tso'_d.

[0146] When applying the assisted read scheme disclosed herein, the SO development time parameter can be configured as follows. For example, the SO development time parameter is configured to include a second set of SO development times. Specifically, if the second sample value corresponds to the third Vth range 1002, the SO development time parameter can be configured to be a third SO development time Tso'_1, so that the third SO development time Tso'_1 can be applied when reading the target memory cell. Alternatively, if the second sample value corresponds to the fourth Vth range 1004, the SO development time parameter can be configured to be a fourth SO development time Tso'_2, so that the fourth SO development time Tso'_2 can be applied when reading the target memory cell. The third SO development time Tso'_1 can be less than the fourth SO development time Tso'_2.

[0147] Figure 10E A table (Table 8) listing different configurations of bias level voltage parameters of target memory cells is shown. By default (when the assisted read scheme disclosed herein is not applied), the bias level voltage parameters may be configured to a default bias level voltage Vbl'_d.

[0148] When applying the assisted read scheme disclosed herein, the bias level voltage parameters can be configured as follows. For example, the bias level voltage parameters are configured to include a second set of bias level voltages for the target memory cell. Specifically, if the second sample value corresponds to the third Vth range 1002, the bias level voltage parameters can be configured to be a third bias level voltage Vbl'_1, so that the third bias level voltage Vbl'_1 can be applied to the bit line when reading the target memory cell. Alternatively, if the second sample value corresponds to the fourth Vth range 1004, the bias level voltage parameters can be configured to be a fourth bias level voltage Vbl'_2, so that the fourth bias level voltage Vbl'_2 can be applied to the bit line when reading the target memory cell. The third bias level voltage Vbl'_1 can be greater than the fourth bias level voltage Vbl'_2.

[0149] Figure 10F A table (Table 9) listing different configurations of pass voltage parameters for target memory cells is shown. By default (when the assisted read scheme disclosed herein is not applied), the pass voltage parameter Vpass may be configured to a default pass voltage Vpass'_d.

[0150] When applying the assisted read scheme disclosed herein, the pass voltage parameter Vpass can be configured as follows. For example, the pass voltage parameter Vpass is configured to include a second set of pass voltages. Specifically, if the second sample value corresponds to a third Vth range 1002, the pass voltage parameter Vpass can be configured to a third pass voltage Vpass'_1, such that the third pass voltage Vpass'_1 can be applied to one or more unselected word lines when reading the target memory cell. Alternatively, if the second sample value corresponds to a fourth Vth range 1004, the pass voltage parameter Vpass can be configured to a fourth pass voltage Vpass'_2, such that the fourth pass voltage Vpass'_2 can be applied to one or more unselected word lines when reading the target memory cell. The third pass voltage Vpass'_1 can be less than the fourth pass voltage Vpass'_2.

[0151] Figure 10G A table (Table 10) is shown that provides a comparison of read parameters when the second sample value corresponds to the third Vth range 1002 and the fourth Vth range 1004, respectively. For example, the first row of Table 10 indicates that the third bias level voltage Vbl'_1 (when the second sample value corresponds to the third Vth range 1002) can be less than the fourth bias level voltage Vbl'_2 (when the second sample value corresponds to the fourth Vth range 1004), as described above with reference to FIG. Figure 10E The second row of Table 10 indicates that the third SO development time Tso'_1 may be less than the fourth SO development time Tso'_2, as described above with reference to Figure 10D The third row of Table 10 indicates that the third pass voltage Vpass'_1 may be less than the fourth pass voltage Vpass'_2, as described above with reference to Figure 10F described.

[0152] The fourth row of Table 10 indicates that the read offset of the read voltage Vread(1)_1 in the first subset of read voltages may be smaller than the read offset of the corresponding read voltage Vread(1)_2 in the second subset of read voltages, as described above with reference to Figure 10C Similarly, the read offset of the read voltage Vread(2)_1 in the first subset of read voltages may be smaller than the read offset of the corresponding read voltage Vread(2)_2 in the second subset of read voltages. The read offset of the read voltage Vread(3)_1 in the first subset of read voltages may be smaller than the read offset of the corresponding read voltage Vread(3)_2 in the second subset of read voltages.

[0153] Figure 11A and Figure 11B1 shows an example structure of a page buffer circuit in a page buffer (eg, page buffer / sense amplifier 504) according to some aspects of the present disclosure. In some embodiments, Figure 11A The page buffer in FIG. 1 includes a plurality of page buffer circuits 1102, each of which is coupled to a corresponding one of the bit lines 416. In other words, each page buffer circuit 1102 can be coupled to a corresponding column of memory cells 406 (e.g., a NAND memory string 408) via a corresponding bit line 416 and configured to temporarily store a set of N-bit data for programming a corresponding selected memory cell 406 (coupled to a selected word line 418 and a corresponding bit line 416) in a programming operation. All page buffer circuits 1102 together can temporarily store an entire page of data (e.g., Q sets of N-bit data) for programming a selected row of memory cells 406 coupled to a selected word line 418 in a programming operation. For example, for a TLC with N=3 and Q=8, each page buffer circuit 1102 can be configured to temporarily store a corresponding set of 8 sets of 3-bit data corresponding to 8 levels, respectively. The eight sets of 3-bit data may include 000, 001, 010, 011, 100, 101, 110, and 111.

[0154] According to some aspects of the present disclosure, Figure 11A or Figure 11B The page buffer circuit 1102 shown can be coupled to a column of memory cells 406 including a target memory cell via corresponding bit lines 416 and is configured to temporarily store a set of N bits of data for programming the target memory cell (which is coupled to both the select word line WL(n) and the corresponding bit line 416) in a programming operation. In some embodiments, the page buffer circuit 1102 can include a plurality of memory cells and a bias circuit 1104 coupled to the SO node. The plurality of memory cells can include N-1 data storage cells (D1, ..., D N-1 ) 1108, 1109, a cache storage unit 1106, a bias level (BL) storage unit 1110, a sense storage unit 1112 and one or more sample storage units 1114.

[0155] During a programming operation, each of the N-1 data storage units 1108, 1109 can be configured to store a corresponding bit in an N-bit data set (e.g., a corresponding bit in N bits). As a result, the N-1 data storage units 1108, 1109 can store N-1 bits in a set of N-bit data (e.g., N-1 bits in N bits). The cache memory unit 1106 in the page buffer circuit 1102 can also be configured to store one of the N bits from the set of N-bit data. That is, according to some embodiments, the cache memory unit 1106 is configured to sequentially store one of the N bits from the set of N-bit data and each of the N bits from the next set of N-bit data. In other words, the cache memory unit 1106 can act as both a data storage unit and a cache memory unit in a time-division manner. Therefore, the number of data storage units 1108, 1109 in each page buffer circuit 1102 becomes N-1 (D1 to D N-1 ).

[0156] In some embodiments, the sense memory cell 1112 and the BL memory cell 1110 can be configured to store non-data page information, i.e., any information other than bits in a set of N-bit data. For example, the sense memory cell 1112 can be configured to store information indicating whether the current operation performed by the page buffer / sense amplifier 504 is a read operation or a programming operation. The BL memory cell 1110 (e.g., a 3BL memory cell) can be configured to store bias information for the corresponding bit line 416 coupled to the page buffer circuit 1102. In some embodiments, the BL memory cell 1110 can be a multi-purpose memory cell that acts as both a BL memory cell and a cache memory cell in a time-division manner. The bias circuit 1104 can be coupled to the corresponding bit line 416 and configured to apply a bias level voltage to the corresponding bit line 416 coupled to the target memory cell during a programming operation. For example, a high voltage level or a low voltage level can be used as the bias level voltage to bias the corresponding bit line 416. In some embodiments, to optimize the threshold voltage distribution, for example, to increase the read margin between adjacent levels and reduce the width of each level, a medium voltage level is also used to bias the voltage of the corresponding bit line 416. That is, three voltage levels (e.g., high, medium, and low) can be applied to the corresponding bit line 416 (referred to herein as 3BL). In some embodiments, the voltage level (e.g., 3BL bias) applied to the corresponding bit line 416 is non-data page information stored in the BL memory cell 1110.

[0157] In some embodiments, one or more sample storage cells 1114 can be configured to store a first sample value of a first storage cell or a second sample value of a second storage cell. The first storage cell is coupled to a first word line adjacent to a selected word line, and the second storage cell is coupled to a second word line adjacent to the selected word line. The first and second storage cells are coupled to the same bit line 416 as the target storage cell and are adjacent to the target storage cell. For example, if the first sample value or the second sample value has 1 bit, then the page buffer circuit 1102 can include one sample storage cell 1114. In another example, if the first sample value or the second sample value has 2 bits, then the page buffer circuit 1102 can include two sample storage cells 1114.

[0158] It should be understood that each memory cell in the page buffer circuit 1102 (including each of the data storage cells 1108 and 1109, the cache storage cell 1106, the BL storage cell 1110, the sense storage cell 1112, and the sample storage cell 1114) can be any circuit having two stable states for storing a single bit of data, such as a latch or a flip-flop. For example, each memory cell can include a latch.

[0159] Figure 12A 1 shows the change of the Vth distribution of the memory cell after data retention according to some examples. Figure 12A , and similar descriptions will not be repeated in this article.

[0160] Figure 12B FIG. 4 shows a change in the Vth distribution of a memory cell after data retention when an auxiliary verification scheme is applied according to some aspects of the present disclosure. Figure 12A To describe Figure 12B For example, suppose Figure 12A The first, second, and third Vth distributions of the memory cells in the program are left-shifted due to lateral charge migration (e.g., charge loss). Then, the auxiliary verification scheme disclosed herein can be applied during the programming operation of each memory cell. As a result, the first, second, and third Vth distributions of the memory cells can be right-shifted and configured to be narrowed in advance (before maintenance), as respectively determined by Figure 12B After the hold, the first, second and third Vth distributions of the memory cell are respectively given by Figure 12B Even though the first Vth distribution, the second Vth distribution, and the third Vth distribution of the memory cell may shift to the left and become wider after holding, the first Vth distribution and the second Vth distribution of the memory cell may be consistent with each other. Figure 12ACompared with part (b), the first, second and third Vth distributions of the memory cells can still be narrower. Therefore, the margin loss after the maintenance can be reduced or recovered by applying the auxiliary verification scheme.

[0161] Figure 12C 1 shows the change of the Vth distribution of the memory cell when the auxiliary reading scheme disclosed herein is applied according to some aspects of the present disclosure. Figure 12A To describe Figure 12C For example, after holding (when the assisted verification scheme disclosed herein is not applied), the first, second, and third Vth distributions of the memory cell are left-shifted and become wider due to lateral charge migration (e.g., charge loss), as shown in FIG. Figure 12C As shown in curves 1244, 1246 and 1242 in part (a). Figure 12C The curves 1244, 1246 and 1242 in part (a) can be respectively Figure 12A The auxiliary read scheme disclosed herein can be applied during the read operation of each memory cell so that the first, second and third Vth distributions of the memory cell can be right-shifted and become narrower, as shown in FIG. Figure 12C The first Vth distribution and the second Vth distribution of the memory cell become consistent with each other. Therefore, the margin loss after the retention can be reduced or recovered by applying the auxiliary read scheme.

[0162] Figure 12D 1 shows the change in Vth distribution of memory cells when a combination of the assisted verification scheme and the assisted reading scheme disclosed herein is applied according to some aspects of the present disclosure. Figure 12B-12C To describe Figure 12D For example, the assisted read scheme disclosed herein may be applied during a programming operation of each memory cell so that the first, second, and third Vth distributions of the memory cell may be right-shifted and configured to be narrowed in advance (before holding), as respectively determined by Figure 12D After the hold, the first, second and third Vth distributions of the memory cell are respectively given by Figure 12D Even though the first Vth distribution, the second Vth distribution, and the third Vth distribution of the memory cell may shift leftward and become wider after holding, the first Vth distribution and the second Vth distribution of the memory cell may be consistent with each other. Figure 12A The first, second and third Vth distributions of the memory cell can still be narrower when compared with part (b).

[0163] Assume that an auxiliary verification scheme is performed based on a first sample read of each of the first adjacent memory cells coupled to the first adjacent word line. Then, the influence of the Vth of the first adjacent memory cell on the Vth of the memory cell can be reduced or eliminated by the auxiliary verification scheme. The influence of the Vth of the second adjacent memory cell coupled to the second adjacent word line on the Vth of the memory cell still exists. For example, the first, second, and third Vth distributions of the memory cell due to the influence of the Vth of the second adjacent memory cell coupled to the second adjacent word line can be respectively calculated using Figure 12D Next, the auxiliary read scheme disclosed herein can be applied during the read operation of each memory cell. As a result, the first, second, and third Vth distributions of the memory cell can be right-shifted and narrowed, as shown by curves 1293, 1294, and 1288 in part (c) of FIG. Figure 12D As shown in curves 1296, 1297, and 1295 in part (d), the first Vth distribution and the second Vth distribution of the memory cell become consistent with each other. Therefore, the margin loss after the maintenance can be reduced or recovered by applying the auxiliary verification scheme and the auxiliary reading scheme.

[0164] Figure 13 According to some aspects of the present disclosure, an application Figures 9A-9G Auxiliary verification scheme and Figures 10A-10G An example block 1300 of memory cells (eg, MLCs with programming states P0-P3) using an assisted read scheme. Figures 9A-9G and Figures 10A-10G describe Figure 13 Assume that memory cells 1302a and 1302b are coupled to word line WL(n) with the same target program state P2. Memory cells 1304a and 1304b are coupled to word line WL(n-1) with target program states P2 and P1, respectively. Memory cells 1306a and 1306b are coupled to word line WL(n+1) with target program states P0 and P3, respectively. Memory cells 1302a, 1304a, and 1306a are coupled to bit line 1320a. Memory cells 1302b, 1304b, and 1306b are coupled to bit line 1320b.

[0165] By default, in Figure 13 During a programming operation of a memory cell, default verification parameters such as default verification voltages (Vverify(1)_d, Vverify(2)_d, Vverify(3)_d), a default SO development time (Tso_d), a default bias voltage level (Vbl_d), and a default pass voltage (Vpass_d) are applied.

[0166] Assume that the memory cells 1304a and 1304b coupled to word line WL(n-1) have been programmed to their respective target programmed states P2 and P1. When the memory cells 1302a and 1302b coupled to word line WL(n) are programmed to their target programmed states P2, the auxiliary verification scheme disclosed herein is applied during the programming operation. First, a first sample read is applied to the memory cells 1304a and 1304b coupled to word line WL(n-1) to obtain first sample values ​​S1 and S0, respectively. The first sample value S0 corresponds to Figure 9A The first sample value S1 corresponds to the first Vth range 902. Figure 9A The second Vth range 904. Next, a program voltage may be applied to the select word line WL(n) to program the memory cells 1302a and 1302b.

[0167] In some embodiments, when Figure 9B When the verification voltage parameter Vverify(2) is used to verify programming of memory cells 1302a and 1302b having a target programming state P2, first, a first verification voltage Vverify(2)_1 may be applied to the selected word line WL(n) to verify programming of memory cell 1302b (e.g., Vverify(2)=Vverify(2)_1) because the first sample value of the adjacent memory cell 1304b is S0, corresponding to the first Vth range 902. Subsequently, a second verification voltage Vverify(2)_2 may be applied to the selected word line WL(n) to verify programming of memory cell 1302a (e.g., Vverify(2)=Vverify(2)_2) because the first sample value of the adjacent memory cell 1304a is S1, corresponding to the second Vth range 904.

[0168] In some embodiments, when Figure 9B When a verification voltage parameter Vverify(2) is used to verify programming of memory cells 1302a and 1302b having a target programming state P2 (e.g., where Vverify(2)=Vverify(2)_d), first, during verification of memory cell 1302b, a first pass voltage Vpass_1 may be applied to the adjacent word line WL(n-1) and / or the adjacent word line WL(n) because the first sample value of the adjacent memory cell 1304b is S0, corresponding to the first Vth range 902. Subsequently, during verification of memory cell 1302a, a second pass voltage Vpass_2 may also be applied to the adjacent word line WL(n-1) and / or the adjacent word line WL(n) because the first sample value of the adjacent memory cell 1304b is S0, corresponding to the second Vth range 904.

[0169] In some embodiments, when Figure 9B When the verification voltage parameter Vverify(2) is used to verify programming of memory cells 1302a and 1302b having target programming state P2 (e.g., where Vverify(2)=Vverify(2)_d), (a) since the first sample value of adjacent memory cell 1304b is S0, corresponding to the first Vth range 902, a first bias level voltage Vbl_1 can be applied to bit line 1320b, and simultaneously, (b) since the first sample value of adjacent memory cell 1304a is S1, corresponding to the second Vth range 904, a second bias level voltage Vbl_2 can be applied to bit line 1320a.

[0170] In some embodiments, when Figure 9B When the verification voltage parameter Vverify(2) is used to verify programming of memory cells 1302a and 1302b having a target programming state P2 (e.g., where Vverify(2)=Vverify(2)_d), (a) since the first sample value of the adjacent memory cell 1304b is S0, corresponding to the first Vth range 902, a first SO development time Tso_1 can be applied to the verification of the memory cell 1302b, and at the same time, (b) since the first sample value of the adjacent memory cell 1304a is S1, corresponding to the second Vth range 904, a second SO development time Tso_2 can be applied to the verification of the memory cell 1302a.

[0171] When memory cells 1306a and 1306b coupled to word line WL(n+1) are programmed to their respective target program states P0 and P3, the auxiliary verification scheme disclosed herein may also be applied during the programming operation. Similar descriptions are not repeated herein.

[0172] By default, in Figure 13 During a read operation of the memory cells of the present invention, default read parameters such as default read voltages (Vverify(1)_d, Vverify(2)_d, Vverify(3)_d), default SO development time (Tso'_d), default bias voltage level (Tso'_d), and default pass voltage (Vpass'_d) are applied. When the memory cells 1302a and 1302b coupled to the word line WL(n) are read, the assisted read scheme disclosed herein is applied during the read operation. First, a second sample read is applied to the memory cells 1306a and 1306b coupled to the word line WL(n+1) to obtain second sample values ​​S0 and S1, respectively. The second sample value S0 corresponds to Figure 10A The second sample value S1 corresponds to the third Vth range 1002. Figure 10A The fourth Vth range 1004.

[0173] In some embodiments, when Figure 10B When the read voltage parameter Vread(1) is used to read the memory cells 1302a and 1302b, a first read voltage Vread(1)_1 may be applied to the selected word line WL(n) to read the memory cell 1302a (e.g., Vread(1)=Vread(1)_1) because the second sample value of the adjacent memory cell 1304b is S0, corresponding to the third Vth range 1002. Subsequently, a second read voltage Vread(1)_2 may be applied to the selected word line WL(n) to read the memory cell 1302b (e.g., Vread(1)=Vread(1)_2) because the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004.

[0174] Next, when Figure 10B When the read voltage parameter Vread(2) is used to read the memory cells 1302a and 1302b, a first read voltage Vread(2)_1 may be applied to the selected word line WL(n) to read the memory cell 1302a (e.g., Vread(2)=Vread(2)_1) because the second sample value of the adjacent memory cell 1306a is S0, corresponding to the third Vth range 1002. Subsequently, a second read voltage Vread(2)_2 may be applied to the selected word line WL(n) to read the memory cell 1302b (e.g., Vread(2)=Vread(2)_2) because the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004.

[0175] Later, when Figure 10B When the read voltage parameter Vread(3) is used to read the memory cells 1302a and 1302b, a first read voltage Vread(3)_1 may be applied to the selected word line WL(n) to read the memory cell 1302a (e.g., Vread(3)=Vread(3)_1) because the second sample value of the adjacent memory cell 1304b is S0, corresponding to the third Vth range 1002. Subsequently, a second read voltage Vread(3)_2 may be applied to the selected word line WL(n) to read the memory cell 1302b (e.g., Vread(3)=Vread(3)_2) because the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004.

[0176] In some embodiments, when Figure 10BWhen each of the read voltage parameters Vread(1), Vread(2), and Vread(3) is used to read memory cells 1302a and 1302b (e.g., where Vread(1)=Vread(1)_d), Vread(2)=Vread(2)_d, and Vread(3)=Vread(3)_d, first, during the read of memory cell 1302a, a first pass voltage Vpass'_1 may be applied to the adjacent word line WL(n-1) and / or the adjacent word line WL(n) because the second sample value of the adjacent memory cell 1306a is S0, corresponding to the third Vth range 1002. Subsequently, during the read of memory cell 1302b, a second pass voltage Vpass'_2 may also be applied to the adjacent word line WL(n-1) and / or the adjacent word line WL(n) because the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004.

[0177] In some embodiments, when Figure 10B When each of the read voltage parameters Vread(1), Vread(2), and Vread(3) is used to read memory cells 1302a and 1302b (e.g., where Vread(1)=Vread(1)_d), Vread(2)=Vread(2)_d, and Vread(3)=Vread(3)_d), (a) since the second sample value of the adjacent memory cell 1306a is S0, corresponding to the third Vth range 1002, the first bias level voltage Vbl'_1 can be applied to the bit line 1320a, and at the same time, (b) since the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004, the second bias level voltage Vbl'_2 can be applied to the bit line 1320b.

[0178] In some embodiments, when Figure 10B When each of the read voltage parameters Vread(1), Vread(2) and Vread(3) is used to read the memory cells 1302a and 1302b (for example, where Vread(1)=Vread(1)_d), Vread(2)=Vread(2)_d, and Vread(3)=Vread(3)_d), (a) since the second sample value of the adjacent memory cell 1306a is S0, corresponding to the third Vth range 1002, the first SO development time Tso'_1 can be applied to the reading of the memory cell 1302a, and at the same time, (b) since the second sample value of the adjacent memory cell 1306b is S1, corresponding to the fourth Vth range 1004, the second SO development time Tso'_2 can be applied to the reading of the memory cell 1302b.

[0179] The foregoing descriptions of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0180] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for operating a storage device comprising a storage unit, the method comprising: programming a target memory cell coupled to a selected word line; performing a first sample read on a first memory cell coupled to a first word line adjacent to the selected word line to obtain a first sample value of the first memory cell; configuring one or more verification parameters of the target storage unit based on the first sample value; performing a second sample read on a second memory cell coupled to a second word line adjacent to the selected word line to obtain a second sample value of the second memory cell; as well as One or more read parameters of the target memory cell are configured based on the second sample value.

2. The method according to claim 1, wherein The first word line includes a word line WL(n-1), the selection word line includes a word line WL(n), and the second word line includes a word line WL(n+1), where n is an integer and n≥1.

3. The method according to claim 1 or 2, wherein: The first sample read is associated with a first set of threshold voltage (Vth) ranges, and the second sample read is associated with a second set of Vth ranges.

4. The method according to claim 3, wherein: The one or more verification parameters include at least one of: a set of verification voltages, a first set of sense node (SO) development times, a first set of pass voltages, or a first set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

5. The method according to claim 4, wherein Configuring the one or more verification parameters of the target storage unit based on the first sample value includes: determining a first verification voltage for the target memory cell based on a target program state of the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second verification voltage for the target memory cell based on the target program state of the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and a first offset of the first verification voltage relative to a default verification voltage associated with the target programming state is greater than a second offset of the second verification voltage relative to the default verification voltage.

6. The method according to claim 4, wherein: Configuring the one or more verification parameters of the target storage unit based on the first sample value further includes: determining a first SO development time for the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second SO development time for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, The first SO development time is greater than the second SO development time.

7. The method according to claim 4, wherein: Configuring the one or more verification parameters of the target storage unit based on the first sample value further includes: determining a first pass voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second pass voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, The first pass voltage is greater than the second pass voltage.

8. The method according to claim 4, wherein Configuring the one or more verification parameters of the target storage unit based on the first sample value further includes: determining a first bias level voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second bias level voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, The first bias level voltage is greater than the second bias level voltage.

9. The method according to claim 3, wherein: The one or more read parameters include at least one of: a set of read voltages, a second set of sense node (SO) development times, a second set of pass voltages, or a second set of bias level voltages for biasing a voltage of a bit line coupled to the target memory cell.

10. The method according to claim 9, wherein: Configuring the one or more read parameters of the target memory cell based on the second sample value includes: determining a first subset of read voltages for the target memory cells in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a second subset of read voltages for the target memory cells in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is smaller than a fourth Vth value in the fourth Vth range, and Wherein, for each read voltage in the first subset of read voltages, an offset of the read voltage relative to a corresponding default read voltage is smaller than an offset of a corresponding read voltage in the second subset of read voltages relative to the corresponding default read voltage.

11. The method according to claim 9, wherein Configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third SO development time for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth SO development time for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third SO development time is smaller than the fourth SO development time.

12. The method according to claim 9, wherein Configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third pass voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth pass voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third pass voltage is smaller than the fourth pass voltage.

13. The method according to claim 9, wherein: Configuring the one or more read parameters of the target memory cell based on the second sample value further includes: determining a third bias level voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth bias level voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third bias level voltage is smaller than the fourth bias level voltage.

14. The method according to any one of claims 1 to 13, wherein: The storage device includes a NAND flash memory device.

15. The method according to any one of claims 1 to 14, wherein The target memory cell, the first memory cell, and the second memory cell are coupled to a same bit line of the memory device.

16. A storage device comprising: a memory cell including a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first word line and the second word line; as well as a peripheral circuit coupled to the memory cell and configured to: Programming the target memory cell; performing a first sample read on the first storage unit to obtain a first sample value of the first storage unit; configuring one or more verification parameters of the target storage unit based on the first sample value; performing a second sample read on the second storage unit to obtain a second sample value of the second storage unit; as well as One or more read parameters of the target memory cell are configured based on the second sample value.

17. The storage device according to claim 16, wherein: The first word line includes a word line WL(n-1), the third word line includes a word line WL(n), and the second word line includes a word line WL(n+1), where n is an integer and n≥1.

18. The storage device according to claim 16 or 17, wherein: The first sample read is associated with a first set of threshold voltage (Vth) ranges, and the second sample read is associated with a second set of Vth ranges.

19. The storage device according to claim 18, wherein The one or more verification parameters include at least one of: a set of verification voltages, a first set of sense node (SO) development times, a first set of pass voltages, or a first set of bias level voltages for biasing a voltage of a bit line coupled to the target memory cell.

20. The storage device according to claim 19, wherein In order to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determining a first verification voltage for the target memory cell based on a target program state of the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second verification voltage for the target memory cell based on the target program state of the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, wherein a first Vth value in the first Vth range is less than a second Vth value in the second Vth range, and a first offset of the first verification voltage relative to a default verification voltage associated with the target programming state is greater than a second offset of the second verification voltage relative to the default verification voltage.

21. The storage device according to claim 19, wherein In order to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determining a first sense node (SO) development time for the target memory cell in response to a first sample value corresponding to a first Vth range from a first set of Vth ranges; or determining a second SO development time for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, A first Vth value in the first Vth range is smaller than a second Vth value in the second Vth range, and the first SO development time is greater than the second SO development time.

22. The storage device according to claim 19, wherein In order to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determining a first pass voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second pass voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, A first Vth value in the first Vth range is smaller than a second Vth value in the second Vth range, and the first pass voltage is greater than the second pass voltage.

23. The storage device according to claim 19, wherein In order to configure the one or more verification parameters of the target memory cell based on the first sample value, the peripheral circuit is further configured to: determining a first bias level voltage for the target memory cell in response to a first sample value corresponding to a first Vth range from the first set of Vth ranges; or determining a second bias level voltage for the target memory cell in response to a first sample value corresponding to a second Vth range from the first set of Vth ranges, A first Vth value in the first Vth range is smaller than a second Vth value in the second Vth range, and the first bias level voltage is greater than the second bias level voltage.

24. The storage device according to claim 18, wherein The one or more read parameters include at least one of a set of read voltages, a second set of sense node (SO) development times, a second set of pass voltages, or a second set of bias level voltages for biasing a voltage of a bit line coupled to a target memory cell.

25. The storage device according to claim 24, wherein In order to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determining a first subset of read voltages for the target memory cells in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a second subset of read voltages for the target memory cells in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, wherein a third Vth value in the third Vth range is smaller than a fourth Vth value in the fourth Vth range, and Wherein, for each read voltage in the first subset of read voltages, an offset of the read voltage relative to a corresponding default read voltage is smaller than an offset of a corresponding read voltage in the second subset of read voltages relative to the corresponding default read voltage.

26. The storage device according to claim 24, wherein In order to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determining a third SO development time for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth SO development time for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third SO development time is smaller than the fourth SO development time.

27. The storage device according to claim 24, wherein In order to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determining a third pass voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth pass voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third pass voltage is smaller than the fourth pass voltage.

28. The storage device according to claim 24, wherein In order to configure the one or more read parameters of the target memory cell based on the second sample value, the peripheral circuit is further configured to: determining a third bias level voltage for the target memory cell in response to a second sample value corresponding to a third Vth range from the second set of Vth ranges; or determining a fourth bias level voltage for the target memory cell in response to a second sample value corresponding to a fourth Vth range from the second set of Vth ranges, The third Vth value in the third Vth range is smaller than the fourth Vth value in the fourth Vth range, and the third bias level voltage is smaller than the fourth bias level voltage.

29. The storage device according to any one of claims 16 to 28, wherein: The storage device includes a NAND flash memory device.

30. The storage device according to any one of claims 16 to 29, wherein: The target memory cell, the first memory cell, and the second memory cell are coupled to a same bit line of the memory device.

31. A system comprising: A storage device configured to store data and comprising: a memory cell including a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first word line and the second word line; and a peripheral circuit coupled to the memory cell and configured to: Programming the target memory cell; performing a first sample read on the first storage unit to obtain a first sample value of the first storage unit; configuring one or more verification parameters of the target storage unit based on the first sample value; performing a second sample read on the second storage unit to obtain a second sample value of the second storage unit; and configuring one or more read parameters of the target memory cell based on the second sample value; and A memory controller is coupled to the memory device and configured to control operations of the memory device.

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