Storage device for performing read reclaim operations

Abstract

A memory device according to the present disclosure includes a non-volatile memory device including a plurality of memory blocks, and a memory controller configured to determine a plurality of error bit counts, each of the plurality of error bit counts indicating a number of error bits of a respective memory block of the plurality of memory blocks, generating recovery group information indicating a respective allocated recovery group for each of the plurality of memory blocks based on the plurality of error bit counts, and controlling the non-volatile memory device to perform a respective read recovery operation for each of the plurality of recovery groups based on the recovery group information, and executing corresponding read recovery operations according to different recovery time periods.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0036280 filed in the Korean Intellectual Property Office on March 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a storage device for performing a read reclaim operation. Background Art

[0004] A storage device may include a nonvolatile memory device for storing data and a storage controller for controlling the nonvolatile memory device. Over time, error bits may appear in the data stored in the nonvolatile memory device. Before the number of error bits included in the data becomes greater than the number of uncorrectable error bits, the storage device may perform a read recovery operation to ensure the reliability of the data stored in the nonvolatile memory device. Summary of the Invention

[0005] The present disclosure attempts to provide a memory device capable of performing a read reclaim operation in consideration of characteristics of each of a plurality of memory blocks.

[0006] According to an exemplary embodiment, a storage device includes a nonvolatile memory device and a storage controller, wherein the nonvolatile memory device includes multiple memory blocks, the storage controller is configured to determine multiple error bit counts, each of the multiple error bit counts indicating the number of error bits of a corresponding memory block in the multiple memory blocks, generate recycling group information associated with multiple recycling groups based on the multiple error bit counts, the recycling group information indicating a corresponding assigned recycling group from the multiple recycling groups for each of the multiple memory blocks, wherein each of the multiple recycling groups is associated with a corresponding error bit count range, and control the nonvolatile memory device to perform a corresponding read recycling operation for each of the multiple recycling groups based on the recycling group information, wherein, for each of the multiple recycling groups, the corresponding read recycling operation is performed according to different recycling periods.

[0007] According to an exemplary embodiment, a storage device includes a nonvolatile memory device and a storage controller, the nonvolatile memory device including a plurality of memory blocks, the storage controller being configured to assign a first group of memory blocks among the plurality of memory blocks to a first recycling group, the first group of memory blocks having corresponding error bit counts falling within a first reference error bit count range, assign a second group of memory blocks among the plurality of memory blocks to a second recycling group, the second group of memory blocks having corresponding error bit counts falling within a second reference error bit count range, and control the nonvolatile memory device to perform a read recycling operation on the first recycling group according to a first recycling period, and to perform a read recycling operation on the second recycling group according to a second recycling period different from the first recycling period.

[0008] According to an exemplary embodiment, a memory controller includes a memory interface and a read reclamation controller, wherein the memory interface is configured to communicate with a non-volatile memory device including a plurality of memory blocks, the read reclamation controller is configured to control the non-volatile memory device to perform a read reclamation operation on the plurality of memory blocks, determine a plurality of error bit counts based on the read reclamation operations performed on the plurality of memory blocks, the plurality of error bit counts including a corresponding error bit count for each of the plurality of memory blocks, and identify, from the plurality of memory blocks, a first group of memory blocks on which the read reclamation operation is performed according to a first reclamation period and a second group of memory blocks on which the read reclamation operation is performed according to a second reclamation period longer than the first reclamation period, based on the plurality of error bit counts. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram for explaining an electronic system including a storage device according to an exemplary embodiment.

[0010] Figure 2 is a diagram for explaining a change in threshold voltage distribution of memory cells according to an exemplary embodiment.

[0011] Figure 3 is a diagram for explaining a memory device that performs a read reclaim operation at a fixed period according to an exemplary embodiment.

[0012] Figure 4 is a diagram for explaining a memory device that detects the number of error bits of a memory cell based on a reference program state according to an exemplary embodiment.

[0013] Figure 5 is a diagram for explaining a memory device that detects the number of error bits of memory cells connected to a weak word line according to an exemplary embodiment.

[0014] Figure 6 is a diagram for explaining a memory device that allocates memory blocks to reclaim groups based on error bit counts of the memory blocks, according to an exemplary embodiment.

[0015] Figure 7 is a diagram for explaining a memory device that generates reclaim group information based on an error bit count of a memory block, according to an exemplary embodiment.

[0016] Figure 8 is a diagram for explaining a storage device that performs a read reclaim operation on different reclaim groups according to different reclaim periods, according to an exemplary embodiment.

[0017] Figure 9 is a diagram for explaining a storage device that performs a read reclaim operation based on reclaim group information according to an exemplary embodiment.

[0018] Figure 10 is a flowchart for explaining a storage device that performs corresponding read reclamation operations on two different reclamation groups according to two different reclamation periods, according to an exemplary embodiment.

[0019] Figure 11 is a diagram for explaining a nonvolatile memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0020] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that, unless the context indicates otherwise, the component is formed solely of that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed solely of the listed elements.

[0021] Ordinal numbers such as "first," "second," and "third" may simply be used as labels for certain elements, steps, and the like to distinguish them from one another. Terms that are not described using "first," "second," and the like in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0022] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are merely examples, and many implementations and variations that do not require the details provided herein are possible. It should also be emphasized that the present disclosure provides details of alternative examples, but this list of alternatives is not exhaustive. Furthermore, any consistency in details between the various examples should not be construed as requiring such details - it is impractical to list every possible variation of every feature described herein. In determining the requirements of the present invention, reference should be made to the language of the claims.

[0023] The drawings and description are to be regarded as illustrative in nature and not restrictive. Throughout the specification, like reference numerals refer to like elements.

[0024] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0025] Figure 1 is a diagram for explaining an electronic system including a storage device according to an exemplary embodiment.

[0026] refer to Figure 1 , the electronic system 50 may include a storage device 1000 and a host 2000 .

[0027] The storage device 1000 may be a device for storing data under the control of the host 2000. In an exemplary embodiment, the storage device 1000 may be manufactured in the form of a solid state drive (SSD), a universal flash storage (UFS), or the like.

[0028] The memory device 1000 may include a nonvolatile memory device 1100 and a memory controller 1200 .

[0029] The nonvolatile memory device 1100 can store data. The nonvolatile memory device 1100 can operate in response to the control of the memory controller 1200. In an exemplary embodiment, the nonvolatile memory device 1100 can be a NAND flash memory. The nonvolatile memory device 1100 can include a plurality of memory blocks BLK1 to BLKz for storing data. Each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells.

[0030] The nonvolatile memory device 1100 may receive a command and an address from the memory controller 1200 and perform an operation indicated by the command on the area indicated by the address. The nonvolatile memory device 1100 may perform a program operation (write operation) for storing data, a read operation for reading data, and an erase operation for erasing data on the area indicated by the address.

[0031] The memory controller 1200 may control overall operations of the memory device 1000 .

[0032] In an exemplary embodiment, when power is applied to the storage device 1000, the storage controller 1200 may execute instructions or codes included in the firmware. The firmware may include a host interface layer for controlling communication with the host 2000, a flash translation layer for controlling communication between the host 2000 and the nonvolatile memory device 1100, and a memory interface layer for controlling communication with the nonvolatile memory device 1100. In an exemplary embodiment, the flash translation layer may convert a logical address of the host 2000 into a physical address of the nonvolatile memory device 1100.

[0033] In an exemplary embodiment, the memory controller 1200 may control the nonvolatile memory device 1100 so that the nonvolatile memory device 1100 performs a write operation, a read operation, an erase operation, etc. according to a request from the host 2000. For a write operation, the memory controller 1200 may provide a write command, an address, and data to the nonvolatile memory device 1100. For a read operation, the memory controller 1200 may provide a read command and an address to the nonvolatile memory device 1100. For an erase operation, the memory controller 1200 may provide an erase command and an address to the nonvolatile memory device 1100.

[0034] In an exemplary embodiment, the memory controller 1200 may include a processor 1210 , a volatile memory 1220 , a host interface 1230 , an error correction circuit 1240 , and a memory interface 1250 .

[0035] The processor 1210 may control the overall operation of the memory controller 1200. The processor 1210 may control the operation of the memory controller 1200 so that the memory controller stores data provided by the host 2000 in the nonvolatile memory device 1100.

[0036] The volatile memory 1220 may be used as a buffer memory, a cache memory, an operation memory, etc. of the memory controller 1200 .

[0037] The volatile memory 1220 may temporarily store data provided from the host 2000 and / or data read from the non-volatile memory device 1100. In an exemplary embodiment, the volatile memory 1220 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). In an exemplary embodiment, the volatile memory 1220 may be located inside the memory controller 1200 or may be located outside the memory controller 1200.

[0038] The host interface 1230 may perform communication with the host 2000. The host interface 1230 may receive data from the host 2000 and provide data to the host 2000.

[0039] The error correction circuit 1240 may perform error correction operations. In an exemplary embodiment, the error correction circuit 1240 may perform error correction encoding (ECC encoding) on ​​data to be stored in the nonvolatile memory device 1100 through the memory interface 1250. The error correction encoded data may be transferred to the nonvolatile memory device 1100 through the memory interface 1250. In an exemplary embodiment, the error correction circuit 1240 may perform error correction decoding (ECC decoding) on ​​data received from the nonvolatile memory device 1100.

[0040] The memory interface 1250 may perform communication with the nonvolatile memory device 1100. The memory interface 1250 may provide a command, an address, data, etc. to the nonvolatile memory device 1100. The memory interface 1250 may receive data stored in the nonvolatile memory device 1100.

[0041] In an exemplary embodiment, the processor 1210 may include a read reclaim controller 1211. The read reclaim controller 1211 may control the non-volatile memory device 1100 to perform a read reclaim operation on a plurality of memory blocks BLK1 to BLKz of the non-volatile memory device 1100. Any such read reclaim operation may involve migrating data stored in one or more memory blocks to one or more other memory blocks. In an exemplary embodiment, one or more other memory blocks may be free blocks. A free block may be a memory block in which no data is stored.

[0042] In an exemplary embodiment, a read reclaim operation may be performed to prevent the number of error bits included in data stored in a memory block of a nonvolatile memory device from becoming greater than the number of uncorrectable error bits. In an exemplary embodiment, after data is stored in any given memory block, the number of error bits in the data stored in the memory block may tend to increase as read operations are cyclically performed on the memory block. In an exemplary embodiment, the number of error bits in the data stored in any given memory block may tend to increase as the amount of time that has passed since the data was stored in the memory block increases.

[0043] In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation based on read counts of the plurality of memory blocks BLK1 to BLKz. In an exemplary embodiment, the read count may be the number of times a read operation has been performed on the plurality of memory blocks BLK1 to BLKz since the data stored in the plurality of memory blocks BLK1 to BLKz was stored. In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation on a memory block having an associated read count greater than a reference read count.

[0044] In an exemplary embodiment, the read reclaim operation may include reading data from one or more of the memory blocks BLK1 to BLKz, storing the data in other memory blocks, and designating one or more memory blocks as free blocks.

[0045] In an exemplary embodiment, the read reclamation controller 1211 may determine a plurality of error bit counts, including a corresponding error bit count for each of the plurality of memory blocks BLK1 to BLKz. In an exemplary embodiment, each of the plurality of error bit counts may indicate the number of error bits included in data stored in a corresponding memory block among the plurality of memory blocks BLK1 to BLKz. In an exemplary embodiment, the read reclamation controller 1211 may control the nonvolatile memory device 1100 to perform a read reclamation operation based on the plurality of error bit counts. In an exemplary embodiment, the read reclamation controller 1211 may control the nonvolatile memory device 1100 to perform a read reclamation operation on a memory block having an associated error bit count greater than a reference error bit count.

[0046] In an exemplary embodiment, the read reclaim controller 1211 may allocate a plurality of memory blocks BLK1 to BLKz to a reclaim group based on a plurality of error bit counts.

[0047] In an exemplary embodiment, the read reclamation controller 1211 may assign memory blocks having error bit counts falling within the same reference error bit count range to the same reclamation group associated with the reference error bit count range. In an exemplary embodiment, the read reclamation controller may assign each memory block to one of a plurality of reclamation groups based on the error bit count of the memory block. In an exemplary embodiment, the read reclamation controller 1211 may control the nonvolatile memory device 1100 to perform a read reclamation operation on a per reclamation group basis.

[0048] In an exemplary embodiment, the read reclaim controller 1211 may assign a first group of memory blocks among the plurality of memory blocks BLK1 to BLKz to a first reclaim group, the first group of memory blocks having corresponding error bit counts falling within a first reference error bit count range. In an exemplary embodiment, the read reclaim controller 1211 may assign a second group of memory blocks among the plurality of memory blocks BLK1 to BLKz to a second reclaim group, the second group of memory blocks having corresponding error bit counts falling within a second reference error bit count range. In an exemplary embodiment, the minimum error bit count included in the first reference error bit count range may exceed the maximum error bit count included in the second reference error bit count range.

[0049] In an exemplary embodiment, the read reclaim controller 1211 may determine a corresponding reclaim period according to which a read reclaim operation is performed for each of the plurality of reclaim groups. In an exemplary embodiment, the read reclaim controller 1211 may apply a different corresponding reclaim period to the read reclaim operation for each of the plurality of reclaim groups.

[0050] In an exemplary embodiment, read reclaim controller 1211 may assign a plurality of memory blocks BLK1 to BLKz to reclaim groups and generate reclaim group information 1221. Reclaim group information 1221 includes ID information associated with corresponding memory blocks assigned to each of the plurality of reclaim groups and reclaim period information indicating a corresponding reclaim period applicable to each of the plurality of reclaim groups. In an exemplary embodiment, read reclaim controller 1211 may store reclaim group information 1221 in volatile memory 1220.

[0051] In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation for each of the plurality of reclaim groups based on the reclaim group information 1221. In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a corresponding read reclaim operation for each of the plurality of reclaim groups according to different reclaim periods indicated by reclaim period information included in the reclaim group information 1221. In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation for a first reclaim group according to a first reclaim period, and to perform a read reclaim operation for a second reclaim group according to a second reclaim period, and the second reclaim period may be shorter than the first reclaim period.

[0052] In an exemplary embodiment, the volatile memory 1220 may store information indicating a corresponding read count of each of the plurality of memory blocks BLK1 to BLKz. In an exemplary embodiment, the volatile memory 1220 may store information indicating a corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz.

[0053] In an exemplary embodiment, the volatile memory 1220 may store reclaim group information 1221. The reclaim group information 1221 may be information identifying a corresponding group memory block assigned to each of a plurality of reclaim groups, a corresponding applicable reclaim period for each of the plurality of reclaim groups, and a corresponding reference error bit count range associated with each of the plurality of reclaim groups.

[0054] Figure 2 is a diagram for explaining a change in threshold voltage distribution of memory cells according to an exemplary embodiment.

[0055] exist Figure 2 The horizontal axis of the graph represents the threshold voltage V of the memory cell. th , and the vertical axis of the graph represents the number of memory cells (number of cells).

[0056] refer to Figure 2 , a case where a memory cell is programmed as a four-level cell (QLC) for storing four-bit data will be described as an example. Figure 2 , the nonvolatile memory device 1100 may perform a program operation to store data in a plurality of memory cells included in the plurality of memory blocks BLK1 to BLKz in response to a program command of the memory controller 1200 .

[0057] The programming operation may involve programming each of the plurality of memory cells to one of a plurality of logic states. The plurality of logic states may include an erased state E and a first programming state P1 to a fifteenth programming state P15. Associated with each logic state may be a different corresponding programming voltage, which indicates that the threshold voltage V of the memory cell may be increased. th The erased state E may have an associated programming voltage V E , and the first to fifteenth program states P1 to P15 may have corresponding associated program voltages VP1 to VP 15 Thus, for example, a memory cell may be programmed to a first programmed state P1 by setting its threshold voltage to VP1.

[0058] When the nonvolatile memory device 1100 programs a memory cell, the actual threshold voltage V th can vary slightly from the "target" programming voltage associated with its logic state. For any given logic state, the achieved threshold voltage V th A distribution around an associated programming voltage may be assumed such that some threshold voltages are below the programming voltage while other threshold voltages exceed the programming voltage.

[0059] Figure 2 Depicts the voltage distribution D E and D P1 to D P15 , which shows the threshold voltage V that can be achieved when the memory cells are programmed to the erase state E and the first to fifteenth programmed states P1 to P15, respectively. th Example of voltage distribution D E and D P1 to D P15 Each of the voltage distributions D is approximately centered at the programming voltage associated with its corresponding logic state. E At approximately the programming voltage V associated with the erased state E E As the center, the voltage distribution D P1 At approximately the programming voltage V associated with the first programming state P1 P1 as the center, and so on.

[0060] In an exemplary embodiment, the nonvolatile memory device 1100 can read data stored in its memory cells according to a plurality of read voltages. The plurality of read voltages may include a first read voltage Vr1 to a fifteenth read voltage Vr15, and each of the first read voltage Vr1 to the fifteenth read voltage Vr15 may correspond to a corresponding programming state from a first programming state P1 to a fifteenth programming state P15. To read data from a memory cell, the nonvolatile memory device 1100 may detect the logic state of the memory cell based on a maximum read voltage that is less than the threshold voltage of the memory cell. For example, the nonvolatile memory device 1100 may detect the logic state of the memory cell for a memory cell having a voltage exceeding Vr1. P15 The fifteenth programming state P15 can be detected for cells with a threshold voltage exceeding V P14 But not more than V P15 , a cell having a threshold voltage of 1100, a fourteenth programmed state P14 is detected, and so on. In the depicted example involving QLC memory cells, each possible logical state can have a predefined association with a corresponding four-bit value, and thus by detecting the logical state of a memory cell, the nonvolatile memory device 1100 can read four bits of data from the memory cell.

[0061] In an exemplary embodiment, the threshold voltages of a plurality of memory cells may tend to degrade over time. Relative to cells programmed to any one of the first to fifteenth programmed states P1 to P15, the threshold voltages may tend to decrease over time such that they are respectively assumed to be lower relative to the voltage distribution D P1 to D P15 The degraded threshold voltage distribution D shifted to the left P1' to D P15' With respect to cells programmed to the erased state E, the threshold voltage may tend to increase (shift rightward) over time such that it assumes a voltage distribution D relative to the cell. E The degraded threshold voltage distribution D shifted to the right E' .

[0062] In an exemplary embodiment, as Figure 2 As shown, the voltage distribution shift associated with the degradation of the cell threshold voltage can cause the threshold voltage of some memory cells to become lower than the read voltage associated with their programmed logical state. As a result, their logical states and therefore the bits they contain may be misidentified. For example, for Figure 2In the example shown, for memory cells initially programmed to the fifteenth programmed state P15, voltage degradation causes the threshold voltage of approximately half of these cells to drop below the read voltage Vr15 associated with the fifteenth programmed state P15. As a result, approximately half of the cells intended to be in the fifteenth programmed state P15 may be incorrectly determined to be in the fourteenth programmed state P14 and therefore contain the four-bit value associated with the fourteenth programmed state P14 rather than the four-bit value associated with the fifteenth programmed state P15. Consequently, those memory cells may include erroneous bits.

[0063] In an exemplary embodiment, the threshold voltage of the plurality of memory cells may vary more over time for programmed states having higher associated programming voltages.

[0064] In an exemplary embodiment, the rate at which the threshold voltage of a memory cell storing a larger number of bits degrades may be greater than the rate at which the threshold voltage of a memory cell storing a smaller number of bits degrades. Thus, for example, the rate at which the threshold voltage of a four-level cell (QLC) that can store up to 4 bits of data per memory cell degrades may be greater than the rate at which the threshold voltage of a three-level cell (TLC) that can store up to 3 bits of data per memory cell degrades. In an exemplary embodiment, because the rate at which the threshold voltage of the QLC degrades is greater than the rate at which the threshold voltage of the TLC degrades, error bits may accumulate faster in the QLC than in the TLC. In an exemplary embodiment, because error bits may accumulate faster in the QLC, the QLC may benefit from operations for correcting error bits or operations for reading data including fewer error bits than uncorrectable error bits.

[0065] In an exemplary embodiment, since the error bits are caused by the threshold voltage of some memory cells being degraded to a voltage lower than their associated programming voltage, the storage device 1000 can perform a read reclamation operation on the memory block including those memory cells before the number of error bits in those memory cells becomes greater than the number of uncorrectable error bits.

[0066] In an exemplary embodiment, when four or more bits of data are stored in each of the plurality of memory cells, the threshold voltages of the plurality of memory cells vary more significantly over time. Therefore, the storage device 1000 may additionally perform an operation for correcting error bits or an operation for reading data including fewer error bits than uncorrectable error bits, thereby potentially degrading the performance of the storage device 1000. Therefore, the storage device 1000 may periodically perform a read reclaim operation on the plurality of memory blocks BLK1 to BLKz at a fixed interval before the number of error bits in the plurality of memory blocks BLK1 to BLKz becomes greater than the number of uncorrectable error bits. In an exemplary embodiment, the storage device 1000 may perform a read reclaim operation on the plurality of memory blocks BLK1 to BLKz when a predetermined time has passed since the last time a read operation was performed on each of the plurality of memory blocks BLK1 to BLKz, before the number of error bits in the plurality of memory blocks BLK1 to BLKz becomes greater than the number of uncorrectable error bits.

[0067] Figure 3 is a diagram for explaining a memory device that performs a read reclaim operation at a fixed period according to an exemplary embodiment.

[0068] refer to Figure 3 At a time point T0 , the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on the plurality of memory blocks BLK1 to BLKz.

[0069] In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on the plurality of memory blocks BLK1 to BLKz at a time point T1 after a fixed period (fixed period) has passed from the time point T0 .

[0070] In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on the plurality of memory blocks BLK1 to BLKz at each of time points T2, T3, and T4 having intervals of a fixed period (fixed period).

[0071] In an exemplary embodiment, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation on the plurality of memory blocks BLK1 to BLKz at a fixed period (fixed period).

[0072] In an exemplary embodiment, in data stored in one of the plurality of memory blocks BLK1 to BLKz, the number of uncorrectable error bits may be reached before a fixed period (fixed period) has passed. In an exemplary embodiment, in data stored in another of the plurality of memory blocks BLK1 to BLKz, the number of uncorrectable error bits may not be reached even after the fixed period has passed two or more times. In an exemplary embodiment, the corresponding number of error bits occurring in the data stored in the plurality of memory blocks BLK1 to BLKz may vary over time.

[0073] In an exemplary embodiment, when a read reclamation operation is performed with a fixed period (fixed period), the storage device 1000 can determine the corresponding error bit count of each of the multiple memory blocks BLK1 to BLKz, and determine different corresponding reclamation periods according to which the read reclamation operation is performed on each of the multiple memory blocks BLK1 to BLKz based on their corresponding error bit counts.

[0074] Figure 4 is a diagram for explaining a memory device that detects the number of error bits of a memory cell based on a reference program state according to an exemplary embodiment.

[0075] exist Figure 4 , the horizontal axis of the graph represents the threshold voltage Vth of the memory cell, and the vertical axis of the graph represents the number of memory cells (the number of cells).

[0076] refer to Figure 4 The read reclamation controller 1211 may control the nonvolatile memory device 1100 to perform a read reclamation operation on the plurality of memory blocks BLK1 to BLKz at a fixed period. When performing the read reclamation operation at the fixed period, the read reclamation controller 1211 may read data stored in the plurality of memory blocks BLK1 to BLKz and determine a corresponding error bit count for each of the plurality of memory blocks BLK1 to BLKz.

[0077] In an exemplary embodiment, the read recycling controller 1211 may be configured to generate a read voltage lower than a read voltage associated with a reference programmed state and higher than an offset voltage V based on the read voltage of the plurality of memory blocks BLK1 to BLKz. offset A corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz is determined based on a corresponding number of memory cells having a threshold voltage of 0.00447 W / m 2 .

[0078] In an exemplary embodiment, the reference programming state may be a programming state having a maximum associated rate of threshold voltage degradation. In an exemplary embodiment, the plurality of memory blocks BLK1 to BLKz may include QLC, and the reference programming state may be a fifteenth programming state P15. Figure 4 , a case where the reference program state is the fifteenth program state P15 will be described as an example.

[0079] In an exemplary embodiment, the read recycling controller 1211 may determine a corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz using a fifteenth read voltage Vr15 associated with the fifteenth program state P15 and an offset voltage Voffset. The offset voltage Voffset may be a voltage having a preset difference from the fifteenth read voltage Vr15.

[0080] Specifically, to determine the error bit count of a given memory block, the read recycling controller 1211 may control the nonvolatile memory device 1100 to apply the fifteenth read voltage Vr15 to determine the number of memory cells of the memory block having a threshold voltage exceeding the fifteenth read voltage, and apply the offset voltage V offset To determine the memory block has more than the offset voltage V offse The number of memory cells with a threshold voltage of t.

[0081] The read recycling controller 1211 may determine the error bit count of the memory block as the number of memory cells having a threshold voltage exceeding the fifteenth read voltage Vr15 divided by the number of memory cells having a threshold voltage exceeding the offset voltage V offset The difference between the threshold voltages of the memory cells.

[0082] Figure 5 is a diagram for explaining a memory device that detects the number of error bits of memory cells connected to a weak word line according to an exemplary embodiment.

[0083] refer to Figure 5 The first memory block BLK1, one of the plurality of memory blocks BLK1 to BLKz, may include a plurality of word lines WL1 to WLn connected between a string selection line SSL and a ground selection line GSL. A plurality of memory cells MC1 to MCn may be connected to each of the plurality of word lines WL1 to WLn.

[0084] In an exemplary embodiment, while performing a read reclaim operation at a fixed period, the read reclaim controller 1211 may read data stored in the plurality of memory blocks BLK1 to BLKz and determine a corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz.

[0085] In an exemplary embodiment, the read reclaim controller 1211 may determine a corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz based on the number of error bits of weak memory cells Weak_MC connected to weak word lines of the memory blocks.

[0086] In an exemplary embodiment, the weak word line of any given memory block may be the word line to which the memory cell with the largest associated rate of voltage degradation (weak memory cell or Weak_MC) is connected. The weak memory cells Weak_MC and weak word lines of the various memory blocks may be determined through testing performed during the production phase. Figure 5 In the illustrated example, the weak word line of the first memory block BLK1 is the first word line WL1 , and the weak memory cell Weak_MC including the first memory cell MC1 is connected to the first word line WL1 .

[0087] In an exemplary embodiment, the read recycling controller 1211 may detect the number of error bits of the weak memory cell Weak_MC connected to the weak word line using a plurality of read voltages and an offset voltage corresponding to the plurality of read voltages. In an exemplary embodiment, the read recycling controller 1211 may determine the corresponding error bit count of each of the plurality of memory blocks BLK1 to BLKz as the number of error bits in the weak memory cell Weak_MC connected to the corresponding weak word line of each of the plurality of memory blocks BLK1 to BLKz.

[0088] Figure 6 is a diagram for explaining a memory device that allocates memory blocks to reclaim groups based on error bit counts of the memory blocks, according to an exemplary embodiment.

[0089] refer to Figure 6 The read reclamation controller 1211 may control the nonvolatile memory device 1100 to perform a read reclamation operation on each of the plurality of memory blocks BLK1 to BLKz at a fixed period. When performing the read reclamation operation on each of the plurality of memory blocks BLK1 to BLKz, the read reclamation controller 1211 may read data stored in each of the plurality of memory blocks BLK1 to BLKz and determine a corresponding error bit count for each of the plurality of memory blocks BLK1 to BLKz.

[0090] In an exemplary embodiment, the read reclaim controller 1211 may assign each of the plurality of memory blocks BLK1 to BLKz to one of the plurality of reclaim groups based on an error bit count of the memory block. The read reclaim controller 1211 may assign the memory blocks to the reclaim groups based on a comparison of the error bit count of the memory block with a reference error bit count range. The read reclaim controller 1211 may assign each memory block to a reclaim group having an associated reference error bit count range that includes the error bit count of the memory block.

[0091] In an exemplary embodiment, the read reclaim controller 1211 may allocate memory blocks having error bit counts falling within a first reference error bit count range to a first reclaim group RC Group 1 .

[0092] In an exemplary embodiment, the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 may have error bit counts equal to or greater than a minimum value of the first reference error bit count range and equal to or less than a maximum value of the first reference error bit count range, and thus may be assigned to the first recycling group RC group 1.

[0093] In an exemplary embodiment, the read reclaim controller 1211 may allocate memory blocks having error bit counts falling within a second reference error bit count range to a second reclaim group RC Group 2 .

[0094] In an exemplary embodiment, the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 may have error bit counts equal to or greater than the minimum value of the second reference error bit count range and equal to or less than the maximum value of the second reference error bit count range, and thus may be assigned to the second recycling group RC group 2.

[0095] In an exemplary embodiment, a maximum value of the second reference error bit count range may be lower than a minimum value of the first reference error bit count range. In an exemplary embodiment, the number of error bits in each of the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 may be greater than the number of error bits in each of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8.

[0096] In an exemplary embodiment, the read reclaim controller 1211 may allocate memory blocks having error bit counts falling within a fifth reference error bit count range to a fifth reclaim group RC Group 5 .

[0097] In an exemplary embodiment, the third memory block BLK3, the fourth memory block BLK4, and the sixth memory block BLK6 may have error bit counts equal to or greater than the minimum value of the fifth reference error bit count range and equal to or less than the maximum value of the fifth reference error bit count range, and thus may be assigned to the fifth recycling group RC group 5.

[0098] In an exemplary embodiment, the maximum value of the fifth reference error bit count range may be lower than the minimum value of the second reference error bit count range. In an exemplary embodiment, the number of error bits in each of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 may be greater than the number of error bits in each of the third memory block BLK3, the fourth memory block BLK4, and the sixth memory block BLK6.

[0099] although Figure 6 An example is shown in which each of the plurality of memory blocks BLK1 to BLKz is assigned to one of the five reclaim groups RCGroup1 to RCGroup5, but four or fewer reclaim groups or six or more reclaim groups may be implemented.

[0100] Figure 7 is a diagram for explaining a memory device that generates reclaim group information based on an error bit count of a memory block, according to an exemplary embodiment.

[0101] refer to Figure 7 The read reclaim controller 1211 may assign the plurality of memory blocks BLK1 to BLKz to reclaim groups based on the respective error bit counts of the plurality of memory blocks BLK1 to BLKz, and generate reclaim group information 1221 associated with the plurality of reclaim groups.

[0102] In an exemplary embodiment, the read reclaim controller 1211 may generate ID information BLK ID indicating the ID of a memory block included in each of the plurality of reclaim groups. The read reclaim controller 1211 may generate reclaim period information RC Period indicating a reclaim period according to which a read reclaim operation is performed on each of the plurality of reclaim groups. The read reclaim controller 1211 may generate reference error bit count range information (reference error bit range) describing a reference error bit count range associated with each of the plurality of reclaim groups.

[0103] In an exemplary embodiment, the read recycling controller 1211 can assign multiple memory blocks BLK1 to BLKz to recycling groups, generate recycling group information 1221, and store the recycling group information 1221 in the volatile memory 1220, the recycling group information 1221 including ID information BLK ID for identifying the corresponding memory blocks assigned to each of the multiple recycling groups, reference error bit count range information (reference error bit range) and recycling period information RC period.

[0104] In an exemplary embodiment, the recycling group information 1221 may include information associated with the first recycling group RC Group 1 to the fifth recycling group RC Group 5. In an exemplary embodiment, the information associated with the first recycling group RC Group 1 to the fifth recycling group RC Group 5 may include ID information BLK ID indicating IDs of memory blocks included in the first recycling group RC Group 1 to the fifth recycling group RC Group 5.

[0105] In an exemplary embodiment, information associated with the first recycling group RC Group 1 may include ID information of the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9, and each of the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 may have an error bit count falling within a first reference error bit count range (first reference error bit range). In an exemplary embodiment, information associated with the second recycling group RC Group 2 may include ID information of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8, and each of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 may have an error bit count falling within a second reference error bit count range (second reference error bit range).

[0106] In an exemplary embodiment, the recycling group information 1221 may include reference error bit count range information (reference error bit range) corresponding to each of the first recycling group RC Group 1 to the fifth recycling group RC Group 5. In an exemplary embodiment, the recycling group information 1221 may include reference error bit count range information indicating that the reference error bit count range corresponding to the first recycling group RC Group 1 is a first reference error bit count range (first reference error bit range). In an exemplary embodiment, the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 included in the first recycling group RC Group 1 may have error bit counts that fall within the first reference error bit count range (first reference error bit range).

[0107] In an exemplary embodiment, the first reference error bit count range (first reference error bit range) may be a range higher than the second reference error bit count range (second reference error bit range). The second reference error bit count range (second reference error bit range) may be a range higher than the fifth reference error bit count range (fifth reference error bit range). In an exemplary embodiment, the number of error bits of each of the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 included in the first recycling group RC group 1 may be greater than the number of error bits of each of the memory blocks included in other recycling groups. In an exemplary embodiment, the number of error bits of each of the third memory block BLK3, the fourth memory block BLK4, and the sixth memory block BLK6 included in the fifth recycling group RC group 5 may be less than the number of error bits of each of the memory blocks included in other recycling groups.

[0108] In an exemplary embodiment, the recycling group information 1221 may include recycling period information RC period indicating the corresponding recycling period according to which the read recycling operation is performed on the first recycling group RC group 1 to the fifth recycling group RC group 5. In an exemplary embodiment, the recycling group information 1221 may include first recycling period information (period 1) indicating that the recycling period applicable to the first recycling group RC group 1 is the first recycling period. The recycling group information 1221 may include second recycling period information (period 2) indicating that the recycling period applicable to the second recycling group RC group 2 is the second recycling period. The recycling group information 1221 may include fifth recycling period information (period 5) indicating that the recycling period applicable to the fifth recycling group RC group 5 is the fifth period.

[0109] In an exemplary embodiment, the first recycling period may be shorter than the second recycling period. In an exemplary embodiment, the second recycling period may be shorter than the fifth recycling period. In an exemplary embodiment, the first recycling period may be shorter than a recycling period applicable to a read recycling operation performed on a recycling group other than the first recycling group. In an exemplary embodiment, the fifth recycling period may be longer than a recycling period applicable to a read recycling operation performed on a recycling group other than the fifth recycling group.

[0110] Figure 8 is a diagram for explaining a storage device that performs a read reclaim operation on different reclaim groups according to different reclaim periods, according to an exemplary embodiment.

[0111] Reference Figure 8 , the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on a plurality of reclaim groups based on the reclaim group information 1221 stored in the volatile memory 1220 .

[0112] In an exemplary embodiment, the read reclaim controller 1211 may identify the memory blocks included in the reclaim group based on the ID information of the memory blocks included in the reclaim group information 1221. The read reclaim controller 1211 may identify the reclaim period according to which the read reclaim operation RRC is performed on the reclaim group based on the reclaim period information included in the reclaim group information 1221.

[0113] In an exemplary embodiment, based on the reclaim group information 1221, the read reclaim controller 1211 may identify the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 as included in the first reclaim group, and identify the reclaim period according to which the read reclaim operation RRC is performed on the first reclaim group RC Group 1 as the first reclaim period Period 1. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the first reclaim group RC Group 1 according to the first reclaim period Period 1.

[0114] In an exemplary embodiment, at time point T0, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on the first reclaim group RC Group 1. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the first reclaim group RC Group 1 at each of time points T1, T2, T3, and T4 having an interval of the first reclaim period Period 1.

[0115] In an exemplary embodiment, based on the reclaim group information 1221, the read reclaim controller 1211 may identify the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 as included in the second reclaim group RC Group 2, and identify the reclaim period according to which the read reclaim operation RRC is performed on the second reclaim group RC Group 2 as the second period Period 2. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the second reclaim group RC Group 2 according to the second reclaim period Period 2.

[0116] In an exemplary embodiment, at time point T0, the read reclaim controller 1211 may control the nonvolatile memory device to perform a read reclaim operation RRC on the second reclaim group RC Group 2. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the second reclaim group RC Group 2 at each of time points T1, T2, T3, and T4 having an interval of the second reclaim period Period 2.

[0117] In an exemplary embodiment, the first recycling period Period 1 may be shorter than the second recycling period Period 2. In an exemplary embodiment, the number of error bits of each of the first memory block BLK1, the fifth memory block BLK5, and the ninth memory block BLK9 included in the first recycling group RC Group 1 may be greater than the number of error bits of each of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 included in the second recycling group RC Group 2.

[0118] In an exemplary embodiment, the storage device 1000 may perform read reclamation operations on a reclamation group including memory blocks having a larger number of error bits at a higher frequency than the frequency with which it performs read reclamation operations on a reclamation group including memory blocks having a smaller number of error bits, so as to prevent the memory blocks having a larger number of error bits from accumulating more than the number of uncorrectable error bits.

[0119] In an exemplary embodiment, based on the reclaim group information 1221, the read reclaim controller 1211 may identify the third memory block BLK3, the fourth memory block BLK4, and the sixth memory block BLK6 as included in the fifth reclaim group RC Group 5, and identify the reclaim period according to which the read reclaim operation RRC is performed on the fifth reclaim group RC Group 5 as the fifth reclaim period Period 5. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the fifth reclaim group RC Group 5 according to the fifth reclaim period Period 5.

[0120] In an exemplary embodiment, at time point T0, the read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform a read reclaim operation RRC on the fifth reclaim group RC Group 5. The read reclaim controller 1211 may control the nonvolatile memory device 1100 to perform the read reclaim operation RRC on the fifth reclaim group RC Group 5 at each of time points T1, T2, T3, and T4 having an interval of the fifth reclaim period Period 5.

[0121] In an exemplary embodiment, the fifth recycling period Period 5 may be longer than the second recycling period Period 2. In an exemplary embodiment, the number of error bits of each of the third memory block BLK3, the fourth memory block BLK4, and the sixth memory block BLK6 included in the fifth recycling group RC Group 5 may be smaller than the number of error bits of each of the second memory block BLK2, the seventh memory block BLK7, and the eighth memory block BLK8 included in the second recycling group RC Group 2.

[0122] In an exemplary embodiment, the storage device 1000 may perform read reclamation operations on a reclamation group including memory blocks having a smaller number of error bits at a lower frequency than the frequency with which it performs read reclamation operations on a reclamation group including memory blocks having a larger number of error bits, so as to prevent unnecessary performance of read reclamation operations on memory blocks having a smaller number of error bits.

[0123] Figure 9 is a diagram for explaining a storage device that performs a read reclaim operation based on reclaim group information according to an exemplary embodiment.

[0124] refer to Figure 9 In step S10, the storage device 1000 may perform a read-reclaim operation on a plurality of memory blocks.

[0125] In step S12, the memory device 1000 may detect the number of error bits in the plurality of memory blocks based on the results of the read reclaim operation. In an exemplary embodiment, the memory device 1000 may determine the number of error bits in the plurality of memory blocks based on the difference between the number of memory cells in the memory block having a threshold voltage exceeding a read voltage associated with a reference programming state and the number of memory cells in the memory block having a threshold voltage exceeding an offset voltage. The reference programming state may be a programming state with a maximum associated rate of threshold voltage degradation. In some examples, the memory device 1000 may determine the number of error bits in the memory block as the number of error bits in weak memory cells connected to a weak word line of the memory block.

[0126] In step S14, based on the number of error bits detected in step S12, the storage device 1000 may generate recycling group information associated with a plurality of recycling groups, each of the plurality of recycling groups including memory blocks having a number of error bits falling within the same reference error bit count range. In an exemplary embodiment, the recycling group information may include ID information indicating IDs of memory blocks included in each of the plurality of recycling groups, reference error bit count range information corresponding to each of the plurality of recycling groups, and recycling period information indicating a corresponding recycling period according to which a read recycling operation is performed on each of the plurality of recycling groups.

[0127] In step S16 , the storage device 1000 may perform a read reclaim operation on each of the plurality of reclaim groups having different corresponding reclaim periods based on the reclaim group information.

[0128] Figure 10 is a flowchart for explaining a storage device that performs corresponding read reclamation operations on two different reclamation groups according to two different reclamation periods, according to an exemplary embodiment.

[0129] Reference Figure 10 In step S20, the storage device 1000 may detect the number of error bits of the plurality of memory blocks based on a first read reclamation operation performed on the plurality of memory blocks according to a first reclamation period. The first reclamation period may correspond to the above reference period. Figure 3 In an exemplary embodiment, when performing a first read reclaim operation, the memory device 1000 may read data stored in a plurality of memory blocks and detect the number of error bits included in the data.

[0130] In step S22 , the memory device 1000 may compare the number of error bits of the plurality of memory blocks with a reference error bit range.

[0131] In step S24 , the memory device 1000 may determine a first memory block having a number of error bits falling within a first reference error bit count range as a first recycling group.

[0132] In step S26, the storage device 1000 may perform a second read reclaim operation on the first reclaim group according to a second reclaim period. In an exemplary embodiment, the second reclaim period may be shorter than the first reclaim period.

[0133] In step S28, the storage device 1000 may determine the second memory blocks having a number of error bits falling within a second reference error bit count range as a second recycling group. In an exemplary embodiment, the second reference error bit count range may be a range lower than the first reference error bit count range. In an exemplary embodiment, the number of error bits in each of the second memory blocks may be less than the number of error bits in each of the first memory blocks.

[0134] In step S30, the storage device 1000 may perform a third read reclaim operation on the second reclaim group according to a third reclaim period. In an exemplary embodiment, the third reclaim period may be longer than the first reclaim period.

[0135] Figure 11 is a diagram for explaining a nonvolatile memory device according to an exemplary embodiment.

[0136] refer to Figure 11 , a nonvolatile memory device (NVM) 1100 may include a memory cell array 110 , a voltage generator 120 , a row decoder 130 , a page buffer group 140 , and control logic 150 .

[0137] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the row decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 140 through bit lines BL.

[0138] Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In example embodiments, the plurality of memory cells may be nonvolatile memory cells.

[0139] The voltage generator 120 may generate the operating voltage Vop using an external power supply voltage provided to the nonvolatile memory device 1100. The voltage generator 120 may operate in response to the control of the control logic 150.

[0140] In an exemplary embodiment, the voltage generator 120 may generate an operating voltage Vop to be used in a program operation, a read operation, and an erase operation. For example, the voltage generator 120 may generate an erase voltage, a program voltage, a pass voltage, and a read voltage. The operating voltage Vop may be supplied to the memory cell array 110 by the row decoder 130.

[0141] The row decoder 130 may be connected to the memory cell array 110 through row lines RL. The row lines RL may include a drain select line, a word line, and a source select line.

[0142] The row decoder 130 may be configured to operate in response to the control of the control logic 150. The row decoder 130 may receive a row address X-ADDR from the control logic 150. In an exemplary embodiment, the row decoder 130 may select at least one word line from a plurality of word lines based on the row address X-ADDR and apply the operating voltage Vop provided from the voltage generator 120 to the at least one word line.

[0143] In an exemplary embodiment, during a program operation, the row decoder 130 may apply a program voltage to a word line selected from a plurality of word lines and apply a pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 130 may apply a verification voltage to a selected word line and apply a verification pass voltage having a level higher than the verification voltage to unselected word lines.

[0144] During a read operation, the row decoder 130 may apply a read voltage to a selected word line and apply a read pass voltage having a higher level than the read voltage to unselected word lines.

[0145] The page buffer group 140 may include a plurality of page buffers PB1 to PBn. The plurality of page buffers PB1 to PBn may be connected to the memory cell array 110 through bit lines BL, respectively. The plurality of page buffers PB1 to PBn may operate in response to control of the control logic 150.

[0146] In an exemplary embodiment, the plurality of page buffers PB1 to PBn may receive data DATA from the outside and may select at least one bit line from the bit lines BL based on a column address Y-ADDR received from the control logic 150 .

[0147] In an exemplary embodiment, during a program operation, the plurality of page buffers PB1 to PBn may transmit data received from the outside to the memory cells of the memory cell array 110 through the bit lines BL. The memory cells may be programmed according to the received data. During a program verification operation, the plurality of page buffers PB1 to PBn may sense the data stored in the memory cells through the bit lines BL.

[0148] During a read operation, the plurality of page buffers PB1 to PBn may sense data stored in memory cells through the bit lines BL and store the sensed data in the plurality of page buffers PB1 to PBn.

[0149] The control logic 150 may be connected to the voltage generator 120, the row decoder 130, and the page buffer group 140. The control logic 150 may be configured to control the overall operation of the nonvolatile memory device 1100. The control logic 150 may operate in response to a command CMD received from the outside. The control logic 150 may generate various signals in response to the command CMD and the address ADDR to control the voltage generator 120, the row decoder 130, and the page buffer group 140.

[0150] While the invention has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage device comprising: a non-volatile memory device comprising a plurality of memory blocks; as well as Storage controller, configured as: determining a plurality of error bit counts, each of the plurality of error bit counts indicating a number of error bits for a corresponding memory block of the plurality of memory blocks; generating, based on the plurality of error bit counts, reclaim group information associated with a plurality of reclaim groups, the reclaim group information indicating, for each of the plurality of memory blocks, a corresponding assigned reclaim group from the plurality of reclaim groups, wherein each of the plurality of reclaim groups is associated with a corresponding error bit count range; and The nonvolatile memory device is controlled to perform a corresponding read reclamation operation for each of the plurality of reclamation groups based on the reclamation group information, wherein the corresponding read reclamation operation is performed according to a different reclamation period for each of the plurality of reclamation groups.

2. The storage device according to claim 1, wherein: The reclaim group information includes reclaim period information indicating a corresponding reclaim period for each of the plurality of reclaim groups.

3. The storage device according to claim 1, wherein: The memory controller is configured to generate the reclaim group information based on comparing the plurality of error bit counts to a reference error bit count range.

4. The storage device according to claim 3, wherein: The plurality of recycling groups include: a first reclaimed group comprising a first group of memory blocks of the plurality of memory blocks, the first group of memory blocks having associated error bit counts that fall within a first reference error bit count range; and A second reclaimed group includes a second group of memory blocks in the plurality of memory blocks, the second group of memory blocks having associated error bit counts that fall within a second reference error bit count range.

5. The storage device according to claim 4, wherein: The corresponding read reclamation operation for the first reclamation group is performed according to a first reclamation period, and the corresponding read reclamation operation for the second reclamation group is performed according to a second reclamation period different from the first reclamation period.

6. The storage device according to claim 5, wherein: The first recycling period is shorter than the second recycling period; and The associated error bit counts of the first group of memory blocks included in the first reclaim group are greater than the associated error bit counts of the second group of memory blocks included in the second reclaim group.

7. The storage device according to claim 1, wherein: The memory controller is configured to determine the plurality of error bit counts based on a reference programming state, wherein the reference programming state is one of a plurality of programming states recognized by the memory controller. The storage device according to claim 7 , wherein: The storage controller is configured to: For each of the plurality of memory blocks, a respective associated error bit count is determined based on a number of memory cells of the memory block having a threshold voltage below a read voltage associated with the reference programmed state and above an offset voltage.

9. The storage device according to claim 8, wherein: The read voltage associated with the reference programmed state is higher than the corresponding read voltage associated with each other programmed state of the plurality of programmed states.

10. A storage device comprising: a non-volatile memory device comprising a plurality of memory blocks; as well as Storage controller, configured as: assigning a first group of memory blocks of the plurality of memory blocks to a first recycling group, the first group of memory blocks having respective error bit counts that fall within a first reference error bit count range; assigning a second group of memory blocks of the plurality of memory blocks to a second recycling group, the second group of memory blocks having respective error bit counts that fall within a second reference error bit count range; as well as The nonvolatile memory device is controlled to perform a read reclamation operation on the first reclamation group according to a first reclamation period, and to perform a read reclamation operation on the second reclamation group according to a second reclamation period different from the first reclamation period.

11. The storage device according to claim 10, wherein: a minimum error bit count included in the first reference error bit count range exceeds a maximum error bit count included in the second reference error bit count range; and The first recovery period is shorter than the second recovery period.

12. The storage device according to claim 10, wherein: The storage controller is configured to: The respective error bit counts of the first group of memory blocks and the respective error bit counts of the second group of memory blocks are determined based on read reclamation operations performed on the plurality of memory blocks.

13. The storage device according to claim 12, wherein: The storage controller is configured to generate reclaim group information including first reclaim period information indicating the first reclaim period and second reclaim period information indicating the second reclaim period.

14. The storage device according to claim 10, wherein: The memory controller is configured to control the nonvolatile memory device to migrate data stored in the first group of memory blocks and data stored in the second group of memory blocks to free blocks when performing the corresponding read reclamation operations on the first reclamation group and the second reclamation group.

15. The storage device according to claim 10, wherein The storage controller is configured to: determining the respective error bit counts of the first group of memory blocks based on a number of error bits of memory cells connected to respective weak word lines of the first group of memory blocks; as well as The respective error bit counts of the second group of memory blocks are determined based on a number of error bits of memory cells connected to respective weak word lines of the second group of memory blocks.

16. The storage device according to claim 10, wherein: Each of the plurality of memory blocks includes a plurality of memory cells; and Each of the plurality of memory cells is programmable to store at least 4 bits of data.

17. A storage controller comprising: a memory interface configured to communicate with a nonvolatile memory device comprising a plurality of memory blocks; as well as Read the recycling controller, which is configured as: controlling the nonvolatile memory device to perform a read reclaim operation on the plurality of memory blocks; determining a plurality of error bit counts based on the read reclaim operations performed on the plurality of memory blocks, the plurality of error bit counts comprising a respective error bit count for each of the plurality of memory blocks; as well as Based on the plurality of error bit counts, a first group of memory blocks for which read reclamation operations are performed according to a first reclamation period and a second group of memory blocks for which read reclamation operations are performed according to a second reclamation period longer than the first reclamation period are identified from the plurality of memory blocks.

18. The storage controller according to claim 17, wherein: The read reclamation controller is configured to control the nonvolatile memory device to perform the read reclamation operation on the plurality of memory blocks according to a third reclamation period that is longer than the first reclamation period and shorter than the second reclamation period.

19. The memory controller of claim 17, wherein: The respective error bit counts of the first group of memory blocks fall within a first reference error bit count range, and the respective error bit counts of the second group of memory blocks fall within a second reference error bit count range, wherein a minimum error bit count included in the first reference error bit count range exceeds a maximum error bit count included in the second reference error bit count range.

20. The memory controller of claim 17, wherein: each of the plurality of memory blocks comprising a corresponding plurality of memory cells; In each of the plurality of memory blocks, each of the corresponding plurality of memory cells is programmable to any one of a plurality of programming states, the plurality of programming states including an erased state and first to fifteenth programming states; as well as The read reclamation controller is configured to determine, for each of the plurality of memory blocks, the respective error bit count based on a number of memory cells of the memory block having a threshold voltage below a read voltage associated with the fifteenth programmed state and above an offset voltage.

Images