Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor chip includes: a command address input circuit configured to generate a rising command address and a falling command address by receiving an external command address, and configured to output the rising command address and the falling command address to a through electrode; and a test circuit configured to generate a detection signal by latching the remaining one of the rising command address and the falling command address as any one of the rising command address and the falling command address, and a detection unit configured to detect a fault in transmission of the rising command address and the falling command address by detecting a logic level of the detection signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0036098 filed on March 14, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of the present disclosure relate generally to semiconductor devices, and more particularly, to a semiconductor device including a semiconductor chip configured to detect a failure in transmission of a command address output through a signal path. Background Art

[0003] With the development of technology for manufacturing semiconductor chips, packaging technology for multiple memory chips used to implement semiconductor chips has gradually improved the integration and performance of semiconductor chips. In the packaging technology used to implement semiconductor chips, in addition to the two-dimensional structure in which multiple memory chips are placed flat on a printed circuit board (PCB), technologies related to three-dimensional structures in which multiple memory chips are stacked vertically have been developed in various ways. Semiconductor chips with three-dimensional structures can be implemented by stacking multiple memory chips via through silicon vias (TSVs) (hereinafter referred to as "through electrodes"), or by stacking multiple memory chips via wire bonding, such as high-bandwidth memory (HBM).

[0004] The plurality of memory chips perform operations by receiving command addresses for controlling the operations of the memory chips via the plurality of through-electrodes. When a failure occurs in the transmission of the command addresses received via the plurality of through-electrodes, all the plurality of memory chips are considered to have failed, and therefore an operation is required to detect the failure in the transmission of the command addresses. Summary of the Invention

[0005] In one embodiment, a semiconductor chip may include: a command address input circuit configured to generate a rising command address and a falling command address by receiving an external command address, and configured to output the rising command address and the falling command address to a through electrode; and a test circuit configured to generate a detection signal by latching any one of the rising command address and the falling command address as the remaining one of the rising command address and the falling command address, and configured to detect a fault in the transmission of the rising command address and the falling command address by detecting the logic level of the detection signal.

[0006] In one embodiment, a semiconductor chip may include: a command address input circuit configured to generate a first rising command address and a second rising command address and a first falling command address and a second falling command address by receiving first to fourth external command addresses, and configured to output the first rising command address and the second rising command address and the first falling command address and the second falling command address to a through electrode; and a test circuit configured to generate a first detection signal and a second detection signal by latching any one of the first rising command address and the second rising command address and the first falling command address and the second falling command address as the remaining one of the first rising command address and the second rising command address and the first falling command address and the second falling command address, and configured to detect a fault in the transmission of the first rising command address and the second rising command address and the first falling command address and the second falling command address when the first detection signal and the second detection signal are different from a set value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a configuration of a semiconductor chip according to an embodiment of the present disclosure.

[0008] Figure 2 It shows that according to Figure 1 is a block diagram of a configuration of an embodiment of a base chip included in a semiconductor chip shown in .

[0009] Figure 3 is a timing diagram for describing an external command address input in synchronization with an external clock signal according to an embodiment of the present disclosure.

[0010] Figure 4 is used to describe Figure 2 1 is a timing diagram of an embodiment of the operation of the clock generation circuit included in the base chip shown in FIG.

[0011] Figure 5 is used to describe Figure 2 1 is a timing diagram of an embodiment of the operation of the command address input circuit included in the base chip shown in FIG.

[0012] Figure 6 It shows that according to Figure 2 is a block diagram of the construction of an embodiment of a test circuit included in a base chip shown in .

[0013] Figure 7 is used to describe Figure 6 1 is a timing diagram of an embodiment of the operation of the frequency dividing circuit included in the test circuit shown in FIG.

[0014] Figure 8 It shows that according to Figure 6 2 is a diagram of a configuration of an embodiment of a comparison circuit included in a test circuit shown in FIG.

[0015] Figure 9 is a table for describing an operation of detecting a failure in transmission of a command address by a semiconductor chip according to an embodiment of the present disclosure.

[0016] Figure 10 is a diagram for describing a three-dimensional structure of a semiconductor chip according to an embodiment of the present disclosure.

[0017] Figure 11 It shows that the Figures 1 to 10 A diagram illustrating the configuration of an embodiment of an electronic system of a semiconductor chip is shown. DETAILED DESCRIPTION

[0018] In the following description of the embodiment, the term "preset" means that when a parameter is used in a process or algorithm, the value of the parameter is predetermined. According to one embodiment, the value of the parameter can be set when the process or algorithm starts or when the process or algorithm is executed.

[0019] Terms such as "first" and "second" used to distinguish between multiple components are not limited to the components. For example, the first component can be called the second component, and vice versa.

[0020] When a component is referred to as being “coupled” or “connected” to another component, it should be understood that the components may be directly coupled or connected to each other or coupled or connected to each other with another component disposed therebetween. Conversely, when a component is referred to as being “directly coupled” or “directly connected” to another component, it should be understood that the components are directly coupled or connected to each other without another component disposed therebetween.

[0021] "Logical high level" and "logical low level" are used to describe the logic levels of a signal. A signal having a "logical high level" is distinguished from a signal having a "logical low level". For example, when a signal having a first voltage corresponds to a signal having a "logical high level", a signal having a second voltage may correspond to a signal having a "logical low level". According to one embodiment, the "logical high level" may be set to a voltage higher than the voltage of the "logical low level". According to one embodiment, the logic levels of a signal may be set to different logic levels or opposite logic levels. For example, a signal having a logical high level may be set to have a logical low level in some embodiments, and a signal having a logical low level may be set to have a logical high level in some embodiments.

[0022] The present disclosure will be described in more detail below through examples. The examples are only used to illustrate the present disclosure, and the scope of the present disclosure is not limited by the examples.

[0023] like Figure 1As shown, the semiconductor chip 1 according to an embodiment of the present disclosure may include a base chip 10 , a first memory chip 20 , a second memory chip 30 , a third memory chip 40 and a fourth memory chip 50 .

[0024] The base chip 10 may be electrically connected to the first bump BUMP1, the second bump BUMP2, and the first signal path TSV1. The first bump BUMP1, the second bump BUMP2, and the first signal path TSV1 may be electrically connected.

[0025] The base chip 10 may include a test circuit (TEST CIR) 210 .

[0026] The test circuit 210 may be included in a through-electrode region ( Figure 2 200 in the test circuit 210. The test circuit 210 can be configured to execute the command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 The remaining one of CAF<1:2> in the rising command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 CAF<1:2>) to generate a detection signal ( Figure 6 DT<1:2> in ). The test circuit 210 can detect the detection signal ( Figure 6 DT<1:2>) to detect the rising command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 CAF<1:2>) in the transmission. When the detection signal ( Figure 6 When DT<1:2> in ) is different from the set value, the test circuit 210 can detect the rising command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 A failure occurred during the transfer of CAF<1:2> in the SPI.

[0027] The basic chip 10 can increase the command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 The remaining one of CAF<1:2> in the rising command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 CAF<1:2>) to generate a detection signal ( Figure 6 DT<1:2> in ). The basic chip 10 can detect the detection signal ( Figure 6 DT<1:2>) to detect the rising command address ( Figure 2 CAR<1:2> in the ) and the falling command address ( Figure 2 A fault in the transmission of CAF<1:2> in the SPI.

[0028] The first memory chip 20 may be electrically connected to the second bump BUMP2, the third bump BUMP3, and the second signal path TSV2. The second bump BUMP2, the third bump BUMP3, and the second signal path TSV2 may be electrically connected. The first memory chip 20 may be stacked on the base chip 10 through the second bump BUMP2 and the second signal path TSV2. The first memory chip 20 may be electrically connected to the base chip 10 through the second bump BUMP2 and the second signal path TSV2. The first memory chip 20 may be electrically connected to the second memory chip 30 through the second signal path TSV2 and the third bump BUMP3.

[0029] The first memory chip 20 may store transmission data ( Figure 2 TD<1:N> in the first memory chip 20). After the read operation starts, the first memory chip 20 can transfer the transmission data ( Figure 2 TD<1:N> in the SPI<1:1> are output to the basic chip 10.

[0030] The second memory chip 30 may be electrically connected to the third bump BUMP3, the fourth bump BUMP4, and the third signal path TSV3. The third bump BUMP3, the fourth bump BUMP4, and the third signal path TSV3 may be electrically connected. The second memory chip 30 may be stacked on the first memory chip 20 through the third bump BUMP3 and the third signal path TSV3. The second memory chip 30 may be electrically connected to the first memory chip 20 through the third bump BUMP3 and the third signal path TSV3. The second memory chip 30 may be electrically connected to the third memory chip 40 through the third signal path TSV3 and the fourth bump BUMP4.

[0031] The second memory chip 30 may store the transmission data ( Figure 2 TD<1:N> in the second memory chip 30). After the read operation starts, the second memory chip 30 can transfer the transmission data ( Figure 2 TD<1:N> in the SPI<1:1> are output to the basic chip 10.

[0032] The third memory chip 40 may be electrically connected to the fourth bump BUMP4, the fifth bump BUMP5, and the fourth signal path TSV4. The fourth bump BUMP4, the fifth bump BUMP5, and the fourth signal path TSV4 may be electrically connected. The third memory chip 40 may be stacked on the second memory chip 30 through the fourth bump BUMP4 and the fourth signal path TSV4. The third memory chip 40 may be electrically connected to the second memory chip 30 through the fourth bump BUMP4 and the fourth signal path TSV4. The third memory chip 40 may be electrically connected to the fourth memory chip 50 through the fourth signal path TSV4 and the fifth bump BUMP5.

[0033] The third memory chip 40 may store transmission data ( Figure 2 TD<1:N> in the third memory chip 40). After the read operation starts, the third memory chip 40 can transfer the transmission data ( Figure 2 TD<1:N> in the SPI<1:1> are output to the basic chip 10.

[0034] The fourth memory chip 50 may be electrically connected to the fifth bump BUMP5 and the fifth signal path TSV5. The fifth bump BUMP5 and the fifth signal path TSV5 may be electrically connected. The fourth memory chip 50 may be stacked on the third memory chip 40 through the fifth bump BUMP5 and the fifth signal path TSV5. The fourth memory chip 50 may be electrically connected to the third memory chip 40 through the fifth bump BUMP5 and the fifth signal path TSV5.

[0035] The fourth memory chip 50 may store the transmission data ( Figure 2 TD<1:N> in the fourth memory chip 50). After the read operation starts, the fourth memory chip 50 can store the transmission data ( Figure 2 TD<1:N> in the SPI<1:1> are output to the basic chip 10.

[0036] The first bump BUMP1, the second bump BUMP2, the third bump BUMP3, the fourth bump BUMP4 and the fifth bump BUMP5 can all be implemented in the form of balls implemented by using conductive materials so as to be directly connected to the circuit board. The first bump BUMP1, the second bump BUMP2, the third bump BUMP3, the fourth bump BUMP4 and the fifth bump BUMP5 can all be implemented to include multiple bumps. The first signal path TSV1, the second signal path TSV2, the third signal path TSV3, the fourth signal path TSV4 and the fifth signal path TSV5 can all be implemented as through-electrodes, which are implemented as through-silicon vias (TSVs). The first signal path TSV1, the second signal path TSV2, the third signal path TSV3, the fourth signal path TSV4 and the fifth signal path TSV5 can all be implemented to include multiple through-electrodes.

[0037] exist Figure 1 , the first to fourth memory chips 20, 30, 40, and 50 have been implemented to be stacked on the base chip 10. However, according to an embodiment, various numbers of memory chips (eg, 8 or 16) may be implemented to be stacked on the base chip 10.

[0038] Figure 1 The semiconductor chip 1 shown in FIG has been implemented such that the base chip 10 and the first to fourth memory chips 20 to 50 are implemented to be stacked through through electrodes, like a high bandwidth memory (HBM). However, according to one embodiment, Figure 1 The semiconductor chip 1 shown in FIG may be implemented such that a plurality of memory chips are implemented as stacked by wire bonding. According to an embodiment, wire bonding may be provided as a signal path for signals input and output to and from the base chip 10 and the first to fourth memory chips 20 to 50.

[0039] Figure 2 It shows that according to Figure 1 0 is a block diagram of a configuration of an embodiment of a base chip 10 included in a semiconductor chip 1 shown in 0. The base chip 10 may include an interface region 100 and a through-electrode region 200.

[0040] The interface region 100 may include a clock generation circuit (CLK GEN) 110, a command address input circuit (CA IN) 120, and a data input / output circuit (DATA IN / OUT) 130. The interface region 100 may be provided as a region including circuits for controlling operations of the first to fourth memory chips 20, 30, 40, and 50.

[0041] The clock generation circuit 110 can receive the external clock signal ECK through the bump B1. The clock generation circuit 110 can generate a rising clock signal RCLK and a falling clock signal FCLK based on the external clock signal ECK. The clock generation circuit 110 can generate a rising clock signal RCLK including a pulse generated synchronously with the rising edge of the external clock signal ECK. The clock generation circuit 110 can generate a falling clock signal FCLK including a pulse generated synchronously with the falling edge of the external clock signal ECK. The external clock signal ECK can be set to a signal that switches periodically so as to synchronize the operations of the base chip 10 and the first to fourth memory chips 20, 30, 40 and 50. The clock generation circuit 110 can output the rising clock signal RCLK and the falling clock signal FCLK through the through-electrode TSV11. The rising clock signal RCLK and the falling clock signal FCLK can be set to signals having opposite phases and being switched periodically. The following can be referred to Figure 4 The operation of generating the rising clock signal RCLK and the falling clock signal FCLK based on the external clock signal ECK by the clock generation circuit 110 is described.

[0042] The command address input circuit 120 can generate the first rising command address and the second rising command address CAR<1:2> and the first falling command address and the second falling command address CAF<1:2> based on the first to fourth external command addresses ECA<1:4> in synchronization with the rising clock signal RCLK and the falling clock signal FCLK. The command address input circuit 120 can latch the first external command address ECA by synchronizing with the rising edge of the rising clock signal RCLK. <1> To generate the first rising command address CAR <1> The command address input circuit 120 can latch the third external command address ECA by synchronizing with the rising edge of the rising clock signal RCLK. <3> To generate the second rising command address CAR <2> The command address input circuit 120 can latch the second external command address ECA by synchronizing with the rising edge of the falling clock signal FCLK. <2> To generate the first falling command address CAF <1> The command address input circuit 120 may latch the fourth external command address ECA by synchronizing with the rising edge of the falling clock signal FCLK. <4> To generate the second falling command address CAF <2> . The command address input circuit 120 can output the first rising command address and the second rising command address CAR<1:2> and the first falling command address and the second falling command address CAF<1:2> through the through electrode TSV12. The first to fourth external command addresses ECA<1:4> can each be set to include a signal of a command and an address for controlling the operation of each of the first to fourth memory chips 20, 30, 40 and 50. In one embodiment, the first to fourth external command addresses ECA<1:4> are signals input serially from the outside of the base chip 10. In one embodiment, the first to fourth external command addresses ECA<1:4> are signals input serially from the outside of the semiconductor chip 1. In one embodiment, the first to fourth external command addresses ECA<1:4> are signals input serially from the outside of the test circuit 210. The following can refer to Figure 5 The operation of generating first and second rising command addresses CAR<1:2> and first and second falling command addresses CAF<1:2> based on first to fourth external command addresses ECA<1:4> by the command address input circuit 120 in synchronization with the rising clock signal RCLK and the falling clock signal FCLK is described.

[0043] The data input / output circuit 130 may receive the first to Nth data DATA<1:N> through the bump B3 after a write operation starts. The data input / output circuit 130 may generate the first to Nth transmission data TD<1:N> from the first to Nth data DATA<1:N> after a write operation starts. The data input / output circuit 130 may output the first to Nth transmission data TD<1:N> through the through-electrodes TSV13 after a write operation starts. The data input / output circuit 130 may output the first to Nth transmission data TD<1:N> to the first to fourth memory chips 20, 30, 40, and 50 through the through-electrodes TSV13 after a write operation starts. The data input / output circuit 130 may receive the first to Nth transmission data TD<1:N> through the through-electrodes TSV13 after a read operation starts. The data input / output circuit 130 may receive the first to Nth transmission data TD<1:N> from the first to fourth memory chips 20, 30, 40, and 50 through the through-electrodes TSV13 after a read operation starts. The data input-output circuit 130 may generate first to Nth data DATA<1:N> from the first to Nth transmission data TD<1:N> after the start of the read operation. The data input-output circuit 130 may output the first to Nth data DATA<1:N> through the bump B3 after the start of the read operation.

[0044] The through-electrode region 200 may include a test circuit 210. The through-electrode region 200 may be provided as a region including a plurality of through-electrodes.

[0045] The test circuit 210 may receive a rising clock signal RCLK and a falling clock signal FCLK through the through-electrode TSV11. The test circuit 210 may receive a first rising command address and a second rising command address CAR<1:2> and a first falling command address and a second falling command address CAF<1:2> through the through-electrode TSV12. The test circuit 210 may latch the remaining one of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> as any one of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>. The test circuit 210 may generate a first detection signal and a second detection signal ( Figure 6 DT<1:2> in ). The test circuit 210 can detect the first detection signal and the second detection signal ( Figure 6 The logic level of DT<1:2> in the DT<1:2> is used to detect the failure in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>. Figure 6 When the first detection signal and the second detection signal ( DT<1:2> in ) are different from the set value, the test circuit 210 can detect that a failure has occurred in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>. Figure 6 When DT<1:2> in CAR<1:2> is the same as the set value, the test circuit 210 can detect that no failure occurs in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>.

[0046] Figure 3 is a timing diagram for describing an external command address input in synchronization with an external clock signal according to an embodiment of the present disclosure. The first to fourth external command addresses ECA<1:4> input in synchronization with the external clock signal ECK may refer to Figure 3 Description is as follows.

[0047] At time T1, that is, the rising edge of the external clock signal ECK, the first external command address ECA <1> Can be entered.

[0048] At time T2, that is, the falling edge of the external clock signal ECK, the second external command address ECA <2> Can be entered.

[0049] At time T3, that is, the rising edge of the external clock signal ECK, the third external command address ECA <3> Can be entered.

[0050] At time T4, that is, the falling edge of the external clock signal ECK, the fourth external command address ECA <4> Can be entered.

[0051] Figure 4 is used to describe Figure 2 The operation of the clock generation circuit 110 to generate the rising clock signal RCLK and the falling clock signal FCLK based on the external clock signal ECK can be referred to as the timing diagram of the embodiment of the operation of the clock generation circuit included in the basic chip shown in FIG. Figure 4 Description is as follows.

[0052] At time T11 , the clock generation circuit 110 may generate a rising clock signal RCLK including pulses periodically generated in synchronization with a rising edge of the external clock signal ECK.

[0053] At time T12 , the clock generation circuit 110 may generate a falling clock signal FCLK including pulses periodically generated in synchronization with a falling edge of the external clock signal ECK.

[0054] The rising clock signal RCLK and the falling clock signal FCLK may be generated by being periodically switched in opposite phases.

[0055] Figure 5 is used to describe Figure 2 The timing diagram of an embodiment of the operation of the command address input circuit included in the basic chip shown in FIG. The operation of generating the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> based on the first to fourth external command addresses ECA<1:4> by the command address input circuit 120 in synchronization with the rising clock signal RCLK and the falling clock signal FCLK can be referred to. Figure 5 is described below.

[0056] At time T21, the command address input circuit 120 may latch the first external command address ECA in synchronization with the rising edge of the rising clock signal RCLK. <1> To generate the first rising command address CAR <1> .

[0057] At time T22, the command address input circuit 120 may latch the second external command address ECA in synchronization with the rising edge of the falling clock signal FCLK. <2> To generate the first falling command address CAF <1> .

[0058] At time T23, the command address input circuit 120 may latch the third external command address ECA in synchronization with the rising edge of the rising clock signal RCLK. <3> To generate the second rising command address CAR <2> .

[0059] At time T24, the command address input circuit 120 may latch the fourth external command address ECA in synchronization with the rising edge of the falling clock signal FCLK. <4> To generate the second falling command address CAF <2> .

[0060] Figure 6 It shows that according to Figure 2 A block diagram of the configuration of an embodiment of a test circuit included in a basic chip shown in FIG. Figure 6 The test circuit 210 may include a frequency dividing circuit (DIV CIR) 211 , a test mode signal generating circuit (TM GEN) 212 , a comparison circuit (CMP CIR) 213 , an output pad 214 , and a fault detection circuit (FAIL DET CIR) 215 .

[0061] The frequency dividing circuit 211 can generate a first frequency-divided clock signal DCK1 and a second frequency-divided clock signal (DCK2) by dividing the frequencies of the rising clock signal RCLK and the falling clock signal FCLK. Figure 7 DCK2 in), the third divided clock signal ( Figure 7DCK3 in) and the fourth divided clock signal ( Figure 7 The frequency dividing circuit 211 can generate a first frequency-divided clock signal DCK1 including a pulse generated in synchronization with the rising edge of the rising clock signal RCLK. The frequency dividing circuit 211 can generate a first frequency-divided clock signal DCK1 having a frequency 1 / 2 of the frequency of the rising clock signal RCLK in synchronization with the rising edge of the rising clock signal RCLK. The frequency dividing circuit 211 can generate a second frequency-divided clock signal ( Figure 7 The frequency dividing circuit 211 can generate a second frequency-divided clock signal (DCK2) having a frequency of 1 / 2 of the frequency of the falling clock signal FCLK in synchronization with the rising edge of the falling clock signal FCLK. Figure 7 The frequency dividing circuit 211 may generate a third frequency-divided clock signal (DCK2) including a pulse generated in synchronization with the rising edge of the rising clock signal RCLK. Figure 7 The frequency dividing circuit 211 can generate a third frequency-divided clock signal (DCK3) having a frequency of 1 / 2 of the frequency of the rising clock signal RCLK in synchronization with the rising edge of the rising clock signal RCLK. Figure 7 The frequency dividing circuit 211 may generate a fourth frequency-divided clock signal (DCK3) including a pulse generated in synchronization with the rising edge of the falling clock signal FCLK. Figure 7 The frequency dividing circuit 211 can generate a fourth frequency-divided clock signal (DCK4) having a frequency of 1 / 2 of the frequency of the falling clock signal FCLK in synchronization with the rising edge of the falling clock signal FCLK. Figure 7 The frequency dividing circuit 211 may output a first frequency-divided clock signal DCK1. The frequency dividing circuit 211 has been implemented to output the first frequency-divided clock signal DCK1. However, according to one embodiment, the frequency dividing circuit 211 may be implemented to output a second frequency-divided clock signal ( Figure 7 DCK2 in), the third divided clock signal ( Figure 7 DCK3 in) and the fourth divided clock signal ( Figure 7 Any one of DCK4 in . Figure 7 The frequency dividing circuit 211 divides the frequencies of the rising clock signal RCLK and the falling clock signal FCLK to generate the first frequency-divided clock signal DCK1 and the second frequency-divided clock signal ( Figure 7 DCK2 in), the third divided clock signal ( Figure 7 DCK3 in) and the fourth divided clock signal ( Figure 7 DCK4) operation.

[0062] The test mode signal generating circuit 212 can generate a first test mode signal TM1, a second test mode signal TM2 and a test shift signal TSHF based on the first mode signal and the second mode signal MD<1:2>. <1> With a logic high level and the second mode signal MD <2> When the first mode signal MD has a logic low level, the test mode signal generating circuit 212 may generate an enabled first test mode signal TM1. <1> With a logic high level and the second mode signal MD <2> When the first mode signal MD has a logic low level, the test mode signal generating circuit 212 may generate a disabled second test mode signal TM2. <1> With a logic low level and the second mode signal MD <2> When the first mode signal MD has a logic high level, the test mode signal generating circuit 212 may generate an enabled first test mode signal TM1. <1> With a logic low level and the second mode signal MD <2> When the first mode signal MD has a logic high level, the test mode signal generating circuit 212 may generate an enabled second test mode signal TM2. <1> With a logic high level and the second mode signal MD <2> When at a logic high level, the test mode signal generating circuit 212 may generate an enabled test shift signal TSHF. The logic levels of the first and second mode signals MD<1:2> used by the test mode signal generating circuit 212 to generate the first and second test mode signals TM1, TM2, and the test shift signal TSHF may be variously set according to embodiments.

[0063] The comparison circuit 213 can latch the remaining one of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> as either the first or second rising command addresses CAR<1:2> or the first or second falling command addresses CAF<1:2> based on the first test mode signal TM1 and the second test mode signal TM2. The comparison circuit 213 can generate first and second detection signals DT<1:2> based on the latched first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> in synchronization with the first divided clock signal DCK1. The comparison circuit 213 can output the serially generated first and second detection signals DT<1:2> to the output pad 214.

[0064] The fault detection circuit 215 can detect a fault in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> by detecting the logic levels of the first detection signal and the second detection signal DT<1:2>. When the first detection signal and the second detection signal DT<1:2> are different from the set values, the fault detection circuit 215 can detect that a fault has occurred in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>. When the first detection signal and the second detection signal DT<1:2> are the same as the set values, the fault detection circuit 215 can detect that a fault has not occurred in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>. The fault in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> can be set to be due to the through electrode ( Figure 2 TSV12) failure caused by the through-hole electrode ( Figure 2 The first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> inputted by the TSV12 in the through-hole electrode ( Figure 2 In the embodiment of the present invention, the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> outputted from the TSV 12 in the circuit 120 have different logic levels. In addition, a failure in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> can be set to a situation where the first to fourth external command addresses ECA<1:4> and the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> are generated to have different logic levels due to a failure of the command address input circuit 120.

[0065] Figure 7 is used to describe Figure 6 The operation of the frequency dividing circuit 211 to generate the first frequency-divided clock signal DCK1, the second frequency-divided clock signal DCK2, the third frequency-divided clock signal DCK3, and the fourth frequency-divided clock signal DCK4 by dividing the frequencies of the rising clock signal RCLK and the falling clock signal FCLK can be referred to. Figure 7 is described below.

[0066] At time T31, the frequency division circuit 211 may generate a first frequency-divided clock signal DCK1 including a pulse generated in synchronization with a rising edge of the rising clock signal RCLK during one cycle of the rising clock signal RCLK. The frequency division circuit 211 may generate the first frequency-divided clock signal DCK1 having a frequency ½ that of the rising clock signal RCLK in synchronization with the rising edge of the rising clock signal RCLK.

[0067] At time T32, the frequency dividing circuit 211 may generate a second frequency-divided clock signal DCK2 including a pulse generated in synchronization with the rising edge of the falling clock signal FCLK during one cycle of the falling clock signal FCLK. The frequency dividing circuit 211 may generate the second frequency-divided clock signal DCK2 having a frequency ½ that of the falling clock signal FCLK in synchronization with the rising edge of the falling clock signal FCLK.

[0068] At time T33, the frequency dividing circuit 211 may generate a third frequency-divided clock signal DCK3, which includes a pulse generated in synchronization with the rising edge of the rising clock signal RCLK during one cycle of the rising clock signal RCLK. The frequency dividing circuit 211 may generate the third frequency-divided clock signal DCK3 having a frequency ½ that of the rising clock signal RCLK in synchronization with the rising edge of the rising clock signal RCLK.

[0069] At time T34, the frequency dividing circuit 211 may generate a fourth frequency-divided clock signal DCK4, which includes a pulse generated in synchronization with the rising edge of the falling clock signal FCLK during one cycle of the falling clock signal FCLK. The frequency dividing circuit 211 may generate the fourth frequency-divided clock signal DCK4 having a frequency ½ that of the falling clock signal FCLK in synchronization with the rising edge of the falling clock signal FCLK.

[0070] The frequency division circuit 211 can generate a first frequency-divided clock signal DCK1, a second frequency-divided clock signal DCK2, a third frequency-divided clock signal DCK3 and a fourth frequency-divided clock signal DCK4 by dividing the frequency of each of the rising clock signal RCLK and the falling clock signal FCLK, and these frequency-divided clock signals respectively have a phase difference corresponding to 1 / 2 the frequency of each of the rising clock signal RCLK and the falling clock signal FCLK.

[0071] Figure 8 It shows that according to Figure 6. The comparison circuit 213 may include a transfer address generation circuit 310, an internal transfer address generation circuit 320, an address transfer circuit 330, and a detection signal generation circuit 340.

[0072] The transmission address generation circuit 310 may include a multiplexer 311, a multiplexer 312, an XOR gate 313, and a flip-flop (F / F) 314. When the second test mode signal TM2 is disabled as a logic low level, the multiplexer 311 may output the first rising command address CAR. <1> As the first choice address SA <1> When the second test mode signal TM2 is enabled as a logic high level, the multiplexer 311 may output the first falling command address CAF <1> As the first choice address SA <1> When the second test mode signal TM2 is disabled as a logic low level, the multiplexer 312 may output the first falling command address CAF <1> As the first selection clock signal SC <1> When the second test mode signal TM2 is enabled as a logic high level, the multiplexer 312 may output the first rising command address CAR. <1> As the first selection clock signal SC <1> When the first transmission address TA <1> and the first choice address SA <1> When the first comparison signal C has the same logic level, the XOR gate 313 can generate a first comparison signal C with a logic low level. <1> When the first transmission address TA <1> and the first choice address SA <1> When the comparison signal C has different logic levels, the XOR gate 313 may generate a first comparison signal C having a logic high level. <1> When the first test mode signal TM1 is enabled to a logic high level, the flip-flop 314 can turn the first transfer address TA <1> The logic level is initialized to a logic low level. When the first selection clock signal SC <1> When the trigger 314 changes from a logic low level to a logic high level, it can latch the first comparison signal C <1> The flip-flop 314 can output the first selection clock signal SC <1> The first comparison signal C that has been latched when it changes from a logic low level to a logic high level <1> As the first transmission address TA <1> .

[0073] When the first test mode signal TM1 is enabled to a logic high level, the transfer address generation circuit 310 may generate the first transfer address TA <1> The logic level of the first test mode signal TM2 is initialized to a logic low level. When the second test mode signal TM2 is disabled as a logic low level, the transmission address generation circuit 310 can be connected to the first falling command address CAF. <1> The first selected clock signal SC is generated <1> Synchronously from the first rising command address CAR <1> Generate the first selected address SA <1> When the first selected address SA <1> and the first transmission address TA <1> When the transmission address generation circuit 310 has different logic levels, it can generate a first transmission address TA having a logic high level. <1> When the first selected address SA <1> and the first transmission address TA <1> have the same logic level, the transmission address generation circuit 310 may generate a first transmission address TA having a logic low level. <1> .

[0074] The internal transmission address generation circuit 320 may include a multiplexer 321, a multiplexer 322, an XOR gate 323, and a flip-flop (F / F) 324. When the second test mode signal TM2 is disabled as a logic low level, the multiplexer 321 may output the second rising command address CAR <2> As the second choice address SA <2> When the second test mode signal TM2 is enabled as a logic high level, the multiplexer 321 may output the second falling command address CAF <2> As the second choice address SA <2> When the second test mode signal TM2 is disabled as a logic low level, the multiplexer 322 may output the second falling command address CAF <2> As the second selection clock signal SC <2> When the second test mode signal TM2 is enabled as a logic high level, the multiplexer 322 may output the second rising command address CAR. <2> As the second selection clock signal SC <2> When the internal transmission address ITA and the second selection address SA <2> When the comparison signal C has the same logic level, the XOR gate 323 can generate a second comparison signal C with a logic low level. <2> When the internal transmission address ITA and the second selection address SA <2> When the logic levels are different, the XOR gate 323 can generate a second comparison signal C having a logic high level. <2> When the first test mode signal TM1 is enabled to a logic high level, the flip-flop 324 can initialize the logic level of the internal transfer address ITA to a logic low level. <2> When the trigger 324 changes from a logic low level to a logic high level, it can latch the second comparison signal C <2> The flip-flop 324 can output the second selection clock signal SC <2> The second comparison signal C is latched when it changes from a logic low level to a logic high level. <2> As the internal transmission address ITA.

[0075] When the first test mode signal TM1 is enabled as a logic high level, the internal transfer address generation circuit 320 can initialize the logic level of the internal transfer address ITA to a logic low level. When the second test mode signal TM2 is disabled as a logic low level, the internal transfer address generation circuit 320 can generate a command address from the second falling command address CAF. <2> The generated second selection clock signal SC <2> Synchronously from the second rising command address CAR <2> Generate the second selected address SA <2> When the second selected address SA <2> When the second selection address SA has a different logic level from the internal transmission address ITA, the internal transmission address generation circuit 320 may generate the internal transmission address ITA with a logic high level. <2> When the internal transmission address ITA has the same logic level as the internal transmission address ITA, the internal transmission address generation circuit 320 may generate the internal transmission address ITA with a logic low level.

[0076] The address transmission circuit 330 may include a flip-flop (F / F) 331. The flip-flop 331 may generate a first divided clock signal DCK. <1> The internal transmission address ITA is latched when the logic level changes from a low level to a high level. The trigger 331 can output the first divided clock signal DCK <1> The internal transmission address ITA that has been latched when it changes from a logic low level to a logic high level is used as the second transmission address TA <2> .

[0077] The address transmission circuit 330 can be connected to the first frequency-divided clock signal DCK <1> Synchronously output the internal transfer address ITA as the second transfer address TA <2> .

[0078] The detection signal generating circuit 340 may include a multiplexer 341 and a flip-flop (F / F) 342. The multiplexer 341 may receive the first transfer address TA when the test shift signal TSHF is disabled at a logic low level. <1> To output the first transmission address TA <1> The multiplexer 341 can receive the second transfer address TA when the test shift signal TSHF is enabled to a logic high level. <2> To output the second transmission address TA <2> The trigger 342 can be used to generate a first divided clock signal DCK. <1> When the output signal of the multiplexer 341 is latched when the logic level changes from a low level to a high level, the flip-flop 342 can output the first divided clock signal DCK. <1> The output signal of the multiplexer 341 that is latched when transitioning from a logic low level to a logic high level serves as the first detection signal and the second detection signal DT<1:2>.

[0079] When the test shift signal TSHF is disabled as a logic low level, the detection signal generating circuit 340 may output the first transfer address TA. <1> As the first detection signal DT <1> When the test shift signal TSHF is enabled to a logic high level, the detection signal generating circuit 340 may output the second transfer address TA <2> As the second detection signal DT <2> The first and second detection signals DT<1:2> may be serially output through the output pads 214 .

[0080] Figure 9 TABLE 1 is a table for describing an operation of detecting a failure in transmission of a command address by a semiconductor chip according to an embodiment of the present disclosure. The operation of detecting a failure in transmission of a command address may be described, but a case where the second test mode signal TM2 is disabled and the set value is set to "L, L" may be referred to as an example. Figure 9 is described below.

[0081] Before the description, the set value may represent the first external command address ECA having a logic low level L <1> , a second external command address ECA having a logic high level H <2> , a third external command address ECA having a logic low level L <3> and a fourth external command address ECA having a logic high level H <4> The situation being entered.

[0082] First, a case where a failure does not exist (PASS) in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> may be described as an example as follows.

[0083] The command address input circuit 120 may generate a first rising command address CAR having a logic low level L based on the first to fourth external command addresses ECA<1:4> in synchronization with the rising clock signal RCLK and the falling clock signal FCLK. <1> , a second rising command address CAR having a logic low level L <2> , a first falling command address CAF having a logic high level H <1> and a second falling command address CAF having a logic high level H <2> .

[0084] When the first mode signal MD <1> With a logic high level and the second mode signal MD <2> When the first mode signal MD has a logic low level, the test mode signal generating circuit 212 of the test circuit 210 may generate an enabled first test mode signal TM1. <1> With a logic high level and the second mode signal MD <2> With a logic low level, the test mode signal generating circuit 212 may generate a disabled second test mode signal TM2 .

[0085] The comparison circuit 213 of the test circuit 210 can generate a first selection clock signal and a second selection clock signal SC<1:2> from the first and second falling command addresses CAF<1:2> based on the first test mode signal TM1 and the second test mode signal TM2. The comparison circuit 213 can generate a first selection clock signal SC<1:2> and a second selection clock signal SC<1:2> from the first and second falling command addresses CAF<1:2>. <1> Synchronously from the first rising command address CAR with a logic low level L <1> Generates a first detection signal DT having a logic low level L <1> The comparison circuit 213 can be connected to the second selection clock signal SC <2> Synchronously from the second rising command address CAR with a logic low level L <2> Generates a second detection signal DT having a logic low level L <2> .

[0086] When the first and second detection signals DT<1:2> are identical to the set values ​​“L, L”, the fail detection circuit 215 may detect that no failure (PASS) occurs in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>.

[0087] Next, a case where a failure (FAIL) occurs in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2> may be described as an example as follows.

[0088] The command address input circuit 120 may generate a first rising command address CAR having a logic low level L based on the first to fourth external command addresses ECA<1:4> in synchronization with the rising clock signal RCLK and the falling clock signal FCLK. <1> , a second rising command address CAR having a logic low level L <2> , a first falling command address CAF having a logic high level H <1> and a second falling command address CAF having a logic high level H <2> .

[0089] When the first mode signal MD <1> With a logic high level and the second mode signal MD <2> When the first mode signal MD has a logic low level, the test mode signal generating circuit 212 of the test circuit 210 may generate an enabled first test mode signal TM1. <1> With a logic high level and the second mode signal MD <2> With a logic low level, the test mode signal generating circuit 212 may generate a disabled second test mode signal TM2 .

[0090] The comparison circuit 213 of the test circuit 210 can generate a first selection clock signal and a second selection clock signal SC<1:2> from the first and second falling command addresses CAF<1:2> based on the first test mode signal TM1 and the second test mode signal TM2. The comparison circuit 213 can generate a first selection clock signal SC<1:2> from the first and second falling command addresses CAF<1:2>. <1> Synchronously from the first rising command address CAR having a logic low level L <1> Generates a first detection signal DT having a logic low level L <1> The comparison circuit 213 can be connected to the second selection clock signal SC <2> Synchronously from the second rising command address CAR with a logic low level L <2> Generates a second detection signal DT having a logic high level H <2> .

[0091] When the first and second detection signals DT<1:2> are different from the set values ​​“L, L”, the fail detection circuit 215 can detect a failure (FAIL) in the transmission of the first and second rising command addresses CAR<1:2> and the first and second falling command addresses CAF<1:2>.

[0092] A semiconductor chip 1 according to an embodiment of the present disclosure can detect a failure in the transmission of a command address output through a signal path. The semiconductor chip 1 can generate a detection signal DT<1:2> for detecting a failure in the transmission of the rising command address CAR<1:2> or the falling command address CAF<1:2> by latching the remaining one of the rising command address CAR<1:2> and the falling command address CAF<1:2> output in synchronization with different clock signals RCLK and FCLK as either the rising command address CAR<1:2> or the falling command address CAF<1:2>. When the logic levels of the rising command address CAR<1:2> and the falling command address CAF<1:2> output in synchronization with different clock signals RCLK and FCLK differ from a set value, the semiconductor chip 1 can detect the failure in the transmission of the rising command address CAR<1:2> or the falling command address CAF<1:2>.

[0093] Figure 10 is a diagram for describing a three-dimensional structure of a semiconductor chip according to an embodiment of the present disclosure.

[0094] The base chip 10 may include an interface area PHY AREA and a through-electrode area TSV AREA. The through-electrode area TSV AREA (indicated by a dotted line) may be provided at the center of the base chip 10. The interface area PHY AREA may be provided on the left and right sides of the through-electrode area TSV AREA (indicated by a dotted line) as the center.

[0095] The first memory chip 20 may be vertically stacked on the base chip 10 .

[0096] The first memory chip 20 may include an interface area PHY AREA and a through-electrode area TSV AREA. The through-electrode area TSV AREA (indicated by a dotted line) may be provided at the center of the first memory chip 20. The interface area PHY AREA may be provided on the left and right sides of the through-electrode area TSV AREA (indicated by a dotted line) as the center.

[0097] The second memory chip 30 may be vertically stacked on the first memory chip 20 .

[0098] The second memory chip 30 may include an interface area PHY AREA and a through-electrode area TSV AREA. The through-electrode area TSV AREA (indicated by a dotted line) may be provided at the center of the second memory chip 30. The interface area PHY AREA may be provided on the left and right sides of the through-electrode area TSV AREA (indicated by a dotted line) as the center.

[0099] The third memory chip 40 may be vertically stacked on the second memory chip 30 .

[0100] The third memory chip 40 may include an interface area PHY AREA and a through-electrode area TSV AREA. The through-electrode area TSV AREA (indicated by a dotted line) may be provided at the center of the third memory chip 40. The interface area PHY AREA may be provided on the left and right sides of the through-electrode area TSV AREA (indicated by a dotted line) as the center.

[0101] The fourth memory chip 50 may be vertically stacked on the third memory chip 40 .

[0102] The fourth memory chip 50 may include an interface area PHY AREA and a through-electrode area TSV AREA. The through-electrode area TSV AREA (indicated by a dotted line) may be provided at the center of the fourth memory chip 50. The interface area PHY AREA may be provided on the left and right sides of the through-electrode area TSV AREA (indicated by a dotted line) as the center.

[0103] Figure 11 1 is a block diagram showing the configuration of a stacked memory system 1000 according to an example of the present disclosure. Figure 11 As shown, the stacked memory system 1000 may include a semiconductor chip 1100 , a processor 1200 , an interposer 1300 , and a substrate 1400 .

[0104] An interposer 1300 may be formed on a substrate 1400. The semiconductor chip 1100 and the processor 1200 may be formed on the interposer 1300. The interposer 1300 may be used to electrically connect the substrate 1400, the semiconductor chip 1100, and the processor 1200. In one embodiment, since there is a large difference in the spacing between the substrate 1400, the semiconductor chip 1100, and the processor 1200, the substrate 1400, the semiconductor chip 1100, and the processor 1200 may be electrically connected using the interposer 1300 including conductive lines formed in various manners.

[0105] The processor 1200 may include a processor interface circuit (PPHY) 1210 . The processor 1200 may apply signals including commands and addresses for controlling various internal operations of the semiconductor chip 1100 to the semiconductor chip 1100 through the processor interface circuit 1210 , and may receive data from the semiconductor chip 1100 through the processor interface circuit 1210 .

[0106] The semiconductor chip 1100 may include a base chip 1110 and memory chips 1120, 1130, 1140, and 1150. The semiconductor chip 1100 may be implemented as Figure 1 The semiconductor chip 1 is shown in FIG.

[0107] The memory chips 1120 , 1130 , 1140 , and 1150 may be sequentially stacked on the base chip 1110 and may receive various signals from the base chip 1110 through the through-electrodes T1100 .

[0108] The basic chip 1110 may include a core interface circuit (CPHY) 1111 and an operation control circuit (OP CTR) 1112. The core interface circuit 1111 may be configured to communicate with the operation control circuit 1112, and may transmit signals including commands and addresses received from the processor 1200 to the operation control circuit 1112, and apply data generated by the operation control circuit 1112 to the processor 1200. The core interface circuit 1111 may be implemented as Figure 2 The test signal generating circuit 11 and the chip ID generating circuit 12 shown in FIG. The operation control circuit 1112 can be implemented as Figure 2 The test signal generating circuit 11, the logic test circuit 12 and the fault detection circuit 13 shown in FIG.

[0109] Semiconductor chip 1100 can detect a failure in the transmission of command addresses output through multiple signal paths connected to multiple memory chips 1120, 1130, 1140, and 1150. Semiconductor chip 1100 can generate a detection signal DT<1:2> for detecting a failure in the transmission of the rising command addresses CAR<1:2> and the falling command addresses CAF<1:2> by latching the remaining one of the rising command addresses CAR<1:2> and the falling command addresses CAF<1:2> output in synchronization with different clock signals RCLK and FCLK as either the rising command addresses CAR<1:2> or the falling command addresses CAF<1:2>. Semiconductor chip 1100 can detect a failure in the transmission of the rising command addresses CAR<1:2> and the falling command addresses CAF<1:2> when the logic levels of the rising command addresses CAR<1:2> and the falling command addresses CAF<1:2> output in synchronization with different clock signals RCLK and FCLK differ from a set value.

[0110] So far, the embodiments of the present disclosure have been described. Personnel with ordinary knowledge of the field to which this specification belongs will understand that the embodiments can be implemented in modified forms without departing from the inherent characteristics of the present disclosure. Therefore, the disclosed embodiments should be considered from a descriptive perspective rather than from a restrictive perspective. The scope of the present disclosure is described in the claims, rather than in the foregoing description, and all differences within the scope of equivalence should be interpreted as being included in the present disclosure.

Claims

1. A semiconductor chip comprising: a command address input circuit that: receives an external command address to generate a rising command address and a falling command address; and outputs the rising command address and the falling command address to the through-electrode; and A test circuit, which: generates a detection signal by latching any one of the rising command address and the falling command address output synchronously with a rising clock signal and a falling clock signal as the remaining one of the rising command address and the falling command address; and detects a fault in the transmission of the rising command address and the falling command address by detecting a logic level of the detection signal.

2. The semiconductor chip according to claim 1, wherein: The command address input circuit is included in the interface area, and The test circuit is included in a through-electrode region including the through-electrode.

3. The semiconductor chip according to claim 1, wherein: The command address input circuit generates the rising command address by latching the external command address in synchronization with the rising clock signal, and The command address input circuit generates the falling command address by latching the external command address in synchronization with the falling clock signal.

4. The semiconductor chip according to claim 3, wherein The rising clock signal and the falling clock signal are signals having opposite phases and being periodically switched. The semiconductor chip according to claim 1 , wherein: The test circuit generates the detection signal by latching the falling command address as the rising command address, or generates the detection signal by latching the rising command address as the falling command address. The semiconductor chip according to claim 1 , wherein: The test circuit comprises: a test mode signal generating circuit that generates a first test mode signal and a second test mode signal based on the mode signal; a transfer address generation circuit that: initializes a transfer address based on the first test mode signal; generates a selection clock signal from either one of the rising command address and the falling command address based on the second test mode signal; generates a selection address by latching the remaining one of the rising command address and the falling command address in synchronization with the selection clock signal; and generates the transfer address based on the selection address; a detection signal generating circuit that outputs the transfer address as the detection signal in synchronization with a frequency-divided clock signal; and A failure detection circuit detects the failure in the transmission of the rising command address and the falling command address by detecting the logic level of the detection signal.

7. The semiconductor chip according to claim 6, wherein The transmission address generating circuit generating the selection clock signal from the falling command address when the second test mode signal is disabled, and The selection address is generated by latching the rising command address in synchronization with the selection clock signal.

8. The semiconductor chip according to claim 6, wherein The transmission address generating circuit generating the selection clock signal from the rising command address when the second test mode signal is enabled, and The selection address is generated by latching the falling command address in synchronization with the selection clock signal.

9. A semiconductor chip comprising: a command address input circuit that: generates a first rising command address and a second rising command address and a first falling command address and a second falling command address by receiving first to fourth external command addresses; and outputs the first rising command address and the second rising command address and the first falling command address and the second falling command address to the through-electrodes; and A test circuit, which: generates a first detection signal and a second detection signal by latching any one of the first rising command address and the second rising command address and the first falling command address and the second falling command address output synchronously with a rising clock signal and a falling clock signal as the remaining one of the first rising command address and the second rising command address and the first falling command address and the second falling command address; and detects a fault in the transmission of the first rising command address and the second rising command address and the first falling command address and the second falling command address when the first detection signal and the second detection signal are different from set values.

10. The semiconductor chip according to claim 9, wherein The first to fourth external command addresses are signals serially input from outside the test circuit.

11. The semiconductor chip according to claim 9, wherein: The command address input circuit is included in the interface area, and The test circuit is included in a through-electrode region including the through-electrode.

12. The semiconductor chip according to claim 9, wherein: The command address input circuit generates the first rising command address and the second rising command address from the first external command address and the third external command address in synchronization with a rising clock signal, and The command address input circuit generates the first falling command address and the second falling command address from a second external command address and a fourth external command address in synchronization with a falling clock signal.

13. The semiconductor chip according to claim 9, wherein The test circuit comprises: a test mode signal generating circuit for generating a first test mode signal, a second test mode signal and a test shift signal based on the mode signal; a comparison circuit that: generates a first transfer address and a second transfer address by latching the remaining one of the first rising command address and the second rising command address and the first falling command address and the second falling command address as any one of the first rising command address and the second rising command address and the first falling command address and the second falling command address based on the first test mode signal and the second test mode signal; and outputs the first transfer address and the second transfer address as the first detection signal and the second detection signal through an output pad by serializing the first transfer address and the second transfer address based on a divided clock signal and the test shift signal; and A fault detection circuit detects the fault in the transmission of the first rising command address and the second rising command address and the first falling command address and the second falling command address by detecting logic levels of the first detection signal and the second detection signal.

14. The semiconductor chip according to claim 13, wherein The comparison circuit comprises: a transfer address generation circuit that: initializes the first transfer address based on the first test mode signal; generates a first selection clock signal from either one of the first rising command address and the first falling command address based on the second test mode signal; generates a first selection address by latching the remaining one of the first rising command address and the first falling command address in synchronization with the first selection clock signal; and generates the first transfer address based on the first selection address; an internal transfer address generation circuit that: initializes an internal transfer address based on the first test mode signal; generates a second selection clock signal from either one of the second rising command address and the second falling command address based on the second test mode signal; generates a second selection address by latching the remaining one of the second rising command address and the second falling command address in synchronization with the second selection clock signal; and generates the internal transfer address based on the second selection address; an address transmission circuit that outputs the internal transmission address as the second transmission address in synchronization with the frequency-divided clock signal; and A detection signal generating circuit serializes the first transfer address and the second transfer address based on the test shift signal, and outputs the first transfer address and the second transfer address as the first detection signal and the second detection signal.

15. The semiconductor chip according to claim 14, wherein: The transfer address generation circuit generates the first selection clock signal from the first falling command address when the second test mode signal is disabled, and generates the first selection address by latching the first rising command address in synchronization with the first selection clock signal, and The transfer address generation circuit generates the first selection clock signal from the first rising command address when the second test mode signal is enabled, and generates the first selection address by latching the first falling command address in synchronization with the first selection clock signal.

16. The semiconductor chip according to claim 14, wherein: the internal transfer address generation circuit generates the second selection clock signal from the second falling command address when the second test mode signal is disabled, and generates the second selection address by latching the second rising command address in synchronization with the second selection clock signal, and The internal transfer address generation circuit generates the second selection clock signal from the second rising command address when the second test mode signal is enabled, and generates the second selection address by latching the second falling command address in synchronization with the second selection clock signal.

17. The semiconductor chip according to claim 14, wherein: The detection signal generating circuit outputs the first transfer address as the first detection signal in synchronization with the frequency-divided clock signal when the test shift signal is disabled, and The detection signal generating circuit outputs the second transfer address as the second detection signal in synchronization with the frequency-divided clock signal when the test shift signal is enabled. 18 . The semiconductor chip according to claim 14 , further comprising a frequency dividing circuit that generates the divided clock signal by dividing the frequencies of a rising clock signal and a falling clock signal.

19. The semiconductor chip according to claim 18, wherein The rising clock signal and the falling clock signal are signals having opposite phases and being periodically switched.

20. The semiconductor chip according to claim 18, wherein The frequency-divided clock signal is generated so that its frequency is substantially half the frequency of each of the rising clock signal and the falling clock signal.

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