Self-checking circuit and self-checking method for memory specified address error injection

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a self-checking circuit and a self-checking method for memory specified address error injection, the self-checking circuit comprises a processor, a memory, a read-write control module, an error injection control module and an error injection configuration module, the memory and the read-write control module are respectively connected with an ECC generator and an ECC checker; the processor is respectively connected with the error injection configuration module and the read-write control module corresponding to the memory; the processor is used for controlling the read-write control module to perform data writing and reading operation on the memory, and configuring an error injection address and error injection data of a specified address through the error injection configuration module according to the space use condition of the memory; the error injection control module is used for responding to the data reading operation of the processor on the memory, judging whether the data reading address of the memory is matched with the error injection address or not, if yes, performing error injection on the error injection data, and the ECC verifier is used for verifying the error-injected data. According to the invention, an accurate and controllable error injection self-checking function can be supported.

Claims

1. A self-check circuit for memory address injection errors, comprising a processor, at least one memory, and a read / write control module, wherein a data write terminal of the memory is connected to an ECC generator, a data output terminal of the memory is connected to an ECC checker, and the read / write control module is connected to the ECC generator and the ECC checker, respectively; characterized in that: The self-check circuit for memory designated address injection error further includes an injection error control module and an injection error configuration module, the memory is respectively in one-to-one correspondence with the read-write control module and the injection error control module, the processor is respectively connected to the injection error configuration module and the read-write control module corresponding to the memory; the injection error control module is respectively connected to the memory and the injection error configuration module; The processor is used to control the read-write control module to perform data writing and reading operations on the memory, and configure the error annotation address and error annotation data of the specified address through the error annotation configuration module according to the space usage of the memory; the error annotation control module is used to respond to the processor's data reading operation on the memory, determine whether the address of the memory read data matches the error annotation address in the error annotation configuration module, if so, the error annotation data is performed, and if not, no error annotation is performed; the ECC checker is used to check the data after error annotation.

2. The self-check circuit for memory designated address injection error according to claim 1, characterized in that: The error injection configuration module includes a global control register, at least one error injection control register and at least one register group. The global control register is the main switch of the error injection configuration module. The error injection control register is used to specify the register group, select the number of error injection positions and control whether reverse configuration of the error injection address is required. The register group is used to store the starting address, error injection range and error injection bit position required for the error injection operation; the error injection control register and the memory are in one-to-one correspondence.

3. The self-check circuit for memory designated address injection error according to claim 2, characterized in that: Each register group includes an address register, a range register and a position register; the address register is used to configure the starting address of the error annotation, the range register is used to configure the error annotation range, and the position register is used to configure the error annotation position.

4. The self-check circuit for memory designated address injection error according to claim 3, characterized in that: The bit fields in the error injection control register include SEL[1:0], POS1_EN, POS0_EN and INV; SEL[1:0] is used to specify the register group; POS1_EN and POS0_EN are used to select the number of error injection positions. If POS1_EN=1, POS0_EN=1, it means 2-bit error injection. If either POS0_EN or POS1_EN is configured to 1 and the other is configured to 0, it means single-bit error injection. If both POS0_EN and POS1_EN are configured to 0, no error injection is performed. INV is used to control the reverse configuration of the error injection address. If INV=0, it means that the reverse error injection function is not enabled, and the error injection operation is only performed from the starting address configured by the error injection address register and within the range set by the range register; if INV=1, it means that the reverse error injection function is enabled, and the address range defined by the error injection address register and the range register will be regarded as an exclusion zone for non-error injection, and the remaining address ranges are all error injection ranges.

5. The self-checking circuit for memory designated address injection error according to claim 4, characterized in that: Before system startup or self-test, the processor selects an idle address range that has not been used or can be used for error injection self-test as the error injection address based on the space usage of each memory; the processor writes the error injection configuration information to the register group, writes the starting error injection address in the selected target memory into the address register, writes the range into the range register, and then writes the position of the bit to be error injected into the position register.

6. The self-check circuit for memory designated address injection error according to claim 5, characterized in that: After the processor writes the error injection configuration information into the register group, the processor further includes: The processor specifies the register group corresponding to the target memory in the error injection control register, and performs single-bit, double-bit or no error injection operation through the error injection position enable bit setting, and then determines whether to reverse configure the error injection address. After completing the configuration, the processor sets the control bit in the global control register to the enabled state.

7. The self-check circuit for memory designated address injection error according to claim 4, characterized in that: When the processor controls the read-write control module to read data from the memory, the error injection control module synchronously obtains the chip select signal of the memory, the address in the memory where the read data is located, and the read-write control signal. If the error injection control module detects that the chip select signal of the memory is valid and the read-write control signal indicates a read operation, it means that the memory corresponding to the error injection control module is performing a data reading operation. The error injection control module determines whether the address in the memory where the read data is located matches the error injection address in the error injection configuration module. If so, the error injection operation is performed; otherwise, the error injection operation is not performed.

8. The self-checking circuit for memory designated address injection error according to claim 7, characterized in that: If the reverse error injection function is not enabled in the error injection control register, and the address in the memory where the read data is located is within the range of the error injection address, the error injection operation is performed; if the reverse error injection function is enabled in the error injection control register, and the address in the memory where the read data is located is not within the range of the error injection address, the error injection operation is performed.

9. The self-check circuit for memory designated address injection error according to claim 1, characterized in that: The ECC checker receives the data after the error is injected and performs a check. If the ECC checker checks an error, it means that the ECC checker circuit functions normally and the self-check passes; otherwise, it means that the ECC checker circuit is abnormal and cannot work normally, and the self-check fails.

10. A self-checking method for memory designated address injection errors, applied to the self-checking circuit for memory designated address injection errors as claimed in any one of claims 1 to 9, characterized in that: The method comprises: The processor configures the error annotation address and error annotation data of the specified address in the error annotation configuration module based on the space usage of the specified memory; In response to a data read operation of the processor on the designated memory, the error injection control module obtains the address where the read data is located, the chip select signal, and the read / write control signal, and when the chip select signal is valid and the read / write control signal indicates a read operation, determines whether the address where the read data is located matches the error injection address; If there is a match, the error-annotated data will be annotated, and the data after error annotation will be checked by ECC. If the check is wrong, it means that the ECC check circuit functions normally, otherwise it means that the ECC check circuit is abnormal. If there is no match, the error annotation operation of the error-annotated data will not be performed.

Images