Storage repair system based on multiple parallel BISR chains

Abstract

The invention relates to the technical field of integrated circuit repair, in particular to a storage repair system based on multiple parallel BISR chains, and the system sets state information for each target register chain, so that a control unit can determine a current register chain according to the state information of each target register chain and repair the current register chain. The current register chain reads the corresponding compression repair data in the nonvolatile memory, and when the current register chain needs to decompress the received compressed sub-data, the current register chain is changed, so that a plurality of target register chains can read the compression repair data in parallel; compared with the situation that in the scheme that multiple register chains are used in the prior art, after one register chain is repaired, the other register chain can be repaired, the storage repairing efficiency can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit repair, and in particular to a storage repair system based on multiple parallel BISR chains. Background Art

[0002] With the rapid development of emerging applications such as artificial intelligence, big data, and the Internet of Things, as well as continuous advancements in process technology, chips are required to process increasing amounts of data, and on-chip memory is also taking up a growing share of the chip. The increasing chip area and amount of on-chip memory increase the probability of on-chip memory defects, which in turn poses challenges to chip yield and cost. To improve chip yield, it is necessary to develop repair solutions for on-chip memory. These include adding redundant arrays to the on-chip memory, adding built-in self-analysis circuits corresponding to the on-chip memory, and adding non-volatile memory to store and read the repair data analyzed by the built-in self-analysis circuits.

[0003] When a memory built-in self-test (BIST) detects a defect within the memory, if the memory has a redundant array, the built-in self-analysis circuitry (BSA) analyzes the repair data and uses it to select the appropriate redundant array to replace the defective row or column, thereby repairing the memory. After the BSA analysis is complete, the repair data is updated to the built-in self-repair register chain (BISR chain). The BISR chain is connected to the on-chip non-volatile memory controller. By shifting the BISR chain, the repair data can be stored directly or compressed into the on-chip non-volatile memory.

[0004] In the prior art, there are typically two types of BISR registers, external and internal, corresponding to parallel and serial repair memories, respectively. Updating repair data from the built-in self-analysis circuit to the external BISR register is relatively simple and fast, accomplished through parallel sampling between registers, typically requiring only one or two clock cycles. However, updating repair data from the built-in self-analysis circuit to the internal BISR register requires serial shifting, requiring a number of clock cycles proportional to the length of the internal BISR chain.

[0005] However, when using a parallel strategy to repair the memory, the external BISR register requires more complex control logic. When there are a large number of on-chip memories, each on-chip memory needs to correspond to an external BISR register and control logic, which results in the chip area being too large. In order to simplify the control logic, the existing technology usually uses a serial strategy to repair the memory. However, when there are a large number of on-chip memories, the length of the BISR chain formed will also be longer, resulting in a longer time-consuming memory repair, and even causing the chip system power-on time to fail to meet expected requirements.

[0006] Therefore, how to improve the efficiency of memory repair in chips has become an urgent problem to be solved. Summary of the Invention

[0007] In view of the above technical problems, the technical solution adopted by the present invention is: A storage repair system based on multiple parallel BISR chains, the system comprising: P repair modules and their corresponding target register chains, a non-volatile memory and its corresponding control unit, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer.

[0008] For any target register chain, the target register chain determines its state information according to its own repair state and read state. The repair state is initially an unrepaired state, and the read state is initially a read request state.

[0009] When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information satisfies the condition.

[0010] When there is a current register chain, the control unit sends the compressed repair data corresponding to the current register chain from the non-volatile memory to the current register chain in a sub-data manner, wherein the compressed repair data includes a plurality of sub-data, and the sub-data belongs to uncompressed sub-data or compressed sub-data.

[0011] If the current register link receives uncompressed sub-data, it continues to read the next sub-data.

[0012] If the current register chain receives compressed sub-data, it stops reading the next sub-data, decompresses the latest received compressed sub-data, determines that the reading state of the current register chain is the stop reading state, and changes the current register chain to the target register chain.

[0013] For any target register chain, if the target register chain has completed decompression of the most recently received compressed sub-data, the read state of the target register chain is determined to be a request read state.

[0014] If the target register chain receives all sub-data in the compressed repair data corresponding to the target register chain, and the most recently received compressed data is decompressed, it is determined that the repair state of the target register chain is the repaired state.

[0015] When the repair states corresponding to all target register chains are in the repaired state, the repair of the P repair modules is completed.

[0016] Compared with the prior art, the present invention has significant benefits. By means of the above technical solution, the storage repair system based on multiple parallel BISR chains provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following beneficial effects: The present invention sets status information for each target register chain, so that the control unit can determine the current register chain based on the status information of each target register chain, and read the corresponding compressed repair data in the non-volatile memory by the current register chain. When the current register chain needs to decompress the received compressed sub-data, the current register chain is changed, so that multiple target register chains can read the compressed repair data in parallel. Compared with the existing technology using multiple register chains, which requires waiting for the repair of one register chain to be completed before repairing another register chain, it can effectively improve the storage repair efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a storage repair system based on a polymorphic BISR chain provided in the first embodiment of the present invention; Figure 2 A flowchart of a storage repair system based on multiple parallel BISR chains provided in the second embodiment of the present invention; Figure 3 A structural diagram of a storage repair system based on multiple parallel BISR chains provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] This embodiment 1 provides a storage repair system based on a polymorphic BISR chain, the system comprising: M repair modules, a non-volatile memory, and a control unit corresponding to the non-volatile memory, wherein each repair module corresponds to a first selector, and M is a positive integer; The mth repair module a mContains N(m) storage units, in a m In the example, the i-th storage unit b i There is an off-chip register c i , b i There are also corresponding repair types, which include serial type and parallel type. i When the corresponding repair type is serial type, b i Including on-chip registers d i , m is an integer in the range [1, M], i is an integer in the range [1, N(m)]; In a m In, when b i When it is parallel type, b i with c i connect; When b i For serial type, if i=1, then c i d i The input terminals are connected to a m The corresponding output terminal of the first selector is connected. If i≠1, then c i d i The input terminals are connected to c i-1 The output terminal connection; When b i For parallel type, if i=1, then c i The input terminal and a m The corresponding output terminal of the first selector is connected. If i≠1, then c i The input terminal and c i-1 The output terminal connection; When i=N(m), if m≠M, then c i The output terminals are connected to a m The first input terminal of the corresponding first selector and a m+1 The second input terminal of the corresponding first selector is connected. If m=M, then c i The output terminals are connected to a m The first input terminal of the corresponding first selector is connected to the input terminal of the control unit; When m=1, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit; When each first selector selects the first input terminal, the multiple off-chip registers respectively included in the M repair modules form M first off-chip register chains, which are used to support the repair of each storage unit in the corresponding repair module.

[0021] Among them, the repair module can be controlled by a memory built-in self-test controller (Memory Built In Self Test Controller, MBIST Controller), each repair module can correspond to a memory built-in self-test controller respectively, the repair module includes a number of storage units, and the storage units included in any repair module can be configured by the implementer. The non-volatile memory can use an electrical fuse (eFuse), which is different from on-chip registers and off-chip registers. The non-volatile memory can retain data without an external power supply. The control unit corresponding to the non-volatile memory can be used to configure the selection status of each first selector, as well as configure the clock frequency and then configure the serial shift time of each repair module.

[0022] Specifically, the number of storage units included in each repair module may be different, and the repair types of the included storage units may be different. The repair types may include serial type and parallel type. The on-chip register may be used to support serial type storage unit repair.

[0023] In a m In, when b i When it is parallel type, b i with c i Connect, c i Directly through b i The port sends the repair data to b i .

[0024] When b i When it is a serial type, d i The repair data needs to be obtained by stringing in the data bit by bit. If i=1, then c i d i The input terminals are connected to a m The output end of the corresponding first selector is connected, that is, the input ends of c1 and d1 are connected to the output end of the first selector corresponding to the corresponding repair module. If i≠1, then c i d i The input terminals are connected to c i-1 The output terminal of the connection, that is, c i d i The input ends of the registers are connected to the output ends of the previous external register.

[0025] When b i For parallel type, if i=1, then c i The input terminal and a m The output terminal of the corresponding first selector is connected, that is, the input terminal of c1 is connected to the output terminal of the first selector corresponding to the corresponding repair module. If i≠1, then c i The input terminal and c i-1The output terminal of the connection, that is, c i The input terminals of the register are connected to the output terminals of the previous external register, thus forming a m The external register chain.

[0026] When i=N(m), it means c i is the last storage unit of the repair module. If m≠M, then c i The output terminals are connected to a m The first input terminal of the corresponding first selector and a m+1 The second input terminal of the corresponding first selector is connected, that is, when c i When the repair module is not the last repair module, c i are respectively connected to the first input end of the first selector corresponding to the corresponding repair module and the second input end of the first selector corresponding to the next repair module. If m=M, then c i The output terminals are connected to a m The first input terminal of the corresponding first selector is connected to the input terminal of the control unit, that is, when c i When the repair module is the last repair module, c i They are respectively connected to the first input end of the first selector corresponding to the corresponding repair module and the input end of the control unit of the non-volatile memory.

[0027] When m=1, it means a m is the first repair module, a m The second input end of the corresponding first selector is connected to the output end of the control unit, that is, the second input end of the first selector corresponding to the first repair module is connected to the output end of the control unit.

[0028] When each first selector selects the first input end, M first off-chip register chains are formed by several off-chip registers respectively included in the M repair modules. The identifier of the first input end can be 1, and correspondingly, the representation of the second input end can be 0. When each first selector selects the first input end, for any repair module, the input end of the first storage unit in the repair module receives the data of the output end of the last storage unit in the repair module, that is, the repair module only serially transmits the repair data in the off-chip registers it contains, without the need for repair data outside the repair module, and thus each repair module corresponds to a first off-chip register chain.

[0029] See also Figure 1, which is a structural diagram of a storage repair system based on a polymorphic BISR chain provided in Example 1 of the present invention. The structural diagram takes two repair modules, each of which includes three storage units, as an example. To facilitate the distinction and description, the two repair modules are marked as repair module 1 and repair module 2, respectively. The three storage units included in repair module 1 are storage unit 11, storage unit 12, and storage unit 13, respectively. Storage unit 12 is a parallel type, and storage unit 11 and storage unit 13 are serial types. The three storage units included in repair module 2 are storage unit 21, storage unit 22, and storage unit 23, respectively. Storage unit 22 is a serial type, and storage unit 21 and storage unit 23 are parallel types.

[0030] The first off-chip register chain is used to support the repair of each storage unit in the corresponding repair module. When the storage unit in the repair module needs to be repaired, a single repair module performs serial transmission of the repair data through its corresponding first off-chip register chain. It can be known that if the sum of the chain lengths of the off-chip registers included in the first off-chip register chain is L, then the repair module can complete the serial transmission after performing a serial shift by L bits through its corresponding first off-chip register chain.

[0031] In a specific embodiment, the on-chip register includes an input port, a clock port, and a reset port, wherein the reset port is used to initialize the state of the corresponding on-chip register; When repairing any serial type storage unit, the on-chip register corresponding to the storage unit receives a clock signal through the clock port, and transmits the repair data bit by bit according to the clock signal.

[0032] The clock port can be used to receive a clock signal provided by a control unit of the non-volatile memory, thereby controlling the shift time interval of the on-chip register.

[0033] In a specific embodiment, when b i When it is parallel type, b i Including input terminal; When repairing any parallel type of storage unit, the storage unit receives repair data through its input terminal.

[0034] Among them, the parallel type storage unit can directly receive the repair data through the input end without shifting and stringing it in, that is, the input end bit width of the parallel type storage unit is the same as the sum of the repair data bit width and the repair enable flag bit width.

[0035] In a specific embodiment, the on-chip register further includes an output terminal, and each serial type storage unit corresponds to a second selector; Accordingly, when b iFor serial type, if i≠1 and b i-1 The corresponding repair type is serial type, then c i d i The input terminals are connected to b i-1 The corresponding output terminal of the second selector is connected; When b i For parallel type, if i≠1 and b i-1 The corresponding repair type is serial type, then c i The input terminal and b i-1 The corresponding output terminal of the second selector is connected; When b i When the serial type is used, c i The output terminal and b i The first input terminal of the corresponding second selector is connected, d i The output terminal and b i The second input terminal of the corresponding second selector is connected.

[0036] The second selector can be used to select the output of the off-chip register and the output of the second on-chip register.

[0037] In a specific implementation, when a path test of an on-chip register is required, the second input terminal of each second selector is selected.

[0038] Among them, in the test phase, in order to enable the path of the on-chip register to be tested, this embodiment selects the second input end through the second selector, that is, the output of the on-chip register of the current storage unit is sent to the next storage unit through the second selector, rather than the output of the off-chip register of the current storage unit, so that the validity of each on-chip register can be determined in the path test phase.

[0039] In a specific embodiment, when each first selector selects the second input terminal, all off-chip registers form a second off-chip register chain, which is used to support the non-volatile memory to record the repair data of each off-chip register.

[0040] Among them, when each first selector selects the second input terminal, all the off-chip registers included in each repair module form a second off-chip register chain. The second off-chip register chain is used to perform serial shifting through the second off-chip register chain when the non-volatile memory has not yet stored the repair data of each storage unit, and directly or compressedly store the repair data of each off-chip register in the non-volatile memory.

[0041] In a specific embodiment, each storage unit has a corresponding built-in self-analysis circuit, and the built-in self-analysis circuit is used to analyze the repair data of the corresponding storage unit and send the repair data of the corresponding storage unit to the off-chip register of the corresponding storage unit; For any repair module, determine the chain length corresponding to the repair module according to the sum of the bit widths of the repair data of each storage unit contained in the repair module; Determine the repair time of the repair module according to the chain length corresponding to the repair module and the preset clock cycle; The maximum repair time of each repair module is taken as the overall repair time; The repair module to which each storage unit belongs is determined based on the overall time consumption and a preset time consumption threshold.

[0042] Among them, when the first off-chip register chain is used to repair the storage unit, the overall time consumption is the maximum value of the repair time consumption of each first off-chip register chain. When the overall time consumption is less than the preset time consumption threshold, it can be considered that the duration of the overall storage repair meets expectations, and the current repair module division method can be used for repair. When the overall time consumption is greater than or equal to the preset time consumption threshold, it can be considered that the duration of the overall storage repair exceeds expectations, and the storage units included in the repair module need to be adjusted. The adjustment method may include adding a new repair module and adjusting the storage units in the repair module to other repair modules. The implementer can determine the adjustment method of each repair module based on actual conditions.

[0043] In a specific embodiment, each repair module corresponds to a shift counter; For any repair module, determine the bit width of the shift counter corresponding to the repair module according to the chain length corresponding to the repair module; Determine the area increase amount according to the bit width of the shift counter corresponding to each repair module; The repair module to which each storage unit belongs is determined according to the area increase and a preset increase threshold.

[0044] When the first off-chip register chain is used to repair the storage unit, additional control logic needs to be added to the repair module, thereby increasing the chip area. The increase in chip area is mainly related to the bit width of the shift counter.

[0045] When the area increase is greater than or equal to the preset increase threshold, it can be considered that the area increase exceeds expectations and the storage units contained in each repair module need to be adjusted. When the area increase is less than the preset increase threshold, it can be considered that the area increase meets expectations and the current repair module division method can be used for repair.

[0046] In one embodiment, the division method of the repair module is determined collaboratively based on the above-mentioned overall time consumption and area increase. If only the overall time consumption is considered, it is obvious that taking a single storage unit as a repair module has the lowest overall time consumption. If only the area increase is considered, it is obvious that taking all storage units as a repair module has the lowest area increase. Only when the overall time consumption is less than a preset time consumption threshold and the area increase is less than a preset increase threshold can a reasonable division method of the repair module be obtained.

[0047] In the first embodiment of the present invention, the storage units in the chip are divided into multiple repair modules, and multiple first off-chip register chains are formed by several off-chip registers respectively contained in each repair module. When the storage units in the chip are repaired, the multiple first off-chip register chains can be used for repair at the same time, so that the repair time of the chip storage units is determined according to the maximum chain length of each first off-chip register chain. Compared with the prior art in which the repair time of the chip storage units is determined according to the sum of the chain lengths of all off-chip registers, the storage repair time is greatly reduced, thereby improving the storage repair efficiency. In the storage repair process, the storage units can adopt a parallel repair method or a serial repair method, and the storage repair can be compatible with storage units of different repair types.

[0048] The second embodiment provides a storage repair system based on multiple parallel BISR chains, the system comprising: P repair modules and corresponding target register chains, a non-volatile memory and a corresponding control unit, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer; For any target register chain, the target register chain determines the state information of the target register chain according to its own repair state and read state. The repair state is initially an unrepaired state, and the read state is initially a read request state. When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information satisfies the condition; When a current register chain exists, the control unit sends compressed repair data corresponding to the current register chain from the non-volatile memory to the current register chain in a sub-data manner, wherein the compressed repair data includes a plurality of sub-data, and the sub-data are uncompressed sub-data or compressed sub-data; If the current register link receives uncompressed sub-data, it continues to read the next sub-data; If the current register chain receives compressed sub-data, it stops reading the next sub-data, decompresses the most recently received compressed sub-data, determines that the reading state of the current register chain is the stop reading state, and changes the current register chain to the target register chain; For any target register chain, if the target register chain has completed decompression of the most recently received compressed sub-data, determining that the read state of the target register chain is a request read state; If the target register chain receives all sub-data in the compressed repair data corresponding to the target register chain, and the newly received compressed data is decompressed, then the repair state of the target register chain is determined to be a repaired state; When the repair states corresponding to all target register chains are in the repaired state, the repair of the P repair modules is completed.

[0049] Among them, the target register chain is used to support the repair of each storage unit in the corresponding repair module. When the storage unit in the repair module needs to be repaired, the single repair module performs serial transmission of the repair data through its corresponding target register chain. In this embodiment, the target register chain is stored in a compressed form in the non-volatile memory, which is expressed as compressed repair data. The repair data is binary data. When any data bit in the repair data is 1, it indicates that the array corresponding to the data bit needs to be repaired. When any data bit in the repair data is 0, it indicates that the array corresponding to the data bit does not need to be repaired. In this embodiment, the compression method is specifically to convert the repair data bit by bit into a compressed form. The compressed sub-data is sent to the non-volatile memory. If the current data bit is 1, the current data bit is sent to the non-volatile memory as uncompressed sub-data. If the current data bit is 0, the number of consecutive data bits that are 0 is counted, and the count result is sent to the non-volatile memory as compressed sub-data. For W consecutive data bits that are 0, only compressed sub-data with a width of log2W bits is required to be stored in the non-volatile memory, effectively saving storage space of the non-volatile memory. In addition, since the number of faulty arrays in a chip is usually not too large, otherwise they will be regarded as waste chips, the compression method of this embodiment can usually achieve a high compression rate.

[0050] See also Figure 2 , which is a flow chart of a storage repair system based on multiple parallel BISR chains provided in the second embodiment of the present invention, wherein Y indicates that the corresponding conditions are met, and N indicates that the corresponding conditions are not met.

[0051] Specifically, when the current register chain receives compressed sub-data, it needs to decompress the compressed sub-data by decrementing the counter. It can be seen that for compressed sub-data with a width of log2W bits, W clock cycles are required to complete decompression. During these W clock cycles used for decompression, the current register chain will not continue to receive sub-data. Therefore, to improve repair efficiency, this embodiment changes the current register chain to the target register chain when the current register chain decompresses the most recently received compressed sub-data. After the change, the current register chain may no longer exist. The control unit needs to determine a new current register chain from each target register chain whose status information meets the conditions. The target register chain corresponding to the previous current register chain cannot be determined as the current register chain again during the decompression process.

[0052] In a specific embodiment, the state information includes a busy state and an idle state; The target register chain determines the state information of the target register chain according to its own repair state and read state, including: If the repair state of the target register chain is an unrepaired state and the read state of the target register chain is a read request state, determining that the state information of the target register chain is a busy state; Otherwise, it is determined that the state information of the target register chain is an idle state.

[0053] The busy state may indicate that the corresponding target register chain needs to read the corresponding compression repair data from the non-volatile memory, and the idle state may indicate that the corresponding target register chain does not need to read the corresponding compression repair data from the non-volatile memory.

[0054] Specifically, when the repair state of any target register chain is the unrepaired state, and the read state of the target register chain is the stop reading state, the state information of the target register chain is the idle state.

[0055] When the repair state of any target register chain is the repaired state, the state information of the target register chain is also the idle state.

[0056] In a specific embodiment, when the current register chain does not exist, the control unit determines the current register chain from each target register chain whose status information satisfies the condition, including: When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information is busy.

[0057] Since the busy state may indicate that the corresponding target register chain needs to read the corresponding compressed repair data from the non-volatile memory, the current register chain is determined from each target register chain whose status information is the busy state.

[0058] In a specific embodiment, when the current register chain does not exist, the control unit determines the current register chain from each target register chain whose status information is busy, including: When there is no current register chain, the control unit arbitrates a target register chain as the current register chain from the target register chains whose status information is busy according to a preset priority.

[0059] Among them, since all target register chains need to be repaired when the repair is completed, there is no need to set a special priority. In this embodiment, the preset priority order can be set according to the identifier of the target register chain, that is, the first target register chain has the highest priority, and the last target register chain has the lowest priority.

[0060] It should be noted that the implementer may select other arbitration methods according to actual conditions, such as polling arbitration, etc. No matter which arbitration method is used to determine the current register chain, it is within the protection scope of this embodiment.

[0061] In a specific embodiment, the pth repair module f p Contains S(p) storage units, at f p In the g-th storage unit h g There is an off-chip register k corresponding to g , h g There are also corresponding repair types, which include serial type and parallel type. g When the corresponding repair type is serial type, h g Including on-chip registers g , when h g When the corresponding repair type is parallel, p is an integer in the range [1, P], and g is an integer in the range [1, S(p)]; In f p In, by f p The S(p) off-chip registers in form the pth target register chain, where when h g When it is parallel type, k g With h g connect; When h g For serial type, if g=1, then k g 、l g The input terminals of the control unit are connected to the output terminals of the control unit. If g≠1, then kg 、l g The input terminals are connected to k g-1 The output terminal connection; When h g For parallel type, if g=1, then k g The input end is connected to the output end of the control unit. If g≠1, then k g The input terminal and k g-1 The output terminal connection; When g=S(p), k g The output end of is connected to the input end of the control unit.

[0062] Among them, each repair module can be controlled by a control unit, and the repair module includes several storage units. The storage units included in any repair module can be configured by the implementer. The non-volatile memory can use an electrical fuse (eFuse). Different from on-chip registers and off-chip registers, the non-volatile memory can retain data without an external power supply. The control unit corresponding to the non-volatile memory can also be used to configure the clock frequency and thus configure the serial shift time of each repair module.

[0063] Specifically, the number of storage units included in each repair module may be different, and the repair types of the included storage units may be different. The repair types may include serial type and parallel type. The on-chip register may be used to support serial type storage unit repair.

[0064] In f p In, when h g When it is parallel type, k g With h g Connect, k g Directly through h g The port sends the repair data to h g When h g When the serial type is used, l g The repair data needs to be obtained by stringing in the data bit by bit.

[0065] See also Figure 3, which is a structural diagram of a storage repair system based on multiple parallel BISR chains provided in Example 2 of the present invention. The structural diagram takes two repair modules, each of which includes three storage units, as an example. To facilitate the distinction and description, the two repair modules are marked as repair module 3 and repair module 4 respectively. The three storage units included in repair module 3 are storage unit 31, storage unit 32 and storage unit 33 respectively. Storage unit 32 is a parallel type, and storage unit 31 and storage unit 33 are serial types. The three storage units included in repair module 4 are storage unit 41, storage unit 42 and storage unit 43 respectively. Storage unit 42 is a serial type, and storage unit 41 and storage unit 43 are parallel types.

[0066] In a specific embodiment, the on-chip register includes an input port, a clock port, and a reset port, wherein the reset port is used to initialize the state of the corresponding on-chip register; When repairing any serial type storage unit, the on-chip register corresponding to the storage unit receives a clock signal through the clock port, and transmits the repair data bit by bit according to the clock signal.

[0067] The clock port can be used to receive a clock signal provided by a control unit of the non-volatile memory, thereby controlling the shift time interval of the on-chip register.

[0068] In a specific embodiment, when h g When it is parallel type, h g Including input terminal; When repairing any parallel type of storage unit, the storage unit receives repair data through its input terminal.

[0069] Among them, the parallel type storage unit can directly receive the repair data through the input end without shifting and stringing it in, that is, the input end bit width of the parallel type storage unit is the same as the sum of the repair data bit width and the repair enable flag bit width.

[0070] In a specific embodiment, the on-chip register further includes an output terminal, and each serial type storage unit corresponds to a second selector; Accordingly, when h g For serial type, if g≠1 and h g-1 The corresponding repair type is serial type, then k g 、l g The input terminals are connected to h g-1 The corresponding output terminal of the second selector is connected; When h g For parallel type, if g≠1 and h g-1 The corresponding repair type is serial type, then kg The input terminal and h g-1 The corresponding output terminal of the second selector is connected; When h g When it is a serial type, k g The output terminal and h g The first input terminal of the corresponding second selector is connected, l g The output terminal and h g The second input terminal of the corresponding second selector is connected.

[0071] Among them, the second selector can be used to select the output of the off-chip register and the output of the on-chip register. When the second selector selects the second input terminal, the path test of the on-chip register can be performed, that is, the output of the on-chip register of the current storage unit is sent to the next storage unit through the second selector, rather than the output of the off-chip register of the current storage unit, so that the validity of each on-chip register can be determined in the path test stage.

[0072] It should be noted that the polymorphic BISR chain provided in the above-mentioned embodiment 1 and the multiple parallel BISR chains provided in embodiment 2 can exist simultaneously in an MBIST repair system. For example, the target register chain in embodiment 2 can include multiple repair sub-modules, and each repair sub-module corresponds to a first off-chip register chain.

[0073] In the second embodiment, status information is set for each target register chain, so that the control unit can determine the current register chain based on the status information of each target register chain, and read the corresponding compressed repair data in the non-volatile memory from the current register chain. When the current register chain needs to decompress the received compressed sub-data, the current register chain is changed, so that multiple target register chains can read the compressed repair data in parallel. Compared with the existing solution of using multiple register chains, which requires waiting for the completion of the repair of one register chain before repairing another register chain, this can effectively improve the storage repair efficiency.

[0074] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A storage repair system based on multiple parallel BISR chains, characterized in that: The system includes: P repair modules and corresponding target register chains, a non-volatile memory and a corresponding control unit, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer; For any target register chain, the target register chain determines the state information of the target register chain according to its own repair state and read state. The repair state is initially an unrepaired state, and the read state is initially a read request state. When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information satisfies the condition; When a current register chain exists, the control unit sends compressed repair data corresponding to the current register chain from the non-volatile memory to the current register chain in a sub-data manner, wherein the compressed repair data includes a plurality of sub-data, and the sub-data are uncompressed sub-data or compressed sub-data; If the current register link receives uncompressed sub-data, it continues to read the next sub-data; If the current register chain receives compressed sub-data, it stops reading the next sub-data, decompresses the most recently received compressed sub-data, determines that the reading state of the current register chain is the stop reading state, and changes the current register chain to the target register chain; For any target register chain, if the target register chain has completed decompression of the most recently received compressed sub-data, determining that the read state of the target register chain is a request read state; If the target register chain receives all sub-data in the compressed repair data corresponding to the target register chain, and the newly received compressed data is decompressed, then the repair state of the target register chain is determined to be a repaired state; When the repair states corresponding to all target register chains are in the repaired state, the repair of the P repair modules is completed.

2. The storage repair system based on multiple parallel BISR chains according to claim 1, characterized in that: The state information includes a busy state and an idle state; The target register chain determines the state information of the target register chain according to its own repair state and read state, including: If the repair state of the target register chain is an unrepaired state and the read state of the target register chain is a read request state, determining that the state information of the target register chain is a busy state; Otherwise, it is determined that the state information of the target register chain is an idle state.

3. The storage repair system based on multiple parallel BISR chains according to claim 2, characterized in that: When the current register chain does not exist, the control unit determines the current register chain from each target register chain whose status information satisfies the condition, including: When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information is busy.

4. The storage repair system based on multiple parallel BISR chains according to claim 3, characterized in that: When the current register chain does not exist, the control unit determines the current register chain from each target register chain whose status information is busy, including: When there is no current register chain, the control unit arbitrates a target register chain as the current register chain from the target register chains whose status information is busy according to a preset priority.

5. The storage repair system based on multiple parallel BISR chains according to claim 1, characterized in that: The pth repair module f p Contains S(p) storage units, at f p In the g-th storage unit h g There is an off-chip register k corresponding to g , h g There are also corresponding repair types, which include serial type and parallel type. g When the corresponding repair type is serial type, h g Including on-chip registers g p is an integer in the range [1, P], g is an integer in the range [1, S(p)]; In f p In, by f p The S(p) off-chip registers in form the pth target register chain, where when h g When it is parallel type, k g With h g connect; When h g For serial type, if g=1, then k g 、l g The input terminals of the control unit are connected to the output terminals of the control unit. If g≠1, then k g 、l g The input terminals are connected to k g-1 The output terminal connection; When h g For parallel type, if g=1, then k g The input end is connected to the output end of the control unit. If g≠1, then k g The input terminal and k g-1 The output terminal connection; When g=S(p), k g The output end of is connected to the input end of the control unit.

6. The storage repair system based on multiple parallel BISR chains according to claim 5, characterized in that: The on-chip register includes an input terminal, a clock port and a reset port, wherein the reset port is used to initialize the state of the corresponding on-chip register; When repairing any serial type storage unit, the on-chip register corresponding to the storage unit receives a clock signal through the clock port, and transmits the repair data bit by bit according to the clock signal.

7. The storage repair system based on multiple parallel BISR chains according to claim 5, characterized in that: When h g When it is parallel type, h g Including input terminal; When repairing any parallel type of storage unit, the storage unit receives repair data through its input terminal.

8. The storage repair system based on multiple parallel BISR chains according to claim 6, characterized in that: The on-chip register further includes an output terminal, and each serial type storage unit corresponds to a second selector; Accordingly, when h g For serial type, if g≠1 and h g-1 The corresponding repair type is serial type, then k g 、l g The input terminals are connected to h g-1 The corresponding output terminal of the second selector is connected; When h g For parallel type, if g≠1 and h g-1 The corresponding repair type is serial type, then k g The input terminal and h g-1 The corresponding output terminal of the second selector is connected; When h g When it is a serial type, k g The output terminal and h g The first input terminal of the corresponding second selector is connected, l g The output terminal and h g The second input terminal of the corresponding second selector is connected.

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