Power management circuit and device

Abstract

The invention relates to a power management circuit and device, and the circuit comprises a protocol management module, and a protocol communication end of the protocol management module is used for negotiating a power transmission protocol of external equipment through a power transmission interface, so as to adjust the output state of a level output control end of the protocol management module through the power transmission protocol; the enabling end of the power management module is connected with the enabling control end of the protocol management module, and the voltage output end of the power management module provides voltage for external equipment; the controlled end of the voltage division circuit selection module is connected with the level output control end of the protocol management module; the voltage division input end of the voltage division circuit selection module is connected with the feedback input end of the power management module; the voltage division circuit selection module adjusts the voltage division value through the output state of the level output control end. And the feedback input voltage input by the power supply management module changes along with the partial voltage value and is used for adjusting the voltage provided for the external equipment. Through the structure, the cost of the power management circuit can be reduced.

Description

Technical Field

[0001] The present application relates to the field of power management technology, and in particular to a power management circuit and device. Background Art

[0002] With the rapid development of fast-charging technology for end devices, existing hardware circuit designs that use a PD chip (Power Delivery chip) to control a power management chip typically rely on communication protocols such as I2C and SPI for interaction. This approach requires the power management chip to have dedicated communication interface pins (such as SDA and SCL) and to connect to the PD chip via external circuitry. This design enables high-precision power parameter configuration and status monitoring in complex systems and has become a mainstream technical solution in the industry.

[0003] However, the introduction of a communication interface in the related technology forces the power management chip to add additional dedicated pins and supporting circuits. During the implementation process, the applicant discovered that the related technology at least has the problem of excessively high costs for the power management circuit. Summary of the Invention

[0004] Based on this, the purpose of this application is to solve at least one of the above-mentioned technical defects, especially the technical defect that the power management circuit in the prior art is difficult to handle. This application provides a power management circuit and device.

[0005] In a first aspect, the present application provides a power management circuit, the circuit comprising:

[0006] A protocol management module, wherein the protocol communication terminal of the protocol management module is used to negotiate the power transmission protocol of the external device through the power transmission interface, so as to adjust the output state of the level output control terminal of the protocol management module through the power transmission protocol;

[0007] The power management module has an enable terminal connected to the enable control terminal of the protocol management module, and a voltage output terminal that provides voltage to external devices;

[0008] A voltage divider circuit selection module, wherein the controlled end of the voltage divider circuit selection module is connected to the level output control end of the protocol management module; and the voltage divider input end of the voltage divider circuit selection module is connected to the feedback input end of the power management module;

[0009] The voltage divider circuit selection module adjusts the voltage divider value through the output state of the level output control terminal; the feedback input voltage input by the power management module changes with the voltage divider value and is used to adjust the voltage provided to the external device.

[0010] In one embodiment, the voltage divider circuit selection module includes:

[0011] Multiple voltage dividing units, the controlled end of each voltage dividing unit is respectively connected to multiple level output control ends of the protocol management module;

[0012] The voltage division input terminal of each voltage division unit is connected to the feedback input terminal of the power management module;

[0013] The voltage divider output terminal of each voltage divider unit is used for grounding.

[0014] In one embodiment, the voltage dividing unit includes:

[0015] A voltage divider resistor unit, one end of which is connected to a feedback input terminal of the power management module;

[0016] A transistor unit, wherein a controlled end of the transistor unit is connected to a level output control end of the protocol management module, an input end of the transistor unit is connected to the other end of the voltage divider resistor unit, and an output end of the transistor unit is grounded;

[0017] The resistance values ​​of the voltage-dividing resistor units are different.

[0018] In one embodiment, the transistor unit includes:

[0019] NMOS transistor, the gate is connected to the level output control terminal of the protocol management module, the drain is connected to the other end of the voltage divider resistor unit, and the source is used for grounding;

[0020] A pull-down resistor has one end connected to the level output control terminal of the protocol management module and the gate of the NMOS tube, and the other end connected to the source of the NMOS tube.

[0021] In one embodiment, the circuit further comprises:

[0022] A fixed voltage divider module, wherein a first end of the fixed voltage divider module is respectively connected to a voltage divider input end of the voltage divider circuit selection module and a feedback input end of the power management module; and a second end of the fixed voltage divider module is used for grounding;

[0023] The voltage division value of the fixed voltage division module is not equal to the voltage division value of the voltage division circuit selection module.

[0024] In one embodiment, the circuit further comprises:

[0025] The impedance matching module has a first end connected to the level output control end of the protocol management module and a second end connected to the controlled end of the voltage divider circuit selection module.

[0026] In one embodiment, the impedance matching module includes:

[0027] A first resistor, one end of which is the level output control end of the protocol management module and the other end is grounded;

[0028] A second resistor, one end of which is connected to the level output control end of the protocol management module and one end of the first resistor respectively, and the other end of the second resistor is connected to the controlled end of the voltage divider circuit selection module;

[0029] The capacitor has one end connected to the other end of the second resistor and the controlled end of the voltage divider circuit selection module, and the other end is grounded.

[0030] In one embodiment, the power management module includes:

[0031] Input stabilization unit, the first end is used to connect to the system power supply;

[0032] A power management chip, wherein the enable terminal is connected to the enable control terminal of the protocol management module, and the voltage input terminal is used to connect to the second terminal of the input stabilization unit;

[0033] The output stabilization unit has a first end connected to the voltage output end of the power management chip, and a second end connected to the feedback input end of the power management chip and the voltage divider input end of the voltage divider circuit selection module, and is also used to output a stable voltage to external devices.

[0034] In one embodiment, the output stabilization unit includes:

[0035] A high-frequency filter unit, a first end of which is connected to the voltage output end of the power management chip, and a second end of which is grounded;

[0036] The multi-frequency filtering unit has a first end connected to the voltage output end of the power management chip and the first end of the high-frequency filtering unit respectively, and a second end of the multi-frequency filtering unit is used to connect to an external device.

[0037] In a second aspect, the present application provides a power management device, comprising the power management circuit as described above.

[0038] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0039] The power management circuit and device provided by the present application can control the enablement of the power management module and thus control the working state of the power management module by connecting the protocol management module to the enablement of the power management module and controlling the voltage divider value selected by the voltage divider circuit selection module through the level output control terminal of the protocol management module. When the power management module is in the working state, the voltage divider of the voltage divider circuit selection module can be adjusted to adjust the input feedback of the power management module, thereby allowing the power management module to adjust the voltage provided to the external device. In this way, compared with traditional technologies, the present application, through the above-mentioned structure, does not rely on additional dedicated pins and supporting circuits, and can implement adjustment feedback management of the circuit management module and output a voltage that meets the negotiation with the external device, thereby reducing the cost of the power management circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 A schematic diagram of the structure of a power management circuit provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of the specific structure of a voltage divider circuit selection module provided in an embodiment of the present application;

[0043] Figure 3 A schematic structural diagram of a voltage divider unit provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the structure of another power management circuit provided in an embodiment of the present application;

[0045] Figure 5 A schematic structural diagram of an impedance matching module provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the structure of a PD module provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of the structure of a power management module provided in an embodiment of the present application;

[0048] Figure 8 A schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0049] Figure 9 A schematic diagram of the structure of a power management circuit based on GPIO port control of a PD module provided in an embodiment of the present application.

[0050] Reference numerals:

[0051] 10-power management circuit; 20-external device; 110-protocol management module; 120-power management module; 130-voltage divider circuit selection module; 130a-voltage divider unit; 140-fixed voltage divider module; 150-impedance matching module; 121-input stabilization unit; 122-power management chip; 123-output stabilization unit. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] With the rapid development of fast charging technology for terminal devices, in existing hardware circuit design, using PD chips to control power management chips usually requires I2C or other communication methods. This solution requires the power management chip to have external communication pins, but adopting this method in some simple applications will result in high costs and increased difficulty.

[0054] Based on this, the present application provides a power management circuit and device that can utilize the PD's GPIO port to control the power management chip without requiring additional communication pins and circuitry, thereby reducing the complexity and cost of hardware design. Furthermore, the GPIO port's control logic is relatively simple, and the delay and noise introduced during the communication process are relatively low, thereby improving the real-time performance and accuracy of power management.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0056] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0058] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0059] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0060] In an exemplary embodiment, Figure 1 A schematic diagram of a power management circuit according to an embodiment of the present invention is shown in FIG. Figure 1 As shown, a power management circuit 10 is provided, which includes:

[0061] The protocol management module 110 , the protocol communication terminal of the protocol management module 110 is used to negotiate the power transmission protocol of the external device 20 through the power transmission interface, so as to adjust the output state of the level output control terminal of the protocol management module 110 through the power transmission protocol.

[0062] The protocol management module 110 may be a module for managing a power transmission protocol or a power transmission protocol. For example, it may be a power transmission management module based on a USB (Universal Serial Bus) interface. For example, the protocol management module 110 may be referred to as a PD module. The power transmission protocol may refer to a charging protocol, for example, including key information such as charging voltage and current. This communication negotiation process may be based on the PD protocol to ensure an effective match between power supply and demand. The external device 20 refers to a device connected to the power management circuit 10, for example, a device that requires charging.

[0063] Illustratively, the protocol management module 110 includes a protocol communication terminal that can be used to connect to the communication terminal of the protocol interface of the external device 20. For example, the protocol communication terminal of the protocol management module 110 is used to connect to the CC line of the Type-C interface of the external device 20 to communicate and negotiate with the sink terminal of the external device 20 to determine key information such as charging voltage and current. This communication process is based on the PD protocol and ensures an effective match between power supply and demand.

[0064] The protocol management module 110 can adjust the output state of the level output control terminal of the protocol management module 110 based on the power transmission protocol to control the circuit state of the subsequent circuit and realize the input and output control of the power management. For example, the protocol management module 110 can be a PD chip. The PD chip completes communication with the sink end and receives a clear charging instruction. It will adjust its internal logic according to the received signal to make the corresponding GPIO port output a high or low level signal. These GPIO ports are specially designed to be used to control the enable state of the external power management chip 122.

[0065] The power management module 120 has an enable terminal connected to the enable control terminal of the protocol management module 110 , and a voltage output terminal that provides voltage to the external device 20 .

[0066] The power management module 120 may be the core power processing unit of the power management circuit 10, which can dynamically adjust the output voltage based on the feedback signal and provide a stable power supply to the external device 20. The power management module 120 may be a PMIC (Power Management Integrated Circuit) module.

[0067] For example, the enable control terminal of the protocol management module 110 (e.g., the EN pin of the PD chip) can be directly connected to the enable terminal of the power management module 120 (e.g., the EN pin of the PMIC module). The voltage output terminal of the protocol management module 110 can be directly connected to the external device 20 (e.g., a mobile phone, tablet, etc.), providing the external device 20 with a negotiated target voltage (e.g., 5V / 9V / 12V, etc.).

[0068] In actual applications, when the protocol negotiation is completed, the protocol management module 110 can output a valid level (such as a high level) by enabling the control terminal to trigger the power management module 120 to start; if the negotiation fails or the power supply needs to be shut down, an invalid level (such as a low level) can be output.

[0069] The voltage divider circuit selection module 130 has a controlled end connected to the level output control end of the protocol management module 110 ; and a voltage divider input end connected to the feedback input end of the power management module 120 .

[0070] The voltage divider circuit selection module 130 adjusts the voltage divider value through the output state of the level output control terminal; the feedback input voltage input by the power management module 120 changes with the voltage divider value and is used to adjust the voltage provided to the external device 20.

[0071] Among them, the voltage divider circuit selection module 130 can be a key circuit module for feedback control. It can change the feedback voltage value by switching different voltage divider resistor networks, thereby indirectly controlling the output voltage of the power management module 120. The controlled end refers to the one that can be used to receive the level output control signal (such as GPIO high / low level combination) of the protocol management module 110 to select different voltage divider paths. The feedback input end of the protocol management module 110 can receive the voltage divider value signal of the voltage divider circuit selection module 130 to adjust the output voltage in real time to meet the demand.

[0072] For example, the level output control terminal of the protocol management module 110 (e.g., a GPIO pin of a PD chip) is connected to the controlled terminal of the voltage divider circuit selection module 130. The voltage divider input terminal of the voltage divider circuit selection module 130 can be connected to the feedback input terminal of the power management module 120 (e.g., the FB pin of the PMIC module) to transmit the voltage divider value to the power management module 120.

[0073] Specifically, the protocol management module 110 may output a specific level combination (such as 01 or 10) through the GPIO according to the negotiation result (such as the target voltage 9V), and control the voltage divider circuit selection module 130 to switch to the corresponding voltage divider resistor network.

[0074] The voltage divider value (such as the R1 / R2 ratio) of the voltage divider circuit selection module 130 can determine the feedback voltage value. The power management module 120 dynamically adjusts the output voltage according to the feedback voltage (such as by adjusting the duty cycle or reference voltage), and ultimately achieves an output voltage that matches the protocol negotiation result (such as 9V).

[0075] In this embodiment, by enabling the protocol management module 110 and the power management module 120, and controlling the voltage divider value selected by the voltage divider circuit selection module 130 through the level output control terminal of the protocol management module 110, the power management module 120 can be enabled, thereby controlling the operating state of the power management module 120. When the power management module 120 is in the operating state, the voltage divider of the voltage divider circuit selection module 130 can be used to adjust the input feedback of the power management module 120, thereby allowing the power management module 120 to adjust the voltage provided to the external device 20. In this way, compared with conventional technologies, the present application, through the above-mentioned structure, does not rely on additional dedicated pins and supporting circuits, and can implement adjustment feedback management of the power management module, output a voltage that meets the negotiation with the external device 20, thereby reducing the cost of the power management circuit 10.

[0076] In an exemplary embodiment, Figure 2 A schematic diagram of the specific structure of a voltage divider circuit selection module provided in an embodiment of the present application; Figure 2 As shown, the voltage divider circuit selection module 130 includes:

[0077] The plurality of voltage dividing units 130 a are configured, and the controlled end of each voltage dividing unit 130 a is respectively connected to the plurality of level output control ends of the protocol management module 110 .

[0078] The voltage division input terminal of each voltage division unit 130 a is connected to the feedback input terminal of the power management module 120 .

[0079] The voltage division output terminal of each voltage division unit 130a is grounded.

[0080] The voltage dividing unit 130a may be an independent resistor network branch, and may include a switch element (such as a MOSFET, a transistor) and a voltage dividing resistor unit.

[0081] Exemplarily, the controlled end of each voltage dividing unit 130 a is connected to a certain level output control end (such as GPIO1 , GPIO2 , etc.) of the protocol management module 110 to receive a switch control signal.

[0082] The voltage divider inputs of all voltage divider units 130a can be connected in parallel to the feedback input (FB) of the power management module 120 to form a feedback voltage sampling point. Furthermore, the voltage divider outputs of each voltage divider unit 130a are connected to ground (GND), forming a pull-down path for the voltage divider loop, ensuring a closed circuit.

[0083] Specifically, the protocol management module 110 determines the requirements of the external device 20 through the PD protocol. The protocol management module 110 outputs a specific GPIO combination (for example, GPIO1 = high, GPIO2 = low, GPIO3 = high), turning on the switches of the corresponding voltage divider units 130a. The conducting voltage divider units 130a (such as those controlled by GPIO1 and GPIO3) have their voltage divider resistors (R1 + R3) connected to the feedback loop. The resistors of the non-conducting voltage divider units 130a (such as those controlled by GPIO2) are bypassed because their switches are off.

[0084] In this embodiment, the voltage divider circuit selection module 130 can directly use the general GPIO pin of the protocol management module 110 (such as the PD chip) to control the switch of the voltage divider unit 130a. There is no need to add a dedicated communication interface to the power management module 120, and the internal communication protocol parsing logic (such as the I2C controller) of the power management chip 122 can be omitted, simplifying the chip design. The voltage divider circuit selection module 130 only requires switching elements (such as MOS tubes) and voltage divider resistors, and directly controls the switch state through the GPIO high and low levels, without the need for complex interface circuits, thereby reducing costs.

[0085] In an exemplary embodiment, the voltage dividing unit includes:

[0086] A voltage divider resistor unit, one end of which is connected to a feedback input terminal of the power management module;

[0087] A transistor unit, wherein a controlled end of the transistor unit is connected to a level output control end of the protocol management module, an input end of the transistor unit is connected to the other end of the voltage divider resistor unit, and an output end of the transistor unit is grounded;

[0088] The resistance values ​​of the voltage-dividing resistor units are different.

[0089] The voltage-divider resistor unit can be the core component of the voltage-divider circuit. Its resistance difference can form a voltage-divider network with the pull-up resistor included in the power management module, generating a feedback voltage for output voltage regulation. The transistor unit can act as an electronic switch, controlled by a level signal from the protocol management module to open or close the ground path of the voltage-divider resistor unit, thereby dynamically switching the voltage-divider network.

[0090] For example, one end of the voltage divider resistor unit can serve as the voltage divider input end of the voltage divider unit to receive the output voltage signal to be divided, and the other end of the voltage divider resistor unit is connected to the input end of the transistor unit to form a pull-down path of the voltage divider loop.

[0091] The controlled terminal (e.g., base or gate) of the transistor unit can be connected to the level output control terminal (e.g., GPIO pin) of the protocol management module to receive the switch control signal. The input terminal (e.g., collector or drain) of the transistor unit can be connected to the other end of the voltage divider resistor unit, thus joining the voltage divider loop. The output terminal (e.g., emitter or source) of the transistor unit can be directly connected to ground to complete the voltage divider loop.

[0092] Specifically, different resistance values ​​can be used to achieve multi-level voltage output, and dedicated communication interfaces can be replaced by reusing GPIO pins to reduce the number of chip pins, thereby reducing costs.

[0093] In this embodiment, voltage level division can be achieved at the hardware level through voltage-dividing resistor units with different resistance values, without relying on software configuration or programmable devices, and the target voltage can be set directly through a fixed resistance value, which can significantly reduce hardware costs. The general GPIO pins of the protocol management module can be reused as the level output control terminal of the protocol management module, eliminating the dedicated communication interface of the power management module, thereby greatly reducing the cost of the power management circuit.

[0094] In an exemplary embodiment, Figure 3 A schematic diagram of a voltage divider unit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, combined Figure 2 , the transistor unit includes:

[0095] NMOS transistor U2, with a gate connected to the level output control terminal of the protocol management module 110, a drain connected to the other end of the voltage divider resistor unit, and a source connected to ground;

[0096] The pull-down resistor R18 has one end connected to the level output control terminal of the protocol management module 110 and the gate of the NMOS transistor, and the other end connected to the source of the NMOS transistor.

[0097] Among them, NMOS (N-channel metal oxide semiconductor field effect transistor) can be used as an electronic switch to control the conduction state between the drain and the source through the gate voltage, so that it can be selected whether the voltage divider resistor unit is connected to the feedback loop.

[0098] For example, the gate of the NMOS transistor is connected to a level output control terminal (e.g., a GPIO pin) of the protocol management module 110 to receive a control signal (high / low level). The drain of the NMOS transistor is connected to the other end of the voltage divider resistor unit, forming the input path of the voltage divider loop. The source of the NMOS transistor can be directly grounded, closing the voltage divider loop.

[0099] The pull-down resistor is connected between the gate and source (ground) of the NMOS tube to ensure that the gate remains at a low level when there is no control signal, avoiding the NMOS tube from being mis-turned on due to a floating state.

[0100] Optionally, when the GPIO outputs a high level (such as 3.3V), the NMOS transistor is turned on and the voltage divider resistor unit is connected to the feedback loop. When the GPIO outputs a low level (0V), the NMOS transistor is turned off and the voltage divider resistor unit is bypassed.

[0101] When the NMOS is on, the voltage divider current flows from the FB pin of the power management module 120, the voltage divider resistor unit, the NMOS drain, the NMOS source, and the ground in sequence to form a closed loop. When the NMOS is off, the voltage divider loop is disconnected and the voltage divider resistor unit does not participate in generating the feedback voltage.

[0102] In this embodiment, only NMOS tubes and pull-down resistors are required to realize voltage divider network switching, without the need for additional driving circuits or level conversion devices. In this way, the cost of the power management circuit 10 can be reduced, and the risk of gate floating can be eliminated through the pull-down resistors, ensuring that the NMOS tube is reliably shut down when there is no signal, avoiding incorrect access to the voltage divider network, and can also suppress gate noise through the pull-down resistors, thereby improving the anti-interference ability of the digital signal of the GPIO port of the protocol management module 110.

[0103] Alternatively, as Figure 3 As shown, the voltage divider resistor unit includes: two resistors connected in series, wherein one end of the resistor R20 is connected to the feedback input end of the power management module 120, the other end of the resistor R20 is connected to one end of the resistor R19, and the other end of the resistor R19 is connected to the drain of the NMOS tube U2.

[0104] In actual applications, another voltage divider unit includes an NMOS transistor U3, a resistor R12 (pull-down resistor), a resistor R13, and a resistor R14 (voltage divider resistor unit); another voltage divider unit includes an NMOS transistor U4, a resistor R15 (pull-down resistor), a resistor R16, and a resistor R17 (voltage divider resistor unit).

[0105] In an exemplary embodiment, Figure 4 This is a structural diagram of another power management circuit 10 provided in an embodiment of the present application, as shown in FIG. Figure 4 As shown, the circuit also includes:

[0106] The fixed voltage divider module 140 has a first end connected to the voltage divider input of the voltage divider circuit selection module and the feedback input of the power management module 120 ; and a second end of the fixed voltage divider module 140 is grounded.

[0107] The voltage division value of the fixed voltage division module 140 is not equal to the voltage division value of the voltage division circuit selection module 130 .

[0108] Exemplarily, the fixed voltage divider module 140 can be a fixed resistor network permanently connected to the feedback loop. It is connected in parallel with the voltage divider circuit selection module 130 between the feedback input of the power management module 120 and ground, forming a composite voltage divider network for providing a reference voltage divider value or expanding the voltage regulation range. The first terminal of the fixed voltage divider module 140 can be connected to the voltage divider input of the voltage divider circuit selection module 130 and to the feedback input of the power management module 120. The second terminal of the fixed voltage divider module 140 can be directly connected to ground, completing the voltage divider loop.

[0109] In practical applications, a fixed voltage division ratio is achieved by the fixed voltage division module 140 , whose voltage division value is not equal to the voltage division value of the voltage division circuit selection module 130 , and the total feedback voltage can be affected by the parallel structure.

[0110] Optionally, in the PMIC module circuit, when the PMIC chip is enabled and all related MOS tubes are in the off state, the circuit can enter the default state, set a default output voltage, and connect a fixed resistor (fixed voltage divider module 140) to the FB pin of the PMIC.

[0111] In this embodiment, by connecting the fixed voltage divider module 140 in parallel with the switchable voltage divider unit 130a, a finer or wider range of voltage divider values ​​can be generated by adjusting the on / off state of the voltage divider unit 130a, and by always connecting the fixed voltage divider module 140 to the circuit, the feedback loop is avoided from being open when the voltage divider circuit selection module 130 is fully turned off, thereby improving system stability.

[0112] In an exemplary embodiment, Figure 4As shown, the circuit also includes:

[0113] The impedance matching module 150 has a first end connected to the level output control end of the protocol management module 110 and a second end connected to the controlled end of the voltage divider circuit selection module.

[0114] Among them, the impedance matching module 150 may refer to a circuit unit for optimizing the signal transmission quality. Its core function is to reduce signal reflection or attenuation by adjusting the output impedance of the signal source to match the input impedance of the load, thereby ensuring that the control level of the protocol management module 110 can stably and efficiently drive the controlled end of the voltage divider circuit selection module.

[0115] For example, a first terminal of the impedance matching module 150 is connected to a level output control terminal (e.g., a GPIO pin) of the protocol management module 110 to receive the original control signal. A second terminal of the impedance matching module 150 can be connected to a controlled terminal (e.g., the gate of an NMOS transistor) of the voltage divider circuit selection module to output the control signal after impedance matching.

[0116] In this embodiment, the impedance matching module 150 is used to perform impedance matching with the sink end to ensure effective signal transmission, suppress high-frequency noise and ringing of the control signal, and avoid malfunction of the voltage divider circuit selection module 130.

[0117] In an exemplary embodiment, Figure 5 A schematic diagram of the structure of an impedance matching module 150 provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the impedance matching module 150 includes:

[0118] A first resistor R5, one end of which is connected to the level output control terminal of the protocol management module 110, and the other end of which is grounded;

[0119] A second resistor R4, one end of which is connected to the level output control terminal of the protocol management module 110 and one end of the first resistor, and the other end of which is connected to the controlled end of the voltage divider circuit selection module;

[0120] The capacitor C10 has one end connected to the other end of the second resistor and the controlled end of the voltage divider circuit selection module, and the other end is grounded.

[0121] Exemplarily, the first resistor can be a pull-down resistor, connected between the level output control terminal of the protocol management module 110 and the ground, to ensure that when the protocol management module 110 does not output a valid level, the control terminal potential is pulled down to the ground, thereby avoiding malfunction caused by the controlled terminal floating.

[0122] The second resistor may be a series resistor connected between the level output control terminal of the protocol management module 110 and the controlled terminal of the voltage divider circuit selection module, and is used to limit the driving current, suppress signal reflection, and achieve impedance matching.

[0123] One end of the capacitor can be connected to the other end of the second resistor and the controlled end of the voltage divider circuit selection module (such as the NMOS tube gate), and the other end is grounded. The capacitor and the second resistor can form a low-pass filter network for filtering out high-frequency noise and stabilizing the control signal.

[0124] Optionally, the impedance matching module 150 further includes a first resistor R7, a second resistor R6, and a capacitor C11.

[0125] Optionally, the impedance matching module 150 further includes a first resistor R8, a second resistor R9, and a capacitor C12.

[0126] Optionally, the impedance matching module 150 further includes a first resistor R11 , a second resistor R10 , and a capacitor C13 .

[0127] Alternatively, as Figure 5 As shown, the 15V_SET port, 12V_SET port, and 9V_SET port are used to control Figure 3 The gate of the corresponding NMOS tube is shown.

[0128] In this embodiment, the first resistor eliminates the floating risk, and the second resistor and capacitor suppress ringing and noise, ensuring that the control signal is clean and stable.

[0129] Optionally, Figure 6 A schematic diagram of the structure of a PD module provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the protocol management module 110 is a PD module, which includes GPIO1 pin, GPIO2 pin, GPIO3 pin, and GPIO4 pin. GPIO1 pin is used to output PD_Control_15V_IC signal, GPIO2 pin is used to output PD_Control_12V_IC signal, GPIO3 pin is used to output PD_Control_9V_IC signal, and GPIO4 pin is used to output PD_ON_IC signal. The above pins are connected to the following pins: Figure 5 corresponding ports as shown.

[0130] In an exemplary embodiment, Figure 7 A schematic diagram of the structure of a power management module 120 provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the power management module 120 includes:

[0131] The first end of the input stabilization unit 121 is used to access the system power supply.

[0132] The power management chip 122 has an enable terminal connected to the enable control terminal of the protocol management module 110 , and a voltage input terminal used to connect to the second terminal of the input stabilization unit 121 .

[0133] The output stabilization unit 123 has a first end connected to the voltage output end of the power management chip 122, and a second end connected to the feedback input end of the power management chip 122 and the voltage divider input end of the voltage divider circuit selection module, and is also used to output a stable voltage to the external device 20.

[0134] The input stabilization unit 121 may include the front-end filtering and voltage stabilization circuits of the power management module 120, which can be used to suppress noise, surges, and voltage fluctuations in the input power supply, providing a stable DC power supply for subsequent circuits. The power management chip 122 may be the core power processing unit of the system, dynamically adjusting the output voltage based on the feedback signal and controlling its start and stop status by the enable signal of the protocol management module 110. The output stabilization unit 123 may be the post-stage filtering and feedback network of the power management module 120, used to smooth the output voltage ripple and feed back the voltage-dividing signal to the power management chip 122, while providing stable power to the external device 20.

[0135] Exemplarily, the first end of the input stabilization unit 121 is directly connected to the system power supply (such as the 12V DC power supply input by the adapter), and the second end of the input stabilization unit 121 outputs the filtered stable voltage to the voltage input end of the power management chip 122.

[0136] The enable terminal of the power management chip 122 is connected to the enable control terminal (e.g., EN pin) of the protocol management module 110 and receives high / low level signals to start or shut down the chip. The voltage input terminal of the power management chip 122 is connected to the second terminal of the input stabilization unit 121 to receive filtered input power. The voltage output terminal of the power management chip 122 outputs the regulated voltage to the output stabilization unit 123. The feedback input terminal of the power management chip 122 receives the voltage-divided feedback signal from the output stabilization unit 123 for closed-loop regulation of the output voltage.

[0137] The first terminal of the output stabilization unit 123 is connected to the voltage output terminal of the power management chip 122 and receives the adjusted voltage. The second terminal of the output stabilization unit 123 is connected to the feedback input terminal (FB pin) of the power management chip 122, providing a voltage-dividing feedback signal. This is connected to the voltage-dividing input terminal of the voltage-dividing circuit selection module, allowing an external circuit to adjust the feedback ratio and output the final stable voltage to the external device 20 (such as a mobile phone or tablet).

[0138] In this embodiment, the input stabilization unit 121 suppresses power supply noise, ensuring that the power management chip 122 can still operate normally under severe input conditions.

[0139] In an exemplary embodiment, Figure 7 As shown, the output stabilization unit 123 includes:

[0140] The high-frequency filter unit has a first end connected to the voltage output end of the power management chip 122 and a second end for grounding.

[0141] The multi-frequency filtering unit has a first end connected to the voltage output end of the power management chip 122 and the first end of the high-frequency filtering unit respectively, and a second end of the multi-frequency filtering unit is used to connect to the external device 20.

[0142] The high-frequency filter unit can be a high-frequency noise suppression circuit of the output stabilization unit 123, which can be used to filter out high-frequency noise in the output voltage of the power management chip 122, ensuring the high-frequency purity of the output power. The multi-frequency filter unit can be a wide-band filter circuit of the output stabilization unit 123, covering low-frequency to medium- and high-frequency noise, further smoothing the output voltage, suppressing multi-band interference, and providing stable power to the external device 20.

[0143] Exemplarily, the first end of the high-frequency filter unit is directly connected to the voltage output of the power management chip 122, and the second end of the high-frequency filter unit is grounded, forming a bypass path for high-frequency noise. The first end of the multi-frequency filter unit is connected to the voltage output of the power management chip 122 and the first end of the high-frequency filter unit, respectively, to form a composite filter input node that receives the raw output voltage. The second end of the multi-frequency filter unit is connected to the power interface of the external device 20 to output the final stable voltage.

[0144] In this embodiment, the high-frequency filtering unit can effectively attenuate high-frequency noise, significantly reduce output voltage ripple, and can suppress low-frequency to medium- and high-frequency noise through the multi-frequency filtering unit.

[0145] Alternatively, as Figure 7 As shown, the input stabilization unit 121 includes capacitors C1, C2, C3, and C4; the high-frequency filtering unit includes capacitor C5 and resistor R1; and the multi-frequency filtering unit includes capacitors C6, C7, C8, and C9.

[0146] Alternatively, as Figure 7 As shown, the power management module 120 further includes a pull-up resistor R2; and the fixed voltage dividing module 140 includes a fixed voltage dividing resistor R3.

[0147] For example, Figure 7 The FB_SET ports shown are connected Figure 3 The corresponding port in the EN pin is connected Figure 5The PD_ON port shown, the SW pin outputs voltage, and after passing through the multi-frequency filtering unit, it is output to the +VCC_OUT port for charging the external device 20.

[0148] In an exemplary embodiment, Figure 8 A schematic diagram of the structure of a power supply module provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the power module includes:

[0149] In the DC-IN module, the CENTER+ pin is used to output the system power +VSYS, and the TIP_SPRING- pin, SHUNT pin, GND_1 pin, and GND_2 pin are all used for grounding. In this way, the system power can be effectively and stably provided to the power management circuit 10. Figure 8 The +VSYS port is connected as follows Figure 7 Connect the corresponding +VSYS port as shown and connect it through Figure 7 The VIN pin in the circuit is input for voltage processing.

[0150] In an exemplary embodiment, Figure 9 A schematic diagram of a power management circuit based on GPIO port control of a PD module provided in an embodiment of the present application; Figure 9 As shown, including: system total power supply, PIMC, PD, TYPE-C.

[0151] Among them, each of the above modules can be implemented by the modules corresponding to the above embodiments.

[0152] For example, in combination Figures 1 to 9 In the power management system, the PD chip communicates with the sink via the CC line of the Type-C interface to negotiate with the sink to determine key information such as charging voltage and current. This communication process, based on the PD protocol, ensures an effective match between power supply and demand. Once the PD chip completes communication with the sink and receives a clear charging instruction, it adjusts its internal logic based on the received signal, causing the corresponding GPIO port to output a high or low signal. These GPIO ports are designed to control the enable state of the external power management chip 122. Under the control of the GPIO port output signal, the enable pin of the PMIC chip is activated or disabled, thereby controlling whether the PMIC starts operating. When the PMIC is enabled, it begins outputting voltage according to the preset configuration. At this time, the PD chip also assigns different voltage divider resistors to the PMIC's FB pin through the GPIO port. By changing the voltage divider resistor value on the FB pin, the PMIC's output voltage can be adjusted. This adjustment mechanism ensures that the output voltage precisely matches the sink's requirements.

[0153] Optionally, four or more GPIO ports are reserved in the PD chip, depending on the voltages required at the sink end.

[0154] Optionally, the impedance matching module 150 is used to perform impedance matching with the sink end to ensure effective transmission of the signal.

[0155] Optionally, the voltage divider circuit selection module 130 includes multiple parallel voltage divider resistor combinations within the voltage divider resistor module circuit. Each combination has a different resistance value to accommodate different output voltage requirements. Each voltage divider resistor combination is connected to the FB pin of the PMIC via a MOS transistor. These MOS transistors act as electronic switches, and their conduction state is determined by the PD chip.

[0156] Optionally, in the PMIC module circuit, when the PMIC chip is enabled and all related MOS transistors are in the off state, the circuit enters a default state. To set a default output voltage, a fixed resistor R3 is connected to the FB pin of the PMIC.

[0157] Optionally, for the design of the above-mentioned power management circuit 10, it is possible to confirm in advance how much voltage the PD protocol to be used requires; reserve a GPIO port on the PD chip as required; design a corresponding voltage divider resistor selection module as required; and connect the voltage divider resistor selection module to the FB pin of the PMIC chip.

[0158] Optionally, users can reconfigure the PD chip control logic through software. The specific configuration operations are as follows: communicate the PD protocol through CC to negotiate voltage and current; determine how many modes there are; select the GPIO high level / low level of the EN pin according to different modes to control the enable / disable of the PMIC chip; select different GPIO ports as high level / low level according to different modes.

[0159] In a specific embodiment, a comparison of the material cost and power performance of the power management circuit provided by the embodiment of the present application and the related technology of PD I2C controlling PMIC is shown in Table 1 and Table 2.

[0160] Table 1 Cost comparison between traditional methods and this application

[0161]

[0162] The cost price is about 35% of the traditional method, saving about 65% of the cost.

[0163] Comparison of power supply performance between traditional methods and this application

[0164]

[0165] From Table 1 and Table 2, we can see that the performance is improved slightly while the cost is reduced by 65%.

[0166] It should be noted that Figures 1 to 9 The figure shows some ports and connection relationships of each module / unit, but in actual application, other connection relationships of the ports of each module / unit can be set according to actual needs, and the connection structure of some pins of the chip module and other units, modules or circuits provided in the embodiment of the present application is shown. Other pins not shown can be set according to actual conditions. Figures 1 to 9 The examples shown in the accompanying drawings are not intended to limit the present application.

[0167] In an exemplary embodiment, the present application provides a power management device, including the power management circuit as described above.

[0168] For example, a power management device provided in an embodiment of the present application has the same inventive concept as the above-mentioned power management circuit, and the implementation solution provided by the power management device to solve the problem is similar to the implementation solution recorded in the above-mentioned power management circuit. Therefore, the specific limitations in the provided power management device embodiment can refer to the limitations on the power management circuit above. The power management device described below and the power management circuit described above can be referenced to each other, and will not be repeated here.

[0169] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, article, or device comprising the element.

[0170] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referenced to each other.

[0171] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power management circuit, characterized in that: The circuit comprises: a protocol management module, wherein the protocol communication terminal of the protocol management module is used to negotiate a power transmission protocol of an external device through a power transmission interface, so as to adjust the output state of the level output control terminal of the protocol management module through the power transmission protocol; A power management module, wherein the enable terminal is connected to the enable control terminal of the protocol management module, and the voltage output terminal provides voltage for the external device; a voltage divider circuit selection module, wherein a controlled end of the voltage divider circuit selection module is connected to the level output control end of the protocol management module; and a voltage divider input end of the voltage divider circuit selection module is connected to the feedback input end of the power management module; The voltage divider circuit selection module adjusts the voltage divider value according to the output state of the level output control terminal; the feedback input voltage input by the power management module changes with the voltage divider value and is used to adjust the voltage provided to the external device.

2. The circuit according to claim 1, characterized in that The voltage divider circuit selection module includes: A plurality of voltage dividing units, wherein the controlled end of each voltage dividing unit is respectively connected to a plurality of level output control ends of the protocol management module; The voltage division input terminal of each voltage division unit is connected to the feedback input terminal of the power management module; The voltage dividing output terminal of each voltage dividing unit is used for grounding.

3. The circuit according to claim 2, characterized in that The voltage dividing unit includes: A voltage-dividing resistor unit, one end of which is connected to the feedback input end of the power management module; a transistor unit, wherein a controlled end of the transistor unit is connected to the level output control end of the protocol management module, an input end of the transistor unit is connected to the other end of the voltage-dividing resistor unit, and an output end of the transistor unit is grounded; Wherein, the resistance values ​​of the voltage-dividing resistor units are different.

4. The circuit according to claim 3, characterized in that The transistor unit includes: An NMOS tube, the gate of which is connected to the level output control terminal of the protocol management module, the drain of which is connected to the other end of the voltage divider resistor unit, and the source of which is grounded; A pull-down resistor, one end of which is connected to the level output control terminal of the protocol management module and the gate of the NMOS tube respectively, and the other end of which is connected to the source of the NMOS tube.

5. The circuit according to claim 1, wherein: The circuit further comprises: a fixed voltage divider module, wherein a first end of the fixed voltage divider module is respectively connected to a voltage divider input end of the voltage divider circuit selection module and a feedback input end of the power management module; and a second end of the fixed voltage divider module is used for grounding; Wherein, the voltage division value of the fixed voltage division module is not equal to the voltage division value of the voltage division circuit selection module.

6. The circuit according to claim 1, wherein: The circuit further comprises: An impedance matching module has a first end connected to the level output control end of the protocol management module and a second end connected to the controlled end of the voltage divider circuit selection module.

7. The circuit according to claim 6, characterized in that The impedance matching module includes: a first resistor, one end of which is connected to the level output control terminal of the protocol management module, and the other end of which is grounded; a second resistor, one end of which is connected to the level output control terminal of the protocol management module and one end of the first resistor respectively, and the other end of the second resistor is connected to the controlled end of the voltage divider circuit selection module; A capacitor, one end of which is respectively connected to the other end of the second resistor and the controlled end of the voltage divider circuit selection module, and the other end of which is grounded.

8. The circuit according to claim 1, wherein: The power management module includes: Input stabilization unit, the first end is used to connect to the system power supply; A power management chip, wherein the enable terminal is connected to the enable control terminal of the protocol management module, and the voltage input terminal is used to connect to the second terminal of the input stabilization unit; An output stabilization unit, the first end of which is connected to the voltage output end of the power management chip, the second end of which is respectively connected to the feedback input end of the power management chip and the voltage divider input end of the voltage divider circuit selection module, and is also used to output a stable voltage for the external device.

9. The circuit according to claim 8, characterized in that The output stabilization unit includes: a high-frequency filtering unit, a first end of which is connected to the voltage output end of the power management chip, and a second end of which is grounded; The multi-frequency filtering unit has a first end connected to the voltage output end of the power management chip and the first end of the high-frequency filtering unit respectively, and a second end of the multi-frequency filtering unit is used to connect to the external device.

10. A power management device, characterized in that: The method comprises the power management circuit according to any one of claims 1 to 9.

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