Power management chip high-low side driving signal time sequence optimization method and system

Abstract

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip high-side and low-side drive signal timing optimization, and in particular to a method and system for optimizing the timing of high-side and low-side drive signals of a power management chip. Background Art

[0002] Under conditions of sudden high-current load changes, the high- and low-side drive signals of power management chips are prone to dead-zone timing misalignment due to factors such as hot carrier effects and parasitic parameter coupling, leading to the risk of bridge arm shoot-through or increased switching losses. Especially in scenarios such as new energy vehicles and high-power converters, rapid load current jumps can exacerbate phase shifts in the drive signals. Traditional open-loop control makes it difficult to dynamically compensate for timing deviations. Therefore, a closed-loop optimization method that can monitor dead-zone timing and adaptively adjust the slope of the drive signal edges is urgently needed.

[0003] A typical solution to this problem currently involves dynamic dead-band adjustment technology based on gate voltage sampling feedback. This technology uses high-speed acquisition of the gate voltage waveforms of the high-side and low-side MOSFETs, combined with a digital controller to detect timing deviations between the rising and falling edges, and dynamically adjusts the dead-band time to prevent shoot-through. This solution utilizes hardware-in-the-loop simulation to optimize control parameters, enabling microsecond-level responses to sudden load changes.

[0004] While the above solution can alleviate timing misalignment, it relies on voltage sampling feedback and cannot directly sense the impact of internal chip junction temperature changes and nonlinear perturbations in hot carrier mobility. Especially under high-temperature, high-current transient conditions, gate voltage edge distortion is strongly correlated with hot carrier concentration. It is difficult to accurately quantify the phase shift caused by thermal-electric coupling effects using electrical signal feedback alone, resulting in compensation lag or overshoot, ultimately limiting improvements in system dynamic performance. Summary of the Invention

[0005] The present application provides a method and system for optimizing the timing of high-side and low-side drive signals of a power management chip, so as to solve the problem of poor timing of high-side and low-side drive signals of the chip in the prior art.

[0006] In a first aspect, the present application provides a method for optimizing the timing of high-side and low-side drive signals of a power management chip, comprising: Collect infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtain the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the chip power device area are extracted; By embedding thermoelectric materials in specific hot spots of the chip packaging layer, the temperature gradient in the temperature change characteristic is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network; Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; Reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters output by the coupling response relationship; By matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the driving signal caused by the hot carrier concentration is compensated during the switching cycle.

[0007] Optionally, the phase deviation of the driving signal caused by the hot carrier concentration is compensated during the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, including: At the beginning of a switching cycle, monitoring the peak timing of a bus voltage waveform generated by the dynamic thermoelectric feedback network in the current cycle, and retrieving dynamic compensation parameters from a corresponding relationship table established by the coupling response relationship according to the peak timing of the bus voltage waveform, the dynamic compensation parameters including a rising edge slope compensation coefficient and a falling edge slope compensation coefficient; Multiplying the rising edge slope compensation coefficient by the positive voltage change rate of the reconstructed accelerated rising segment to obtain the compensated rising edge execution parameter; similarly, multiplying the falling edge slope compensation coefficient by the negative voltage change rate of the reconstructed accelerated falling segment to obtain the compensated falling edge execution parameter; Within the rising edge time window of the current switching cycle, the positive voltage change rate output by the driving circuit is controlled according to the compensated rising edge execution parameters. Similarly, within the falling edge time window, the negative voltage change rate output by the driving circuit is controlled according to the compensated falling edge execution parameters.

[0008] Optionally, reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameter output by the coupling response relationship includes: Obtaining an initial rising edge time point and an initial falling edge time point of the original gate drive signal within a switching cycle, and calculating a required advance time amount for the initial rising edge time point and a required backward time amount for the initial falling edge time point based on a phase offset in the time-varying disturbance parameter; A new rising edge starting point is set at a position shifted forward by a time amount before the initial rising edge time point, and the positive voltage change rate is increased based on the original rising edge slope to form an accelerated rising section. Similarly, a new falling edge starting point is set at a position shifted backward by a time amount after the initial falling edge time point, and the negative voltage change rate is increased based on the original falling edge slope to form an accelerated falling section. The end point of the accelerated rising section is connected to the original rising edge vertex, and the starting point of the accelerated falling section is connected to the original falling edge starting point to complete the reconstructed rising edge slope and falling edge slope waveforms.

[0009] Optionally, based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupled response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-side and low-side MOSFET devices, including: Synchronously collecting the bus voltage waveform and gate drive signal waveform of the thermoelectric feedback network during the switching transient process, and measuring the timing deviation between the peak timing of the bus voltage waveform and the rising / falling edge turning point of the gate drive signal; Establishing a correspondence table between bus voltage change rate and gate drive signal timing deviation, and converting discrete voltage distribution data into drive signal phase offset through the correspondence table; The hot carrier mobility disturbance parameter is calculated according to the cumulative effect of the phase shift amount with the number of switching cycles.

[0010] Optionally, based on the spatial continuity of the three-dimensional temperature field distribution, extracting the temperature variation characteristics of the chip power device area includes: Identifying a spatial coordinate range corresponding to a power device region in the three-dimensional temperature field distribution, and extracting a time-temperature variation curve of all grid points in the power device region during a switching cycle; Calculating the similarity of temperature change curves between adjacent grid points, merging continuous spatial regions where the similarity exceeds a threshold, and selecting the grid point with the largest temperature change amplitude in the merged continuous region as a characteristic monitoring point; The maximum temperature value, the minimum temperature value and the temperature change rate of the characteristic monitoring point in each switching cycle are recorded as temperature change characteristics.

[0011] Optionally, by embedding thermoelectric materials in specific hotspot areas of the chip packaging layer, the temperature gradient in the temperature change characteristic is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network, including: Embedding a bismuth telluride-based thermoelectric material unit array in an area corresponding to the spatial position of the characteristic monitoring point in the chip packaging layer; Connecting the two ends of each thermoelectric material unit to the upper surface of the packaging layer and the junction area of ​​the silicon substrate respectively. When an axial temperature gradient is generated in the power device area, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between its two ends. The discrete voltage signal output ends of all the thermoelectric material units are connected in parallel to form a feedback bus, thereby constituting a thermoelectric feedback network with a spatially discrete voltage distribution.

[0012] Optionally, infrared thermal imaging data of the power management chip under transient switching conditions is collected to simultaneously obtain the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature, including: Aim a high-speed infrared thermal imager at the upper surface of the chip packaging layer and collect infrared thermal image data under transient switching conditions; Based on the thickness and thermal conductivity parameters of each layer of the chip packaging layer, an axial heat conduction equation is established from the surface of the packaging layer to the internal junction temperature area, and the infrared thermal imaging data is input into the axial heat conduction equation as a boundary condition to calculate the axial temperature distribution inside the packaging material and the junction temperature area layer by layer; The axial temperature distribution at each sampling moment is spatially superimposed with the surface two-dimensional infrared thermal image data at the corresponding moment to form a three-dimensional temperature field distribution.

[0013] In a second aspect, the present application provides a system for optimizing the timing of high-side and low-side drive signals of a power management chip, comprising: The acquisition module collects infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtains the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; An extraction module, which extracts temperature variation characteristics of a chip power device region based on the spatial continuity of the three-dimensional temperature field distribution; A building module, which converts the temperature gradient in the temperature change characteristic into a spatially discrete Seebeck voltage distribution by embedding thermoelectric materials in specific hot spots of the chip packaging layer to construct a dynamic thermoelectric feedback network; Establishing a module that establishes a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, so as to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; A reconstruction module, which reconstructs the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters output by the coupling response relationship; The switching module compensates for the phase deviation of the driving signal caused by the hot carrier concentration during the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope.

[0014] In a third aspect, an embodiment of the present application provides a computing device comprising a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement a method for optimizing the timing of high and low side drive signals of a power management chip as described in the first aspect above.

[0015] In a fourth aspect, an embodiment of the present application provides a computer storage medium storing a computer program. When the computer program is executed by a computer, it implements a method for optimizing the timing of high and low side drive signals of a power management chip as described in the first aspect.

[0016] In an embodiment of the present application, infrared thermal imaging data of a power management chip under transient switching conditions is collected, and the three-dimensional temperature field distribution of the surface and internal junction temperature of the chip packaging layer is synchronously obtained; based on the spatial continuity of the three-dimensional temperature field distribution, the temperature change characteristics of the chip power device area are extracted; by embedding thermoelectric materials in specific hot spot areas of the chip packaging layer, the temperature gradient in the temperature change characteristics is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network; based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupled response relationship between the dynamic response of the hot carrier concentration and the phase offset of the drive signal is established to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-side and low-side MOSFET devices; based on the time-varying disturbance parameters output from the coupled response relationship, the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices are reconstructed; by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the drive signal caused by the hot carrier concentration is compensated within the switching cycle.

[0017] This application has the following beneficial effects: Achieve non-contact, high-precision, simultaneous monitoring of the chip surface and internal junction temperatures, providing spatially continuous temperature field data for thermal analysis. Focus on key heat-generating areas, identify temperature gradient variations under transient conditions, and provide input features for thermoelectric feedback. Utilize the thermoelectric effect to directly sense thermal disturbances and build a dynamic feedback network to avoid the delay of traditional electrical signal sampling. Quantify the time-varying impact of hot carrier mobility fluctuations on switching delays, revealing the physical mechanism of thermal-electric coupling. Dynamically adjust the drive signal waveform to offset the phase deviation caused by hot carriers and suppress timing misalignment at the source. Closely correct the drive signal edge within the switching cycle to ensure dead-zone timing accuracy and avoid bridge arm shoot-through or increased losses.

[0018] Furthermore, at the beginning of the switching cycle, the present application retrieves the rising edge / falling edge slope compensation coefficient from the pre-established coupling relationship table through the bus voltage peak timing of the dynamic thermoelectric feedback network; multiplies the coefficient with the reconstructed positive / negative voltage change rate to generate the compensated execution parameter; finally, the output of the drive circuit is controlled according to the corrected slope within the corresponding time window to achieve closed-loop compensation of the phase deviation.

[0019] This application realizes adaptive adjustment of the driving signal slope within the switching cycle through dynamic matching of bus voltage timing and compensation parameters, accurately offsets the phase shift caused by hot carrier concentration fluctuations, and significantly improves the performance and reliability of dead zone timing control.

[0020] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A flowchart of a method for optimizing the timing of high-side and low-side drive signals of a power management chip provided by the present application is shown; Figure 2 A schematic diagram of the structure of a high-side and low-side drive signal timing optimization system for a power management chip provided by the present application is shown; Figure 3 A schematic structural diagram of a computing device provided by the present application is shown. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0024] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to being different types.

[0025] In the field of high- and low-side drive signal timing control for power management chips, existing solutions mainly rely on dynamic dead-zone adjustment technology based on gate voltage sampling feedback, which detects the edge timing of the drive signal at high speed and corrects the dead-zone time in a closed loop. However, this solution has an essential flaw: it only indirectly adjusts the timing through electrical signal feedback and cannot directly sense the dynamic changes in the hot carrier concentration and junction temperature distribution inside the chip. Especially under sudden load changes, the nonlinear fluctuations in hot carrier mobility can cause thermal distortion of the gate voltage waveform. Traditional electrical signal sampling is difficult to quantify this thermal-electrical coupling effect, and the compensation response is delayed due to temperature sensing lag, which ultimately causes over-compensation or under-compensation of the dead-zone timing, seriously restricting the reliability of the switch in high-current scenarios.

[0026] In response to the above problems, the present invention proposes a driving signal timing optimization method based on the fusion of infrared thermal imaging and thermoelectric feedback. Its innovation lies in synchronously acquiring the three-dimensional temperature field distribution of the chip through infrared thermal imaging, combining embedded thermoelectric materials to directly convert the temperature gradient into Seebeck voltage, and constructing a thermo-electric coupled feedback network. Specifically, by establishing a dynamic response model of hot carrier concentration and phase shift, the impact of temperature disturbance on switching delay is accurately quantified, and the rising / falling slope of the gate voltage is dynamically reconstructed for compensation. This method breaks through the limitations of traditional electrical signal feedback and realizes full-link closed-loop control from "temperature field → carrier mobility → driving timing", fundamentally solving the problem of monitoring and compensation of thermally induced phase shift, avoiding the inherent defects of temperature sensing lag, and improving the response accuracy of hot spot areas through the spatial discrete distribution of thermoelectric materials, ultimately ensuring the stability and reliability of dead zone timing under large current mutation conditions.

[0027] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] Figure 1 A flowchart of a method for optimizing the timing of high and low side drive signals of a power management chip is provided for an embodiment of the present application. Figure 1 As shown, the method includes: 101. Collect infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtain the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; Optionally, collecting infrared thermal imaging data of the power management chip under a switching transient condition in step 101 and synchronously acquiring a three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature may specifically include: 1011. Aim a high-speed infrared thermal imager at the upper surface of the chip packaging layer and collect infrared thermal image data under a transient switching condition; 1012. Based on the thickness and thermal conductivity parameters of each layer of the chip packaging layer, establish an axial heat conduction equation from the packaging layer surface to the internal junction temperature region, input the infrared thermal imaging data as boundary conditions into the axial heat conduction equation, and calculate the axial temperature distribution inside the packaging material and the junction temperature region layer by layer; 1013. Spatially superimpose the axial temperature distribution at each sampling moment with the surface two-dimensional infrared thermal image data at the corresponding moment to form a three-dimensional temperature field distribution.

[0029] In the above solution, a high-speed infrared thermal imager is a device that can quickly capture infrared radiation from an object's surface. By detecting the intensity of thermal radiation at different locations on the surface, it generates an image reflecting the surface temperature distribution. This camera is suitable for capturing temperature changes over short periods of time. Switching transients refer to the rapid on-off transitions of switching elements (such as MOSFETs) within a power management chip. During these transitions, the current and voltage within the chip fluctuate dramatically, potentially causing rapid local temperature increases or fluctuations. The packaging layer is the protective structure surrounding the chip, typically composed of multiple layers of materials (such as ceramic, metal, and plastic). It secures the chip, connects circuits, and dissipates heat. The thickness and thermal conductivity of each layer vary, affecting the rate of heat transfer. Thermal conductivity is a measure of a material's ability to conduct heat. A higher value indicates a better heat transfer (e.g., metals have higher thermal conductivity, while plastics have lower thermal conductivity). The axial heat conduction equation is a mathematical model that describes heat transfer through the thickness (axial) direction of the packaging layer. It takes into account factors such as temperature variations over time and space, as well as the thermal conductivity of the material, and is used to calculate the temperature distribution at different locations within the packaging layer. Surface 2D infrared thermal imaging data refers to the temperature distribution image of the chip package layer's upper surface, captured by a high-speed infrared thermal imager. This image presents the temperature values ​​at each point in a 2D plane, reflecting the immediate surface temperature conditions under transient operating conditions. 3D temperature field distribution combines 2D surface temperature data from the package layer with internal axial temperature distribution data to form a 3D spatial temperature distribution model containing temperature information at all locations on the surface and internally, comprehensively demonstrating the chip's temperature distribution under transient operating conditions.

[0030] In the embodiment of the present application, a high-speed infrared thermal imager is first aligned with the upper surface of the chip packaging layer in step 1011. Acquisition is initiated during a transient switching condition, rapidly acquiring infrared thermal image data at multiple time points. For example, at the moment when the chip's switch element switches from off to on, which lasts for, say, 10 microseconds, the thermal imager continuously captures images at a high frame rate, such as 5000 frames per second, recording temperature distribution images of the packaging layer surface at each instant. These images contain temperature information at each point on the surface, providing basic data for subsequent calculations.

[0031] Next, in step 1012, based on the thickness of each layer of the packaging layer, for example, the bottom ceramic layer is 0.1 mm thick, the middle metal layer is 0.2 mm thick, and the top plastic layer is 0.3 mm thick, and the thermal conductivity parameters, for example, the thermal conductivity of the ceramic layer is 10 W / (m·K), the metal layer is 50 W / (m·K), and the plastic layer is 0.5 W / (m·K), an equation describing the heat transfer in the axial direction is established in the form of: ,in is the thermal diffusivity, from It is concluded that is the density, is the specific heat capacity, is the temperature, For time, is the axial distance along the normal line of the package layer surface into the chip. Using the infrared thermal imaging data collected in 1011 as the boundary condition, i.e., the initial temperature value of each surface point, after being substituted into the equation, numerical calculation methods, such as the finite difference method, are used to calculate the temperature distribution of each layer inside the package material at different times. For example, starting from the top plastic layer, the temperature change of the next metal layer is calculated based on its thermal conductivity and surface temperature, and then the temperature of the bottom ceramic layer is calculated in sequence until the junction temperature area inside the chip is reached, i.e., the core heat-generating part of the chip.

[0032] Finally, step 1013 spatially overlays the axial temperature distribution within the package layer (including the temperature values ​​of each material layer at different depths) calculated in step 1012 at each sampling time (e.g., time t1, t2, and t3) with the surface two-dimensional infrared thermal image data (temperature values ​​at each surface point) collected in step 1011 at the corresponding time. For example, the surface thermal image data at time t1 shows a surface temperature of 80°C, while the axial calculation results show that the metal layer temperature 0.1mm below this point is 90°C, the ceramic layer temperature 0.3mm below this point is 70°C, and the junction temperature region temperature 0.5mm below this point is 100°C. These temperature values ​​at different depths are integrated with the surface temperature value in the same three-dimensional coordinate system to form a three-dimensional temperature field distribution model that includes temperature information at each surface and internal location, intuitively displaying the temperature changes from the surface to the internal junction temperature region of the chip under transient operating conditions.

[0033] For example, in the actual test, a power management chip with a multi-layer packaging structure (denoted as chip X) was selected. Its packaging layer consists of a ceramic substrate (thickness 0.15mm, thermal conductivity 12W / (m·K)), a copper metal layer (thickness 0.2mm, thermal conductivity 380W / (m·K)), and an epoxy resin layer (thickness 0.3mm, thermal conductivity 0.3W / (m·K)). A high-speed infrared thermal imager model H (frame rate 5000 frames / second) was used. Specifically, during the transient process from off to on of the switching element of chip X (lasting about ), aiming at the upper surface of the packaging layer and continuously shooting, collecting Then, based on the thickness and thermal conductivity parameters of each layer of material, an axial heat conduction equation was established. The surface thermal image data at t=0μs (initial temperature at each point) was substituted into the equation as the boundary condition and calculated using the finite difference method. The results were the temperature distribution inside the ceramic substrate at t=2μs (e.g., 75°C at 0.05mm from the surface and 60°C at 0.15mm), the temperature distribution of the copper metal layer at t=5μs (e.g., 85°C at 0.2mm from the surface), the temperature distribution of the epoxy resin layer at t=8μs (e.g., 90°C at 0.25mm from the surface), and the temperature of the junction temperature area (e.g., 110°C at 0.5mm from the surface). Finally, these axial temperature distributions at different times are superimposed with the corresponding surface thermal image data to form a three-dimensional temperature field distribution from the surface to the junction temperature area. For example, at t = 5 μs, the temperature of a certain point on the surface is 95°C, the temperature of the copper layer 0.1mm below it is 100°C, the temperature of the epoxy resin layer at 0.3mm is 80°C, and the temperature of the junction temperature area at 0.5mm is 110°C, thus fully demonstrating the temperature distribution of the chip under this transient operating condition.

[0034] This step collects and calculates the surface and internal temperature data of the chip package layer under transient switching conditions. This allows accurate acquisition of the three-dimensional temperature distribution of the chip from the surface to the junction temperature area during this process. This provides specific temperature data support for subsequent analysis of the impact of high- and low-side drive signal timing on temperature, helps identify temperature anomaly areas and critical time nodes, and thus provides a basis for optimizing drive signal timing to reduce the risk of local overheating.

[0035] 102. Extracting temperature variation characteristics of the chip power device region based on the spatial continuity of the three-dimensional temperature field distribution; Optionally, in step 102 , extracting the temperature variation characteristics of the chip power device region based on the spatial continuity of the three-dimensional temperature field distribution may specifically include: 1021. Identify a spatial coordinate range corresponding to a power device region in the three-dimensional temperature field distribution, and extract a time-temperature variation curve of all grid points in the power device region during a switching cycle; 1022. Calculate the similarity of temperature change curves between adjacent grid points, merge continuous spatial regions where the similarity exceeds a threshold, and select the grid point with the largest temperature change amplitude in the merged continuous region as a characteristic monitoring point; 1023. Record the highest temperature value, the lowest temperature value, and the temperature change rate of the characteristic monitoring point in each switching cycle as a temperature change characteristic.

[0036] In the above scheme, temperature variation characteristics are key indicators used to describe dramatic temperature changes at characteristic monitoring points, primarily including heat flux and temperature gradient. A three-dimensional temperature field distribution records the specific temperature value at each sampling moment for every tiny location within the chip's entire three-dimensional space, from the package surface to the core junction. This is like creating a three-dimensional temperature map of the chip's interior over time. Spatial continuity refers to the fact that temperature variation behaviors (such as the trend and speed of temperature rise / fall) at adjacent locations in physical space are generally similar. This is similar to how the temperature variations in adjacent rooms are often more similar than those in far-flung rooms. The power device region refers to the area within the chip where the core electronic components actually perform switching operations (turning current on or off). These areas generate concentrated heat during switching and are the focus of thermal analysis. Grid points refer to the division of the chip space into countless fine three-dimensional grids (similar to tiny cubes) for ease of computation and storage in the three-dimensional temperature field. Each grid vertex (or center point) represents a temperature data point. A time-temperature curve is a graph showing the temperature change over time at a specific grid point over a period of time (e.g., a complete switching cycle). Similarity is a numerical metric used to compare the degree of similarity between the shapes of two time-temperature curves. The closer the shapes (e.g., when the temperatures are increasing or decreasing simultaneously), the higher the similarity. Feature monitoring points are a small number of key locations within the power device region that best represent the region's overall temperature fluctuations (i.e., the largest fluctuations or the fastest changes).

[0037] In an embodiment of the present application, first, step 1021 locates the "block" occupied by the power device in the three-dimensional space based on the three-dimensional temperature field data generated in step 101, and obtains a three-dimensional coordinate set of all grid points in this block. Then, for each grid point in the power device block, the temperature value recorded at each sampling moment during a complete one or more power switch switching processes (such as a cycle of a MOS tube from off to on and then off) is extracted. These temperature values ​​are connected in chronological order to obtain a "time-temperature variation curve" for each grid point. This is equivalent to drawing a chart for each tiny location in the power device area, recording how its own temperature fluctuates over time. For example, in a power device area containing 1,000 grid points, this step generates 1,000 independent temperature variation curves.

[0038] Next, step 1022 is used to traverse the grid points in the power device area. , for each grid point, its time-temperature curve Several neighboring points (e.g. 6 face neighbors) time-temperature curve Calculate the similarity one by one. A commonly used calculation method is the Pearson correlation coefficient , the formula is as follows:

[0039] in, Neighboring grid points and At the moment temperature, Neighboring grid points and The average temperature during the entire switching cycle, is the total number of sampling moments contained in the switching cycle. The value ranges from -1 to 1: values ​​greater than 0.9 are generally considered to be highly positively correlated (change trends are highly synchronized), and values ​​greater than 0.7 are considered to be significantly correlated. Set a high threshold, for example, threshold = 0.85. If the values ​​calculated for two adjacent points are If this threshold is exceeded, it is considered that the temperature changes of the two points are almost "synchronized" and should belong to the same thermal reaction area. Merge continuous spatial regions with high similarity: use the region growing algorithm in image processing. Starting from a seed point, continuously include points adjacent to the current point and with a similarity exceeding the threshold into the same area block. Finally, the entire power device area is divided into several (possibly one or more) continuous sub-regions with highly consistent internal temperature changes. Then, in each merged continuous sub-region, traverse all the grid points in the region, calculate the temperature change amplitude recorded on the temperature change curve of each point, that is, the difference between the highest temperature and the lowest temperature, and select the grid point with the largest amplitude value as the monitoring point representing the drastic temperature change characteristics of the entire continuous sub-region.

[0040] Finally, in step 1023, for each characteristic monitoring point selected in step 1022 (one for each sub-region), analyze its temperature change curve in each complete switching cycle, such as from the low-side switch being turned off to being turned on and then turned off, find the highest temperature value of the curve in this cycle and record it, find the lowest temperature value of the curve in this cycle and record it, find the part of the curve where the temperature rises or falls the fastest, that is, usually when it is just turned on or just turned off. According to the temperature difference between the two points in this time period, The time difference with the corresponding The temperature change rate is calculated from the ratio of , and then record the highest temperature value, lowest temperature value and temperature change rate of each characteristic detection point as temperature change characteristics.

[0041] For example, analyzing the thermal behavior of a power chip used for motor control during switching transients: Specifically, the transient three-dimensional temperature field of a chip (designated as Chip B) during power switching was first constructed. Using Chip B's layout information, the region containing two power MOSFETs (MOSFET 1 and MOSFET 2) was located as the target power device region. Temperature data for 1500 grid points within this region over 10 consecutive switching cycles was then extracted, generating 1500 temperature curves. By calculating the Pearson correlation coefficient between the curves of adjacent grid points, it was found that the correlation coefficients within the region containing MOSFET 1 were generally above 0.9 (very similar). The similarity within the region containing MOSFET 2 was also high (above the threshold of 0.85). However, the similarity between the points on MOSFETs 1 and 2 was below 0.7 (unsynchronized). Therefore, the entire power device region was divided into two contiguous subregions (Subregion A represents MOSFET 1, and Subregion B represents MOSFET 2). Within sub-area A, we found grid point M (where the temperature fluctuated dramatically from 45°C to 125°C during the switching process, with a temperature difference of 80°C), and within sub-area B, we found grid point N (where the temperature fluctuated dramatically from 42°C to 118°C, with a temperature difference of 76°C). These were each used as characteristic monitoring points. Next, we recorded the temperature characteristics of point M for the third switching cycle: The maximum heating rate occurs within 1 microsecond after the switch is turned on. (For example, the temperature rises from 50°C to 106°C within 0.8μs), and the maximum cooling rate is recorded at the same time. . Make the same record for point N. These indicators represent the drastic temperature changes in the core areas of the two power MOS tubes. The core effect of this step is to make full use of the natural law of temperature changes inside the chip (similar changes at adjacent points), intelligently locate the core high-temperature area of ​​the most critical heat-generating device from the massive three-dimensional transient temperature data, and screen out a small number of representative monitoring points in the area that can most intuitively reflect the drastic temperature fluctuations, and then extract the key indicators (highest temperature, lowest temperature and temperature change rate) that quantitatively describe this drastic fluctuation. This greatly simplifies the complexity of subsequent analysis, allowing analysts to quickly and centrally grasp the most severe hot spots and thermal shock states of chip power devices during switching transients.

[0042] 103. By embedding thermoelectric materials in specific hot spots of the chip packaging layer, the temperature gradient in the temperature change characteristic is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network; Optionally, in step 103, converting the temperature gradient in the temperature variation characteristic into a spatially discrete Seebeck voltage distribution by embedding thermoelectric materials in specific hotspot areas of the chip packaging layer to construct a dynamic thermoelectric feedback network may specifically include: 1031. Embed a bismuth telluride-based thermoelectric material unit array in an area corresponding to the spatial position of the characteristic monitoring point in the chip packaging layer; 1032. Connecting the two ends of each thermoelectric material unit to the upper surface of the packaging layer and the junction region of the silicon substrate, respectively. When an axial temperature gradient is generated in the power device region, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between the two ends thereof. 1033. Connect the discrete voltage signal output terminals of all the thermoelectric material units in parallel to form a feedback bus, thereby constituting a thermoelectric feedback network with a spatially discrete voltage distribution.

[0043] In the above scheme, thermoelectric materials refer to special materials that can directly convert heat into electricity. When a temperature difference exists across the two ends of this material, a voltage is generated across them, similar to a micro-thermoelectric generator. Specific hotspots refer to the key areas identified in step 102, namely, the locations of the power devices within the chip and the vicinity of the selected characteristic monitoring points. These areas experience the most dramatic temperature fluctuations during the switching process. The temperature gradient (axial) refers to the temperature difference measured in step 101, measured vertically from the chip package surface downward toward the chip's core operating area. The lower end, closer to the chip core, has a higher temperature, while the upper end, closer to the package surface, has a relatively lower temperature, resulting in a temperature variation. The Seebeck effect is the basic operating principle of thermoelectric materials: when a temperature difference exists across the material, a voltage (called the Seebeck voltage) is generated within the material. The greater the temperature difference, the greater the generated voltage. A spatially discrete Seebeck voltage distribution refers to the process of independently placing thermoelectric material units at multiple locations within the key hotspots of the chip package layer. Each unit generates a voltage signal based on the temperature difference across its two ends. These voltage signals originate from different spatial locations (discrete points), and their collection constitutes the "spatial distribution" of voltage. A dynamic thermoelectric feedback network aggregates the voltage signals generated by these multiple thermoelectric material units in parallel to form a single data signal line (feedback bus). The total voltage signal on this bus changes (dynamically) with temperature fluctuations in hotspots caused by chip switching. This signal serves as a feedback input for the chip control system.

[0044] In the embodiment of the present application, a plurality of tiny independent thermoelectric material units are precisely embedded in the area corresponding to the position of the characteristic monitoring point determined in step 102, that is, above the core area of ​​the chip where the thermal changes are most intense. These units are arranged in a regular array, such as a tiny dot matrix or a grid. The shape of each unit can be designed to be micro-column or sheet, and its height direction is exactly consistent with the axial direction (thickness direction) of the chip packaging layer. For example, if step 102 determines that the characteristic monitoring point M is located at coordinates , then when encapsulating, it will be located in the encapsulation layer A thermoelectric unit is vertically embedded above the plane coordinate point If there are three characteristic monitoring points, three thermoelectric units are embedded above the corresponding three points. .

[0045] Secondly, step 1032 ensures that both ends of each embedded thermoelectric material unit in the thickness direction (axial direction) are exposed at specific positions, with the upper end connected to (or close to) the top surface of the packaging layer, that is, the chip housing or heat sink position, and the lower end connected to (or close to) the silicon substrate below the characteristic monitoring point, that is, the core area where the chip actually works.

[0046] For example, Company C develops a high-performance power converter chip (chip D). With this arrangement, when the power devices in the chip are operating, the high temperature generated in the junction area below it will form a vertical temperature difference with the upper surface of the package (usually at a lower temperature). According to the Seebeck effect, each thermoelectric material unit will be based on the actual temperature difference between its two ends. Independently generate a small voltage signal , the voltage signal is proportional to the temperature difference, and its direction depends on the direction of the temperature difference (negative at the high temperature end and positive at the low temperature end). Its mathematical expression is: .in is the Seebeck voltage generated by the thermoelectric material unit, is the Seebeck coefficient of the thermoelectric material unit, which is a material property parameter. is the temperature difference between the lower and upper ends of the thermoelectric material unit.

[0047] Finally, in step 1033, the output electrodes (the pair of electrodes that generate voltage) of all thermoelectric material units (e.g., U1, U2, and U3) embedded at multiple hotspot locations (e.g., corresponding to characteristic monitoring points) are connected to a common conductor (i.e., connected in parallel). The total voltage on this common conductor (the feedback bus) then represents the sum of the output voltages of all parallel thermoelectric units, or, in the case of a linear system, the average effect of the individual unit voltages. This total voltage varies with the temperature gradient at different hotspot locations within the chip and the overall thermal state of the chip. This dynamically changing voltage signal can be output as the thermoelectric feedback signal for the control system. For example, if the 15mV generated by U1, the 10mV generated by U2, and the 12mV generated by U3 are connected in parallel to the same feedback bus, assuming no load, the bus voltage is approximately the combined value of their combined effects (parallel connections are typically signal convergence points).

[0048] Specifically, it was first determined that there are two key characteristic monitoring points P1 and P2 in the core power area of ​​chip D. During the packaging process of chip D, a bismuth telluride thermoelectric unit H1 is precisely buried in the packaging layer directly above position P1, and a thermoelectric unit H2 is buried directly above position P2. H1 and H2 are both tiny columnar structures, the top of which is connected to the bottom surface of the aluminum cover of the packaging shell (as a cold end reference point), and the bottom is connected to the silicon chip junction area (hot end heat source). When the power transistor inside chip D switches at high speed, an axial temperature difference of about 100 degrees is generated at P1, and an axial temperature difference of 80 degrees is generated at P2. The Seebeck coefficient of the Bi2Te3 thermoelectric material used is approximately Therefore, the voltage generated by the H1 unit is ; The voltage generated by the H2 unit The two voltage output lines are connected in parallel to the same feedback bus F. The voltage signal on bus F is It comprehensively reflects the dynamic temperature changes of the two core hot spots of chip D and is led to the control circuit part of the chip as a thermal state feedback signal.

[0049] The core effect of this step is to achieve in-situ, passive (no external power required), and direct electrical sensing of temperature gradients at key points within the chip. By embedding thermoelectric material units directly beneath specific hotspots within the packaging layer and cleverly utilizing the vertical temperature difference (temperature gradient) generated by the chip's operation, the temperature difference is automatically converted into a discrete electrical signal using the Seebeck effect. These electrical signals from the core hotspots are connected in parallel and combined to form a global feedback voltage signal that dynamically reflects the overall temperature rise of the hotspots within the chip. This provides a direct and reliable physical basis for feedback pathways for subsequent precise thermal monitoring and closed-loop management (such as adaptive adjustment of switching frequency) within the chip without the need for complex external sensors.

[0050] 104. Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, establish a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal to quantify the time-varying disturbance of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; Optionally, in step 104, establishing a coupled response relationship between the dynamic response of the hot carrier concentration and the phase shift of the driving signal based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network to quantify the time-varying disturbance of the nonlinear fluctuation of the hot carrier mobility on the switching delay of the high-side and low-side MOSFET devices may specifically include: 1041. Synchronously collect the bus voltage waveform and gate drive signal waveform of the thermoelectric feedback network during the switching transient process, and measure the timing deviation between the peak timing of the bus voltage waveform and the rising / falling edge turning point of the gate drive signal; 1042. Establish a correspondence table between bus voltage change rate and gate drive signal timing deviation, and convert discrete voltage distribution data into drive signal phase offset using the correspondence table. 1043. Calculate a hot carrier mobility disturbance parameter according to the cumulative effect of the phase offset and the number of switching cycles.

[0051] In the above solution, the dynamic thermoelectric feedback network refers to an array of thermoelectric units embedded in hotspots in the chip package layer, which converts the axial temperature gradient it senses into discrete voltage signals and then connects them in parallel to form a total feedback voltage. The Seebeck voltage distribution data refers to the changing total voltage signal, which comprehensively reflects the dynamic temperature rise in the chip's core area. Hot carriers are high-energy electrons (charge carriers) generated by thermal excitation within the chip. Higher temperatures increase the concentration of high-energy electrons and their mobility becomes more active. The dynamic response of the hot carrier concentration refers to how quickly the number of high-energy electrons changes with transient fluctuations in chip temperature. Drive signal phase offset refers to the time delay between the rising and falling edges of the electrical signal (such as the gate voltage) that actually controls the switching of the MOSFET. Ideally, the signal transition should be punctual, but thermal effects can interfere with this timing. Hot carrier mobility describes the ease with which electrons can move in semiconductor materials. As temperature rises, lattice vibrations intensify, hindering electron movement and leading to a decrease in mobility. Nonlinear fluctuations refer to the fact that the magnitude of mobility changes with temperature, not in a fixed linear relationship, but rather in a complex, irregular manner. Time-varying disturbances in switching delay refer to unstable changes in mobility caused by temperature fluctuations, which result in unpredictable and immediate changes in the time (switching delay) required for MOSFETs (such as high-side and low-side transistors) to actually turn on or off after receiving a drive command.

[0052] In the embodiment of the present application, first, through step 1041, a high-speed data acquisition device is used to simultaneously record two key waveforms: one is the voltage on the thermoelectric feedback bus, and the other is the gate drive signal that controls the power MOSFET switch, such as the signal that controls the high-side or low-side MOS tube. When the MOSFET switching action occurs, for example, the rising edge of the gate voltage represents the turn-on instruction, due to the thermal effect, the actual turn-on or turn-off action will lag. Analysts focus on Voltage The peak point represents the position on the time axis when the thermal fluctuation is most intense. , and the position of the gate drive signal edge turning point , for example, the midpoint of the rising edge. Calculate the time difference between the two: ,This time difference is the phase offset of the driving signal caused by heat, that is, the timing deviation.

[0053] Secondly, through step 1042, the severity of the change in the thermoelectric voltage, that is, the instantaneous rate of change of the voltage when the thermal shock occurs, is observed. Under different working conditions (producing different degrees of temperature rise fluctuations), multiple sets of data are collected: the instantaneous rate of change of the thermoelectric voltage near the peak moment of the thermal fluctuation and the time difference corresponding to the switch are recorded, and these data are sorted into a one-to-one elicitation table.

[0054] Finally, a hot carrier mobility perturbation parameter is defined according to the phase offset in step 1043. , a commonly used calculation method is based on the most recent continuous The phase shift of the switching action is used to calculate a cumulative effect factor: , or using a weighted average (the more recent the effect): ,in For the The weight coefficient of the secondary switch is ,parameter It is a quantitative indicator used to characterize the overall degree of interference with hot carrier mobility due to the accumulation of multiple thermal shocks.

[0055] For example, Company D develops a high-efficiency server power module: Specifically, the dynamic thermoelectric feedback network established monitors the temperature rise fluctuations at key points inside the chip. When testing the switching process of a bridge power circuit (including high-side and low-side MOSFETs), the falling edge of the gate drive of the low-side MOSFET, that is, the moment of the shutdown instruction, is captured synchronously. ) and the subsequent thermoelectric feedback voltage peak value is calculated as . Also recorded in The slope of the thermoelectric voltage nearby (The negative sign indicates a voltage drop). Through the pre-established correspondence table, The rate of change corresponds to (Close to the actual measured 0.13μs). Continuously test 10 switch operations and get 10 When calculating the mobility perturbation parameter, take the last Unweighted averaging of switches: , then the parameter .this The average time deviation of the switching delay caused by the carrier mobility perturbation of the low-side MOSFET under the recent switching heat accumulation is characterized.

[0056] The core effect of this step is to establish a direct, quantifiable correlation between the chip's internal thermal state fluctuations (indirectly reflected by thermoelectric voltages) and the actual switching time deviation (phase offset) of the power MOSFET. By capturing the relationship between the rate of change of the thermoelectric signal and the time offset of the drive signal, the transient temperature gradient feedback is efficiently converted into an estimate of the switching delay disturbance. Furthermore, considering the thermal accumulation effect of multiple switching cycles, a comprehensive parameter characterizing the degree of sustained perturbation of hot carrier mobility is calculated. This provides a key quantitative indicator for understanding the immediate and cumulative impact of thermal effects on the dynamic characteristics of the switch, and lays a data foundation for subsequent drive signal compensation or thermal management strategy optimization.

[0057] 105. Reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters outputted from the coupling response relationship; Optionally, in step 105, reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameter outputted from the coupling response relationship may specifically include: 1051. Obtain an initial rising edge time point and an initial falling edge time point of the original gate drive signal within a switching cycle, and calculate a required advance time amount for the initial rising edge time point and a required backward time amount for the initial falling edge time point based on a phase offset in the time-varying disturbance parameter; 1052. A new rising edge starting point is set at a position shifted forward by a time amount before the initial rising edge time point, and the positive voltage change rate is increased based on the original rising edge slope to form an accelerated rising segment. Similarly, a new falling edge starting point is set at a position shifted backward by a time amount after the initial falling edge time point, and the negative voltage change rate is increased based on the original falling edge slope to form an accelerated falling segment. 1053. Connect the end point of the accelerated rising segment to the original rising edge vertex, and connect the starting point of the accelerated falling segment to the original falling edge starting point, to complete the reconstructed rising edge slope and falling edge slope waveforms.

[0058] In the above scheme, the time-varying perturbation parameter refers to the hot carrier mobility perturbation parameter, a time quantity that represents the average time delay caused by recent heat accumulation on the switching action. Reconstruction refers to the active modification and adjustment of the original control signal waveform to compensate for the negative impact of thermal effects. The gate voltage is the core signal that controls the MOSFET switching. A high level turns on the device, while a low level turns it off. The rising edge slope refers to the rate of change of the gate voltage when it transitions from a low level to a high level (e.g., V / μs). A larger slope indicates a faster turn-on. The falling edge slope refers to the rate of change of the gate voltage when it transitions from a high level to a low level (e.g., V / μs). A larger slope indicates a faster turn-off. The accelerated rising / falling segments are short, steeper ramp signal segments added to the original signal waveform to accelerate the switching action.

[0059] In an embodiment of the present application, the original, uncompensated gate drive signal waveform is first obtained through step 1051, where the key time points include: the starting point of the initial rising edge, i.e., the moment when the voltage begins to rise; the peak of the initial rising edge, i.e., the moment when the voltage reaches a high level; the starting point of the initial falling edge, i.e., the moment when the voltage begins to fall; and the end point of the initial falling edge, i.e., the moment when the voltage reaches a low level. The time-varying disturbance parameter R obtained in step 104 represents the average delay of the switching action due to thermal effects. Compensation is required for both the turn-on (rising edge) and the turn-off (falling edge), i.e., the required advance time for the initial rising edge time point and the required delay time for the initial falling edge time point are determined based on the difference between the original time and the time-varying disturbance parameter.

[0060] Next, during the power device switching timing compensation process, step 1052 first applies the rising edge action: based on the forward time calculated from the thermal disturbance parameter (e.g., 0.2μs), the original rising edge start time (e.g., t=5.0μs) is adjusted forward to a new coordinate (e.g., t=4.8μs). At this new starting point, the original voltage change rate is no longer used. Instead, a steeper positive slope is designed. Using the original rising slope (e.g., 8V / μs) as a reference, the voltage change intensity is increased by a predetermined ratio (e.g., 1.5 times, or 12V / μs). This creates a shorter but more dramatic accelerated rising segment. This steep slope allows the gate voltage to complete its initial jump in a very short time (e.g., 0.15μs), quickly crossing the critical threshold of the conduction process. Simultaneously, a reverse operation is performed on the falling edge: the original falling edge start point (e.g., t=15.0μs) is shifted back to a new trigger position (e.g., t=15.2μs) based on the delay time (e.g., 0.2μs). On this later time scale, an enhanced negative voltage rate of change is employed—based on the original downward slope (e.g., -10V / μs), the amplitude of change is multiplied (e.g., to -15V / μs) to create a cliff-like acceleration phase. This design allows the gate voltage to exit the conduction range at a near-free-fall speed after the shutdown action is initiated, significantly shortening the shutdown delay window.

[0061] Finally, the key to completing signal reconstruction in step 1053 lies in achieving a seamless transition between the acceleration phase and the original waveform. For the rising edge, once the accelerated rising phase reaches a preset voltage value (e.g., 2.8V) at its enhanced slope (e.g., 12V / μs), the voltage at that moment (in space-time coordinates, e.g., t = 4.95μs, V = 2.8V) is precisely aligned to the target peak of the original rising edge (e.g., the designed value of 21V). The original slope (8V / μs) is then maintained to complete the remaining voltage ramp. This essentially continues the unfinished voltage increment task of the acceleration phase at the original rate, preserving the time gain of the acceleration phase while maintaining the smooth voltage transition required by the design. For the falling edge, mirror logic is employed: the original falling edge first runs at its standard slope (-10V / μs) until the delayed start time (e.g., t = 15.2μs). The instant the voltage drops to the transition point (e.g., 19V), the preset accelerated falling phase (-15V / μs) is immediately engaged to perform the final shutdown sprint. This "original first, then accelerated" relay strategy ensures charge unloading at a regular rate during the first half of the shutdown process, switching to an enhanced slope at a critical moment to achieve brute force clamping in the final stage. Through a dual anchoring mechanism—the rising edge uses the target voltage as the endpoint anchor, and the falling edge uses the starting voltage as the starting anchor—the reconstructed waveform accurately compensates for thermal delay gaps in the time domain while achieving continuous conduction of the turn-on and turn-off traces in the voltage domain. The resulting waveform appears on an oscilloscope as a staircase-like edge with compensated steps, and its macroscopic slope exhibits a piecewise linear transition characteristic.

[0062] For example, in the actual measurement of chip E (used in a power tool motor drive system): Specifically, based on the thermal mobility perturbation parameter R=0.2μs, technicians reconstructed the original drive signal of the high-side MOSFET: first, the starting point of the rising edge was moved forward by 0.2μs from the original t=5.0μs to t=4.8μs, and an acceleration segment lasting 0.15μs was generated with a slope of +12V / μs (1.5 times the original slope of 8V / μs), so that the voltage increased from 1V to 2.8V; then, at t=4.95μs, it seamlessly switched back to the original slope of 8V / μs, and it took 2.275μs to complete the remaining 18.2V rise to the target 21V, and the overall turn-on completion time was optimized to t≈7.225μs (earlier than the original 7.5μs). For the falling edge, the original starting point, t = 15.0 μs, is maintained, with a slope of -10 V / μs decreasing to t = 15.2 μs (at which point the voltage is 19 V). Then, an acceleration phase with a slope of -15 V / μs is initiated, reducing the voltage from 19 V to 1 V in just 1.2 μs, bringing the shutdown process to t = 16.4 μs (0.6 μs shorter than the original 17.0 μs). By precisely splicing the steep acceleration phase with the original phase, this reconstruction strategy effectively offsets the delay caused by thermal effects on the switching timing.

[0063] The core effect of this step is to actively combat the negative impact of switching delays caused by thermal effects. Using the thermal disturbance time parameters quantified in step 104, short but steep voltage ramp segments are intelligently inserted before and after the key time nodes of the original drive signal. This signal reconstruction strategy significantly improves the initial response speed of the turn-on and turn-off actions, effectively "recovering" the delay in switching actions caused by the reduction in hot carrier mobility in the time dimension, ultimately ensuring that the high-side and low-side MOSFET devices can complete the switching action at a more accurate time, improving the power conversion efficiency and reducing the risk of switching losses.

[0064] 106. Compensate for a phase deviation of a driving signal caused by hot carrier concentration during a switching cycle by matching dynamic compensation parameters of the rising edge slope and the falling edge slope.

[0065] Optionally, in step 106, compensating for the phase deviation of the driving signal caused by the hot carrier concentration during the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope may specifically include: 1061. At the beginning of a switching cycle, monitor the peak timing of the bus voltage waveform generated by the dynamic thermoelectric feedback network in the current cycle, and retrieve dynamic compensation parameters from the corresponding relationship table established by the coupling response relationship according to the peak timing of the bus voltage waveform, the dynamic compensation parameters including a rising edge slope compensation coefficient and a falling edge slope compensation coefficient; 1062. Multiply the rising edge slope compensation coefficient by the positive voltage change rate of the reconstructed acceleration rising segment to obtain a compensated rising edge execution parameter. Similarly, multiply the falling edge slope compensation coefficient by the negative voltage change rate of the reconstructed acceleration falling segment to obtain a compensated falling edge execution parameter. 1063. Within the rising edge time window of the current switching cycle, the positive voltage change rate output by the driving circuit is controlled according to the compensated rising edge execution parameters. Similarly, within the falling edge time window, the negative voltage change rate output by the driving circuit is controlled according to the compensated falling edge execution parameters.

[0066] In the above scheme, the dynamic compensation parameter refers to a coefficient dynamically adjusted based on the thermoelectric feedback signal, used to fine-tune the voltage change rate of the reconstructed waveform. The bus voltage waveform refers to the integrated voltage signal output by the parallel thermoelectric units, whose peak occurrence time reflects the moment of the most severe temperature rise within the chip. The rising edge slope compensation coefficient is a proportional factor that adjusts the slope of the accelerated rising phase based on the thermal state. The falling edge slope compensation coefficient is a similar factor used to adjust the slope of the accelerated falling phase. The compensated execution parameter is the actual voltage change rate command value ultimately output to the drive circuit. The switching cycle is the complete time window within which a power device completes a single turn-on and turn-off operation.

[0067] In an embodiment of the present application, first, at the moment the power switch cycle starts, the control system immediately starts tracking the thermoelectric feedback bus voltage through step 1061. That is, the bus signal is generated by the thermoelectric unit array in the hot spot area of ​​the packaging layer, and the time when its voltage peak appears accurately reflects the most severe temperature rise time node inside the chip. The bus waveform data is continuously captured by a high-speed sampling circuit, and a sliding window extreme value detection algorithm (such as local derivative zero crossing determination) is used to lock the absolute peak coordinates within the current cycle (such as detecting a voltage spike at t=5.25μs). This moment is aligned and compared with the theoretical edge standard timing of the drive signal (such as the design value t=5.0μs) at the microsecond level to calculate the thermal delay deviation (in this case, +0.25μs). The system then activates a pre-stored three-dimensional mapping table (created in step 104, containing the correspondence between delay deviation and compensation coefficients) in memory. The system automatically indexes the associated data cells based on the 0.25μs offset value and extracts the dynamic compensation parameter set specific to that operating condition: a rising-edge slope compensation coefficient (e.g., a 1.5x enhancement factor) to improve turn-on speed and a falling-edge slope compensation coefficient (e.g., a 1.4x enhancement factor) to optimize turn-off response. The entire closed-loop decision-making process, from thermal signature monitoring to compensation parameter retrieval, occurs within microseconds, ensuring that each switching cycle accurately matches the current hot carrier perturbation compensation strategy.

[0068] Secondly, step 1062 is performed according to the acceleration rising section basic slope in step 105. And the basic slope of the accelerated descent And the dynamic compensation coefficient group of the current switching cycle, which includes the rising edge slope compensation coefficient (dimensionless proportional factor, >1 indicates enhancement) and falling edge slope compensation coefficient , performs the key operation by multiplication: the slope of the rising edge after compensation , after compensation, the falling edge execution slope .

[0069] Finally, in step 1063, within the precisely defined switching action time window, the driver control system converts the dynamically calculated slope execution parameters into physical outputs. When the switching cycle enters the preset rising edge period (e.g., the accelerated rising window starting from the new starting point t=4.8µs), the driver chip immediately applies the compensated rising edge execution parameters (e.g., +19.5V / µs). The internal current source module forcibly increases the gate voltage ramp rate, charging the MOSFET gate capacitance at a faster-than-normal rate, thereby offsetting the negative effects of hot carrier migration lag. Simultaneously, during the falling edge period (e.g., the delayed turn-off window t=15.2µs to 16.4µs), the control system switches to the compensated negative execution parameters (e.g., -21.6V / µs). The driver chip output stage switches to a high-current sinking mode, rapidly extracting gate charge with a nearly vertical voltage drop slope, significantly compressing the turn-off delay time. This dynamic slope loading mechanism with strict timing locking ensures that the thermal disturbance compensation amount in each switching cycle can be mapped to the actual output intensity of the driving circuit, ultimately presenting a switching trajectory at the power device end that accurately counteracts hot carrier concentration fluctuations.

[0070] For example, a power tool power module (chip F) detects that the peak voltage of the thermoelectric bus occurs during the fifth switching cycle. (Ideal value is 5.0µs, delay is 0.25µs).

[0071] Specifically, query the preset mapping table, and the delay of 0.25µs corresponds to The original slope of the accelerated rising section of the reconstructed waveform of this cycle is +12V / µs, and the original slope of the accelerated falling section is -15V / µs. The calculated execution parameters are: , . The driver chip is (Starting point of new rising edge) outputs at a rate of +18V / µs for 0.2µs, causing the voltage to rise from 1V to 4.6V; The voltage drops from 19V to 1V within 0.8µs at a rate of -21V / µs (starting point of the new falling edge), compressing the switching action into the thermal shock time window.

[0072] This step dynamically enhances the voltage variation of the drive waveform by matching the thermoelectric feedback signal with pre-set mapping rules. When increased thermal delay is detected, the compensation coefficient group is automatically increased, forcing carrier migration to accelerate with a steeper voltage slope. This closed-loop strategy integrates thermal disturbance identification (step 104), waveform reconstruction (step 105), and real-time compensation (step 106) into an adaptive system, ensuring that switching operations always closely adhere to target timing and significantly reducing the parasitic interference of thermal effects on the dynamic performance of power devices.

[0073] The following is a complete example of steps 101 to 106: An industrial servo drive (system B) uses a dual-parallel half-bridge topology. Its core power management chip (PMIC-POWER) experiences a 160ns turn-on delay in the second-phase high-side MOSFET under 10kHz high-frequency switching conditions. Infrared scanning also reveals that the package surface temperature in this area reaches 142°C (versus an average of 102°C in other areas), resulting in a 3.1% reduction in system energy efficiency. To optimize this timing disturbance, the following full-process compensation was performed: First, an HTX-9000 high-speed infrared thermal imager (80,000 frames / second) was used to focus on the second phase of the PMIC-POWER chip, continuously capturing the surface temperature distribution during the MOSFET turn-on transient (15μs duration). A thermal conduction model was established based on the three-layer packaging structure: a silicone layer (0.18mm thick, 0.4W / mK thermal conductivity), a copper layer (0.12mm, 398W / mK), and a ceramic substrate (0.1mm, 25W / mK). At t = 2 μs, the surface hotspot reached 132°C (coordinates x5.1mm, y4.3mm). Using this boundary condition, the solution revealed that at t = 5 μs, the junction temperature at a point 0.2mm below the ceramic substrate soared to 155°C. Finally, by integrating the axial temperature at this moment with the surface thermal image data, a three-dimensional temperature field was constructed, clearly showing a temperature gradient of 23°C / mm from 132°C on the surface to 155°C in the junction area.

[0074] Secondly, frame the core area of ​​the power device in the temperature field ( ), extract the time-temperature curve of 720 grid points. The three thermal response sub-areas were divided by Pearson correlation coefficient analysis (threshold 0.88), and the point P1 with the most drastic temperature jump in sub-area A was selected: The temperature suddenly increased from 48°C to 152°C (a change of 104°C), and the maximum heating rate of 92°C / μs and transient characteristic values ​​were recorded.

[0075] Then, a Bi2Te3 thermoelectric unit TH1 (Seebeck coefficient -240μV / K) is embedded at the corresponding position of the characteristic point P1 (x5.2mm, y4.2mm). The cold end is connected to the heat dissipation cover (constant temperature 65℃), and the hot end is directly connected to the silicon junction area. When the chip is working, the junction area reaches 155℃ ( ), TH1 output voltage: , parallel other phase thermoelectric unit output to form a bus voltage , monitoring found that its main peak appeared at t = 4.8 μs (0.95 μs behind the midpoint of the ideal gate drive rising edge).

[0076] Then, the bus voltage change rate is established Mapping with timing offset: Time correspondence (calibrated by 15 sets of experiments). Take the most recent 6 switches value , by weight Weighted average calculation: The hot carrier mobility perturbation parameters are obtained.

[0077] Then, the original rising edge starting point Move forward R value to ;exist The interval setting is +28V / μs steep slope (1.56 times the original slope of 18V / μs). The gate voltage is pushed up from 1.8V to 5.8V; then it is switched back to the original slope. When the voltage reaches the target 24V, the total turn-on time is shortened by 22%.

[0078] Finally, when the new switching cycle detects that the V_fb peak lag reaches 1.02μs, the dynamic compensation coefficient 1.62 is obtained by looking up the table, and it is multiplied by the preset acceleration slope 28V / μs to obtain the execution parameter 45.36V / μs. Outputting at this rate instantaneously, the 1.8V→7.3V transition is completed in just 0.12μs (37% faster than the original design), ultimately stabilizing the switching delay within the 35±5ns range.

[0079] Figure 2 The present invention provides a schematic diagram of a power management chip high and low side drive signal timing optimization system. Figure 2 As shown, the system includes: Acquisition module 21 collects infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtains the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; An extraction module 22 extracts temperature variation characteristics of the chip power device region based on the spatial continuity of the three-dimensional temperature field distribution; Building module 23, converting the temperature gradient in the temperature change characteristic into a spatially discrete Seebeck voltage distribution by embedding thermoelectric materials in a specific hot spot area of ​​the chip packaging layer to construct a dynamic thermoelectric feedback network; Establishing module 24, based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, establishing a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal, so as to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of the high-side and low-side MOSFET devices; A reconstruction module 25 reconstructs the rising slope and the falling slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters output by the coupling response relationship; The switching module 26 compensates for the phase deviation of the driving signal caused by the hot carrier concentration during the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope.

[0080] Figure 2 The power management chip high and low side drive signal timing optimization system can perform Figure 1 The implementation principles and technical effects of the method for optimizing the timing of high- and low-side drive signals in a power management chip described in the illustrated embodiment will not be elaborated upon. The specific manner in which the various modules and units perform operations in the timing optimization system for optimizing the timing of high- and low-side drive signals in a power management chip in the aforementioned embodiment have been described in detail in the embodiments of the method and will not be elaborated upon here.

[0081] In one possible design, Figure 2 The power management chip high and low side drive signal timing optimization system of the embodiment shown can be implemented as a computing device, such as Figure 3 As shown, the computing device may include a storage component 31 and a processing component 32; The storage component 31 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 32 .

[0082] The processing component 32 is used for the above Figure 1 The embodiment provides a method for optimizing the timing of high-side and low-side drive signals of a power management chip.

[0083] The processing component 32 may include one or more processors to execute computer instructions to complete all or part of the steps in the above method. Of course, the processing component may also be implemented as one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above method.

[0084] The storage component 31 is configured to store various types of data to support operations at the terminal. The storage component can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0085] Of course, a computing device may also include other components, such as input / output interfaces, display components, communication components, etc.

[0086] The input / output interface provides an interface between the processing component and the peripheral interface module, which can be an output device, an input device, etc.

[0087] The communication component is configured to facilitate, among other things, wired or wireless communications between the computing device and other devices.

[0088] Among them, the computing device can be a physical device or an elastic computing host provided by a cloud computing platform, etc. In this case, the computing device can refer to a cloud server, and the above-mentioned processing components, storage components, etc. can be basic server resources rented or purchased from the cloud computing platform.

[0089] The present application also provides a computer storage medium storing a computer program, wherein the computer program can achieve the above-mentioned Figure 1 The embodiment shown is a method for optimizing the timing of high-side and low-side drive signals of a power management chip.

[0090] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0092] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for optimizing the timing of high-side and low-side drive signals of a power management chip, characterized in that: include: Collect infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtain the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the chip power device area are extracted; By embedding thermoelectric materials in specific hot spots of the chip packaging layer, the temperature gradient in the temperature change characteristic is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network; Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; Reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters output by the coupling response relationship; By matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the driving signal caused by the hot carrier concentration is compensated during the switching cycle.

2. The method according to claim 1, characterized in that By matching the dynamic compensation parameters of the rising edge slope and the falling edge slope, the phase deviation of the driving signal caused by the hot carrier concentration is compensated during the switching cycle, including: At the beginning of a switching cycle, monitoring the peak timing of a bus voltage waveform generated by the dynamic thermoelectric feedback network in the current cycle, and retrieving dynamic compensation parameters from a corresponding relationship table established by the coupling response relationship according to the peak timing of the bus voltage waveform, the dynamic compensation parameters including a rising edge slope compensation coefficient and a falling edge slope compensation coefficient; Multiplying the rising edge slope compensation coefficient by the positive voltage change rate of the reconstructed accelerated rising segment to obtain the compensated rising edge execution parameter; similarly, multiplying the falling edge slope compensation coefficient by the negative voltage change rate of the reconstructed accelerated falling segment to obtain the compensated falling edge execution parameter; Within the rising edge time window of the current switching cycle, the positive voltage change rate output by the driving circuit is controlled according to the compensated rising edge execution parameters. Similarly, within the falling edge time window, the negative voltage change rate output by the driving circuit is controlled according to the compensated falling edge execution parameters.

3. The method according to claim 1, characterized in that Reconstructing the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameter output by the coupling response relationship, including: Obtaining an initial rising edge time point and an initial falling edge time point of the original gate drive signal within a switching cycle, and calculating a required advance time amount for the initial rising edge time point and a required backward time amount for the initial falling edge time point based on a phase offset in the time-varying disturbance parameter; A new rising edge starting point is set at a position shifted forward by a time amount before the initial rising edge time point, and the positive voltage change rate is increased based on the original rising edge slope to form an accelerated rising section. Similarly, a new falling edge starting point is set at a position shifted backward by a time amount after the initial falling edge time point, and the negative voltage change rate is increased based on the original falling edge slope to form an accelerated falling section. The end point of the accelerated rising section is connected to the original rising edge vertex, and the starting point of the accelerated falling section is connected to the original falling edge starting point to complete the reconstructed rising edge slope and falling edge slope waveforms.

4. The method according to claim 1, wherein Based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal is established to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices, including: Synchronously collecting the bus voltage waveform and gate drive signal waveform of the thermoelectric feedback network during the switching transient process, and measuring the timing deviation between the peak timing of the bus voltage waveform and the rising / falling edge turning point of the gate drive signal; Establishing a correspondence table between bus voltage change rate and gate drive signal timing deviation, and converting discrete voltage distribution data into drive signal phase offset through the correspondence table; The hot carrier mobility disturbance parameter is calculated according to the cumulative effect of the phase shift amount with the number of switching cycles.

5. The method according to claim 1, characterized in that Based on the spatial continuity of the three-dimensional temperature field distribution, the temperature variation characteristics of the chip power device area are extracted, including: Identifying a spatial coordinate range corresponding to a power device region in the three-dimensional temperature field distribution, and extracting a time-temperature variation curve of all grid points in the power device region during a switching cycle; Calculating the similarity of temperature change curves between adjacent grid points, merging continuous spatial regions where the similarity exceeds a threshold, and selecting the grid point with the largest temperature change amplitude in the merged continuous region as a characteristic monitoring point; The maximum temperature value, the minimum temperature value and the temperature change rate of the characteristic monitoring point in each switching cycle are recorded as temperature change characteristics.

6. The method according to claim 5, characterized in that By embedding thermoelectric materials in specific hotspot areas of the chip packaging layer, the temperature gradient in the temperature change characteristic is converted into a spatially discrete Seebeck voltage distribution to construct a dynamic thermoelectric feedback network, including: Embedding a bismuth telluride-based thermoelectric material unit array in an area corresponding to the spatial position of the characteristic monitoring point in the chip packaging layer; Connecting the two ends of each thermoelectric material unit to the upper surface of the packaging layer and the junction area of ​​the silicon substrate respectively. When an axial temperature gradient is generated in the power device area, each thermoelectric material unit generates a discrete voltage signal according to the temperature difference between its two ends. The discrete voltage signal output ends of all the thermoelectric material units are connected in parallel to form a feedback bus, thereby constituting a thermoelectric feedback network with a spatially discrete voltage distribution.

7. The method according to claim 1, characterized in that Collect infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtain the three-dimensional temperature field distribution of the chip package surface and internal junction temperature, including: Aim a high-speed infrared thermal imager at the upper surface of the chip packaging layer and collect infrared thermal image data under transient switching conditions; Based on the thickness and thermal conductivity parameters of each layer of the chip packaging layer, an axial heat conduction equation is established from the surface of the packaging layer to the internal junction temperature area, and the infrared thermal imaging data is input into the axial heat conduction equation as a boundary condition to calculate the axial temperature distribution inside the packaging material and the junction temperature area layer by layer; The axial temperature distribution at each sampling moment is spatially superimposed with the surface two-dimensional infrared thermal image data at the corresponding moment to form a three-dimensional temperature field distribution.

8. A power management chip high and low side drive signal timing optimization system, characterized in that: include: The acquisition module collects infrared thermal imaging data of the power management chip under transient switching conditions, and simultaneously obtains the three-dimensional temperature field distribution of the chip packaging layer surface and internal junction temperature; An extraction module, which extracts temperature variation characteristics of a chip power device region based on the spatial continuity of the three-dimensional temperature field distribution; A building module, which converts the temperature gradient in the temperature change characteristic into a spatially discrete Seebeck voltage distribution by embedding thermoelectric materials in specific hot spots of the chip packaging layer to construct a dynamic thermoelectric feedback network; Establishing a module that establishes a coupled response relationship between the dynamic response of hot carrier concentration and the phase shift of the driving signal based on the Seebeck voltage distribution data generated by the dynamic thermoelectric feedback network, so as to quantify the time-varying perturbation of the nonlinear fluctuation of hot carrier mobility on the switching delay of high-side and low-side MOSFET devices; A reconstruction module, which reconstructs the rising edge slope and the falling edge slope of the gate voltage of the high-side and low-side MOSFET devices according to the time-varying disturbance parameters output by the coupling response relationship; The switching module compensates for the phase deviation of the driving signal caused by the hot carrier concentration during the switching cycle by matching the dynamic compensation parameters of the rising edge slope and the falling edge slope.

9. A computing device, characterized in that It includes a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement the power management chip high and low side drive signal timing optimization method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that A computer program is stored, and when the computer program is executed by a computer, the method for optimizing the timing of high-side and low-side drive signals of a power management chip according to any one of claims 1 to 7 is implemented.

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