Passive three-phase alternating current filtering and rectifying circuit

Abstract

The invention provides a passive three-phase alternating current filtering and rectifying circuit, and belongs to the technical field of EMI filters. The circuit comprises a filter circuit, a power correction circuit, a rectification circuit and a slow start circuit. The filter circuit is composed of a two-stage common mode inductor, a one-stage differential mode inductor, a corresponding common mode capacitor and a corresponding differential mode capacitor. The power correction circuit is composed of a differential mode inductor; the rectifying circuit adopts six rectifying diodes to carry out full-wave rectification, and a capacitor is used for filtering after rectification; the slow start circuit is composed of an NMOS tube, a resistor and a capacitor, the resistor and the capacitor form a charging circuit, when the capacitor voltage is larger than the threshold voltage of the NMOS tube, the NMOS tube starts to be conducted, the capacitor voltage is increased along with the increase of the charging time, the conduction resistance of the NMOS tube is reduced, and slow start of the circuit is achieved. According to the invention, functions of filtering, power correction, rectification and slow start are integrated, through the design of the two-stage common-mode inductor and the differential-mode inductor, conducted interference is effectively inhibited, the power factor is improved, and the GJB151B-2013 standard is met. The method has the characteristics of low cost, high reliability and strong environmental adaptability.

Description

Technical Field

[0001] The present invention belongs to the technical field of EMI filters, and specifically relates to a passive three-phase AC filter rectifier circuit, which is suitable for three-phase AC power supply equipment in the fields of aviation, industry, and consumer electronics. It can effectively suppress conducted interference, improve the power factor, and has a soft start function. Background Art

[0002] Three-phase EMI filter circuits suppress conducted interference, block the propagation of common-mode and differential-mode noise along power lines, absorb or reflect noise energy, and suppress switching frequency components and their multiples. Three-phase AC power supply systems are widely used in aviation, industry, and other fields. However, nonlinear loads such as switching power supplies can introduce significant amounts of conducted interference (common-mode and differential-mode noise), leading to electromagnetic compatibility (EMC) issues. Existing EMI filter circuits can be categorized as passive, active, and hybrid, depending on whether they are active or not.

[0003] 1. Active filter circuit: small size, fast dynamic response, but high cost and high control complexity; 2. Hybrid filter circuit: takes into account the requirements of low-frequency and high-frequency suppression (such as passive processing 150KHz~1MHz, active processing above 1MHz), but its cost is high and the control is complex; 3. Passive filter circuit: Although it is large in size, it has obvious cost advantages and can meet the requirements of general application scenarios. However, traditional designs cannot meet the requirements of high power factor and broadband noise suppression at the same time.

[0004] Furthermore, with increasingly stringent power factor and electromagnetic compatibility requirements for power supplies in scenarios such as airborne equipment, a low-cost, highly reliable solution is urgently needed. This invention fills this gap in the existing technology by integrating filtering, power correction, rectification, and soft-start functions. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a passive three-phase AC filter rectifier circuit to solve the problems of low power factor and narrow noise suppression range of traditional passive filter circuits, while avoiding the high cost defect of active solutions.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is: A passive three-phase AC filter and rectifier circuit, comprising a filter circuit, a power correction circuit, a rectifier circuit and a soft start circuit; The filtering circuit is connected to the input interface module and is used to suppress common-mode and differential-mode noise. It is composed of two stages of common-mode inductors, one stage of differential-mode inductors, and corresponding common-mode capacitors and differential-mode capacitors. The power correction circuit is composed of differential mode inductors and is used to improve the power factor of the circuit; The rectifier circuit is connected to the output end of the power correction circuit, uses six rectifier diodes to perform full-wave rectification, and uses capacitors to perform filtering after rectification; The slow-start circuit is connected to the DC output end and is composed of an NMOS tube and a resistor and capacitor. The resistor and capacitor form a charging circuit. When the capacitor voltage is charged to a value greater than the threshold voltage of the NMOS tube, the NMOS tube begins to conduct. As the charging time increases, the capacitor voltage increases and the on-resistance of the NMOS tube gradually decreases, thereby achieving slow-start of the circuit.

[0007] Further limiting the above solution, the filtering circuit includes common-mode inductor L1, common-mode inductor L2, differential-mode inductor 1L3, differential-mode inductor 2L3, differential-mode inductor 3L3, resistor 1R1, resistor 2R1, resistor 3R1, differential-mode capacitors: capacitor 1CX2, capacitor 2CX2, capacitor 3CX2, capacitor 1CX3, capacitor 2CX3, capacitor 3CX3, capacitor 1CX4, capacitor 2CX4, capacitor 3CX4, common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, capacitor 8CY1; The power correction circuit includes a differential mode inductor 1L3, a differential mode inductor 2L3, and a differential mode inductor 3L3; The rectifier circuit includes rectifier diodes 1D1, 2D1, 3D1, 4D1, 5D1, and 6D1. Capacitors 6C4, 7C4, and 10C4 are used for filtering after rectification. Their capacitance values ​​are determined based on the back-end load and ripple requirements. The soft start circuit includes capacitor 3C1, capacitor 4C1, resistor 1R2, resistor 4R1, and NMOS transistor N1; Specific circuit connections: Terminal 1 of electrical connector P1 is connected to pin 1 of common-mode inductor L1; Terminal 2 of electrical connector P1 is connected to pin 2 of common-mode inductor L1; Terminal 3 of electrical connector P1 is connected to pin 4 of common-mode inductor L1; Capacitor 1CX2 and resistor 1R1 are connected in parallel between terminals 1 and 2 of electrical connector P1; Capacitor 2CX2 and resistor 2R1 are connected in parallel between terminals 2 and 3 of electrical connector P1; Capacitor 3CX2 and resistor 3R1 are connected in parallel between terminals 1 and 3 of electrical connector P1; Common-mode inductor Connect capacitor 3CY1 in parallel between pin 1 of L1 and KGND; connect capacitor 4CY1 in parallel between pin 2 of common-mode inductor L1 and KGND; connect capacitor 5CY1 in parallel between pin 4 of common-mode inductor L1 and KGND; connect pin 8 of common-mode inductor L1 to pin 1 of common-mode inductor L2; connect pin 7 of common-mode inductor L1 to pin 2 of common-mode inductor L2; connect pin 5 of common-mode inductor L1 to pin 4 of common-mode inductor L2; connect capacitor 1CX3 in parallel between pins 8 and 7 of common-mode inductor L1; A parallel capacitor 2CX3 is connected between pins 5 and 7 of inductor L1; a parallel capacitor 3CX3 is connected between pins 8 and 5 of common-mode inductor L1; a parallel capacitor 1CY3 is connected between pin 8 of common-mode inductor L1 and KGND; a parallel capacitor 2CY3 is connected between pin 7 of common-mode inductor L1 and KGND; a parallel capacitor 3CY3 is connected between pin 5 of common-mode inductor L1 and KGND; pin 8 of common-mode inductor L2 is connected to one end of differential-mode inductor 1L3; pin 7 of common-mode inductor L2 is connected to one end of differential-mode inductor 2L3; Pin 5 of the common-mode inductor L2 is connected to one end of the differential-mode inductor 3L3; a capacitor 2CX4 is connected in parallel between pins 5 and 7 of the common-mode inductor L2; a capacitor 3CX4 is connected in parallel between pins 5 and 8 of the common-mode inductor L2; a capacitor 1CX4 is connected in parallel between pins 8 and 7 of the common-mode inductor L2; a capacitor 8CY1 is connected in parallel between pin 5 of the common-mode inductor L2 and KGND; a capacitor 7CY1 is connected in parallel between pin 7 of the common-mode inductor L2 and KGND; and a capacitor 6CY1 is connected in parallel between pin 8 of the common-mode inductor L2 and KGND. The other end of the differential mode inductor 1L3 is connected to the positive electrode of the rectifier diode 1D1 and the negative electrode of the rectifier diode 4D1; the other end of the differential mode inductor 2L3 is connected to the positive electrode of the rectifier diode 2D1 and the negative electrode of the rectifier diode 5D1; the other end of the differential mode inductor 3L3 is connected to the positive electrode of the rectifier diode 3D1 and the negative electrode of the rectifier diode 6D1; the negative electrode of the rectifier diode 1D1, the negative electrode of the rectifier diode 2D1, and the negative electrode of the rectifier diode 3D1 are connected to one end of the magnetic bead 1L4; the positive electrode of the rectifier diode 4D1, the positive electrode of the rectifier diode 5D1, and the positive electrode of the rectifier diode 6D1 are connected to one end of the magnetic bead 2L4; capacitors 6C4, 7C4, and 10C4 are connected in parallel between V+ and V-; capacitor 1CY1 is connected in parallel between V+ and KGND; capacitor 2 CY1 is connected in parallel between V- and KGND; the other end of ferrite bead 1L4 is connected to terminal 1 of electrical connector P2; one end of TVS diode 1D2 is connected to terminal 1 of electrical connector P2, and the other end is connected to pin S of NMOS transistor N1; the other end of ferrite bead 2L4 is connected to the other end of TVS diode 1D2 and pin S of NMOS transistor N1; one end of capacitor 3C1 is connected to VOUT, and the other end is connected to pin S of NMOS transistor N1; one end of resistor 4R1 is connected to VOUT, and the other end is connected to pin G of NMOS transistor N1; one end of resistor 1R2, connected in parallel with capacitor 4C1, is connected to pin G of NMOS transistor N1, and the other end is connected to pin S of NMOS transistor N1; pin D of NMOS transistor N1 is connected to terminal 2 of electrical connector P2.

[0008] Further limitations on the above scheme: common-mode inductor L1, common-mode inductor L2, differential-mode inductor 1L3, differential-mode inductor 2L3, differential-mode inductor 3L3 are all made of nanocrystalline materials; resistors 1R1, 2R1, and 3R1 are selected from MΩ level for discharge; common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, and capacitor 8CY1 are selected from nF level, preferably 2.2nF to 20nF. F; the inductance of common-mode inductor L1 and common-mode inductor L2 is greater than that of differential-mode inductor 1L3, differential-mode inductor 2L3, and differential-mode inductor 3L3. The inductance of common-mode inductor L1 and common-mode inductor L2 is selected to be 500uH or above; Differential-mode capacitors: The larger the capacity of capacitors 1CX2, 2CX2, 3CX2, 1CX3, 2CX3, 3CX3, 1CX4, 2CX4, and 3CX4, the greater the leakage current, and the preferred range is 0.1uF to 0.47uF.

[0009] To further limit the above scheme, the larger the inductance of differential mode inductor 1L3, differential mode inductor 2L3, and differential mode inductor 3L3, the greater the power factor; the greater the load power, the greater the power factor; if the inductance is too small, the power factor improvement is not significant, and the preferred value is between 100uH and 1mH.

[0010] To further limit the above solution, the parameter settings of resistor 1R2 and resistor 4R1 need to be based on the gate threshold voltage V of NMOS tube N1. GS and the rectified DC voltage VOUT; the startup time is determined by the charging time of the RC charging circuit composed of capacitor 4C1 and resistor 4R1.

[0011] The advantages of the present invention compared with the prior art are: 1. The present invention integrates four functional modules: EMI filtering, power correction, rectification and soft start, reducing design complexity and cost. It can perform reactive power compensation and power factor correction, has a soft start function, can meet the electromagnetic compatibility requirements of CE102 and RE102 in GJB151B-2013, and improve power efficiency. 2. The present invention achieves efficient noise suppression: it adopts a two-stage common-mode inductor and differential-mode capacitor combination to meet the GJB151B-2013 standard; 3. The present invention improves the power factor: realizes the optimized design of differential mode inductance, and the power factor is ≥0.8; 4. The present invention has high reliability: due to the integration of a soft start circuit, surge current is avoided and the life of the device is extended; 5. The design principle of the present invention is concise and clear, the structure is simple, the environmental adaptability is strong, and the reliability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 1 is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0014] It should be noted that, as used herein, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the elements.

[0015] See also Figure 1 , details the embodiments of the present invention.

[0016] Embodiment: A passive three-phase AC filter and rectifier circuit comprises a filter circuit, a power correction circuit, a rectifier circuit and a soft start circuit; The filtering circuit is connected to the input interface module and is used to suppress common-mode and differential-mode noise. It is composed of two common-mode inductors, one differential-mode inductor, and corresponding common-mode capacitors and differential-mode capacitors. It is designed for the 400Hz AC power supply on the machine and meets the CE102 and RE102 requirements of GJB151B-2013.

[0017] The power correction circuit is composed of differential mode inductors to improve the circuit power factor; an inductance of more than 200uH can increase the power factor to more than 0.8; at the same time, the differential mode capacitor capacity in the filter circuit cannot be too large (no more than 0.47uF).

[0018] The rectifier circuit is connected to the output end of the power correction circuit, uses six rectifier diodes to perform full-wave rectification, and uses capacitors to perform filtering after rectification.

[0019] The slow-start circuit is connected to the DC output end and is composed of an NMOS tube and a resistor and capacitor. The resistor and capacitor form a charging circuit. When the capacitor voltage is charged to a value greater than the threshold voltage of the NMOS tube, the NMOS tube begins to conduct. As the charging time increases, the capacitor voltage increases and the on-resistance of the NMOS tube gradually decreases, thereby achieving slow-start of the circuit.

[0020] In a specific embodiment, the filter circuit includes common-mode inductor L1, common-mode inductor L2, differential-mode inductor 1L3, differential-mode inductor 2L3, differential-mode inductor 3L3, resistor 1R1, resistor 2R1, resistor 3R1, differential-mode capacitors: capacitor 1CX2, capacitor 2CX2, capacitor 3CX2, capacitor 1CX3, capacitor 2CX3, capacitor 3CX3, capacitor 1CX4, capacitor 2CX4, capacitor 3CX4, common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, capacitor 8CY1; The power correction circuit includes a differential mode inductor 1L3, a differential mode inductor 2L3, and a differential mode inductor 3L3; The rectifier circuit includes rectifier diodes 1D1, 2D1, 3D1, 4D1, 5D1, and 6D1, and capacitors 6C4, 7C4, and 10C4 are used for filtering after rectification, and their capacitance values ​​are determined according to the back-end load and ripple requirements; The soft start circuit includes capacitor 3C1, capacitor 4C1, resistor 1R2, resistor 4R1, and NMOS transistor N1; The specific circuit connections are as follows: Terminal 1 (network identifier AIN) of the electrical connector P1 is connected to pin 1 of the common-mode inductor L1; Terminal 2 (network identifier BIN) of the electrical connector P1 is connected to pin 2 of the common-mode inductor L1; Terminal 3 (network identifier CIN) of the electrical connector P1 is connected to pin 4 of the common-mode inductor L1; Capacitor 1CX2 and resistor 1R1 are connected in parallel between terminals 1 and 2 of the electrical connector P1; Capacitor 2CX2 and resistor 2R1 are connected in parallel between terminals 2 and 3 of the electrical connector P1; Capacitor 1CX2 and resistor 2R1 are connected in parallel between terminals 1 and 3 of the electrical connector P1. 3CX2 and resistor 3R1; parallel capacitor 3CY1 between pin 1 (network identifier AIN) of common-mode inductor L1 and KGND; parallel capacitor 4CY1 between pin 2 (network identifier BIN) of common-mode inductor L1 and KGND; parallel capacitor 5CY1 between pin 4 (network identifier CIN) of common-mode inductor L1 and KGND; pin 8 of common-mode inductor L1 is connected to pin 1 of common-mode inductor L2; pin 7 of common-mode inductor L1 is connected to pin 2 of common-mode inductor L2; pin 5 of common-mode inductor L1 is connected to pin 4 of common-mode inductor L2 Connections: Connect capacitor 1CX3 in parallel between pins 8 and 7 of the common-mode inductor L1; connect capacitor 2CX3 in parallel between pins 5 and 7 of the common-mode inductor L1; connect capacitor 3CX3 in parallel between pins 8 and 5 of the common-mode inductor L1; connect capacitor 1CY3 in parallel between pin 8 of the common-mode inductor L1 and KGND; connect capacitor 2CY3 in parallel between pin 7 of the common-mode inductor L1 and KGND; connect capacitor 3CY3 in parallel between pin 5 of the common-mode inductor L1 and KGND; connect pin 8 of the common-mode inductor L2 to one end of the differential-mode inductor 1L3; connect pin 7 of the common-mode inductor L2 to the differential-mode inductor 1L3. Connected to one end of the differential mode inductor 2L3; pin 5 of the common mode inductor L2 is connected to one end of the differential mode inductor 3L3; a parallel capacitor 2CX4 is connected between pins 5 and 7 of the common mode inductor L2; a parallel capacitor 3CX4 is connected between pins 5 and 8 of the common mode inductor L2; a parallel capacitor 1CX4 is connected between pins 8 and 7 of the common mode inductor L2; a parallel capacitor 8CY1 is connected between pin 5 of the common mode inductor L2 and KGND; a parallel capacitor 7CY1 is connected between pin 7 of the common mode inductor L2 and KGND; a parallel capacitor 6CY1 is connected between pin 8 of the common mode inductor L2 and KGND; The other end of the differential-mode inductor 1L3 is connected to the anode of the rectifier diode 1D1 and the cathode of the rectifier diode 4D1; the other end of the differential-mode inductor 2L3 is connected to the anode of the rectifier diode 2D1 and the cathode of the rectifier diode 5D1; the other end of the differential-mode inductor 3L3 is connected to the anode of the rectifier diode 3D1 and the cathode of the rectifier diode 6D1; the cathode of the rectifier diode 1D1, the cathode of the rectifier diode 2D1, and the cathode of the rectifier diode 3D1 (network symbol V+) are connected to one end of the ferrite bead 1L4; the anode of the rectifier diode 4D1, the anode of the rectifier diode 5D1, and the anode of the rectifier diode 6D1 (network symbol V-) are connected to one end of the ferrite bead 2L4; capacitors 6C4, 7C4, and 10C4 are connected in parallel between V+ and V-; capacitor 1CY1 is connected in parallel between V+ and KGND; capacitor 2CY1 is connected in parallel between Between V- and KGND; the other end of ferrite bead 1L4 is connected to terminal 1 (net label VOUT) of electrical connector P2; one end of transient suppressor diode 1D2 is connected to terminal 1 (net label VOUT) of electrical connector P2, and the other end is connected to pin S of NMOS transistor N1; the other end of ferrite bead 2L4 is connected to the other end of transient suppressor diode 1D2 and pin S of NMOS transistor N1; one end of capacitor 3C1 is connected to VOUT, and the other end is connected to pin S of NMOS transistor N1; one end of resistor 4R1 is connected to VOUT, and the other end is connected to pin G of NMOS transistor N1; one end of resistor 1R2, connected in parallel with capacitor 4C1, is connected to pin G of NMOS transistor N1, and the other end is connected to pin S of NMOS transistor N1; pin D of NMOS transistor N1 is connected to terminal 2 (net label GND) of electrical connector P2.

[0021] Preferably, the common-mode inductor L1, the common-mode inductor L2, the differential-mode inductor 1L3, the differential-mode inductor 2L3, and the differential-mode inductor 3L3 are all made of nanocrystalline materials; the resistors 1R1, 2R1, and 3R1 are selected to be of the MΩ level for discharge; the common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, and capacitor 8CY1 are selected to have a capacity of nF level, preferably between 2.2nF and 20nF; The inductance of common-mode inductor L1 and common-mode inductor L2 is greater than that of differential-mode inductor 1L3, differential-mode inductor 2L3, and differential-mode inductor 3L3. The inductance of common-mode inductor L1 and common-mode inductor L2 is selected to be 500uH or above; Differential-mode capacitors: The larger the capacity of capacitors 1CX2, 2CX2, 3CX2, 1CX3, 2CX3, 3CX3, 1CX4, 2CX4, and 3CX4, the greater the leakage current, and the preferred value is between 0.1uF and 0.47uF.

[0022] Preferably, the larger the inductance of differential mode inductor 1L3, differential mode inductor 2L3, and differential mode inductor 3L3, the greater the power factor; the greater the load power, the greater the power factor; if the inductance is too small, the power factor is not significantly improved, preferably between 100uH and 1mH.

[0023] Preferably, the parameters of resistor 1R2 and resistor 4R1 need to be set according to the gate threshold voltage V of NMOS tube N1. GS and the rectified DC voltage VOUT; the startup time is determined by the charging time of the RC charging circuit composed of capacitor 4C1 and resistor 4R1.

[0024] Working principle: 1. Filter circuit: The input three-phase AC power suppresses common-mode noise through common-mode inductors L1 and L2, and differential-mode capacitors (1CX2-3CX4) absorb differential-mode noise.

[0025] The common-mode capacitors (3CY1-8CY1) bypass the noise to ground, and the resistors (1R1-3R1) are used for discharge.

[0026] 2. Power correction: Differential mode inductors (1L3-3L3) delay the current phase, match the voltage waveform, and improve the power factor.

[0027] 3. Rectification and filtering: After six diode bridge rectification, capacitors (6C4-10C4) smooth the DC output.

[0028] 4. Soft start: When powered on, the circuit (4R1, 4C1) charges slowly, the gate voltage of the NMOS tube N1 gradually increases, and the on-resistance decreases, achieving soft start.

[0029] This device integrates filtering, power correction, rectification, and soft-start functions. Its two-stage common-mode and differential-mode inductor design effectively suppresses conducted interference and improves the power factor to above 0.8, meeting the GJB151B-2013 standard. It offers low cost, high reliability, and strong environmental adaptability.

[0030] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0031] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A passive three-phase AC filter rectifier circuit, characterized in that: Contains filtering circuit, power correction circuit, rectification circuit and slow start circuit; The filtering circuit is connected to the input interface module and is used to suppress common-mode and differential-mode noise. It is composed of two stages of common-mode inductors, one stage of differential-mode inductors, and corresponding common-mode capacitors and differential-mode capacitors. The power correction circuit is composed of differential mode inductors and is used to improve the power factor of the circuit; The rectifier circuit is connected to the output end of the power correction circuit, uses six rectifier diodes to perform full-wave rectification, and uses capacitors to perform filtering after rectification; The slow-start circuit is connected to the DC output end and is composed of an NMOS tube and a resistor and capacitor. The resistor and capacitor form a charging circuit. When the capacitor voltage is charged to a value greater than the threshold voltage of the NMOS tube, the NMOS tube begins to conduct. As the charging time increases, the capacitor voltage increases and the on-resistance of the NMOS tube gradually decreases, thereby achieving slow-start of the circuit.

2. A passive three-phase AC filter rectifier circuit according to claim 1, characterized in that: The filter circuit includes common-mode inductor L1, common-mode inductor L2, differential-mode inductor 1L3, differential-mode inductor 2L3, differential-mode inductor 3L3, resistor 1R1, resistor 2R1, resistor 3R1, differential-mode capacitors: capacitor 1CX2, capacitor 2CX2, capacitor 3CX2, capacitor 1CX3, capacitor 2CX3, capacitor 3CX3, capacitor 1CX4, capacitor 2CX4, capacitor 3CX4, common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, capacitor 8CY1; The power correction circuit includes a differential mode inductor 1L3, a differential mode inductor 2L3, and a differential mode inductor 3L3; The rectifier circuit includes rectifier diodes 1D1, 2D1, 3D1, 4D1, 5D1, and 6D1, and capacitors 6C4, 7C4, and 10C4 are used for filtering after rectification, and their capacitance values ​​are determined according to the back-end load and ripple requirements; The soft start circuit includes capacitor 3C1, capacitor 4C1, resistor 1R2, resistor 4R1, and NMOS transistor N1; Specific circuit connections: Terminal 1 of electrical connector P1 is connected to pin 1 of common-mode inductor L1; Terminal 2 of electrical connector P1 is connected to pin 2 of common-mode inductor L1; Terminal 3 of electrical connector P1 is connected to pin 4 of common-mode inductor L1; Capacitor 1CX2 and resistor 1R1 are connected in parallel between terminals 1 and 2 of electrical connector P1; Capacitor 2CX2 and resistor 2R1 are connected in parallel between terminals 2 and 3 of electrical connector P1; Capacitor 3CX2 and resistor 3R1 are connected in parallel between terminals 1 and 3 of electrical connector P1; Common-mode inductor Connect capacitor 3CY1 in parallel between pin 1 of L1 and KGND; connect capacitor 4CY1 in parallel between pin 2 of common-mode inductor L1 and KGND; connect capacitor 5CY1 in parallel between pin 4 of common-mode inductor L1 and KGND; connect pin 8 of common-mode inductor L1 to pin 1 of common-mode inductor L2; connect pin 7 of common-mode inductor L1 to pin 2 of common-mode inductor L2; connect pin 5 of common-mode inductor L1 to pin 4 of common-mode inductor L2; connect capacitor 1CX3 in parallel between pins 8 and 7 of common-mode inductor L1; A parallel capacitor 2CX3 is connected between pins 5 and 7 of inductor L1; a parallel capacitor 3CX3 is connected between pins 8 and 5 of common-mode inductor L1; a parallel capacitor 1CY3 is connected between pin 8 of common-mode inductor L1 and KGND; a parallel capacitor 2CY3 is connected between pin 7 of common-mode inductor L1 and KGND; a parallel capacitor 3CY3 is connected between pin 5 of common-mode inductor L1 and KGND; pin 8 of common-mode inductor L2 is connected to one end of differential-mode inductor 1L3; pin 7 of common-mode inductor L2 is connected to one end of differential-mode inductor 2L3; Pin 5 of the common-mode inductor L2 is connected to one end of the differential-mode inductor 3L3; a capacitor 2CX4 is connected in parallel between pins 5 and 7 of the common-mode inductor L2; a capacitor 3CX4 is connected in parallel between pins 5 and 8 of the common-mode inductor L2; a capacitor 1CX4 is connected in parallel between pins 8 and 7 of the common-mode inductor L2; a capacitor 8CY1 is connected in parallel between pin 5 of the common-mode inductor L2 and KGND; a capacitor 7CY1 is connected in parallel between pin 7 of the common-mode inductor L2 and KGND; and a capacitor 6CY1 is connected in parallel between pin 8 of the common-mode inductor L2 and KGND. The other end of the differential mode inductor 1L3 is connected to the positive electrode of the rectifier diode 1D1 and the negative electrode of the rectifier diode 4D1; the other end of the differential mode inductor 2L3 is connected to the positive electrode of the rectifier diode 2D1 and the negative electrode of the rectifier diode 5D1; the other end of the differential mode inductor 3L3 is connected to the positive electrode of the rectifier diode 3D1 and the negative electrode of the rectifier diode 6D1; the negative electrode of the rectifier diode 1D1, the negative electrode of the rectifier diode 2D1, and the negative electrode of the rectifier diode 3D1 are connected to one end of the magnetic bead 1L4; the positive electrode of the rectifier diode 4D1, the positive electrode of the rectifier diode 5D1, and the positive electrode of the rectifier diode 6D1 are connected to one end of the magnetic bead 2L4; capacitors 6C4, 7C4, and 10C4 are connected in parallel between V+ and V-; capacitor 1CY1 is connected in parallel between V+ and KGND; capacitor 2 CY1 is connected in parallel between V- and KGND; the other end of ferrite bead 1L4 is connected to terminal 1 of electrical connector P2; one end of TVS diode 1D2 is connected to terminal 1 of electrical connector P2, and the other end is connected to pin S of NMOS transistor N1; the other end of ferrite bead 2L4 is connected to the other end of TVS diode 1D2 and pin S of NMOS transistor N1; one end of capacitor 3C1 is connected to VOUT, and the other end is connected to pin S of NMOS transistor N1; one end of resistor 4R1 is connected to VOUT, and the other end is connected to pin G of NMOS transistor N1; one end of resistor 1R2, connected in parallel with capacitor 4C1, is connected to pin G of NMOS transistor N1, and the other end is connected to pin S of NMOS transistor N1; pin D of NMOS transistor N1 is connected to terminal 2 of electrical connector P2.

3. The passive three-phase AC filter rectifier circuit according to claim 2, characterized in that: Common-mode inductor L1, common-mode inductor L2, differential-mode inductor 1L3, differential-mode inductor 2L3, and differential-mode inductor 3L3 are all made of nanocrystalline materials; resistors 1R1, 2R1, and 3R1 are selected in the MΩ level for discharge; common-mode capacitors: capacitor 3CY1, capacitor 4CY1, capacitor 5CY1, capacitor 1CY3, capacitor 2CY3, capacitor 3CY3, capacitor 6CY1, capacitor 7CY1, and capacitor 8CY1 are selected in the nF level, preferably between 2.2nF and 20nF; common-mode The inductance of inductor L1 and common-mode inductor L2 is greater than that of differential-mode inductor 1L3, differential-mode inductor 2L3, and differential-mode inductor 3L3. The inductance of common-mode inductor L1 and common-mode inductor L2 is selected to be 500uH or above; Differential-mode capacitors: The larger the capacity of capacitors 1CX2, 2CX2, 3CX2, 1CX3, 2CX3, 3CX3, 1CX4, 2CX4, and 3CX4, the greater the leakage current, and the preferred value is between 0.1uF and 0.47uF.

4. The passive three-phase AC filter rectifier circuit according to claim 2, characterized in that: The larger the inductance of differential mode inductor 1L3, differential mode inductor 2L3, and differential mode inductor 3L3, the greater the power factor; the greater the load power, the greater the power factor; the inductance is preferably between 100uH and 1mH.

5. The passive three-phase AC filter rectifier circuit according to claim 2, characterized in that: The parameter settings of resistor 1R2 and resistor 4R1 need to be based on the gate threshold voltage V of NMOS tube N1. GS and the rectified DC voltage VOUT; the startup time is determined by the charging time of the RC charging circuit composed of capacitor 4C1 and resistor 4R1.

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