Seamless transition efficient hybrid buck-boost switching power supply converter and conversion method

Abstract

The invention discloses a seamless transition high-efficiency hybrid buck-boost switching power supply converter and a conversion method, which can further reduce the inductive current in a buck mode while realizing seamless mode transition through a control mode of adding a capacitor branch and a logic gate. Compared with the SDC-BB, the inductive current can be reduced in the step-down mode. Besides, although the high-efficiency hybrid buck-boost switching power supply converter is additionally provided with a switch compared with an SDC-BB, a normally-closed tube exists in each mode, so that the efficiency can be improved, in addition, high-voltage nodes do not exist, a common process can be used, and the manufacturing difficulty and the area cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of converters, and particularly to a high-efficiency hybrid buck-boost switching power supply converter with seamless transition and a conversion method thereof. Background Art

[0002] In order to meet the requirements of electronic devices powered by lithium batteries, a switching power supply converter that can provide a stable 3.3V output voltage for a target load within the input voltage range of a lithium battery is widely used, and its common application scenarios include radio frequency power amplifiers, battery chargers, and light-emitting diode drivers, etc. The input voltage of a lithium battery usually ranges from 2.7V to 4.2V, and its output voltage will gradually decrease during use. Currently, there is a buck-boost switching power supply converter composed of a buck switching power supply converter and a boost switching power supply converter, which can reduce a higher input voltage to 3.3V; when the input voltage is low, it can raise it to 3.3V. However, there is a problem of seamless transition when the input voltage and the output voltage are close (the voltage conversion ratio is 1), because when the voltage conversion ratio is very close to 1, the duty cycles in the buck mode and the boost mode of the converter are very close to 100% and 0% respectively. In order to provide a stable 3.3V target output voltage for the load throughout the input voltage range of the lithium battery and extend the service life of the battery, there is a great need for a switching power supply converter that has both buck-boost functions and can achieve seamless transition.

[0003] As Figure 6 shown is a high-efficiency buck-boost hybrid converter (Power-Efficient Buck-Boost Convertor, HBUBOC). The converter is divided into a buck mode and a boost mode. The voltage conversion ratios (Convention Ratio, CR) of the buck mode and the boost mode of this converter are respectively expressed by equations (1) and (2), and the ranges are respectively 0.5 < CR < 1 and 1 < CR < +∞.

[0004]

[0005] In the buck mode, the inductor current is CR Buck times the load current. In the boost mode, the inductor current is equal to the load current. This can ensure that the inductor current is always lower than the load current during most of the time when the lithium battery is discharging, especially when the load is heavy, which is beneficial to the improvement of efficiency. However, the voltage conversion ratio of 1 is not included in the conversion ratio range, so there is a problem of inability to achieve seamless transition when the voltage conversion ratio is 1.

[0006] The academic paper "A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9 mV Ripple and 2.1 mV Mode-Change Fluctuation for Mobile OLED Displays" was published in the 2024 IEEE Symposium on VLSI Technology and Circuits, and its circuit structure is as Figure 7 shown. This literature proposed a single-duty-cycled buck-boost switching power converter (SDC-BB). By improving the control method of the three-level buck-boost converter (TLBB), this structure achieved seamless transition and solved the seamless transition problem when the voltage conversion ratio is 1.

[0007] This structure uses two duty-cycle signals with a 180-degree phase difference. The duty cycle directly controls the on and off of the switches. The label S1P on the switch indicates that the switch conducts when S1 is at a high level, and S1N indicates that the switch conducts when S1 is at a low level. The same applies to S2P and S2N. D represents the duty cycle, and T represents the period.

[0008] When D > 0.5, within the time of (2D - 1)*T, the switches controlled by S1P and S2P conduct simultaneously, and the structure operates in a inner loop and is in the boost mode. The DC voltage of the flying capacitor CF is VIN. When D < 0.5, within the time of (1 - 2D)*T, the switches controlled by S1N and S2N conduct simultaneously, and the structure operates in a inner loop and is in the buck mode.

[0009] According to the volt-second balance law of the inductor L, the voltage conversion ratios in the boost and buck modes of this structure can be obtained as equations (3) and (4).

[0010]

[0011] Since the inductor is connected to the output terminal, the relationship between the inductor current and the load current is:

[0012] As can be seen from equations (3) and (4), the voltage conversion ratio range of this structure is 0 < CR < 2, achieving seamless transition between the buck and boost modes. Although the structure proposed in this literature can achieve seamless mode transition, as can be seen from equation (5), the inductor current of this structure is the same as the load current, which will further deteriorate the efficiency under heavy load conditions. Summary of the Invention

[0013] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a seamlessly transitioned, high-efficiency hybrid buck-boost switching power supply converter and a high-efficiency hybrid buck-boost switching power supply conversion method.

[0014] To achieve the above objectives, the technical solutions provided by the present invention are:

[0015] A high-efficiency hybrid buck-boost switching power converter with seamless transition, comprising a second NMOS switch M2, a third NMOS switch M3, a fourth NMOS switch M4, a fifth NMOS switch M5, a PMOS switch M6, an inductor, a flying capacitor CF1, a flying capacitor CF2, and a first NMOS switch M1 with a substrate selection structure;

[0016] The first NMOS switch M1 is connected in series with the flying capacitor CF1 and the inductor; the voltage input terminal is connected to the first NMOS switch M1 and the inductor respectively;

[0017] The drain of the second NMOS switch M2 is connected to the flying capacitor CF1, and the source of the second NMOS switch M2 is grounded;

[0018] The drain of the PMOS switch M6 is connected to the inductor and the flying capacitor CF1 respectively, and the source of the PMOS switch M6 is connected to the drain of the fifth NMOS switch M5 and one end of the flying capacitor CF2 respectively;

[0019] The source of the fifth NMOS switch M5 is connected to the drain of the fourth NMOS switch M4;

[0020] The other end of the flying capacitor CF2 is connected to the source of the fourth NMOS switch M4 and the drain of the third NMOS switch M3 respectively;

[0021] The source of the third NMOS switch M3 is grounded;

[0022] The voltage output terminal is connected to the source of the fifth NMOS switch M5 and the drain of the fourth NMOS switch M4 respectively;

[0023] The first NMOS switch M1, the second NMOS switch M2, the third NMOS switch M3, the fourth NMOS switch M4, the fifth NMOS switch M5, and the PMOS switch M6 are all switched based on the result values ​​of the expressions obtained using their respective control signals;

[0024] Wherein, the expression of the first NMOS switch M1 is S1P×S2N;

[0025] The expressions of the second NMOS switch M2 and the PMOS switch M6 are both S1P×S2P;

[0026] The expression of the third NMOS switch M3 is S2P;

[0027] The expression of the fourth NMOS switch M4 is S1N × S2N;

[0028] The expression of the fifth NMOS switch M5 is S1P + S2P;

[0029] S1 and S2 are two control signals with a phase difference of 180 degrees, and both P and N are polarities (e.g., S1P and S1N represent the polarities of the S1 signal. When S1 is at a positive level, S1P = 1 and S1N = 0; when S1 is at a zero level, S1P = 0 and S1N = 1. The same applies to the S2 signal). "×" represents logical AND, and "+" represents logical OR.

[0030] The first NMOS switch M1, the second NMOS switch M2, the third NMOS switch M3, the fourth NMOS switch M4, and the fifth NMOS switch M5 are all turned on when the result of the expression is "1" and not turned on when the result is "0"; the PMOS switch M6 is相反, that is, it is turned on when the result of its expression is "0" and not turned on when the result is "1". Additionally, the first NMOS switch M1 adopts a substrate selection structure, and its substrate will be automatically connected to the end with a low potential according to different working conditions.

[0031] Furthermore, to achieve the above object, the present invention additionally provides a seamless-transition high-efficiency hybrid buck-boost switching power supply conversion method, which is implemented by using the above seamless-transition high-efficiency hybrid buck-boost switching power supply converter, and it includes:

[0032] When 0 < D < 0.5, where D is the duty cycle, in the buck mode, the circuit cycles between phases ;

[0033] In the buck mode, when the circuit is in phase , the two control signals are respectively S1 = 0 and S2 = 1. Within the time of D*T, the expression of the first NMOS switch M1 is always 0×0, and the calculated result is 0, so the first NMOS switch M1 is not turned on; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 0×1, and the calculated results are both 0, so the second NMOS switch M2 is not turned on and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 1, and the calculated result is 1, so the third NMOS switch M3 is turned on; the expression of the fourth NMOS switch M4 is 1×0, and the calculated result is 0, so the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 0 + 1, and the calculated result is 1, so the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT at the voltage output terminal, discharging to the voltage output terminal, and at the same time, the voltage input terminal directly supplies power to the voltage output terminal;

[0034] In the buck mode, when the circuit is in phase When the two control signals are S1=1 and S2=0, respectively, within the time D*T, the expression of the first NMOS switch M1 is 1×1, the calculation result is 1, and the first NMOS switch M1 is turned on; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×0, the calculation result is 0, the second NMOS switch M2 is not turned on, and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not turned on; the expression of the fourth NMOS switch M4 is 0×1, the calculation result is 0, and the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 1+0, the calculation result is 1, and the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF1 is the voltage of the voltage output end minus the voltage of the voltage input end; the voltage input end directly supplies power to the voltage output end; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 is not discharged or charged;

[0035] In buck mode, the circuit is in phase and phase When the two control signals are S1=0 and S2=0, respectively, within the time of (1-2D)*T, where T is the period, the expressions of the first NMOS switch M1 are both 0×1, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 0×0, the calculation result is 0, the second NMOS switch M2 is not conducting, and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not conducting; the expression of the fourth NMOS switch M4 is 1×1, the calculation result is 1, and the fourth NMOS switch M4 is conducting; the expression of the fifth NMOS switch M5 is 0+0, the calculation result is 0, and the fifth NMOS switch M5 is not conducting; at this time, the voltages across the inductor are respectively twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, and the inductor current charges the flying capacitor CF2;

[0036] The voltage conversion ratio is calculated by the inductor volt-second balance:

[0037]

[0038] From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get:

[0039]

[0040] Inductor current I in buck mode L Reduced to CR Buck times the load current I O ;

[0041] When 0 < D < 0.5, the circuit in boost mode cycles between phases ;

[0042] In boost mode, when the circuit is at phase the two control signals are S1 = 0 and S2 = 1 respectively. During the time of (1 - D)*T, the expression of the first NMOS switch M1 is all 0×0, and the calculation result is 0, so the first NMOS switch M1 is not conducting; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 0×1, and the calculation results are both 0, so the second NMOS switch M2 is not conducting and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 1, and the calculation result is 1, so the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 1×0, and the calculation result is 0, so the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 0 + 1, and the calculation result is 1, so the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT at the voltage output terminal, discharging to the voltage output terminal, and at the same time the voltage input terminal directly supplies power to the voltage output terminal;

[0043] In boost mode, when the circuit is at phase the two control signals are S1 = 1 and S2 = 0 respectively. During the time of (1 - D)*T, the expression of the first NMOS switch M1 is all 1×1, and the calculation result is 1, so the first NMOS switch M1 is conducting; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 1×0, and the calculation results are both 0, so the second NMOS switch M2 is not conducting and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 0, and the calculation result is 0, so the third NMOS switch M3 is not conducting; the expression of the fourth NMOS switch M4 is 0×1, and the calculation result is 0, so the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 1 + 0, and the calculation result is 1, so the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF1 is VOUT - VIN (where VOUT is the voltage at the voltage output terminal and VIN is the voltage at the voltage input terminal), and the voltage input terminal directly supplies power to the voltage output terminal; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 does not discharge or charge;

[0044] In boost mode, when the circuit is at phase and When the two control signals are S1=1 and S2=1, respectively, within the time of (2D-1)*T, the expression of the first NMOS switch M1 is 1×0, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×1, the calculation result is 1, the second NMOS switch M2 is conducting, and the PMOS switch M6 is not conducting; the expression of the third NMOS switch M3 is 1, the calculation result is 1, and the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 0×0, the calculation result is 0, and the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 1+1, the calculation result is 1, and the fifth NMOS switch M5 is conducting; at this time, the voltages across the inductor are twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, respectively, and the inductor current charges the flying capacitor CF2;

[0045] The voltage conversion ratio is calculated by the inductor volt-second balance:

[0046]

[0047] From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get:

[0048] I L =I O

[0049] CR Buck , CR Boost The derivative of the expression at D = 0.5 is 2. Therefore, it can be proved that at the mode switching point, that is, at the moment D = 0.5, the high-efficiency hybrid buck-boost switching power supply converter described in the technical solution can perform smooth and seamless mode switching.

[0050] Compared with the existing technology, the principles and advantages of this technical solution are as follows:

[0051] This technical solution, by adding capacitor branches and logic gate control methods, can further reduce the inductor current in buck mode while achieving seamless mode transition. Compared with SDC-BB, the inductor current can be reduced in buck mode. In addition, although the high-efficiency hybrid buck-boost switching power converter described in this technical solution has an additional switch compared to SDC-BB, it has a "normally off" switch in each mode, thereby improving efficiency. In addition, it does not have high-voltage nodes, so it can use ordinary processes, reducing manufacturing difficulty and area cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 A circuit diagram of a high-efficiency hybrid buck-boost switching power converter with seamless transition according to an embodiment of the present invention;

[0054] Figure 2 This is a working principle diagram of a seamlessly transitioned high-efficiency hybrid buck-boost switching power converter in buck mode according to an embodiment of the present invention;

[0055] Figure 3 This is a working principle diagram of a seamlessly transitioned high-efficiency hybrid buck-boost switching power converter in boost mode according to an embodiment of the present invention;

[0056] Figure 4 A relationship diagram between the voltage conversion ratio and the duty cycle of the seamless transition high-efficiency hybrid buck-boost switching power converter according to an embodiment of the present invention;

[0057] Figure 5 A comparison of the inductor current of the present invention and SDC-BB at the same lithium battery voltage;

[0058] Figure 6 It is the working circuit diagram of the prior art HBUBOC;

[0059] Figure 7 It is the working circuit diagram of the prior art SDC-BB. DETAILED DESCRIPTION

[0060] The present invention will be further described below in conjunction with specific embodiments:

[0061] like Figure 1 As shown, the seamless transition high-efficiency hybrid buck-boost switching power converter described in this embodiment includes a second NMOS switch M2, a third NMOS switch M3, a fourth NMOS switch M4, a fifth NMOS switch M5, a PMOS switch M6, an inductor, a flying capacitor CF1, a flying capacitor CF2, and a first NMOS switch M1 with a substrate selection structure;

[0062] The first NMOS switch M1 is connected in series with the flying capacitor CF1 and the inductor; the voltage input terminal is connected to the first NMOS switch M1 and the inductor respectively;

[0063] The drain of the second NMOS switch M2 is connected to the flying capacitor CF1, and the source of the second NMOS switch M2 is grounded;

[0064] The drain of the PMOS switch M6 is connected to the inductor and the flying capacitor CF1 respectively, and the source of the PMOS switch M6 is connected to the drain of the fifth NMOS switch M5 and one end of the flying capacitor CF2 respectively;

[0065] The source of the fifth NMOS switch M5 is connected to the drain of the fourth NMOS switch M4;

[0066] The other end of the flying capacitor CF2 is connected to the source of the fourth NMOS switch M4 and the drain of the third NMOS switch M3 respectively;

[0067] The source of the third NMOS switch M3 is grounded;

[0068] The voltage output terminal is connected to the source of the fifth NMOS switch M5 and the drain of the fourth NMOS switch M4 respectively;

[0069] The first NMOS switch M1, the second NMOS switch M2, the third NMOS switch M3, the fourth NMOS switch M4, the fifth NMOS switch M5, and the PMOS switch M6 are all switched based on the result values ​​of the expressions obtained using their respective control signals;

[0070] Wherein, the expression of the first NMOS switch M1 is S1P×S2N;

[0071] The expressions of the second NMOS switch M2 and the PMOS switch M6 are both S1P×S2P;

[0072] The expression of the third NMOS switch M3 is S2P;

[0073] The expression of the fourth NMOS switch M4 is S1N×S2N;

[0074] The expression of the fifth NMOS switch M5 is S1P+S2P;

[0075] S1 and S2 are two control signals with a phase difference of 180 degrees. P and N are polarities (such as S1P and S1N represent the polarity of the S1 signal. When S1 is a positive level, S1P=1, S1N=0; when S1 is a zero level, S1P=0, S1N=1. The same is true for the S2 signal). "×" represents logical AND and "+" represents logical OR.

[0076] The first NMOS switch M1, the second NMOS switch M2, the third NMOS switch M3, the fourth NMOS switch M4, and the fifth NMOS switch M5 are all turned on when the result of the expression is "1" and not turned on when the result is "0"; the PMOS switch M6 is the opposite, and it is turned on when the result of its expression is "0" and not turned on when the result is "1". In addition, the first NMOS switch M1 adopts a substrate selection structure, and its substrate will be automatically connected to the end with a low potential according to different working conditions.

[0077] The working principle of the seamless-transition high-efficiency hybrid buck-boost switching power supply converter described in this embodiment is as follows:

[0078] As Figure 2 shown, when 0 < D < 0.5, where D is the duty cycle, the circuit operates in the buck mode and cycles between phases ; the waveform diagrams of the S1 and S2 control signals are as shown in the upper left corner of Figure 2 .

[0079] In the buck mode, when the circuit is in phase , the two control signals are S1 = 0 and S2 = 1 respectively. During the time of D*T, the expression of the first NMOS switch M1 is 0×0, and the calculated result is 0, so the first NMOS switch M1 is not turned on; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 0×1, and the calculated results are both 0, so the second NMOS switch M2 is not turned on and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 1, and the calculated result is 1, so the third NMOS switch M3 is turned on; the expression of the fourth NMOS switch M4 is 1×0, and the calculated result is 0, so the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 0 + 1, and the calculated result is 1, so the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT at the voltage output terminal, discharges to the voltage output terminal, and at the same time the voltage input terminal directly supplies power to the voltage output terminal;

[0080] In the buck mode, when the circuit is in phase When the two control signals are S1=1 and S2=0, respectively, within the time D*T, the expression of the first NMOS switch M1 is 1×1, the calculation result is 1, and the first NMOS switch M1 is turned on; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×0, the calculation result is 0, the second NMOS switch M2 is not turned on, and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not turned on; the expression of the fourth NMOS switch M4 is 0×1, the calculation result is 0, and the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 1+0, the calculation result is 1, and the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF1 is the voltage of the voltage output end minus the voltage of the voltage input end; the voltage input end directly supplies power to the voltage output end; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 is not discharged or charged;

[0081] In buck mode, the circuit is in phase and phase When the two control signals are S1=0 and S2=0, respectively, within the time of (1-2D)*T, where T is the period, the expressions of the first NMOS switch M1 are both 0×1, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 0×0, the calculation result is 0, the second NMOS switch M2 is not conducting, and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not conducting; the expression of the fourth NMOS switch M4 is 1×1, the calculation result is 1, and the fourth NMOS switch M4 is conducting; the expression of the fifth NMOS switch M5 is 0+0, the calculation result is 0, and the fifth NMOS switch M5 is not conducting; at this time, the voltages across the inductor are respectively twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, and the inductor current charges the flying capacitor CF2;

[0082] The voltage conversion ratio is calculated by the inductor volt-second balance:

[0083]

[0084] From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get:

[0085]

[0086] Inductor current I in buck mode L Reduced to CR Buck times the load current I O ;

[0087] As Figure 3 shown, when 0 < D < 0.5, the circuit in boost mode cycles between phases ; the waveform diagrams of the control signals S1 and S2 are as shown in the upper left corner Figure 3 .

[0088] When the circuit in boost mode is at phase , the two control signals are S1 = 0 and S2 = 1 respectively. During the time of (1 - D)*T, the expression of the first NMOS switch M1 is 0×0, and the calculation result is 0, so the first NMOS switch M1 is not conducting; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 0×1, and the calculation results are both 0, so the second NMOS switch M2 is not conducting and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 1, and the calculation result is 1, so the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 1×0, and the calculation result is 0, so the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 0 + 1, and the calculation result is 1, so the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT at the voltage output terminal, discharging to the voltage output terminal, and at the same time the voltage input terminal directly supplies power to the voltage output terminal;

[0089] When the circuit in boost mode is at phase , the two control signals are S1 = 1 and S2 = 0 respectively. During the time of (1 - D)*T, the expression of the first NMOS switch M1 is 1×1, and the calculation result is 1, so the first NMOS switch M1 is conducting; the expressions of the second NMOS switch M2 and the PMOS switch M6 are both 1×0, and the calculation results are both 0, so the second NMOS switch M2 is not conducting and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 0, and the calculation result is 0, so the third NMOS switch M3 is not conducting; the expression of the fourth NMOS switch M4 is 0×1, and the calculation result is 0, so the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 1 + 0, and the calculation result is 1, so the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF1 is VOUT - VIN (the voltage at the voltage output terminal minus the voltage at the voltage input terminal), and the voltage input terminal directly supplies power to the voltage output terminal; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 does not discharge or charge;

[0090] When the circuit in boost mode is at phase and When the two control signals are S1=1 and S2=1, respectively, within the time of (2D-1)*T, the expression of the first NMOS switch M1 is 1×0, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×1, the calculation result is 1, the second NMOS switch M2 is conducting, and the PMOS switch M6 is not conducting; the expression of the third NMOS switch M3 is 1, the calculation result is 1, and the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 0×0, the calculation result is 0, and the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 1+1, the calculation result is 1, and the fifth NMOS switch M5 is conducting; at this time, the voltages across the inductor are twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, respectively, and the inductor current charges the flying capacitor CF2;

[0091] The voltage conversion ratio is calculated by the inductor volt-second balance:

[0092]

[0093] From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get:

[0094] I L =I O

[0095] CR Buck , CR Boost The derivative of the expression at D = 0.5 is 2. Therefore, it can be proved that at the mode switching point, that is, at the moment D = 0.5, the high-efficiency hybrid buck-boost switching power supply converter described in the technical solution can perform smooth and seamless mode switching.

[0096] By adding capacitor branches and logic gate control methods, the present invention achieves seamless mode transition while further reducing the inductor current in buck mode. Compared to the SDC-BB, the inductor current can be reduced in buck mode. Furthermore, while the high-efficiency hybrid buck-boost switching power converter described in this technical solution has an additional switch compared to the SDC-BB, it maintains a normally-off switch in each mode, thereby improving efficiency. Furthermore, it lacks high-voltage nodes, allowing the use of conventional processes, reducing manufacturing difficulty and area costs.

[0097] Figure 5 The comparison diagram of the inductor current of the present invention and SDC-BB at the same lithium battery voltage is shown in FIG. Figure 5 It can be seen that under the same lithium battery voltage, the solution of the present invention obtains a smaller inductor current in the buck mode, which can effectively reduce the conduction loss and switching loss, thereby improving the efficiency.

[0098] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, any changes made based on the shape and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. Seamless transition high-efficiency hybrid buck-boost switching power converter, characterized by: It includes a second NMOS switch M2, a third NMOS switch M3, a fourth NMOS switch M4, a fifth NMOS switch M5, a PMOS switch M6, an inductor, a flying capacitor CF1, a flying capacitor CF2, and a first NMOS switch M1 with a substrate selection structure; The first NMOS switch M1 is connected in series with the flying capacitor CF1 and the inductor; the voltage input terminal is connected to the first NMOS switch M1 and the inductor respectively; The drain of the second NMOS switch M2 is connected to the flying capacitor CF1, and the source of the second NMOS switch M2 is grounded; The drain of the PMOS switch M6 is connected to the inductor and the flying capacitor CF1 respectively, and the source of the PMOS switch M6 is connected to the drain of the fifth NMOS switch M5 and one end of the flying capacitor CF2 respectively; The source of the fifth NMOS switch M5 is connected to the drain of the fourth NMOS switch M4; The other end of the flying capacitor CF2 is connected to the source of the fourth NMOS switch M4 and the drain of the third NMOS switch M3 respectively; The source of the third NMOS switch M3 is grounded; The voltage output terminal is connected to the source of the fifth NMOS switch M5 and the drain of the fourth NMOS switch M4 respectively; The first NMOS switch M1, the second NMOS switch M2, the third NMOS switch M3, the fourth NMOS switch M4, the fifth NMOS switch M5, and the PMOS switch M6 are all switched based on the result values ​​of the expressions obtained using their respective control signals; Wherein, the expression of the first NMOS switch M1 is S1 P×S2N; The expressions of the second NMOS switch M2 and the PMOS switch M6 are both S1 P×S2P; The expression of the third NMOS switch M3 is S2P; The expression of the fourth NMOS switch M4 is S1N×S2N; The expression of the fifth NMOS switch M5 is S1 P+S2P; S1 and S2 are two control signals with a phase difference of 180 degrees. P and N are polarities. "×" represents logical AND, and "+" represents logical OR.

2. A seamless transition high-efficiency hybrid buck-boost switching power supply conversion method, characterized in that: It is implemented by using the seamless-transition high-efficiency hybrid buck-boost switching power supply converter described in claim 1, which includes: when 0 < D < 0.5, D is the duty cycle, and the circuit cycles between phases during the buck mode; In buck mode, the circuit is in phase When the two control signals are S1=0 and S2=1, within the time D*T, the expression of the first NMOS switch M1 is 0×0, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are 0×1, the calculation result is 0, the second NMOS switch M2 is not conducting, and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 1, the calculation result is 1, and the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 1×0, the calculation result is 0, and the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 0+1, the calculation result is 1, and the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT of the voltage output terminal, discharging the voltage output terminal, and at the same time, the voltage input terminal directly supplies power to the voltage output terminal; In buck mode, the circuit is in phase When the two control signals are S1=1 and S2=0, respectively, within the time D*T, the expression of the first NMOS switch M1 is 1×1, the calculation result is 1, and the first NMOS switch M1 is turned on; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×0, the calculation result is 0, the second NMOS switch M2 is not turned on, and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not turned on; the expression of the fourth NMOS switch M4 is 0×1, the calculation result is 0, and the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 1+0, the calculation result is 1, and the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF1 is the voltage of the voltage output end minus the voltage of the voltage input end; the voltage input end directly supplies power to the voltage output end; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 is not discharged or charged; In buck mode, the circuit is in phase and phase When the two control signals are S1=0 and S2=0, respectively, within the time of (1-2D)*T, where T is the period, the expressions of the first NMOS switch M1 are both 0×1, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 0×0, the calculation result is 0, the second NMOS switch M2 is not conducting, and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not conducting; the expression of the fourth NMOS switch M4 is 1×1, the calculation result is 1, and the fourth NMOS switch M4 is conducting; the expression of the fifth NMOS switch M5 is 0+0, the calculation result is 0, and the fifth NMOS switch M5 is not conducting; at this time, the voltages across the inductor are respectively twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, and the inductor current charges the flying capacitor CF2; The voltage conversion ratio is calculated by the inductor volt-second balance: From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get: Inductor current I in buck mode L Reduced to CR Buck times the load current I O ; When 0 < D < 0.5, the circuit in boost mode cycles between phases ; In boost mode, the circuit is in phase When the two control signals are S1=0 and S2=1 respectively, within the time of (1-D)*T, the expression of the first NMOS switch M1 is 0×0, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 0×1, the calculation result is 0, the second NMOS switch M2 is not conducting, and the PMOS switch M6 is conducting; the expression of the third NMOS switch M3 is 1, the calculation result is 1, and the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 1×0, the calculation result is 0, and the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 0+1, the calculation result is 1, and the fifth NMOS switch M5 is conducting; at this time, the voltage on the flying capacitor CF2 is equal to the voltage VOUT of the voltage output terminal, discharging the voltage output terminal, and at the same time, the voltage input terminal directly supplies power to the voltage output terminal; In boost mode, the circuit is in phase When the two control signals are S1=1 and S2=0, respectively, within the time of (1-D)*T, the expression of the first NMOS switch M1 is 1×1, the calculation result is 1, and the first NMOS switch M1 is turned on; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×0, the calculation result is 0, the second NMOS switch M2 is not turned on, and the PMOS switch M6 is turned on; the expression of the third NMOS switch M3 is 0, the calculation result is 0, and the third NMOS switch M3 is not turned on; the expression of the fourth NMOS switch M4 is 0×1, the calculation result is 0, and the fourth NMOS switch M4 is not turned on; the expression of the fifth NMOS switch M5 is 1+0, the calculation result is 1, and the fifth NMOS switch M5 is turned on; at this time, the voltage on the flying capacitor CF1 is the voltage VOUT of the voltage output terminal minus the voltage VIN of the voltage input terminal, and the voltage input terminal directly supplies power to the voltage output terminal; in the entire buck mode, the current path does not involve the flying capacitor CF1, and the flying capacitor CF1 is not discharged or charged; In boost mode, the circuit is in phase and When the two control signals are S1=1 and S2=1, respectively, within the time of (2D-1)*T, the expression of the first NMOS switch M1 is 1×0, the calculation result is 0, and the first NMOS switch M1 is not conducting; the expression of the second NMOS switch M2 and the expression of the PMOS switch M6 are both 1×1, the calculation result is 1, the second NMOS switch M2 is conducting, and the PMOS switch M6 is not conducting; the expression of the third NMOS switch M3 is 1, the calculation result is 1, and the third NMOS switch M3 is conducting; the expression of the fourth NMOS switch M4 is 0×0, the calculation result is 0, and the fourth NMOS switch M4 is not conducting; the expression of the fifth NMOS switch M5 is 1+1, the calculation result is 1, and the fifth NMOS switch M5 is conducting; at this time, the voltages across the inductor are twice the voltage VIN at the voltage input end and twice the voltage VOUT at the voltage output end, respectively, and the inductor current charges the flying capacitor CF2; The voltage conversion ratio is calculated by the inductor volt-second balance: From the flying capacitors CF1, CF2 and the charge balance law of the inductor, we can get: I L =I O CR Buck , CR Boost The derivative of the expression when D = 0.5 is 2.

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