Fractional frequency divider

Abstract

A delta-sigma modulator is used for modulating a static decimal signal into a high-speed dynamic code stream Y, determining a dynamic frequency dividing ratio, and calculating a quantization error between the code stream Y and the static decimal signal and generating a digital phase control word in each output clock period; the multimode frequency divider is used for performing dynamic frequency division on the high-frequency clock according to the dynamic frequency division ratio to obtain an initial frequency division signal; the phase generator is used for generating a first phase clock, a second phase clock and a third phase clock based on the high-frequency clock and the initial frequency division signal; and the digital phase interpolation unit is used for performing linear interpolation between the rising edges of the first phase clock and the second phase clock according to the digital phase control word so as to control the rising edge position of the output clock, and adjusting the duty ratio of the output clock according to the third phase clock. According to the invention, the problems of large area, time sequence interference, frequency limitation and the like of a differential architecture are solved, and optimization can be realized in the aspects of area, speed, power consumption and the like.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a fractional frequency divider. Background Art

[0002] Fractional frequency dividers play an important role in clock systems, communication systems and other fields. For example, in the process of high-resolution frequency synthesis, fractional frequency dividers can be used to generate finer output frequencies to meet the needs of modern high-speed communication systems. For example, in applications such as spread spectrum clocking (SSC), fractional frequency dividers can be used to dynamically adjust the output clock phase and reduce electromagnetic interference.

[0003] Currently, common implementation methods of fractional frequency dividers include open-loop fractional frequency dividers based on charge interpolation, whose typical architecture is a differential structure. The differential design of this type of fractional frequency divider often requires two sets of symmetrical interpolation units, resulting in a large layout area and complex layout. Summary of the Invention

[0004] In view of this, the present application provides a fractional frequency divider to solve the problem that the differential design of a traditional fractional frequency divider often requires two sets of symmetrical interpolation units, resulting in a large layout area and complex layout.

[0005] The present application provides a fractional frequency divider, the fractional frequency divider comprising a multi-mode frequency divider, a phase generator, a digital phase interpolation unit and a delta-sigma modulator;

[0006] The delta-sigma modulator is used to modulate a static fractional signal into a high-speed dynamic code stream Y, determine a dynamic frequency division ratio based on the code stream Y, send the dynamic frequency division ratio to the multi-mode frequency divider, and calculate a quantization error between the code stream Y and the static fractional signal in each output clock cycle to generate a digital phase control word, which is sent to the digital phase interpolation unit; the average value of the code stream Y is the static fractional signal; and the digital phase control word is used to compensate for the phase interpolation error.

[0007] The multi-mode frequency divider is used to dynamically divide the high-frequency clock according to the dynamic frequency division ratio, and send the initial frequency division signal obtained by the dynamic frequency division to the phase generator;

[0008] The phase generator is used to generate a first phase clock, a second phase clock and a third phase clock based on the high frequency clock and the initial frequency division signal; the rising edge interval of the first phase clock and the second phase clock is one clock cycle of the high frequency clock;

[0009] The digital phase interpolation unit is used to linearly interpolate between the rising edges of the first phase clock and the second phase clock according to the digital phase control word to control the rising edge position of the output clock, and adjust the duty cycle of the output clock according to the third phase clock.

[0010] Optionally, the digital phase interpolation unit includes a capacitor, a first switch, a reset latch, a duty cycle adjustment latch, a decoder and k DPI subunits; the input end of the decoder is used to access the digital phase control word, and the output end is connected to the first control end of each of the DPI subunits; the first input end of each of the DPI subunits is used to access the first phase clock, the second input end is used to access the second phase clock, the second control end is connected to the first end of the reset latch, and the output end is respectively connected to the first end of the capacitor, the first end of the first switch, the second end of the reset latch and the first end of the duty cycle adjustment latch; the third end of the reset latch is connected to the second end of the first switch, and the fourth end is used to access the control signal corresponding to the integer division ratio N; the second end of the duty cycle adjustment latch is used to access the third phase clock, and the third end is used to output the output clock; the second end of the capacitor is respectively connected to the third end of the first switch and the ground end; The decoder is used to decode the digital phase control word and output a phase selection signal representing the digital phase control word; each of the DPI sub-units is used to access the corresponding phase clock according to the phase selection signal, and output the corresponding current to the capacitor according to the interpolation enable signal output by the reset latch; the capacitor is used to store energy according to the current input by each of the DPI sub-units to adjust the input phase interpolation positive pulse, and the phase interpolation positive pulse is a phase interpolation signal generated by the DPI sub-unit using the corresponding current value to charge and discharge the capacitor according to the value of the phase selection signal; the reset latch is used to control the first end of the first switch to connect or disconnect its third end according to the phase interpolation positive pulse to charge and discharge the capacitor, reset the phase interpolation positive pulse to 0, and at the same time, the switch control signal is also reset to 0, so that the capacitor waits for the next cycle of charging; the duty cycle adjustment latch is used to adjust the duty cycle of the phase interpolation positive pulse to output the output clock.

[0011] Optionally, the DPI subunit includes a two-way selector, a first NAND gate and a current supply component; the first input end of the two-way selector is used to access the first phase clock, the second input end is used to access the second phase clock, the control end is used to access the phase selection signal, and the output end is connected to the first input end of the first NAND gate; the second input end of the first NAND gate is connected to the first end of the reset latch, and the output end is connected to the first end of the current supply component; the second end of the current supply component is respectively connected to the first end of the capacitor, the first end of the first switch, the second end of the reset latch and the first end of the duty cycle adjustment latch; the two-way selector is used to turn on the first phase clock or the second phase clock according to the phase selection signal; the first NAND gate is used to input an on-off control signal to the current supply component of the corresponding DPI subunit according to the interpolation enable signal; the current supply component is used to output current to the capacitor according to the on-off control signal output by the first NAND gate.

[0012] Optionally, the current providing component includes a second switch, a first inverter, a third switch and a current source; the first end of the second switch serves as the first end of the current providing component, the second end is respectively connected to the output end of the current source and the first end of the third switch, the third end is grounded, and the fourth end is connected to the input end of the first inverter; the output end of the first inverter is connected to the second end of the third switch; the third end of the third switch serves as the second end of the current providing component.

[0013] Optionally, the reset latch is further configured to access a first phase clock, and control the output current of at least part of the current providing component starting from a rising edge of the first phase clock.

[0014] Optionally, the reset latch is also used to control the output current of a preset number of current providing components at the rising edge of the first phase clock; control the output current of all current providing components after a clock cycle of the high-frequency clock; adjust the level characteristics of the switch control signal when the voltage signal is greater than or equal to a preset voltage threshold, and make the switch control signal become a high level after a first time after the phase interpolation positive pulse is equal to the voltage threshold, and adjust the switch control signal to a low level after the high level of the switch control signal lasts for a second time; set the interpolation enable signal to a low level after a third time after the phase interpolation positive pulse is equal to the voltage threshold; and set the interpolation enable signal to a high level after a fourth time starting from the falling edge of the first phase clock.

[0015] Optionally, the reset latch includes a second inverter, a second NAND gate, a third NAND gate, a third inverter, a fourth NAND gate, a fifth NAND gate, a fourth inverter and a first buffer; the input end of the second inverter is used to receive the phase interpolation positive pulse, and the output end is respectively connected to the first input end of the second NAND gate and the first input end of the fourth NAND gate; the second input end of the second NAND gate is connected to the output end of the third NAND gate, and the output end is respectively connected to the input end of the third inverter and the first input end of the third NAND gate; the output end of the third inverter is used to output the interpolation enable signal; the second input end of the third NAND gate is used to receive the first phase clock; the second input end of the fourth NAND gate is connected to the output end of the fifth NAND gate, and the output end is used to output the switch control signal corresponding to the first switch, and is respectively connected to the first input end of the fifth NAND gate and the input end of the fourth inverter; the second input end of the fifth NAND gate is connected to the first end of the first buffer; the second end of the first buffer is connected to the output end of the fourth inverter, and the third end is used to receive the control signal corresponding to the integer division ratio N.

[0016] Optionally, the duty cycle adjustment latch includes a first D flip-flop and a pulse generator; the first input end of the first D flip-flop is used to access a preset voltage, the second input end is used to access the phase interpolation positive pulse, and the clear end is connected to the output end of the pulse generator; the input end of the pulse generator is used to access the third phase clock; the pulse generator is used to generate a clear pulse according to the third phase clock; the first D flip-flop is used to adjust the duty cycle of the phase interpolation positive pulse according to the clear pulse.

[0017] Optionally, the phase generator includes a second D flip-flop, a third D flip-flop and a fourth D flip-flop; the first input end of the second D flip-flop is used to access the initial frequency division signal, the second input end is used to access the high-frequency clock, the output end is used to output the first phase clock and is connected to the first input end of the third D flip-flop; the second input end of the third D flip-flop is used to access the high-frequency clock, the output end is used to output the second phase clock and is connected to the first input end of the fourth D flip-flop; the second input end of the fourth D flip-flop is used to access the high-frequency clock, and the output end is used to output the third phase clock.

[0018] Optionally, the Δ-Σ modulator includes a first adder, a second adder, a third adder, a signal shaper and a fifth D flip-flop; the first input end of the first adder is used to access the static fractional signal, the second input end is connected to the output end of the fifth D flip-flop, and the output end is respectively connected to the first input end of the second adder and the input end of the signal shaper; the second input end of the second adder is respectively connected to the output end of the signal shaper and the first input end of the third adder, the output end is used to output the digital phase control word and connected to the first input end of the fifth D flip-flop; the second input end of the fifth flip-flop is used to access the output clock; the second input end of the third adder is used to access the integer division ratio N, and the output end is used to output the dynamic division ratio.

[0019] In the above-mentioned fractional frequency divider of the present application, the Δ-Σ modulator can modulate the static fractional signal Frac into a high-speed dynamic code stream Y, determine the dynamic frequency division ratio, send the dynamic frequency division ratio to the multi-mode frequency divider, and calculate the quantization error between the code stream Y and the static fractional signal in each output clock cycle, accumulate the quantization error to generate a digital phase control word, and send the digital phase control word to the digital phase interpolation unit. The multi-mode frequency divider can dynamically divide the high-frequency clock according to the dynamic frequency division ratio, and send the initial frequency division signal obtained by the dynamic frequency division to the phase generator. The phase generator can be based on the high-frequency clock and the initial frequency division signal. The digital phase interpolation unit generates a first phase clock, a second phase clock and a third phase clock. The digital phase interpolation unit can linearly interpolate between the rising edges of the first phase clock and the second phase clock according to the digital phase control word to control the rising edge position of the output clock, and adjust the duty cycle of the output clock according to the third phase clock, so as to output the target clock signal. The digital phase interpolation unit solves the problems of large area, timing crosstalk, and limited maximum output frequency of the differential architecture through single-ended phase interpolation design, and can achieve optimization in terms of area, speed, power consumption, etc., which is particularly suitable for high-frequency, low-jitter clock generation scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 1 is a schematic structural diagram of a fractional frequency divider according to an embodiment of the present application;

[0022] Figure 2 is a schematic structural diagram of a fractional frequency divider according to another embodiment of the present application;

[0023] Figure 3 is a schematic structural diagram of a fractional frequency divider according to another embodiment of the present application;

[0024] Figure 4 This is a structural diagram of the DPI subunit 131 according to an embodiment of the present application;

[0025] Figure 5 1 is a schematic diagram of relevant signal waveforms according to an embodiment of the present application;

[0026] Figure 6 1 is a schematic diagram of the reset latch structure of an embodiment of the present application;

[0027] Figure 7 1 is a schematic diagram of the structure of a duty cycle adjustment latch according to an embodiment of the present application;

[0028] Figure 8 Schematic diagram of the structure of a delta-sigma modulator according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0030] The first aspect of the present application provides a fractional frequency divider. Figure 1 As shown, the fractional frequency divider includes a multi-mode frequency divider 110 , a phase generator 120 , a digital phase interpolation unit 130 and a delta-sigma modulator (DSM) 140 .

[0031] The multi-mode frequency divider 110 has a first terminal connected to a high-frequency clock CK_VCO, a second terminal connected to a first terminal of the phase generator 120, and a third terminal connected to a first terminal of the delta-sigma modulator 140. The high-frequency clock CK_VCO may include a clock signal output by a preceding circuit, such as a VCO (voltage-controlled oscillator). The phase generator 120 has a second terminal connected to the high-frequency clock CK_VCO, a third terminal connected to a first terminal of the digital phase interpolation unit 130, and a fourth terminal connected to a second terminal of the digital phase interpolation unit 130. The delta-sigma modulator 140 has a second terminal connected to a static fractional signal Frac, a third terminal connected to a third terminal of the digital phase interpolation unit 130, and a fourth terminal connected to a fourth terminal of the digital phase interpolation unit 130.

[0032] The Δ-Σ modulator 140 is used to modulate the static fractional signal Frac into a high-speed dynamic code stream Y, determine a dynamic frequency division ratio DIV based on the code stream Y, send the dynamic frequency division ratio DIV to the multi-mode divider 110, and calculate the quantization error between the code stream Y and the static fractional signal Frac in each output clock cycle, accumulate the quantization error to generate a digital phase control word Phi_Dig, and send the digital phase control word Phi_Dig to the digital phase interpolation unit 130. The code stream Y takes the value of 0 or 1, and the average value of Y is the static fractional signal Frac. In each cycle of the output clock CKO, there is a quantization error between the code stream Y and Frac. This quantization error causes a phase error between the rising edge of the output clock CKO and the rising edge of the target clock. The digital control signal corresponding to this phase error is the digital phase control word Phi_Dig, and the digital phase control word Phi_Dig can be used to compensate for the phase interpolation error. The above-mentioned code stream Y can be used to determine the division ratio DIV of the multi-mode divider 110. Specifically, DIV=N+Y. When Y=0, the division ratio DIV of the multi-mode divider 110 is N. When Y=1, the division ratio DIV of the multi-mode divider 110 is N+1, where N is the integer part of the division parameter (or division ratio) of the entire fractional divider (also called the integer division ratio).

[0033] The multi-modulus divider (MMD) 110 is configured to dynamically divide the high-frequency clock CK_VCO according to the dynamic division ratio DIV and transmit the resulting initial division signal CKO_MMD to the phase generator 120. The dynamic division ratio DIV switches between N and N+1; specifically, DIV=N+Y. When Y=0, the division ratio DIV is N, and when Y=1, the division ratio DIV is N+1.

[0034] The phase generator 120 is used to generate a first phase clock PHIA, a second phase clock PHIB and a third phase clock PHIC based on the high-frequency clock CK_VCO and the initial frequency division signal CKO_MMD; the rising edge interval of the first phase clock PHIA and the second phase clock PHIB is a clock period Tvco of the high-frequency clock CK_VCO, and the third phase clock PHIC is used to adjust the duty cycle of the output clock CKO.

[0035] The digital phase interpolation unit (DPI) 130 is used to linearly interpolate between the rising edges of the first phase clock PHIA and the second phase clock PHIB according to the digital phase control word Phi_Dig to control the rising edge position of the output clock CKO, and adjust the duty cycle of the output clock CKO according to the third phase clock PHIC.

[0036] In the above-mentioned fractional frequency divider, the Δ-Σ modulator 140 can modulate the static fractional signal Frac into a high-speed dynamic code stream Y, determine the dynamic frequency division ratio DIV, send the dynamic frequency division ratio DIV to the multi-mode frequency divider 110, and calculate the quantization error between the code stream Y and the static fractional signal Frac in each output clock cycle, accumulate the quantization error to generate a digital phase control word Phi_Dig, and send the digital phase control word Phi_Dig to the digital phase interpolation unit 130. The multi-mode frequency divider 110 can dynamically divide the high-frequency clock CK_VCO according to the dynamic frequency division ratio DIV, and send the initial frequency division signal CKO_MMD obtained by the dynamic frequency division to the phase generator 120. The phase generator 120 can be based on the high-frequency clock CK_VC O and the initial frequency division signal CKO_MMD generate the first phase clock PHIA, the second phase clock PHIB and the third phase clock PHIC. The digital phase interpolation unit 130 can linearly interpolate between the rising edges of the first phase clock PHIA and the second phase clock PHIB according to the digital phase control word Phi_Dig to control the rising edge position of the output clock CKO, and adjust the duty cycle of the output clock CKO according to the third phase clock PHIC, so as to output an accurate clock signal; wherein the digital phase interpolation unit solves the problems of large area, timing crosstalk, and limited maximum output frequency of the differential architecture through single-ended phase interpolation design, and can achieve optimization in terms of area, speed, power consumption, etc., and is particularly suitable for high-frequency, low-jitter clock generation scenarios.

[0037] In some embodiments, reference Figures 2 to 4 As shown, the digital phase interpolation unit 130 includes a capacitor C, a first switch S1, a reset latch 132, a duty cycle adjustment latch 133, a decoder and k DPI subunits 131; wherein the k DPI subunits 131 have the same structure, and k is a positive integer.

[0038] The input terminal of the decoder serves as the third terminal of the digital phase interpolation unit 130, for receiving the digital phase control word Phi_Dig. The output terminal is connected to the first control terminal of each of the DPI subunits 131 to output the digital phase control word Phi_Dig to the first control terminal of each DPI subunit 131. The first input terminal of each of the DPI subunits 131 serves as the first terminal of the digital phase interpolation unit 130, for receiving the first phase clock PHIA. The second input terminal serves as the second terminal of the digital phase interpolation unit 130, for receiving the second phase clock PHIB. The second control terminal is connected to the first terminal of the reset latch 132. The output terminal is respectively connected to the first terminal of the capacitor C, the first terminal of the first switch S1, the second terminal of the reset latch 132, and the first terminal of the duty cycle adjustment latch 133. The third terminal of the reset latch 132 is connected to the second terminal of the first switch S1 (i.e., the switch blade control terminal), and the fourth terminal is used to receive the control signal dly_sel corresponding to the integer division ratio N. The second terminal of the duty cycle adjustment latch 133 is used to receive the third phase clock PHIC, and the third terminal is used to output the output clock CKO. The third terminal of the duty cycle adjustment latch 133 can also be connected to the fourth terminal of the delta-sigma modulator 140 to output the corresponding output clock CKO to the delta-sigma modulator 140. The second terminal of the capacitor C is respectively connected to the third terminal of the first switch S1 and the ground terminal.

[0039] The decoder is used to decode the digital phase control word Phi_Dig and output a phase selection signal dpi_sel representing the digital phase control word Phi_Dig. The phase selection signal dpi_sel includes a selection signal corresponding to each DPI subunit 131, which can be used to control the corresponding DPI subunit 131 to access the first phase clock PHIA or the second phase clock PHIB.

[0040] Each of the DPI subunits 131 is configured to access a corresponding phase clock (such as the first phase clock PHIA or the second phase clock PHIB) according to a corresponding phase selection signal dpi_sel, and output a corresponding current to the capacitor C according to the interpolation enable signal sw_en output by the reset latch 132. Specifically, for a DPI subunit 131, when the phase selection signal dpi_sel = 0, the DPI subunit 131 accesses the first phase clock PHIA, and when the phase selection signal dpi_sel = 1, the DPI subunit 131 can access the second phase clock PHIB.

[0041] The capacitor C is used to store energy according to the current input by each DPI sub-unit 131 to adjust the phase interpolation positive pulse PPUL. The phase interpolation positive pulse PPUL is a phase interpolation signal generated by the DPI sub-unit 131 charging and discharging the capacitor C using the corresponding current value according to the value of the phase selection signal dpi_sel.

[0042] The reset latch 132 is used to control the first end of the first switch S1 to connect or disconnect its third end according to the phase interpolation positive pulse PPUL to charge and discharge the capacitor C, reset the phase interpolation positive pulse PPUL to 0, and at the same time, the switch control signal RST is also reset to 0, so that the capacitor C waits for the next cycle of charging. Specifically, the reset latch 132 can output a switch control signal RST to the first switch S1. When the phase interpolation positive pulse PPUL is less than the preset voltage threshold PPUL_VTH, the switch control signal RST is at a low level, and the first end of the first switch S1 disconnects its third end. When the phase interpolation positive pulse PPUL is greater than or equal to the preset voltage threshold PPUL_VTH, the switch control signal RST is at a high level, and the first end of the first switch S1 connects its third end, quickly discharging the capacitor C. The phase interpolation positive pulse PPUL is the ground voltage. After the second time t2, the reset latch 132 can be triggered again to reset the switch control signal RST to 0. At the same time, after a certain time (such as the third time t3), the reset latch 132 resets the interpolation enable signal sw_en to 0; wherein the interpolation enable signal sw_en can be used to control whether the DPI subunit 131 outputs current.

[0043] The duty cycle adjustment latch 133 is used to adjust the duty cycle of the phase interpolation positive pulse PPUL to output the corresponding output clock CKO.

[0044] Specifically, the following describes a process in which the capacitor C, the first switch S1, the reset latch 132, the duty cycle adjustment latch 133, the decoder, and the k DPI sub-units 131 cooperate with each other. The DPI sub-unit 131 charges the capacitor C using a corresponding current value after the input phase clock is the first phase clock PHIA or the second phase clock PHIB according to the value of the phase selection signal dpi_sel. When the voltage of the capacitor C rises to a preset voltage threshold PPUL_VTH, the reset latch 132 is triggered to pull high the switch control signal RST. After the switch control signal RST is pulled high, the first end of the first switch S1 is connected to its third end, rapidly discharging the capacitor C. After the capacitor C is discharged, the reset latch 132 is triggered again to reset the switch control signal RST to 0. At the same time, after a certain time (such as the third time t3), the reset latch 132 resets the interpolation enable signal sw_en to 0.

[0045] In some examples, the DPI subunit 131 includes a two-way gate E1 , a first NAND gate L1 , and a current providing component 1311 .

[0046] The first input terminal of the two-way selector E1 serves as the first input terminal of the DPI subunit 131, for receiving the first phase clock PHIA. The second input terminal serves as the second input terminal of the DPI subunit 131, for receiving the second phase clock PHIB. The control terminal serves as the first control terminal of the DPI subunit 131, for receiving the corresponding phase selection signal dpi_sel. The output terminal is connected to the first input terminal of the first NAND gate L1. The second input terminal of the first NAND gate L1 serves as the second control terminal of the DPI subunit 131, for connecting to the first terminal of the reset latch 132. The output terminal is connected to the first terminal of the current supply component 1311. The second terminal of the current supply component 1311 serves as the output terminal of the DPI subunit 131, and is respectively connected to the first terminal of the capacitor C, the first terminal of the first switch S1, the second terminal of the reset latch 132, and the first terminal of the duty cycle adjustment latch 133.

[0047] The two-way selector E1 is used to turn on the first phase clock PHIA or the second phase clock PHIA according to the phase selection signal dpi_sel; specifically, when the phase selection signal dpi_sel=0, the two-way selector E1 turns on the first phase clock PHIA, and when the phase selection signal dpi_sel=1, the two-way selector E1 of the DPI subunit 131 turns on the second phase clock PHIB.

[0048] The first NAND gate L1 is used to input an on-off control signal to the current providing component 1311 of the corresponding DPI sub-unit 131 according to the interpolation enable signal sw_en and the phase clock turned on by the two-way selector E1, so as to turn on or off the corresponding current providing component 1311; for example, when the on-off control signal indicates that the current providing component 1311 is turned on, the corresponding current providing component 1311 outputs current to the capacitor C, and when the on-off control signal indicates that the current providing component 1311 is turned off, the corresponding current providing component 1311 stops outputting current to the capacitor C, thereby controlling the current output from each DPI sub-unit 131 to the capacitor C.

[0049] The current providing component 1311 is used to output current to the capacitor C according to the on-off control signal output by the first NAND gate L1; optionally, in each DPI sub-unit 131, when the on-off control signal is 1 (corresponding to a high level), it indicates that the current providing component 1311 is turned on, and the corresponding current providing component 1311 outputs current to the capacitor C; when the on-off control signal is 0 (corresponding to a low level), it indicates that the current providing component 1311 is turned off, and the corresponding current providing component 1311 stops outputting current to the capacitor C.

[0050] Specifically, the current supply component 1311 includes a second switch S2, a first inverter N1, a third switch S3, and a current source I1. The output end of the first NAND gate L1 is connected to the first end of the second switch S2 and the input end of the first inverter N1. The first end of the second switch S2 (e.g., a knife control end or a control enable end) serves as the first end of the current supply component 1311 and is connected to the output end of the first NAND gate L1. The second end is connected to the output end of the current source I1 and the first end of the third switch S3. The third end is grounded. The input end of the first inverter N1 is connected to the output end of the first NAND gate L1, and the output end is connected to the second end of the third switch S3 (e.g., a knife control end or a control enable end). The third end of the third switch S3 serves as the second end of the current supply component 1311 and is connected to the first end of the capacitor C, the first end of the first switch S1, the second end of the reset latch 132, and the first end of the duty cycle adjustment latch 133.

[0051] When the first NAND gate L1 outputs a high level, the second end of the second switch S2 is connected to the third end thereof, the first end of the third switch S3 is disconnected from the third end thereof, and the current source I1 does not output current to the capacitor C. When the first NAND gate L1 outputs a low level, the second end of the second switch S2 is disconnected from the third end thereof, the first end of the third switch S3 is connected to the third end thereof, and the current source I1 outputs current to the capacitor C.

[0052] In some examples, such as Figure 3 As shown, the reset latch 132 can also be connected to the first phase clock PHIA to control at least part of the current providing component 1311 to output current to the capacitor C starting from the rising edge of the first phase clock PHIA. Figure 5 As shown, Figure 5In the figure, PHIA represents the first phase clock, PHIB represents the second phase clock, PHIC represents the third phase clock, PPUL represents the phase interpolation positive pulse PPUL, PPUL_VTH represents the voltage threshold, RST represents the switch control signal, sw_en represents the interpolation enable signal, and CKO represents the output clock. Reset latch 132 is used to control the output current of a preset number of current supply components 1311 at the rising edge of the first phase clock PHIA. After a clock cycle Tvco of the high-frequency clock CK_VCO, i.e., after the rising edge of the second phase clock PHIB, all current supply components 1311 are controlled to output current. When the phase interpolation positive pulse PPUL is greater than or equal to the preset voltage threshold PPUL_VTH and the interpolation time tpi is reached, the switch control signal RST is pulled high, and the phase interpolation positive pulse PPUL becomes high after the first time t1, and the phase interpolation positive pulse PPUL is pulled low; after the switch control signal RST is pulled high, the first end of the first switch S1 is connected to its third end, and the capacitor C is quickly discharged. The high level of the switch control signal RST lasts for the second time t2, and the capacitor C is discharged. The switch control signal RST becomes low to accurately charge the capacitor C in the next clock cycle of the output clock CKO; when the phase interpolation positive pulse PPUL is equal to the preset voltage After a third time t3 after the threshold PPUL_VTH is reached, the interpolation enable signal sw_en is set to a low level to shut down the current supply component 1311, causing the current supply component 1311 to stop supplying current to the capacitor C. After a fourth time t4 starting from the falling edge of the first phase clock PHIA, the interpolation enable signal sw_en is set to a high level to re-enable the current supply component 1311 and prepare for the clock cycle adjustment of the next output clock CKO. In this way, in each clock cycle, characteristics such as the rising edge of the output clock CKO are controlled by parameters such as the first phase clock PHIA, the second phase clock PHIB, and the digital phase control word Phi_Dig. Optionally, the interpolation time tpi can be proportional to the digital phase control word Phi_Dig, and the relationship between the two can be: tpi = Vth / (Itotal / C) + Phi_Dig*Tvco, where Vth / (Itotal / C) is a constant determined based on the configuration characteristics of the fractional divider.

[0053] Optionally, the current providing component 1311 may include 256 current sources I1, the circuit size of each current source output is Iunit, and the formula for determining the preset number includes 256-phi_dig[7:0], where phi_dig[7:0] represents the number of DPI subunits 131 connected to the second phase clock PHIB; Figure 5As shown, between the rising edge of the first phase clock PHIA and the rising edge of the second phase clock PHIB, the first phase clock PHIA is at a high level and the second phase clock PHIB is at a low level. At this time, only the DPI subunit 131 connected to the first phase clock PHIA outputs current to the capacitor C. Therefore, the current output by the preset number of current providing components 1311 during this period is as follows: IA = (256-phi_dig[7:0]) * Iunit. After the rising edge of the second phase clock PHIB, the first phase clock PHIA and the second phase clock PHIB are both at a high level. At this time, all DPI subunits 131 output current to the capacitor C, and the current is 256 * Iunit.

[0054] In some examples, reference Figure 6 As shown, the reset latch 132 includes a second inverter N2, a second NAND gate L2, a third NAND gate L3, a third inverter N3, a fourth NAND gate L4, a fifth NAND gate L5, a fourth inverter N4 and a first buffer B1.

[0055] The input of the second inverter N2 serves as the second terminal of the reset latch 132, receiving the phase interpolation positive pulse PPUL. Its output is connected to the first input of the second NAND gate L2 and the first input of the fourth NAND gate L4. The second input of the second NAND gate L2 is connected to the output of the third NAND gate L3, and its output is connected to the input of the third inverter N3 and the first input of the third NAND gate L3. The output of the third inverter N3 serves as the first terminal of the reset latch 132, outputting the interpolation enable signal. The second input of the third NAND gate L3 receives the first phase clock PHIA. The second input of the fourth NAND gate L4 is connected to the output of the fifth NAND gate L5, and its output serves as the third terminal of the reset latch 132, outputting the switch control signal RST corresponding to the first switch S1. The output is connected to the first input of the fifth NAND gate L5 and the input of the fourth inverter N4. The second input of the fifth NAND gate L5 is connected to the first terminal (e.g., the output) of the first buffer B1. The second terminal (e.g., input terminal) of the first buffer B1 is connected to the output terminal of the fourth inverter N4, and the third terminal (e.g., control terminal) serves as the fourth terminal of the reset latch 132, which is used to receive the control signal dly_sel corresponding to the integer division ratio N. The control signal dly_sel is a signal obtained after decoding the integer division ratio N and can be used to represent the integer division ratio N.

[0056] The components in the reset latch 132 assist each other and can be used to independently determine time parameters such as the first time t1, the second time t2, the third time t3, and the fourth time t4, so that the determination processes of the first time t1, the second time t2, the third time t3, and the fourth time t4 do not interfere with each other, thereby improving the reliability of the working process of the reset latch 132. Specifically, Figure 6 As shown, the second inverter N2 and the fourth NAND gate L4 are used to determine the first time t1; the fourth inverter N4, the first buffer B1, the second inverter N2 and the fourth NAND gate L4 are used to determine the second time t2; the second inverter N2, the second NAND gate L2 and the third inverter N3 are used to determine the third time t3; the third NAND gate L3, the second NAND gate L2 and the third inverter N3 are used to determine the third time t3.

[0057] In some examples, reference Figure 7 As shown, the duty cycle adjustment latch 133 includes a first D flip-flop D1 and a pulse generator PulseGen. The first input terminal D of the first D flip-flop D1 is used to receive a preset voltage. The second input terminal clk is the first terminal of the duty cycle adjustment latch 133 and is used to receive the phase interpolation positive pulse PPUL. The reset terminal rb is connected to the output terminal of the pulse generator PulseGen. The input terminal of the pulse generator is used to receive the third phase clock PHIC.

[0058] The pulse generator PulseGen is configured to generate a reset pulse according to the third phase clock PHIC.

[0059] The first D flip-flop D1 is used to adjust the duty cycle of the phase interpolation positive pulse PPUL according to the clear pulse so that the duty cycle of the output clock CKO can be maintained at a proportional value of 50%.

[0060] In some embodiments, as Figure 2 As shown, the phase generator 120 includes a second D flip-flop D2, a third D flip-flop D3 and a fourth D flip-flop D4.

[0061] The first input of the second D flip-flop D2 serves as the first terminal of the phase generator 120 for receiving the initial frequency-divided signal CKO_MMD. The second input serves as the second terminal of the phase generator 120 for receiving the high-frequency clock CK_VCO. The output of the second D flip-flop D2 is configured to output the first phase clock PHIA and is connected to the first input of the third D flip-flop D3. The second input of the third D flip-flop D3 is configured to receive the high-frequency clock CK_VCO and is configured to output the second phase clock PHIB and is connected to the first input of the fourth D flip-flop D4. The second input of the fourth D flip-flop D4 is configured to receive the high-frequency clock CK_VCO and is configured to output the third phase clock PHIC. The rising edge of the second phase clock PHIA is delayed relative to the rising edge of the first phase clock PHIB by one clock period Tvco of the high-frequency clock CK_VCO. The rising edge of the third phase clock PHIC is delayed relative to the rising edge of the second phase clock PHIB by one clock period Tvco of the high-frequency clock CK_VCO.

[0062] In some embodiments, as Figure 2 and Figure 8 As shown, the delta-sigma modulator 140 includes a first adder A1, a second adder A2, a third adder A3, a signal shaper T1, and a fifth D flip-flop D5.

[0063] The first input of the first adder A1 serves as the second terminal of the delta-sigma modulator 140 for receiving the static fractional signal Frac. Its second input is connected to the output of the fifth D-type flip-flop D5. Its output is connected to the first input of the second adder A2 and the input of the signal shaper T1. The second input of the second adder A2 is connected to the output of the signal shaper T1 and the first input of the third adder A3. Its output serves as the third terminal of the delta-sigma modulator 140 for outputting the digital phase control word Phi_Dig and is connected to the first input of the fifth D-type flip-flop D5. The second input of the fifth flip-flop D5 receives the output clock CKO. The second input of the third adder A3 receives an integer division ratio N, and its output outputs the dynamic division ratio DIV.

[0064] The fifth D flip-flop D5 is used to delay the output clock CKO by a clock period Tvco of the high-frequency clock CK_VCO.

[0065] The first adder A1 is used to perform a wig operation on the delayed output clock CKO and the static fractional signal Frac.

[0066] The signal shaper T1 is used to round the addition result output by the first adder A1, that is, to obtain the integer part of the addition result output by the first adder A1 to obtain the code stream Y.

[0067] The second adder A2 is used to perform an addition operation on the addition result output by the first adder A1 and the inverse of the rounded result output by the signal shaper T1 (ie, the code stream Y).

[0068] The third adder A3 is used for performing an addition operation on the integer frequency division ratio N and the rounded result output by the signal shaper T1 to output the dynamic frequency division ratio DIV.

[0069] In the delta-sigma modulator 140, the first adder A1, the second adder A2, the third adder A3, the signal shaper T1, and the fifth D-flip-flop D5, among other components, work together to determine the dynamic division ratio DIV. Within each output clock cycle, they calculate the quantization error between the bit stream Y and the static fractional signal Frac, and accumulate the quantization error to generate the digital phase control word Phi_Dig.

[0070] In the above fractional frequency divider, the Δ-Σ modulator 140 can modulate the static fractional signal Frac into a high-speed dynamic code stream Y, determine the dynamic frequency division ratio DIV, send the dynamic frequency division ratio DIV to the multi-mode frequency divider 110, and calculate the quantization error between the code stream Y and the static fractional signal Frac in each output clock cycle, accumulate the quantization error to generate a digital phase control word Phi_Dig, and send the digital phase control word Phi_Dig to the digital phase interpolation unit 130. The multi-mode frequency divider 110 can dynamically divide the high-frequency clock CK_VCO according to the dynamic frequency division ratio DIV, and send the initial frequency division signal CKO_MMD obtained by dynamic frequency division to the phase generator 120. The phase generator 120 can be based on the high-frequency clock CK_VC O and the initial frequency division signal CKO_MMD generate the first phase clock PHIA, the second phase clock PHIB and the third phase clock PHIC. The digital phase interpolation unit 130 can linearly interpolate between the rising edges of the first phase clock PHIA and the second phase clock PHIB according to the digital phase control word Phi_Dig to control the rising edge position of the output clock CKO, and adjust the duty cycle of the output clock CKO according to the third phase clock PHIC, so as to output an accurate clock signal; wherein the digital phase interpolation unit solves the problems of large area, timing crosstalk, and limited maximum output frequency of the differential architecture through single-ended phase interpolation design, and can achieve optimization in terms of area, speed, power consumption, etc., and is particularly suitable for high-frequency, low-jitter clock generation scenarios.

[0071] A second aspect of the present application provides an electronic device, comprising the fractional frequency divider described in any one of the above embodiments.

[0072] Optionally, the electronic device includes a clock generator and / or a communication device, etc., which require a fractional frequency divider.

[0073] The electronic device includes the fractional frequency divider described in any of the above embodiments, and has all the beneficial effects of the fractional frequency divider described in any of the above embodiments, which will not be described in detail here.

[0074] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementation of this specification shown herein.

[0075] That is, the above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the various embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0076] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals to identify them. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0077] In this application, the word "exemplary" is used to mean "serving as an example, illustration or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as being more preferred or more advantageous than other embodiments. The above description is provided to enable any person skilled in the art to implement and use the present application. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

Claims

1. A fractional frequency divider, characterized in that: The fractional frequency divider includes a multi-mode frequency divider, a phase generator, a digital phase interpolation unit and a delta-sigma modulator; The delta-sigma modulator is used to modulate a static fractional signal into a high-speed dynamic code stream Y, determine a dynamic frequency division ratio based on the code stream Y, send the dynamic frequency division ratio to the multi-mode frequency divider, and calculate a quantization error between the code stream Y and the static fractional signal in each output clock cycle, accumulate the quantization errors to generate a digital phase control word, and send the digital phase control word to the digital phase interpolation unit; the average value of the code stream Y is the static fractional signal; The digital phase control word is used to compensate for phase interpolation error; The multi-mode frequency divider is used to dynamically divide the high-frequency clock according to the dynamic frequency division ratio, and send the initial frequency division signal obtained by the dynamic frequency division to the phase generator; The phase generator is used to generate a first phase clock, a second phase clock and a third phase clock based on the high frequency clock and the initial frequency division signal; the rising edge interval of the first phase clock and the second phase clock is one clock cycle of the high frequency clock; The digital phase interpolation unit is used to linearly interpolate between the rising edges of the first phase clock and the second phase clock according to the digital phase control word to control the rising edge position of the output clock, and adjust the duty cycle of the output clock according to the third phase clock.

2. The fractional frequency divider according to claim 1, wherein: The digital phase interpolation unit includes a capacitor, a first switch, a reset latch, a duty cycle adjustment latch, a decoder and k DPI subunits; The input end of the decoder is used to access the digital phase control word, and the output end is connected to the first control end of each of the DPI subunits; the first input end of each of the DPI subunits is used to access the first phase clock, the second input end is used to access the second phase clock, the second control end is connected to the first end of the reset latch, and the output end is respectively connected to the first end of the capacitor, the first end of the first switch, the second end of the reset latch and the first end of the duty cycle adjustment latch; the third end of the reset latch is connected to the second end of the first switch, and the fourth end is used to access the control signal corresponding to the integer division ratio N; the second end of the duty cycle adjustment latch is used to access the third phase clock, and the third end is used to output the output clock; the second end of the capacitor is respectively connected to the third end of the first switch and the ground end; The decoder is used to decode the digital phase control word and output a phase selection signal representing the digital phase control word; Each of the DPI subunits is configured to access a corresponding phase clock according to the phase selection signal, and output a corresponding current to the capacitor according to an interpolation enable signal output by the reset latch; The capacitor is used to store energy according to the current input by each of the DPI subunits to adjust the input phase interpolation positive pulse, and the phase interpolation positive pulse is a phase interpolation signal generated by the DPI subunit charging and discharging the capacitor using a corresponding current value according to the value of the phase selection signal; The reset latch is used to control the first end of the first switch to connect or disconnect the third end thereof according to the phase interpolation positive pulse, so as to charge and discharge the capacitor, reset the phase interpolation positive pulse to 0, and at the same time reset the switch control signal to 0, so that the capacitor waits for the next cycle of charging; The duty cycle adjustment latch is used to adjust the duty cycle of the phase interpolation positive pulse to output the output clock.

3. The fractional frequency divider according to claim 2, wherein: The DPI subunit includes a two-way gate, a first NAND gate and a current providing component; The first input terminal of the two-way selector is used to receive the first phase clock, the second input terminal is used to receive the second phase clock, the control terminal is used to receive the phase selection signal, and the output terminal is connected to the first input terminal of the first NAND gate; the second input terminal of the first NAND gate is connected to the first terminal of the reset latch, and the output terminal is connected to the first terminal of the current supply component; the second terminal of the current supply component is respectively connected to the first terminal of the capacitor, the first terminal of the first switch, the second terminal of the reset latch, and the first terminal of the duty cycle adjustment latch; The two-way gate is used to switch on the first phase clock or the second phase clock according to the phase selection signal; The first NAND gate is used to input an on-off control signal to the current providing component of the corresponding DPI subunit according to the interpolation enable signal; The current providing component is used to output current to the capacitor according to the on-off control signal output by the first NAND gate.

4. The fractional frequency divider according to claim 3, wherein: The current providing component includes a second switch, a first inverter, a third switch and a current source; The first end of the second switch serves as the first end of the current providing component, the second end is respectively connected to the output end of the current source and the first end of the third switch, and the third end is grounded; the input end of the first inverter is connected to the output end of the first NAND gate, and the output end is connected to the second end of the third switch; the third end of the third switch serves as the second end of the current providing component.

5. The fractional frequency divider according to claim 2, wherein: The reset latch is further configured to access the first phase clock and control the output current of at least part of the current providing component starting from the rising edge of the first phase clock.

6. The fractional frequency divider according to claim 5, wherein: The reset latch is also used to control the output current of a preset number of current providing components at the rising edge of the first phase clock; control the output current of all current providing components after a clock cycle of the high-frequency clock; adjust the level characteristics of the switch control signal when the voltage signal is greater than or equal to a preset voltage threshold, and make the switch control signal become a high level after a first time after the phase interpolation positive pulse is equal to the voltage threshold, and adjust the switch control signal to a low level after the high level of the switch control signal lasts for a second time; set the interpolation enable signal to a low level after a third time after the phase interpolation positive pulse is equal to the voltage threshold; and set the interpolation enable signal to a high level after a fourth time starting from the falling edge of the first phase clock.

7. The fractional frequency divider according to claim 6, wherein: The reset latch includes a second inverter, a second NAND gate, a third NAND gate, a third inverter, a fourth NAND gate, a fifth NAND gate, a fourth inverter and a first buffer; The input end of the second inverter is used to receive the phase interpolation positive pulse, and the output end is respectively connected to the first input end of the second NAND gate and the first input end of the fourth NAND gate; the second input end of the second NAND gate is connected to the output end of the third NAND gate, and the output end is respectively connected to the input end of the third inverter and the first input end of the third NAND gate; the output end of the third inverter is used to output the interpolation enable signal; the second input end of the third NAND gate is used to receive the first phase clock; the second input end of the fourth NAND gate is connected to the output end of the fifth NAND gate, and the output end is used to output the switch control signal corresponding to the first switch, and is respectively connected to the first input end of the fifth NAND gate and the input end of the fourth inverter; the second input end of the fifth NAND gate is connected to the first end of the first buffer; the second end of the first buffer is connected to the output end of the fourth inverter, and the third end is used to receive the control signal corresponding to the integer division ratio N.

8. The fractional frequency divider according to claim 2, wherein: The duty cycle adjustment latch includes a first D flip-flop and a pulse generator; The first input terminal of the first D flip-flop is used to receive a preset voltage, the second input terminal is used to receive the phase interpolation positive pulse, and the reset terminal is connected to the output terminal of the pulse generator; the input terminal of the pulse generator is used to receive the third phase clock; The pulse generator is used to generate a reset pulse according to the third phase clock; The first D flip-flop is used to adjust the duty cycle of the phase interpolation positive pulse according to the clear pulse.

9. The fractional frequency divider according to claim 1, wherein: The phase generator includes a second D flip-flop, a third D flip-flop and a fourth D flip-flop; The first input terminal of the second D flip-flop is used to receive the initial frequency-divided signal, the second input terminal is used to receive the high-frequency clock, the output terminal is used to output the first phase clock, and is connected to the first input terminal of the third D flip-flop; the second input terminal of the third D flip-flop is used to receive the high-frequency clock, the output terminal is used to output the second phase clock, and is connected to the first input terminal of the fourth D flip-flop; the second input terminal of the fourth D flip-flop is used to receive the high-frequency clock, and the output terminal is used to output the third phase clock.

10. The fractional frequency divider according to claim 1, wherein: The delta-sigma modulator includes a first adder, a second adder, a third adder, a signal shaper and a fifth D flip-flop; The first input terminal of the first adder is used to receive the static fractional signal, the second input terminal is connected to the output terminal of the fifth D flip-flop, and the output terminal is respectively connected to the first input terminal of the second adder and the input terminal of the signal shaper; the second input terminal of the second adder is respectively connected to the output terminal of the signal shaper and the first input terminal of the third adder, the output terminal is used to output the digital phase control word and is connected to the first input terminal of the fifth D flip-flop; the second input terminal of the fifth flip-flop is used to receive the output clock; the second input terminal of the third adder is used to receive the integer division ratio N, and the output terminal is used to output the dynamic division ratio.

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