All-digital phase-locked loop architecture based on random phase modulation and demodulation

Abstract

The invention discloses an all-digital phase-locked loop architecture based on random phase modulation and demodulation, and belongs to the technical field of integrated circuits. According to the invention, the periodicity of the phase shifter control signal and the nonlinearity of the phase shifter are decoupled by using the phase modulation and demodulation technology, and fractional spurious is suppressed below the noise floor without correction. In addition, phase alignment is ensured by means of cooperation of the high-speed phase shifter and the low-speed phase shifter, so that ideal phase information can be successfully recovered through phase demodulation. According to the invention, the design complexity and cost of the system are reduced to a great extent, so that the system has unique advantages in multi-band multi-protocol communication application and high-performance radar application.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to a fully digital phase-locked loop architecture based on random phase modulation and demodulation technology, and in particular to a fully digital phase-locked loop architecture capable of achieving extremely low fractional spurious emissions. Background Art

[0002] Fractional-frequency all-digital phase-locked loops (FPLLs) are widely used in modern wireless communications and radar systems. In a FPLL architecture based on a frequency divider, a digital-to-time converter (DTC) circuit is used to eliminate phase errors introduced by integer-division ratios. However, due to the nonideal nature of the DTC circuit, its nonlinearity becomes a major source of fractional spurious signals.

[0003] like Figure 1 As shown, to compensate for the phase residual caused by integer division ratios, the control word of the digital-to-time converter circuit is equal to the integral of the frequency residual between the fractional and integer division ratios, exhibiting strong periodicity. However, the nonlinearity of the digital-to-time converter circuit results in different quantization errors under different control words. Under the modulation of a periodic control word, the quantization error caused by the nonlinearity also exhibits a periodic variation trend, equivalent to the product of the digital-to-time converter circuit's control word and the nonlinearity in the time domain. In the frequency domain, it manifests as the convolution of the control word spectrum and the nonlinearity spectrum.

[0004] Q err =CW(t)·NL(t)

[0005]

[0006] The periodicity of the quantization error passes through the phase comparator and loop filter, ultimately manifesting itself in the oscillator circuit's control word, causing fractional spurious signals. At extremely low division ratios, these spurious signals fall within the fully digital phase-locked loop's filter bandwidth, rendering the loop filter unable to filter and suppress them.

[0007] Fractional spurs in fully digital phase-locked loops (PLLs) can cause multiple system problems. For radar systems, after mixing fractional spurs of the same frequency through the receiver front end, the resulting mixing degrades the overall phase noise and raises the noise floor. Furthermore, mixing between different fractional spurs can lead to ghost signals, affecting system judgment. For communications systems, fractional spurs in the local oscillator signal are up-converted into the transmitter output signal through the mixer, creating high-energy spurious signals in adjacent channels, preventing the overall system from meeting protocol spectrum specifications. Furthermore, the degradation of signal phase noise by fractional spurs can also degrade the overall system's error vector magnitude (EVM) performance.

[0008] Many efforts are currently underway to reduce fractional spurious signals. Salvi et al., in their paper "A66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC" published at the 2024 CICC, proposed a digital-to-time converter circuit based on constant charge and discharge current to improve linearity, but this also results in greater noise contribution. Markulic et al., in their paper "ADTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation" published at the 2016 JSSC, proposed a correction technique based on digital pre-distortion to improve the linearity of the digital-to-time converter circuit, but this requires additional correction time and impacts resource overhead. In their paper, "4.3A 76.7fs-lntegrated-jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering," published at the 2023 ISSCC, Dartizio et al. proposed perturbing the frequency control word to push the fractional spurious frequency farther away, thereby utilizing the loop filter characteristics to suppress the fractional spurious frequency. The proposed solution can suppress near-band fractional spurious frequencies to within 60dB to 70dB at best. Summary of the Invention

[0009] To address these issues, the present invention provides a novel, all-digital phase-locked loop (PLL) that utilizes random phase modulation and demodulation technology, eliminating the need for additional calibration and achieving extremely low fractional spurious emissions. Compared to traditional solutions, the in-band fractional spurious emissions are significantly reduced from approximately 60dB to below the in-band noise floor.

[0010] To achieve the above object, the technical solution of the present invention is as follows:

[0011] A fully digital phase-locked loop architecture, characterized by including a phase comparison circuit, a digital loop filter, an oscillator circuit, a high-speed phase shifter circuit, a low-speed phase shifter circuit, a frequency divider circuit, and a digital control module, wherein the output signal of the oscillator circuit passes through the high-speed phase shifter circuit to produce a preliminary phase shift, and after the high-speed phase shift, the signal passes through the frequency divider circuit, and the output signal of the frequency divider circuit passes through the low-speed phase shifter circuit for secondary phase shifting. The high-speed phase shifter circuit resamples the output signal of the frequency divider circuit, retaining the phase information of the high-speed phase shifted signal in the output signal of the frequency divider circuit; the digital control module uses a random code to phase modulate the high-speed phase shifter and the low-speed phase shifter to achieve random phase cancellation; the output signal of the low-speed phase shifter is compared with a reference clock in the phase comparison circuit to control the loop, and the output result of the phase comparison circuit passes through the digital loop filter to regulate the frequency of the oscillator circuit, thereby achieving phase lock in the closed loop.

[0012] Furthermore, during the phase modulation process of the digital control module, the control word signs of the high-speed phase shifter and the low-speed phase shifter are opposite, the absolute values ​​of the random code parts are the same, and the sum of the low-speed phase shift phase and the high-speed phase shift phase in the time domain is the sum of the ideal phase and the 2π fixed phase. Random phase cancellation is achieved through time domain phase addition.

[0013] Furthermore, the digital control module includes an integral differential modulation module, a residual accumulation module, a random code module and a maximum phase shift control code module. The frequency control word passes through the integral differential modulation module to generate a corresponding frequency division ratio. The corresponding frequency residual is accumulated through the residual accumulation module to obtain an ideal phase shift control word. The ideal phase shift control word and the random code generated by the random code module are added to obtain a high-speed phase shifter control word. The maximum phase shift control code module is used to obtain a maximum phase shift control code. The maximum phase shift control code and the random code are subtracted to obtain a low-speed phase shift control word.

[0014] Furthermore, the output signal of the oscillation circuit passes through a high-speed phase shift circuit to modulate the high-speed phase shift phase and maintain the high-speed clock frequency. After the high-speed phase shift signal passes through a frequency dividing circuit, the signal frequency is reduced to the reference clock frequency, so that the phase of the frequency divided signal is aligned with the high-speed phase shift signal.

[0015] Specifically, the all-digital phase-locked loop architecture of the present invention has the following beneficial effects:

[0016] This invention provides a novel, all-digital phase-locked loop (PLL) architecture with low fractional spurious emissions. It utilizes phase modulation and demodulation techniques to decouple the periodicity of the phase shifter control signal from the phase shifter's nonlinearity, suppressing fractional spurious emissions below the noise floor without requiring correction. Furthermore, the invention utilizes a combination of high-speed and low-speed phase shifters to ensure phase alignment, enabling phase demodulation to successfully recover the ideal phase information. This invention significantly reduces system design complexity and cost, making it uniquely advantageous in multi-band, multi-protocol communications and high-performance radar applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of fractional spurious generation in a fully digital phase-locked loop under a traditional architecture;

[0018] Figure 2 This is a schematic diagram of the random phase modulation and demodulation principle;

[0019] Figure 3 Schematic diagram of the structure of a fully digital phase-locked loop based on random phase modulation and demodulation;

[0020] Figure 4 This is a schematic diagram of the key signal timing of the full digital phase-locked loop;

[0021] Figure 5 Schematic diagram of the fractional spurious suppression effect of the proposed all-digital phase-locked loop based on random phase modulation and demodulation. DETAILED DESCRIPTION

[0022] The present invention utilizes random phase modulation and demodulation technology to decouple the periodicity of the phase shifter control signal from the nonlinearity of the phase shifter, thereby expanding the spectrum of the fractional spurious signal within the reference frequency range and achieving extremely low fractional spurious signal. Figure 2 As shown, random codes are used to phase modulate the high-speed phase shifter and the low-speed phase shifter. The high-speed phase shifter control code is the ideal control code plus the random control code, and the low-speed phase shifter control code is the maximum control code minus the ideal control code. The random range of the random control code covers all phase shifter control code ranges. Taking into account the nonlinearity of the phase shifter, the quantization noise spectra output by the high-speed phase shifter and the low-speed phase shifter are both flat-band noise spectra. Considering that the random control codes of the two phase shifters have the same absolute value and different positive and negative properties, they are added in the time domain for demodulation. The time domain addition ensures that the phase modulation information corresponding to the random control code cancels each other out, and the recovered phase control word is the sum of the ideal control code and the maximum control code. Since the phase difference corresponding to the maximum control code is 2π, and the phase shifter has a truncation process for the phase shift within the range of 2π, the recovered phase information is the ideal phase information. Taking into account the non-correlation between the mutual noise of the two phase shifters, the final output quantization noise floor is improved compared to a single phase shifter. times.

[0023] The structure diagram of the all-digital phase-locked loop architecture of the present invention is as follows Figure 3 As shown. The output signal of the oscillation circuit passes through a high-speed phase shifter and implements high-speed phase shift modulation with reference to the high-speed phase shifter control word. The high-speed phase shift signal enters the frequency division ratio for integer frequency division, and the divided signal is resampled using the high-speed phase shift signal to reduce the signal frequency to the reference clock frequency while retaining the high-speed phase shifter modulation phase information. The output signal of the frequency division circuit enters the low-speed phase shift circuit and performs secondary phase modulation with reference to the low-speed phase shift circuit control word. Since the resampling process retains the modulation phase of the high-speed phase shift circuit, the initial phase of the secondary modulation phase of the low-speed phase shift circuit is the modulation phase of the high-speed phase shift circuit, and the time domain phase addition and demodulation process is realized at the same time. The output signal of the low-speed phase shifter retains the ideal phase information and enters the phase comparison circuit for phase comparison with the reference clock. The output result passes through the loop filter to regulate the frequency of the oscillation circuit, and the closed loop achieves phase lock.

[0024] The digital control module includes an integral differential modulation module, a residual accumulation module, a random code module, and a maximum phase shift control code module. During the phase modulation process in the digital control module, the control word signs of the high-speed and low-speed phase shifters are opposite, while the absolute values ​​of the random code components are the same. Random phase cancellation is achieved through time-domain phase summation. The frequency control word passes through a third-order integral differential modulator to generate a frequency division ratio, achieving an average fractional frequency lock effect over a long period of time. The frequency error information within a single time step passes through the residual accumulation module to obtain the ideal phase residual information, which facilitates phase modulation by the phase shifter to eliminate the residual error and achieve lock. The sum of the ideal phase residual information and the random code serves as the high-speed phase shifter control word, and the difference between the maximum phase shift control code and the random code serves as the low-speed phase shifter control word, respectively regulating the high-speed and low-speed phase shifter circuits. The frequency division ratio, high-speed phase shift control word, low-speed phase shift control word, and random code are updated at the reference clock frequency to ensure timing alignment.

[0025] The key signal timing of the all-digital phase-locked loop based on random phase modulation and demodulation of the present invention is as follows Figure 4 As shown in the figure. The output signal of the actual oscillator circuit passes through a high-speed phase-shifting circuit, which modulates the high-speed phase-shift phase while maintaining the high-speed clock frequency to facilitate subsequent resampling. The high-speed phase-shifted signal passes through a frequency-dividing circuit to generate a frequency-divided signal, reducing the signal frequency to the reference clock frequency. Simultaneously, the output signal is resampled by the high-speed phase-shifted signal to align the phase of the frequency-divided signal with the high-speed phase-shifted signal. The resampled frequency-divided signal enters a low-speed phase shifter to achieve low-speed time phase shifting. The sum of the low-speed phase-shifted phase and the high-speed phase-shifted phase in the time domain is the sum of the ideal phase and the fixed phase of 2π. After truncation to the range of 0-2π, the actual phase-shifted phase equals the ideal phase-shifted phase, ensuring loop locking.

[0026] The random phase modulation and demodulation full digital phase locked loop proposed by the present invention has the following effect on the suppression of fractional spurious signals: Figure 5As shown. Compared with the traditional fractional all-digital phase-locked loop architecture, the in-band fractional spurs of the present invention can be suppressed to below the noise floor. The control word spectra of the high-speed time phase shifter circuit and the low-speed time phase shifter circuit can both obtain a good randomization effect, so that the spectrum appears as a flat-band spectrum. The random phase modulation and demodulation technology of the present invention only needs to be adjusted on the control code timing, and there is no need to calibrate the time phase shift circuit, saving system hardware resource overhead and time overhead. At the same time, the random phase modulation and demodulation technology proposed in the present invention greatly improves the in-band fractional spur suppression effect and achieves fractional spur performance below the noise floor.

[0027] The above describes the novel all-digital phase-locked loop architecture based on random phase modulation and demodulation of the present invention through detailed implementation examples. Researchers and technicians in this field may make non-substantial changes in form or content based on the above steps without departing from the scope of protection of the present invention. Therefore, the present invention is not limited to the contents disclosed in the above embodiments, and the scope of protection of the present invention shall be based on the claims.

Claims

1. A fully digital phase-locked loop architecture, characterized in that: The system comprises a phase comparison circuit, a digital loop filter, an oscillator circuit, a high-speed phase shifter circuit, a low-speed phase shifter circuit, a frequency divider circuit, and a digital control module. The output signal of the oscillator circuit passes through the high-speed phase shifter circuit to generate a preliminary phase shift. The signal after the high-speed phase shift passes through the frequency divider circuit, and the output signal of the frequency divider circuit passes through the low-speed phase shifter circuit for secondary phase shifting. At the same time, the high-speed phase shifter circuit resamples the output signal of the frequency divider circuit, retaining the phase information of the high-speed phase shifted signal in the output signal of the frequency divider circuit. The digital control module uses random codes to phase-modulate the high-speed phase shifter and the low-speed phase shifter to achieve random phase cancellation; the output signal of the low-speed phase shifter is compared with the reference clock in the phase comparison circuit to control the loop; the output result of the phase comparison circuit is passed through the digital loop filter to regulate the frequency of the oscillation circuit, and the closed loop achieves phase lock.

2. The all-digital phase-locked loop architecture according to claim 1, wherein: During the phase modulation process of the digital control module, the control word signs of the high-speed phase shifter and the low-speed phase shifter are opposite, the absolute values ​​of the random code parts are the same, and the sum of the low-speed phase shift phase and the high-speed phase shift phase in the time domain is the sum of the ideal phase and the 2π fixed phase. Random phase cancellation is achieved through time domain phase addition.

3. The all-digital phase-locked loop architecture according to claim 2, wherein: The digital control module includes an integral differential modulation module, a residual accumulation module, a random code module and a maximum phase shift control code module. The frequency control word passes through the integral differential modulation module to generate a corresponding frequency division ratio. The corresponding frequency residual is accumulated by the residual accumulation module to obtain an ideal phase shift control word. The ideal phase shift control word and the random code generated by the random code module are added to obtain a high-speed phase shifter control word. The maximum phase shift control code module is used to obtain a maximum phase shift control code. The maximum phase shift control code and the random code are subtracted to obtain a low-speed phase shift control word.

4. The all-digital phase-locked loop architecture according to claim 3, wherein: The integral differential modulation module is a third-order integral differential modulator.

5. The all-digital phase-locked loop architecture according to claim 3, wherein: The updating frequencies of the frequency division ratio, the high-speed phase-shift control word, the low-speed phase-shift control word and the random code are all reference clock frequencies.

6. The all-digital phase-locked loop architecture according to claim 1, wherein: The output signal of the oscillation circuit passes through a high-speed phase shift circuit to modulate the high-speed phase shift phase and maintain the high-speed clock frequency. After the high-speed phase shift signal passes through a frequency dividing circuit, a frequency dividing signal is generated, and the signal frequency is reduced to the reference clock frequency, so that the phase of the frequency dividing signal is aligned with the high-speed phase shift signal.

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