Time synchronization method and device and time synchronization system of intelligent driving system

Abstract

The invention provides a time synchronization method and device and a time synchronization system of an intelligent driving system, and relates to the technical field of data processing, in particular to the technical fields of automatic driving, electronic technology and time synchronization. The specific implementation scheme of the time synchronization method comprises the following steps: acquiring second-level world time and a corresponding second pulse signal; determining a second global timestamp corresponding to a predetermined edge of the pulse per second signal according to a first local timestamp of the captured pulse per second signal, a second local timestamp of the execution moment of the interrupt service function and the first global timestamp; wherein the interrupt service function is triggered by a second pulse signal; obtaining the second time of the current moment according to the global timestamp of the current moment and the second global timestamp; and obtaining the accurate time of the current moment according to the second-level world time and the within-second time. According to the invention, errors can be reduced, and high-precision global time can be provided.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to the field of autonomous driving, electronic technology, and time synchronization technology. Background Art

[0002] In recent years, the new energy vehicle industry has flourished. New energy vehicles are more electrified and intelligent than traditional fuel vehicles. Their hardware platforms are mostly high-computing multi-core heterogeneous system platforms with complex software and hardware systems and many types of sensors, including ultrasonic radar, millimeter-wave radar, camera, lidar, IMU, etc. Various sensors are connected to different cores. Fusion of multi-sensor perception data can improve the accuracy of obstacle recognition in different scenarios and ensure vehicle driving safety. Therefore, in the process of multi-sensor perception data fusion, a benchmark clock source is required. Time synchronization equipment is used to provide an accurate and unified time source on each processor to ensure the accuracy of multi-sensor perception data fusion. Summary of the Invention

[0003] The present disclosure provides a time synchronization method, apparatus, device, storage medium, and a time synchronization system for an intelligent driving system.

[0004] According to one aspect of the present disclosure, a time synchronization method is provided, comprising:

[0005] Get the second-level world time and the corresponding second pulse signal;

[0006] determining a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal based on a first local timestamp of a captured pulse-per-second signal, a second local timestamp of a time when an interrupt service function is executed, and a first global timestamp; wherein the interrupt service function is triggered by the pulse-per-second signal;

[0007] According to the current global timestamp and the second global timestamp, get the current time in seconds;

[0008] Get the current precise time based on the second-level world time and intra-second time.

[0009] According to another aspect of the present disclosure, a time synchronization system for an intelligent driving system is provided, comprising:

[0010] GPS module, used to output second-level world time and second pulse signal;

[0011] At least one security domain processing unit, comprising:

[0012] The first processing core communicates with the GPS module and is used to receive second-level world time and second pulse signals;

[0013] A GPIO pin associated with the first processing core, configured for a hardware timestamp capture function;

[0014] A hardware timer / register associated with the GPIO pin for capturing a first local timestamp at a predetermined edge of the pulse-per-second signal;

[0015] The first processing core is used to execute the time synchronization method provided by any embodiment of the present disclosure to generate an accurate second global timestamp and / or accurate time.

[0016] According to another aspect of the present disclosure, there is provided a time synchronization device, comprising:

[0017] Acquisition module, used to obtain second-level world time and corresponding second pulse signal;

[0018] a first determining module, configured to determine a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal based on a first local timestamp of a captured pulse-per-second signal, a second local timestamp of a time when an interrupt service function is executed, and a first global timestamp; wherein the interrupt service function is triggered by the pulse-per-second signal;

[0019] A second determining module is used to obtain the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp;

[0020] A combined module used to obtain the current precise time based on second-level universal time and intra-second time.

[0021] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0022] at least one processor; and

[0023] a memory communicatively connected to the at least one processor; wherein,

[0024] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the embodiments of the present disclosure.

[0025] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute any method according to the embodiments of the present disclosure.

[0026] According to another aspect of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the computer program implements any one of the methods according to the embodiments of the present disclosure.

[0027] According to the present disclosure, the accuracy of the global timestamp can be improved, providing high-precision global time.

[0028] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0030] Figure 1 is a schematic diagram of the hardware architecture of an intelligent driving system according to an embodiment of the present disclosure;

[0031] Figure 2 is a flowchart of a time synchronization method according to an embodiment of the present disclosure;

[0032] Figure 3 2. It is a schematic diagram of the relationship between the PPS pulse time and the ISR interrupt service time according to an embodiment of the present disclosure;

[0033] Figure 4 is a structural diagram of a time synchronization system of an intelligent driving system according to an embodiment of the present disclosure;

[0034] Figure 5 is a structural diagram of a time synchronization device according to an embodiment of the present disclosure;

[0035] Figure 6 is a diagram showing the relationship between crystal oscillator temperature drift according to an embodiment of the present disclosure;

[0036] Figure 7 is a time-temperature deviation graph after correction according to an embodiment of the present disclosure;

[0037] Figure 8 It is a block diagram of an electronic device used to implement the time synchronization method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be appreciated by those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] In related technologies, common solutions for time synchronization devices include:

[0040] 1. Use the Precision Time Protocol (PTP) protocol. A PTP network is called a PTP domain. There is only one synchronized clock in a PTP domain, and all devices in the domain are synchronized with this clock.

[0041] 2. Use gPTP protocol, generalized precise time synchronization protocol, full name precision clock synchronization protocol standard for network measurement and control systems, mainly used for clock synchronization of each node in Ethernet and distributed networks.

[0042] The above solution presents several challenges and drawbacks: Ethernet communication must be implemented, and the MAC layer must support timestamp acquisition. Each CPU must have an Ethernet interface, which is costly. PTP and gPTP protocols require a certain amount of communication bandwidth and CPU utilization, which low-end CPUs cannot meet. A gPTP module is also required, increasing software costs.

[0043] In order to at least partially solve one or more of the above-mentioned problems and other potential problems, the embodiments of the present disclosure provide a time synchronization method, device and time synchronization system for an intelligent driving system. By utilizing the technical solutions of the embodiments of the present disclosure, a more accurate time source can be provided for the intelligent driving system without increasing hardware costs.

[0044] To better understand the time synchronization method proposed in the present invention and its advantages, the following is an explanation based on an exemplary intelligent driving system hardware architecture. It should be understood that this is only one possible implementation method and does not limit the scope of protection of the present invention.

[0045] Reference Figure 1 , shows a typical intelligent driving system hardware architecture that supports the time synchronization method of the disclosed embodiments. This architecture primarily includes a Global Positioning System (GPS) module, a security domain processing unit, and a high-performance computing domain processing unit. The security domain processing unit is typically a microcontroller unit (MCU), and the high-performance computing domain processing unit is typically a system on chip (SOC).

[0046] GPS module: Serves as the system's external time reference source. The GPS module connects to the secure domain processing unit via a serial interface, such as a Universal Asynchronous Receiver / Transmitter (UART), to transmit data containing second-level time information. The GPS module connects to the secure domain processing unit via a pulse signal interface, such as a General Purpose Input / Output (GPIO) interface, to output a pulse per second (PPS) signal.

[0047] Security domain processing unit:

[0048] Typically, a multi-core microcontroller that meets the automotive safety integrity level (ASI) or autonomous driving classification standards is used. It is responsible for performing key tasks such as body control, initial sensor data processing, network management (such as CAN / LIN / Ethernet gateways), power management, and diagnostics.

[0049] Connection to GPS module: A designated core within the MCU (e.g. Figure 1 The core 1) shown receives GPS data messages through its serial interface and receives PPS signals through its GPIO pins.

[0050] Internal communication: Multiple cores of the MCU exchange data and control information through inter-process communication (IPC) mechanisms (such as shared memory, message queues, etc.).

[0051] Connection with the high-performance computing domain: The MCU is connected to the high-performance computing domain processing unit through an Ethernet interface to transmit vehicle status information, preliminary sensor processing data, and time synchronization related information.

[0052] High-performance computing domain processing unit (SOC):

[0053] Typically, a powerful multi-core heterogeneous system-on-chip (SoC) is used, which can integrate CPUs, GPUs, and AI acceleration units (NPUs). These systems primarily run complex perception, fusion, positioning, planning, and control algorithms.

[0054] Connection to the Security Domain: The SOC connects to the secure domain MCU via its Ethernet interface, receiving data and instructions from the secure domain and transmitting back computation results or status. Time synchronization information is also primarily obtained through this link. The SOC can also connect to any core of the MCU via GPIO.

[0055] Internal processing: The various processing units within the SOC (CPU, GPU, NPU, etc.) need to work together and have a strong dependence on a precise and unified time base.

[0056] While the aforementioned layered, heterogeneous hardware architecture meets functional safety and performance requirements, the system contains multiple independent computing units (MCU cores, SoC cores, accelerators, etc.), each with its own local clock and communicating through different interfaces. To ensure the consistency and accuracy of various data requiring timestamps (such as multi-sensor data, control instructions, and log records) throughout the system, high-precision time synchronization across domains and cores is crucial.

[0057] Figure 2 FIG. 1 is a flow chart of a time synchronization method according to an embodiment of the present disclosure. Figure 2 As shown, the method comprises at least the following steps:

[0058] S210: Obtain the second-level world time and the corresponding second pulse signal.

[0059] In an embodiment of the present disclosure, the time synchronization system implementing the time synchronization method can be a time synchronization module deployed on the safety domain microcontroller MCU of the intelligent driving system. The time synchronization system needs to obtain basic time information from an authoritative external clock source.

[0060] Second-level world time refers to the coarse time information of Coordinated Universal Time (UTC), accurate to the second level, including, for example, the current year, month, day, hour, minute, and second. In this embodiment, this information can be obtained by parsing the data message output by the GPS module connected to the MCU via a serial interface (such as UART). This second-level time is called utc_s. utc_s is updated based on the GPS message after each PPS signal arrives.

[0061] The corresponding pulse-per-second signal (PPS) is a physical electrical signal output by the same external clock source. This pulse signal is emitted at a fixed period, potentially one pulse per second, hence the name. A specific edge of the pulse-per-second signal (e.g., the rising edge, or "predetermined edge") accurately marks the start of each UTC second. When the clock source is a GPS module, after receiving a GPS satellite broadcast message, the GPS module obtains the time information contained in the broadcast message, processes this information, generates a PPS signal and a data message containing the second-level universal time, and sends this PPS signal and data message to the time synchronization module.

[0062] It should be noted that the GPS module's time information generation and output mechanism includes:

[0063] 1. Generation and output of second-level universal time (utc_s):

[0064] GPS satellites include the current GPS time information (for example, in the form of week numbers and seconds within the week) in the navigation messages they broadcast. The GPS receiver module installed in the intelligent driving system can not only calculate its own position by receiving signals from multiple GPS satellites, but also accurately synchronize its internal local clock to GPS time. Once the internal clock of the GPS module is aligned with the GPS time, it can calculate the current UTC time and extract information such as year, month, day, hour, minute, and second. This information is formatted into standard data messages (such as RMC, GGA, or ZDA statements in the NMEA 0183 protocol). These data messages containing second-level UTC time (utc_s) are asynchronously sent to the connected main processor (such as the security domain MCU in the present disclosure) through the serial communication interface (such as UART) of the GPS module.

[0065] It is important to note that serial data transmission takes time and is usually not completed until after the corresponding UTC second actually begins. Therefore, utc_s data can be understood as the current or immediately past whole second.

[0066] 2. Generation and output of pulse-per-second signals:

[0067] The GPS module uses its own internal high-precision clock that is precisely synchronized to GPS time (and therefore knows UTC time).

[0068] The module's internal hardware logic is configured to generate a precise voltage transition (e.g., a rising edge from low to high) on a dedicated physical pin (the PPS output pin) when its internal clock indicates that UTC time reaches a whole second (e.g., the moment the seconds change from :14 to :15). This voltage transition is the PPS signal. Because it is based on the module's precisely synchronized internal clock and directly driven by hardware, its edge (rising or falling, depending on the module design) has very high timing accuracy and stability (low jitter), reaching nanosecond levels. It constitutes the physical marker of the UTC whole second.

[0069] As can be seen, the utc_s and PPS signals are two interrelated but distinct time information signals generated by the GPS module based on the same internal UTC time reference. The physical instant at which a predetermined edge (e.g., a rising edge) of the PPS signal occurs precisely corresponds to the start of the UTC second indicated in the utc_s data message. For example, when the utc_s data indicates that the time is about to reach or has just reached "10:30:15," a valid pulse edge will be generated simultaneously (within the permitted physical accuracy) on the PPS output pin. While utc_s provides an absolute numerical label for time (year, month, day, hour, minute, and second), the time it transmits to the host processor via the serial port is relatively imprecise. The PPS signal, on the other hand, provides a precise physical marker (pulse edge) of the exact second, but does not inherently contain information about the specific second.

[0070] S220: Determine a second global timestamp corresponding to a predetermined edge of the PPS signal based on the first local timestamp of the captured PPS signal, the second local timestamp of the execution time of the interrupt service function, and the first global timestamp, wherein the interrupt service function is triggered by the PPS signal.

[0071] In the disclosed embodiment, since the PPS signal itself does not contain information about the second, in order to know the global timestamp of the moment (t1) when the PPS pulse physically arrives at the time synchronization system (e.g., the GPIO pin of the MCU), it is necessary to obtain it through the software execution of the interrupt service function. However, there is a delay in the execution of the interrupt service function by the software system, which makes the execution time (t2) of the interrupt service function lag behind t1. Figure 3 As shown, the delay between t1 and t2 is called diff_t.

[0072] First local timestamp: When the predetermined edge of the PPS signal reaches the GPIO pin, the hardware timestamp capture function associated with that GPIO pin almost instantaneously latches the local hardware timer value into a register, generating the first local timestamp, tcar. This timestamp represents the precise mapping of time t1 to the MCU's local time coordinate system. This capture process is performed directly by hardware with extremely low latency (typically in the nanosecond or even picosecond range). Therefore, tcar can be considered to accurately record the local time at time t1.

[0073] Interrupt Service Routine (ISR): A predetermined edge in the PPS signal at time t1 not only triggers the hardware capture tcar but also issues an interrupt request to the MCU core. Due to factors such as operating system scheduling, CPU status, and interrupt priority, the CPU may actually respond to the interrupt request and begin executing the ISR code later than t1. The ISR begins executing at t2.

[0074] Second local timestamp: At time t2, the ISR code reads the current count value of the MCU's local high-precision timer through software instructions to obtain the second local timestamp, which is recorded as tcrr.

[0075] First global timestamp: Also at time t2, the ISR code uses a software instruction to read the current value of a high-precision global time counter maintained by the system, obtaining the first global timestamp, denoted as gtc_isr_now. This first global timestamp is designed to track UTC time as accurately as possible, with nanosecond resolution.

[0076] Second global timestamp: Using the three timestamps tcar, tcrr, and gtc_isr_now, the system can calculate the precise delay between the physical event t1 and the software response t2 (primarily expressed as tcrr-tcar). Then, by subtracting this delay from the global time gtc_isr_now at t2, the actual global timestamp corresponding to t1 (i.e., the expected edge of the PPS signal) can be deduced. This final calculated global timestamp, precisely aligned to the start of the UTC second, is the second global timestamp, denoted as gtc_pps.

[0077] S230: Obtain the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp.

[0078] In the embodiment of the present disclosure, after determining the precise global timestamp gtc_pps of the start of the current second, this step aims to calculate the number of nanoseconds that have passed within the current second at any current moment.

[0079] The current moment refers to any time point between two consecutive PPS signals (ie, within one second).

[0080] The current global timestamp refers to the value of the continuously running high-precision global time counter read by the system at the current moment to obtain gtc_now.

[0081] The time in seconds is calculated by subtracting gtc_now from gtc_pps (i.e., gtc_now - gtc_pps). This gives the precise amount of time that has elapsed since the beginning of the second, typically in nanoseconds. This difference is the current time in seconds, denoted as utc_ns. It represents the fractional fraction of a second within the current time.

[0082] S240: Obtain the current precise time according to the second-level world time and the intra-second time.

[0083] In the disclosed embodiment, the rough whole-second time and the precise intra-second time are combined to form a complete, high-precision representation of the current time.

[0084] The current precise time is obtained by combining utc_s and utc_ns to obtain the complete and highly accurate UTC time representation of the current moment, denoted as utc. For example, a UTC value might be represented as "October 27, 2023, 10:30:15 seconds + 500,123,456 nanoseconds." This final UTC timestamp is highly precise and accurate and can be used by various application modules in intelligent driving systems that require precise time information, such as sensor fusion, logging, and planning and control.

[0085] The solution of the disclosed embodiments effectively combines authoritative time with the precise edges of the PPS signal, utilizing hardware timestamping and software delay compensation techniques to calculate sub-second time, thereby generating and maintaining a highly accurate time base synchronized with UTC. This provides a precise time source for intelligent driving systems.

[0086] It's important to note that during the period from t1 to t2, the GPIO hardware detects the edge change and sends an interrupt request to the MCU's interrupt controller. This process may incur a slight hardware delay and may require synchronization with the MCU's internal clock. Upon receiving the request, the interrupt controller must make an assessment. If a higher-priority interrupt is currently processing or the CPU is executing a non-interruptible instruction, the interrupt request caused by the PPS signal must be queued. This is a significant and variable source of latency.

[0087] By the time the CPU becomes idle and decides to respond to the PPS interrupt, multiple clock cycles may have already passed. The CPU then retrieves the interrupt vector, searches the interrupt vector table for the entry point of the corresponding interrupt service routine (ISR), and jumps to the ISR. The address of the ISR is loaded into the program counter, and execution of the ISR's instructions begins. The moment the ISR begins executing, at time t2, marks the moment of the software event.

[0088] The ISR code contains an instruction for obtaining tcrr and gtc_isr_now and is executed by the CPU. Thus, the software reads the current local hardware timer value to obtain tcrr and reads the global timestamp to obtain the first global timestamp gtc_isr_now.

[0089] gtc_isr_now represents the value of the global time counter currently maintained by the system when the interrupt service function (ISR) is executed (time t2).

[0090] It should be understood that an MCU typically has one (or more) high-precision, continuously running hardware timers / counters. This counter is driven by a local crystal oscillator, which can be a high-frequency crystal oscillator onboard the MCU. This means that its raw accuracy and stability depend on this crystal oscillator.

[0091] Once started, the counter will continue to count based on the frequency of the crystal oscillator. It can be configured to have a very high resolution (for example, a frequency of 250MHz corresponds to a resolution of 4ns).

[0092] In this way, this continuously running counter can be regarded as the system time or time base within the MCU. Various tasks and events in the system can obtain a high-precision timestamp by reading the current value of this counter.

[0093] Therefore, the acquisition process of gtc_isr_now is as follows:

[0094] Interrupt trigger: The edge of the PPS signal triggers an interrupt request.

[0095] System Response: After a delay (diff_t), the CPU responds to the interrupt and begins executing the interrupt service routine (ISR) written for the PPS interrupt. This time is t2.

[0096] Software read: Inside the ISR code, there is an instruction that directly reads the current value of the continuously running high-precision hardware counter.

[0097] Assignment: The read value is assigned to the variable gtc_isr_now.

[0098] It should also be noted that in many MCU implementations, the local timestamp functions used for tcar and tcrr, and the global time counters used for gtc_isr_now and gtc_now, may ultimately originate from the same underlying, high-frequency hardware counter hardware module.

[0099] tcar is the value of the counter automatically captured by the hardware at time t1. tcrr is the value of the counter read by the software at time t2. gtc_isr_now is also the value of the counter read by the software at time t2. Based on tcar and tcrr, we can determine the time difference diff_t between times t1 and t2, and use this time difference to further infer the global timestamp at time t1, i.e., the second global timestamp.

[0100] By combining hardware and software, the arrival time of the physical edge of the PPS signal (i.e., the start time of the UTC whole second) is determined extremely accurately in the system's internal high-precision time coordinate system, thereby eliminating errors caused by system processing delays.

[0101] Every second, when a new PPS pulse arrives, the above steps S210 to S240 are repeated to calculate a new gtc_pps. This is equivalent to periodically calibrating the global time counter driven by the high-resolution but potentially drifting local clock with the global time PPS signal, preventing error accumulation.

[0102] As can be seen, in the solution provided by the above embodiment, global time provides the "anchor point" and long-term accuracy, utc_s provides the "integer part" of time, and the PPS signal provides the precise physical marker for the start of each second. Between two PPS pulses (i.e., within a second), the system relies on the stable counting of the local clock to provide nanosecond time resolution.

[0103] In one possible implementation, S210 acquires the second-level world time and the corresponding second pulse signal, further comprising the following steps:

[0104] S211. Obtain a serial port message using a serial interface connected to a clock source, where the serial port message includes a second-level world time.

[0105] S212. Obtain a pulse-per-second signal using the GPIO pin connected to the clock source.

[0106] In the disclosed embodiment, the clock source may be a GPS module, and the processing unit may be a microcontroller (MCU) in the safety domain of the intelligent driving system. The MCU continuously receives a serial data stream from the GPS module via its internal UART controller. The GPS module encapsulates the UTC time information calculated internally into specific serial data packets / messages according to a preset protocol format (e.g., the industry-standard NMEA 0183 protocol) and transmits them.

[0107] The software on the MCU (e.g., running in a task or driver dedicated to processing GPS data) is responsible for receiving, buffering, and parsing these serial messages. The parsing process aims to extract the fields representing the current UTC time from the received message, including the year, month, day, hour, minute, and second. This parsed UTC time, accurate to the second, is called the second-level universal time (utc_s). The MCU stores this utc_s value and typically updates it with each new GPS message.

[0108] The GPS module's dedicated pulse-per-second output pin is connected to a general-purpose input / output (GPIO) pin on the MCU. The GPS module generates a voltage pulse on its PPS output pin when its internal clock indicates that the UTC time reaches a whole second boundary. The active edge of this pulse is highly synchronized with the start of the UTC whole second, achieving much higher accuracy than can be achieved through serial data transmission.

[0109] The MCU's GPIO peripheral hardware is configured to automatically detect preset edge events on the connected pin. When the rising edge of the PPS signal output by the GPS module reaches the GPIO pin, the MCU's hardware (typically the GPIO controller in conjunction with the interrupt controller or the input capture unit of the timer module) instantly recognizes this event. This hardware-detected edge event serves as the starting point for subsequent high-precision timestamping operations and interrupt triggering. It provides the precise physical time anchor upon which all subsequent precise time calculations rely.

[0110] According to the solution of the embodiments of the present disclosure, two complementary time information can be obtained from the clock source: the second-level universal time (UTC_S) obtained through the serial port message, which identifies the current second, and the valid edge event of the second pulse signal detected by the GPIO pin, which accurately marks the beginning of each second. These two pieces of information together form the basis for subsequent high-precision time synchronization calculations.

[0111] In one possible implementation, S220 determines, based on the first local timestamp of the captured pulse-per-second signal, the second local timestamp of the interrupt service function execution time, and the first global timestamp, a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal, and includes at least the following steps:

[0112] S221 . Obtain a first local timestamp according to a count value of a local timer when a predetermined edge of a pulse-per-second signal is captured.

[0113] In the disclosed embodiment, when the predetermined edge of the second pulse signal (corresponding to the physical time t1) reaches the configured GPIO pin, the current count value of the associated local high-precision hardware timer / counter will be automatically and quickly latched into a specific register by the hardware.

[0114] S222 : Obtain a second local timestamp and a first global timestamp according to the execution time of the interrupt service function triggered by the second pulse signal.

[0115] The predetermined edge of the pulse-per-second signal triggers the hardware capture in step S221 and simultaneously issues an interrupt request to the processing unit.

[0116] The processing unit responds to the interrupt request and, after the system's inherent interrupt processing delay, begins executing the interrupt service routine (ISR) written for the interrupt event. The time when the ISR begins execution is recorded as t2. Time t2 is usually later than t1.

[0117] During the execution of the ISR code, a software instruction reads the current count value of the local high-precision hardware timer / counter associated with the GPIO pin. This read count value is the second local timestamp, denoted as tcrr. tcrr represents the local time value at time t2.

[0118] At the same time, the software instruction reads the current value of the high-precision Global Time Counter (GTC) maintained by the system to track global time. This is the first global timestamp, recorded as gtc_isr_now. gtc_isr_now represents the timestamp of time t2 in the system's global time coordinate system.

[0119] S223 : Determine a second global timestamp corresponding to a predetermined edge of the pulse per second signal according to the first global timestamp and a time difference between the first local timestamp and the second local timestamp.

[0120] Calculate the time difference between the first local timestamp (tcar) and the second local timestamp (tcrr), denoted as diff_t. This time difference, diff_t, reflects the local time interval between the time t1 when the PPS signal edge is accurately captured by the hardware and the time t2 when the ISR begins executing and the software reads the timestamp. The calculation formula is diff_t = tcrr - tcar.

[0121] Then, a second global timestamp that precisely corresponds to the predetermined edge of the pulse-per-second signal can be calculated based on the first global timestamp (gtc_isr_now) and the time difference (diff_t).

[0122] According to the solution of the embodiment of the present disclosure, when each second pulse signal arrives, the corresponding timestamp gtc_pps of the precise physical moment in the nanosecond global time coordinate system can be determined with extremely high accuracy, so as to facilitate further calculation of the time in seconds.

[0123] It's important to note that a dedicated 64-bit free-running counter is typically maintained as the global time base (GTC). gtc_isr_now can be 64 bits wide, while tcrr and tcar can be 32 bits wide. A 64-bit counter operating at nanosecond resolution (e.g., 4ns) has a wraparound period of approximately 2338 years (2^64 * 4ns). This extremely long period means that gtc_isr_now can be considered a monotonically increasing, absolute time value that never wraps around for the lifetime of any practical system. This is crucial for establishing a stable and reliable global time base.

[0124] In one possible implementation, S223 determines the second global timestamp corresponding to the predetermined edge of the pulse-per-second signal based on the first global timestamp and the time difference between the first local timestamp and the second local timestamp, and includes at least the following steps:

[0125] A time difference is obtained according to a difference between the first local timestamp and the second local timestamp.

[0126] The time difference is subtracted from the first global timestamp to obtain a second global timestamp corresponding to a predetermined edge of the pulse per second signal.

[0127] In the disclosed embodiment, the first global timestamp (gtc_isr_now) obtained at ISR execution time t2 is used as a reference point, and the time difference (diff_t) just calculated is subtracted, i.e., gtc_pps = gtc_isr_now - diff_t. The calculated result is the second global timestamp that precisely corresponds to the predetermined edge of the pulse per second signal.

[0128] According to the solution of the embodiment of the present disclosure, by subtracting the delay diff_t accurately measured by the local timestamp from the first global timestamp, the gtc_pps value obtained effectively traces the global time at time t2 back to time t1, thereby eliminating the error caused by the interruption delay and obtaining a high-precision timestamp of the start moment of the UTC whole second in the system global time coordinate system.

[0129] In a possible implementation, the second-level world time and the second global timestamp are updated with the arrival of each second pulse signal.

[0130] In an embodiment of the present disclosure, a processing unit (e.g., MCU core 1) is configured to periodically execute a time synchronization update loop. The loop is triggered by each second pulse signal received. In each loop, the processing unit first executes steps S221-S223 to calculate the latest second global timestamp (gtc_pps) corresponding to the current second pulse signal. At the same time or immediately thereafter, the processing unit parses the latest serial port message received from the GPS module to obtain the latest second-level world time (utc_s) corresponding to the second pulse. The two new time values ​​(utc_s and gtc_pps) calculated and obtained are then used to update the corresponding time reference values ​​stored internally in the system, replacing the value of the previous second.

[0131] According to the solution of the embodiment of the present disclosure, by forcing an update when each PPS signal arrives, it is ensured that the system's global time reference (gtc_pps) can closely track the UTC second boundary of the external authoritative time source, effectively compensating for the drift that may have occurred in the system's internal clock in the previous second, while ensuring that the time "tag" (utc_s) and the precise moment (gtc_pps) are always synchronized, thereby maintaining the high precision and accuracy of the entire system time.

[0132] In a possible implementation, the predetermined edge of the pulse-per-second signal is a rising edge.

[0133] In the disclosed embodiments, the GPIO peripherals and associated interrupt controller / timer input capture units of a processing unit (e.g., an MCU) are explicitly configured to react only to voltage transitions from low to high (i.e., rising edges) on the connected GPIO pins. The hardware is configured to ignore falling edges or other voltage changes.

[0134] According to the solution of the embodiment of the present disclosure, the rising edge is explicitly specified as the trigger event, which ensures that the time synchronization process is always performed at a deterministic moment relative to the UTC second boundary, thereby ensuring the stability and repeatability of the synchronization.

[0135] In a possible implementation, the time unit of the first local timestamp, the second local timestamp, the first global timestamp, the second global timestamp, the global timestamp of the current moment, and the time within a second is nanosecond.

[0136] In the disclosed embodiment, the hardware timers / counters used to generate local timestamps (tcar, tcrr) and global timestamps (gtc_isr_now, gtc_pps, gtc_now) within the processing unit (e.g., MCU) are driven by a high-frequency on-board crystal oscillator (e.g., 250MHz). After reading the raw count values ​​of these hardware counters, the software uses the known crystal oscillator frequency (or period, e.g., 250MHz corresponds to 4 nanoseconds / tick) to convert the raw count values ​​into values ​​in nanoseconds (ns) through multiplication or division operations. All subsequent time calculations are based on these nanosecond values.

[0137] The solution of the disclosed embodiments uses nanoseconds as a unified time unit, providing the system with extremely high time resolution. This high resolution is crucial for accurately measuring and compensating for minute system delays (such as interrupt delay diff_t), and for providing sufficiently precise timestamps for intelligent driving applications (such as high-frequency multi-sensor data fusion, precise event sequencing, and control command issuance). This meets the demanding time accuracy requirements of advanced intelligent driving functions.

[0138] In one possible implementation, the clock source is a GPS module or a microcontroller.

[0139] In the embodiment of the present disclosure, Figure 1 In the architecture shown, the GPS module is connected to core 1 of the MCU domain, and the MCU domain uses the GPS module as the clock source. The SOC domain is connected to the MCU domain through ETH and GPIO, and the SOC domain can use any microcontroller in the MCU domain as the clock source. In other words, the high-performance computing domain processing unit (such as the SOC processor) of the intelligent driving system can not be directly connected to an external clock source (such as GPS), but can use the security domain processing unit (such as the MCU) as its reference clock source to achieve high-precision time synchronization. The following is a description of the specific steps of this implementation:

[0140] 1. Obtain time synchronization information from the MCU (coarse synchronization and reference transfer):

[0141] The SOC establishes a communication connection with the security domain MCU through its Ethernet interface.

[0142] The MCU periodically (for example, every second or on demand) encapsulates its internally maintained, highly precisely synchronized second-level universal time (utc_s) and second global timestamp (gtc_pps) (i.e., the precise global timestamp at the start of the UTC second) into a specific data packet or message.

[0143] MCU sends the time information including utc_s and gtc_pps to SOC via Ethernet.

[0144] The software on the SoC is responsible for receiving and interpreting the time information from the MCU. This provides the SoC with a rough time reference, allowing it to know the current UTC second and the precise start time of the previous second measured on the MCU side.

[0145] 2. Obtain precise time synchronization physical signal:

[0146] To achieve high-precision alignment, in addition to transmitting the time value via Ethernet, a precise physical time stamp signal is also required to be transmitted from the MCU's time domain to the SOC. The edge of this signal needs to be associated with the MCU's gtc_pps moment or a precise time point derived from it. This can be achieved in the following ways:

[0147] PPS signal forwarding: The MCU connects the original PPS signal received from the GPS, or the PPS signal regenerated based on its internal precise time reference, to a GPIO input pin of the SOC through an MCU GPIO output pin.

[0148] PTP event signal: If the PTP protocol is used, the protocol stack can drive a GPIO pin to generate an edge event at the critical moment when a specific synchronization message is sent or received. This event is precisely timed to the PTP timestamp. This GPIO signal is also connected to the corresponding GPIO input pin of the SoC.

[0149] Other synchronization signals: The MCU can drive a GPIO output at the gtc_pps time or a fixed offset time based on its internal logic to generate a custom synchronization signal and transmit it to the SoC.

[0150] In order to achieve high-precision alignment of the SOC and MCU time bases, in addition to transmitting the time values ​​(utc_s, gtc_pps) via Ethernet, an accurate physical time stamp signal is required to be transmitted from the MCU to the SOC. The predetermined edge of this signal (e.g., the rising edge) needs to be accurately associated with the synchronized time base within the MCU. In different embodiments of the present disclosure, this physical signal can be generated and transmitted in one of the following ways:

[0151] Method 1: MCU relays GPS PPS signal

[0152] In this mode, the MCU forwards the raw PPS signal it receives from the GPS module directly or after minimal processing through another GPIO pin of the MCU configured in output mode. This pin is then connected to a GPIO pin of the SoC configured in input mode.

[0153] This method directly transmits the time stamp closest to the source, and the additional delay introduced is relatively fixed and small. The PPS signal edge arriving at the SOC has a direct and fixed time relationship with the GPS original PPS signal edge.

[0154] Method 2: MCU generates PPS signal

[0155] In this way, the MCU does not directly forward the GPS PPS signal, but uses the global time counter that has been accurately synchronized and maintained through steps S221-S223 and the calculated second global timestamp (gtc_pps).

[0156] When the MCU's GTC count reaches the precise moment corresponding to the next UTC full second (for example, equal to gtc_pps + 1,000,000,000 nanoseconds, or a precise future time point calculated based on gtc_pps), the hardware timer module automatically drives a GPIO pin configured in output mode to generate a pulse edge. This pin is also connected to a GPIO pin configured in input mode on the SoC.

[0157] This method generates a signal with less jitter and is not directly affected by the quality of the original GPS PPS signal. The MCU can more flexibly control signal characteristics (such as pulse width).

[0158] Whether using a relay or generation approach, a physical signal with a predetermined edge that is highly synchronized with the MCU's precise time base is ultimately transmitted stably to the SoC pin. This physical signal edge arriving at the SoC serves as a trigger for the SoC to subsequently perform its local high-precision timestamp capture and delay compensation.

[0159] 3. The SOC performs local high-precision timestamp capture and delay compensation:

[0160] The SOC internally performs similar steps (S221-S223) as the aforementioned MCU side, but uses its own hardware resources and time base:

[0161] Step S221': The SOC configures the GPIO pin that receives the synchronization physical signal as a hardware timestamp capture function. When the predetermined edge of the synchronization signal reaches the SOC GPIO pin (t1_soc), the current count value of the SOC's local high-precision hardware timer is automatically latched by the hardware, obtaining the SOC's first local timestamp (tcar_soc).

[0162] Step S222': This synchronization signal edge simultaneously triggers an interrupt request within the SOC. The SOC responds to the interrupt and begins executing the corresponding ISR at a later time, t2_soc. In the ISR, the software reads the current value of the SOC's local hardware timer to obtain the SOC's second local timestamp (tcrr_soc) and reads the current value of the SOC's own global time counter (GTC_soc) to obtain the SOC's first global timestamp (gtc_isr_now_soc).

[0163] Step S223 ′: the SOC calculates its local interrupt delay diff_t_soc=tcrr_soc−tcar_soc, and then calculates the SOC global timestamp gtc_sync_event_soc=gtc_isr_now_soc−diff_t_soc that exactly corresponds to the synchronization signal edge event t1_soc.

[0164] 4. Align the SOC internal time base with the MCU time base:

[0165] The SOC now has the following information: utc_s and gtc_pps received from the MCU via Ethernet, and the locally accurately measured synchronization signal edge timestamp gtc_sync_event_soc.

[0166] The SOC's time synchronization software module uses this information to calibrate or adjust the SOC's own global time counter (GTC_soc) to synchronize it with the MCU's time base (ultimately with UTC). Specific alignment methods can include:

[0167] Offset calibration: The SOC knows that the edge of the received synchronization signal should theoretically correspond to (or be relative to) the gtc_pps value sent by the MCU. By comparing gtc_sync_event_soc with this theoretical value, the current offset of the SOC clock relative to the MCU clock can be calculated and the count value of GTC_soc can be adjusted accordingly or a compensation offset can be set.

[0168] According to the solution of the embodiment of the present disclosure, through the above steps, the SOC in the high-performance computing domain can use the security domain MCU as its trusted time synchronization reference. It combines the absolute time information (utc_s, gtc_pps) transmitted via Ethernet and the precise physical synchronization event markers obtained through GPIO, and uses local hardware timestamp capture and delay compensation technology to achieve high-precision alignment of its own time base with the MCU time base. This approach avoids configuring an independent GPS receiver or external clock source for the SOC, simplifies the system hardware design, and at the same time ensures the consistency and high precision of the internal time of the entire intelligent driving system, including the security domain and the high-performance computing domain.

[0169] In a possible implementation, the method further includes the following steps:

[0170] The second-level world time and the second global timestamp are sent to other processing cores in the microcontroller domain through inter-core communication.

[0171] In the disclosed embodiment, after a master processing core (e.g., MCU core 1 directly connected to the GPS) calculates the latest second-level universal time and the second global timestamp, it uses the inter-core communication (IPC) mechanism provided within the microcontroller to transmit these two critical time information to other slave processing cores on the same MCU chip. The IPC mechanism may include, but is not limited to, writing utc_s and gtc_pps to a shared memory area accessible to all cores, or sending notifications or data packets containing these time information via a software message queue.

[0172] According to the solution of the disclosed embodiments, precise time reference information (utc_s and gtc_pps) is shared through inter-core communication, ensuring that all processing cores within the same security domain microcontroller have access to a unified, highly accurate time view synchronized with external UTC. This avoids the complexity and potential inconsistencies of independent time synchronization for each core, which is crucial for executing tasks requiring coordination and precise timestamps in a multi-core environment, ensuring time determinism for operations within the security domain.

[0173] To further improve the accuracy of time measurement within a second, especially when the frequency of the local clock crystal oscillator drifts with temperature, an embodiment of the present disclosure obtains the time within a second at the current moment based on the global timestamp at the current moment and the second global timestamp at step S230, further comprising the following steps:

[0174] S231 : Determine a correction factor according to the time interval between the global timestamp corresponding to the pulse signal at the Nth second and the global timestamp corresponding to the pulse signal at the N-1th second.

[0175] S232. Obtain the time in seconds of the current moment according to the global timestamp of the current moment, the second global timestamp, and the correction factor, wherein the current moment is within the Nth second.

[0176] In the embodiment of the present disclosure, after the processing unit (e.g., MCU core 1) successfully calculates the second global timestamp gtc_pps(N) corresponding to the current Nth second pulse signal, it reads the stored second global timestamp gtc_pps(N-1) corresponding to the previous (N-1th second) pulse signal (the method of obtaining this value will be described in detail below). Subsequently, the actual time interval delta_gtc = gtc_pps(N) - gtc_pps(N-1) between the global timestamps of these two consecutive full seconds is calculated. This delta_gtc value indicates how many nanoseconds the high-precision global time counter driven by the local crystal oscillator actually counted in the nominal second that just passed. Ideally, this value should be 1,000,000,000ns. By comparing the actual interval with the ideal interval, the correction factor fk used to compensate for the frequency deviation can be calculated, and the calculation formula is fk = 10000000000.0 / delta_gtc. The calculated fk value will be stored and used for the intra-second time calculation in the next time period (i.e., within the Nth second).

[0177] In the disclosed embodiment, for any current moment in the Nth second time period (i.e., from the arrival of the PPS pulse signal at the Nth second to the arrival of the PPS pulse signal at the N+1th second), the processing unit first reads the global timestamp gtc_now for the current moment. It then calculates the raw time difference between the current moment and the start of the second. Finally, this raw time difference is multiplied by the correction factor fk calculated in step S231 based on the previous time interval to obtain the final, compensated time in seconds for the current moment.

[0178] According to the solution of the embodiment of the present disclosure, by calculating the actual count value of the local clock between two consecutive precise full seconds, the average deviation of the local crystal oscillator frequency relative to the standard frequency in the previous second period can be quantitatively measured (including deviations caused by factors such as temperature drift). This deviation can be used to predict and compensate for similar frequency deviations that will occur in the next second, thereby improving the accuracy of time measurement within a second. Applying the calculated correction factor fk to the time calculation within the current second is equivalent to dynamically scaling and adjusting the original time interval measured by the local clock. If the local clock in the previous second is fast (fk<1), the time interval in the current second will be shortened accordingly; if the local clock in the previous second is slow (fk>1), the time interval in the current second will be lengthened accordingly. This compensation mechanism effectively offsets the impact of local clock frequency drift on the cumulative error of time within a second, so that the final time within a second utc_ns is closer to the actual UTC time elapsed, thereby significantly improving the time synchronization accuracy within the entire operating temperature range.

[0179] In a possible implementation, the global timestamp corresponding to the pulse signal at the N-1th second is obtained by storing the second global timestamp calculated at the N-1th second.

[0180] In the embodiment of the present disclosure, a dedicated variable or memory location (e.g., denoted as gtc_pps_pre) is maintained within the processing unit. In each time synchronization cycle, after step S223 calculates the second global timestamp gtc_pps(N) corresponding to the current second (e.g., the Nth second), the value of gtc_pps(N) is saved to the storage unit gtc_pps_pre to overwrite the value stored earlier (the N-1th second). Therefore, when the next time synchronization cycle (processing the PPS signal of the N+1th second) begins to execute step S231, when the "global timestamp corresponding to the pulse signal of the Nth second" is needed, the program will read the value from the gtc_pps_pre storage unit, which is exactly the gtc_pps(N) calculated and stored in the previous cycle (the Nth second).

[0181] According to the solution of the embodiment of the present disclosure, through this periodic calculation, storage and reading mechanism, the global timestamps of two consecutive precise whole second moments can be reliably obtained, so that the correction factor fk can be further determined based on the time interval between them, so that a temperature drift correction algorithm for predictive compensation based on historical measurement data can be implemented.

[0182] In one possible implementation, times below UTC seconds are measured using a local clock. Due to the physical characteristics of crystal oscillator temperature drift, the crystal oscillator's frequency deviates from the reference frequency as temperature changes. Typically, at 25°C, the crystal oscillator's frequency is the same as the reference frequency. The greater the crystal temperature rises or falls, the greater the deviation from the reference frequency. For cost reasons, a crystal oscillator with a 50ppm tolerance is generally selected, meaning the maximum deviation within 1 second over the full temperature range is within 50µS.

[0183] Formula 1 introduces the crystal oscillator temperature drift correction factor fk. The UTC time of the crystal oscillator is obtained by applying the correction factor fk. The correction factor fk is calculated using Formula 2, where gtc_pps is the global timestamp of the current UTC full second, in nanoseconds, and gtc_pps_pre is the global timestamp of the previous full second, in nanoseconds. Because temperature changes linearly and slowly, the crystal oscillator frequency deviation in the previous second can be used to predict the crystal oscillator frequency deviation in the next second. When the temperature remains constant, the deviation remains constant, meaning that fk remains constant.

[0184] utc_ns = (gtc_now - gtc_pps) * fk Formula 1

[0185] fk = 1000000000.0 / (gtc_pps - gtc_pps_pre) Formula 2

[0186] The maximum deviation within a full second is the change in the crystal oscillator frequency per second. Assuming the crystal oscillator frequency changes by 1ppm per second, the error in time synchronization within a full second is 1µS. When the temperature remains constant and the frequency tends to be stable, the error is much less than 1µS.

[0187] To better understand the solution, let's take an example and assume that the crystal temperature drift relationship is as shown in Formula 3, where f0 = 200MHz, t0 = 25°C, and k = 0.04ppm / °C. Between -55°C and 105°C, the frequency deviation is as follows: Figure 6 As shown, the horizontal axis represents temperature and the vertical axis represents frequency deviation, in uS.

[0188] f = f0 * (1 - k * (t-t0)*(t-t0)) Formula 3

[0189] When the crystal temperature rises from -55℃ to 105℃ at 1℃ per second, it can be seen from formula 3 that when t is -55℃ or 105℃, the maximum frequency deviation is f=f0*(1-256*10-6), and the frequency deviation abs(f-f0) is 256uS. The frequency deviation of the crystal oscillator from -55℃ to 105℃ is as follows: Figure 6 As shown, without introducing the temperature correction factor fk, the maximum deviation adjusted per second, that is, the maximum deviation of the crystal oscillator frequency, is 256uS.

[0190] When the temperature correction factor is introduced, the deviation adjusted per second is the frequency change difference caused by the crystal oscillator's temperature change per second. Assuming that the crystal oscillator's temperature changes by 1 degree per second, when t changes from 104°C to 105°C, the two frequencies are obtained from formula 3 as follows:

[0191] f1 = f0 * (1 - 0.04*10-6 *(104-25)*(104-25)) Formula 4

[0192] f2 = f0 * (1 - 0.04*10-6 *(105-25)*(105-25)) Formula 5

[0193] The frequency error obtained from formula 4 and formula 5 is 6.36uS, that is, the maximum frequency change of the crystal oscillator per second is 6.36uS. After introducing the temperature correction factor, the maximum deviation of the crystal oscillator's utc_nc from -55℃ to 105℃ is as follows: Figure 7 As shown in the figure, the maximum deviation of utc_ns is less than ±8uS, which greatly reduces the frequency adjustment error.

[0194] When the crystal oscillator's temperature drift is within 50ppm, the deviation of utc_nc over the full temperature range is less than ±2µS, greatly improving the accuracy of the intelligent driving system's time synchronization module. This allows a lower-cost crystal oscillator to achieve the same accuracy as a higher-cost crystal oscillator.

[0195] Figure 4 FIG. 1 is a schematic diagram of the structure of the time synchronization system of the intelligent driving system provided by an embodiment of the present disclosure. Figure 4 As shown, the system at least includes:

[0196] The GPS module 410 is used to output second-level world time and second pulse signal.

[0197] At least one security domain processing unit 420, including:

[0198] The first processing core 421 communicates with the GPS module and is used to receive second-level world time and second pulse signals.

[0199] A GPIO pin associated with the first processing core is configured as a hardware timestamp capture function.

[0200] A hardware timer / register associated with the GPIO pin is used to capture a first local timestamp at a predetermined edge of the pulse-per-second signal.

[0201] The first processing core is used to execute the time synchronization method provided by any embodiment of the present disclosure to generate an accurate second global timestamp and / or accurate time.

[0202] In the embodiment of the present disclosure, the system includes at least a GPS module 410 and at least one security domain processing unit 420 .

[0203] The GPS module 410 serves as the primary external clock source for the system, and its functions have been described in the previous embodiments (e.g., refer to the section on the GPS module time information generation and output mechanism). In short, the GPS module 410 is configured to:

[0204] A data message containing the universal time in seconds (utc_s) is output via the serial interface 411 (eg, UART).

[0205] A pulse-per-second signal (PPS) that is precisely aligned with the UTC second is output via the pulse signal interface 412 (eg, a PPS signal output pin).

[0206] The safety domain processing unit 420 is typically a microcontroller (MCU) that complies with the Automotive Safety Integrity Level (ASIL) D. It is responsible for performing key safety-related tasks and plays a central role in the time synchronization solution of the present invention. The safety domain processing unit 420 includes at least the following components:

[0207] First processing core 421 (e.g., MCU core 1): This is the main core within the security domain processing unit 420 designated for processing time synchronization. The first processing core 421 communicates with the GPS module 410 through its internal bus and peripheral interface. Specifically:

[0208] The serial communication controller connected to the serial interface 411 receives and parses the serial port message containing utc_s output by the GPS module 410 .

[0209] The pulse signal output by the GPS module 410 is received via the GPIO pin 422 connected to the pulse signal interface 412 .

[0210] GPIO pin 422: A general-purpose input / output pin on the first processing core 421 (or its associated MCU), physically connected to the pulse signal interface 412 of the GPS module 410. This GPIO pin 422 is configured by software as input mode, with its hardware timestamp capture function enabled. This means that this pin is associated with specific hardware logic within the MCU, capable of automatically responding to edge changes in the input signal.

[0211] Hardware timer / register 423: This is a hardware resource closely related to the hardware timestamp capture function of GPIO pin 422. It generally includes:

[0212] A high-precision local hardware timer (not shown separately, it may be global within the MCU or private to the timer module), driven by the MCU's local crystal oscillator, continuously counts.

[0213] A capture register (this register is or is contained in hardware timer / register 423). When GPIO pin 422 detects a predetermined edge (e.g., a rising edge at time t1) of a preconfigured pulse-per-second signal, the hardware logic automatically latches the current count value of the local hardware timer into this capture register. The latched value is the first local timestamp (tcar).

[0214] Functional execution of the first processing core 421: In addition to receiving GPS signals, the first processing core 421 is configured to execute the main computational steps of the time synchronization method described in any embodiment of the present disclosure, including:

[0215] Responds to an interrupt request triggered by an edge of the pulse-per-second signal on the GPIO pin 422 .

[0216] In the interrupt service function (ISR), the current local timer value is read to obtain the second local timestamp (tcrr), and the global time counter (GTC) maintained by the system is read to obtain the first global timestamp (gtc_isr_now).

[0217] The time difference diff_t=tcrr-tcar is calculated, and an accurate second global timestamp (gtc_pps) is calculated based on gtc_isr_now and diff_t. The timestamp corresponds to the predetermined edge time t1 of the pulse per second signal.

[0218] Calculate the current time in seconds (utc_ns).

[0219] Combine the obtained utc_s and the calculated utc_ns to generate the final accurate time (utc).

[0220] By providing the original time and precise physical second pulse signal through the GPS module 410, and working in conjunction with the first processing core 421 within the security domain processing unit 420, the GPIO pin 422 configured with the hardware timestamp function, and the associated hardware timer / register 423, the system shown in this embodiment can effectively execute the time synchronization method described in the present invention, generate and maintain a high-precision time base synchronized with UTC, for use by various applications within the intelligent driving system.

[0221] In a possible implementation, the system further includes:

[0222] At least one computing domain processing unit is configured to communicate with the security domain processing unit.

[0223] The computing domain processing unit obtains time synchronization information from the security domain processing unit and synchronizes local time based on the time synchronization information.

[0224] In a possible implementation, the computing domain processing unit obtains time synchronization information from the security domain processing unit through an Ethernet interface.

[0225] In one possible implementation, the security domain processing unit includes multiple microcontroller processing cores, and the first processing core shares the second-level world time and / or the second global timestamp with other processing cores in the MCU through inter-core communication.

[0226] For the description of specific functions and examples of each module and sub-module of the system in the embodiment of the present disclosure, please refer to the relevant description of the corresponding steps in the above method embodiment, which will not be repeated here.

[0227] Figure 5 FIG. 1 is a schematic diagram of the structure of a time synchronization device provided according to an embodiment of the present disclosure. Figure 5 As shown, the apparatus 500 includes:

[0228] The acquisition module 501 is used to acquire the second-level world time and the corresponding second pulse signal.

[0229] The first determining module 502 is configured to determine a second global timestamp corresponding to a predetermined edge of the PPS signal based on a first local timestamp of a captured PPS signal, a second local timestamp of a time when an interrupt service function is executed, and a first global timestamp. The interrupt service function is triggered by the PPS signal.

[0230] The second determining module 503 is configured to obtain the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp.

[0231] The combining module 504 is used to obtain the current precise time according to the second-level world time and the intra-second time.

[0232] In a possible implementation, the acquisition module 501 is configured to:

[0233] A serial port message is obtained by using a serial interface connected to a clock source. The serial port message includes a second-level world time.

[0234] Use the GPIO pin connected to the clock source to obtain the second pulse signal.

[0235] In a possible implementation, the first determining module 502 is configured to:

[0236] A first local timestamp is obtained according to the count value of the local timer when the predetermined edge of the pulse-per-second signal is captured.

[0237] A second local timestamp and a first global timestamp are obtained according to the execution time of the interrupt service function triggered by the second pulse signal.

[0238] A second global timestamp corresponding to a predetermined edge of the pulse-per-second signal is determined according to the first global timestamp and a time difference between the first local timestamp and the second local timestamp.

[0239] In a possible implementation, the first determining module 502 is configured to:

[0240] A time difference is obtained according to a difference between the first local timestamp and the second local timestamp.

[0241] The time difference is subtracted from the first global timestamp to obtain a second global timestamp corresponding to a predetermined edge of the pulse per second signal.

[0242] In a possible implementation, the second-level world time and the second global timestamp are updated with the arrival of each second pulse signal.

[0243] In a possible implementation, the predetermined edge of the pulse-per-second signal is a rising edge.

[0244] In a possible implementation, the time unit of the first local timestamp, the second local timestamp, the first global timestamp, the second global timestamp, the global timestamp of the current moment, and the time within a second is nanosecond.

[0245] In one possible implementation, the clock source is a GPS module or a microcontroller.

[0246] In a possible implementation, the system further includes:

[0247] The synchronization module is used to send the second-level world time and the second global time stamp to other processing cores in the microcontroller domain through inter-core communication.

[0248] In a possible implementation, the second determining module 503 is configured to:

[0249] The correction factor is determined according to the time interval between the global timestamp corresponding to the pulse signal at the Nth second and the global timestamp corresponding to the pulse signal at the N-1th second.

[0250] The time in seconds of the current moment is obtained according to the global timestamp of the current moment, the second global timestamp, and the correction factor, wherein the current moment is within the Nth second.

[0251] In a possible implementation, the second determining module 503 is configured to:

[0252] The global timestamp corresponding to the pulse signal at the N-1th second is obtained by storing the second global timestamp calculated at the N-1th second.

[0253] For the description of specific functions and examples of each module and submodule of the device in the embodiment of the present disclosure, please refer to the relevant description of the corresponding steps in the above method embodiment, which will not be repeated here.

[0254] In the technical solutions disclosed herein, the acquisition, storage, and application of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0255] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0256] Figure 8A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0257] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0258] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0259] The computing unit 801 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the time synchronization method. For example, in some embodiments, the time synchronization method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the time synchronization method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the time synchronization method by any other appropriate means (e.g., by means of firmware).

[0260] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system comprising at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0261] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0262] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0263] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0264] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0265] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0266] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0267] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A time synchronization method, comprising: Get the second-level world time and the corresponding second pulse signal; determining a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal based on a first local timestamp of capturing the pulse-per-second signal, a second local timestamp of a time when an interrupt service function is executed, and a first global timestamp; wherein the interrupt service function is triggered by the pulse-per-second signal; Obtaining the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp; The precise time of the current moment is obtained according to the second-level world time and the intra-second time.

2. The method according to claim 1, wherein The obtaining of second-level world time and corresponding second pulse signal includes: Acquire a serial port message using a serial interface connected to a clock source, wherein the serial port message includes the second-level world time; The pulse-per-second signal is obtained by utilizing the GPIO pin connected to the clock source.

3. The method according to claim 1, wherein The determining, based on the first local timestamp of the captured second pulse signal, the second local timestamp of the interrupt service function execution time, and the first global timestamp, of a second global timestamp corresponding to a predetermined edge of the second pulse signal includes: Obtaining a first local timestamp according to a count value of a local timer when a predetermined edge of the pulse-per-second signal is captured; Obtaining a second local timestamp and a first global timestamp according to the execution time of the interrupt service function triggered by the second pulse signal; A second global timestamp corresponding to a predetermined edge of the pulse-per-second signal is determined according to the first global timestamp and a time difference between the first local timestamp and the second local timestamp.

4. The method according to claim 3, wherein: The determining, based on the first global timestamp and a time difference between the first local timestamp and the second local timestamp, a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal comprises: Obtaining a time difference according to a difference between the first local timestamp and the second local timestamp; The time difference is subtracted from the first global timestamp to obtain a second global timestamp corresponding to a predetermined edge of the pulse per second signal.

5. The method according to claim 1, wherein The second-level world time and the second global timestamp are updated with the arrival of each second pulse signal.

6. The method according to claim 1, wherein The predetermined edge of the second pulse signal is a rising edge.

7. The method according to claim 1, wherein The time unit of the first local timestamp, the second local timestamp, the first global timestamp, the second global timestamp, the global timestamp of the current moment, and the time within a second is nanosecond.

8. The method according to claim 2, wherein: The clock source is a GPS module or a microcontroller.

9. The method according to claim 2, further comprising: The second-level world time and the second global timestamp are sent to other processing cores in the microcontroller domain through inter-core communication.

10. The method according to claim 1, wherein The step of obtaining the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp includes: Determine a correction factor based on the time interval between the global timestamp corresponding to the pulse signal at the Nth second and the global timestamp corresponding to the pulse signal at the N-1th second; The time in seconds of the current moment is obtained according to the global timestamp of the current moment, the second global timestamp, and the correction factor, wherein the current moment is within the Nth second.

11. The method according to claim 10, wherein: The global timestamp corresponding to the pulse signal at the N-1th second is obtained by storing the second global timestamp calculated at the N-1th second.

12. A time synchronization system for an intelligent driving system, comprising: GPS module, used to output second-level world time and second pulse signal; At least one security domain processing unit, comprising: a first processing core, communicating with the GPS module, for receiving the second-level world time and the second pulse signal; a GPIO pin associated with the first processing core, configured for hardware timestamp capture; a hardware timer / register associated with the GPIO pin, configured to capture a first local timestamp at a predetermined edge of the pulse-per-second signal; The first processing core is configured to execute the method according to any one of claims 1 to 11 to generate an accurate second global timestamp and / or accurate time.

13. The system of claim 12, further comprising: at least one computing domain processing unit, configured to communicate with the security domain processing unit; The computing domain processing unit obtains time synchronization information from the security domain processing unit and synchronizes local time based on the time synchronization information.

14. The system according to claim 13, wherein: The computing domain processing unit obtains the time synchronization information from the security domain processing unit through an Ethernet interface.

15. The system according to claim 12, wherein: The security domain processing unit includes multiple microcontroller processing cores, and the first processing core shares the second-level world time and / or the second global timestamp with other processing cores in the MCU through inter-core communication.

16. A time synchronization device, comprising: Acquisition module, used to obtain second-level world time and corresponding second pulse signal; a first determining module, configured to determine a second global timestamp corresponding to a predetermined edge of the pulse-per-second signal based on a first local timestamp of capturing the pulse-per-second signal, a second local timestamp of a time when an interrupt service function is executed, and a first global timestamp; wherein the interrupt service function is triggered by the pulse-per-second signal; A second determining module, configured to obtain the time in seconds of the current moment according to the global timestamp of the current moment and the second global timestamp; The combination module is used to obtain the precise time of the current moment according to the second-level world time and the intra-second time.

17. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 1.

18. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-11.

19. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 11.

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