MCU network address automatic generation circuit supporting hot plug

Abstract

The invention provides an MCU network address automatic generation circuit supporting hot plug, which comprises a master control MCU, a plurality of nodes, a plurality of voltage measurement circuits, a plurality of equivalent resistors and a plurality of open-drain modules, the master control MCU end is in parallel connection with each node through a network interface connecting line, each node is in parallel connection with each equivalent resistor through an address line, and the open-drain modules are in parallel connection with the master control MCU end. The main control MCU comprises three ports, namely a port 1, a port 2 and a port 3, the port 1 and the port 2 are communication ports, the port 3 is an address generation control port and works in a push-pull output state, the port 1 of each node is connected to a voltage measurement function circuit, the port 2 of each node is connected to a voltage control port of an open-drain module, and the open-drain module is an NMOS (N-channel Metal Oxide Semiconductor) tube. According to the scheme, automatic generation of the network node address can be completed without manual participation, hot plugging is supported, the circuit structure is simple, the cost is low, and high expandability is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessor unit networking, and in particular to an MCU network address automatic generation circuit supporting hot plugging. Background Art

[0002] In current microcontroller unit (MCU) circuit networking systems, the addresses of each node are mostly manually set using a dip switch or fixed through a combination of manual and software methods. Currently, there is no low-cost circuit that can automatically generate network node addresses and support hot swapping.

[0003] The existing networking node addresses are fixed addresses, which not only cannot meet the hot-swap requirements of the circuit, but also have complex circuit design and require multiple IO ports of the MCU to obtain the setting data of the dip switches. At the same time, because the address data needs to be set manually, the installation and maintenance costs are relatively high. Summary of the Invention

[0004] To address the above problems, the present invention proposes an automatic network address generation circuit for MCU that supports hot plugging. The circuit is based on the principle of series resistor voltage division and generates a unique node address by measuring the voltage across the resistor in the series circuit.

[0005] A hot-swappable MCU network address automatic generation circuit comprises: a master MCU, multiple nodes, multiple voltage measurement circuits, multiple equivalent resistors, and multiple open-drain modules. The master MCU is connected in parallel to each node via a network interface line, and each node is connected together in parallel via an address line and an equivalent resistor. The master MCU comprises three ports, namely port 1, port 2, and port 3. Port 1 and port 2 are communication ports, and port 3 is an address generation control port operating in a push-pull output state. Port 1 of each node is connected to the voltage measurement circuit, and port 2 of each node is connected to the voltage control port of the open-drain module. The open-drain module is an NMOS tube.

[0006] Furthermore, when the voltage of the main control MCU port 3 is at a high level, the change in the voltage across the resistor connected to the node is controlled by setting the connection and disconnection of each node port 2, and the network address of the node is uniquely determined through the voltage measurement function of each node port 1.

[0007] Furthermore, the voltage measurement circuit connected to each node port 1 is implemented by an AD converter, which appears to be a high-impedance input state to the outside and is used to connect the AD conversion function inside the circuit; the port 2 of each node works in open-drain output mode and can only output a low level to the outside, but cannot directly output a high level. It is equivalently implemented by an NMOS transistor. When the node port 2 outputs a high level, the NMOS transistor is turned on, and the right end of the resistor corresponding to the node on the address line will be directly connected to the ground. At this time, the voltage at the left end of the resistor is measured by the voltage measurement circuit. By comparing it with the reference voltage, the voltage value of the node port 1 is obtained according to the series resistor voltage divider formula:

[0008] V = U*R / (n*R);

[0009] Where U is the reference voltage, R is the resistor value used to divide the voltage at each node, n is the node number in the circuit, and V is the voltage value measured at node port 1 when node port 2 is high. Transforming the above formula yields:

[0010] n=U / V;

[0011] It can be seen that by calculating the ratio of U and V, the sequence number of the node in the circuit can be obtained, and thus the address of the node can be determined.

[0012] Furthermore, the node address is generated as follows:

[0013] Step 1: Set the initial state. Set port 3 of the master MCU to a low level. When the AD conversion value measured by port 1 of each node is 0, port 2 of each node is set to a high level. The NMOS tubes of all nodes are in the on state. At this time, the address generation function of the circuit is not used.

[0014] Step 2, address generation state, set port 3 of the main control MCU to a high level. At this time, port 2 of node 1 is also high, the NMOS tube of node 1 is turned on, and ports 1 from node 2 to node N in the circuit are all low. At this time, the AD conversion value of port 1 of node 1 is the maximum value. After node 1 records this value, it sets its port 2 to a low level, and the NMOS tube of node 1 is disconnected;

[0015] Step 3: Address generation transfer state. Since the NMOS transistor of node 1 is disconnected, the AD conversion value of port 1 of node 2 is 1 / 2 of the maximum value. Node 2 records this value and sets its port 2 to a low level, disconnecting its corresponding NMOS transistor. In this way, the address generation is transferred. The AD conversion value of port 1 of node 3 is 1 / 3 of the maximum value, and the AD conversion value of port 1 of node N is 1 / N of the maximum value.

[0016] Step 4: Calculate the node address and set the AD conversion value recorded by each node to S n, the number of sampling bits is K, then the maximum value of the sampling is 2 K , calculate the order of the node in the network n = 2 K / S n , each node can use n as the address value of the current node. In the actual circuit, since the AD conversion function of each node may have a certain conversion error, S n The value will not be exactly 1 / n of the maximum conversion value. This error can be eliminated by setting a certain error tolerance range.

[0017] When the circuit is set to the main MCU timing detection address mode, the circuit can also complete the automatic address generation function in the hot plug state.

[0018] The present invention proposes a hot-swappable MCU network address automatic generation circuit. The circuit includes a main control MCU, multiple nodes, multiple voltage measurement circuits, multiple equivalent resistors, and multiple open-drain modules. The main control MCU is connected in parallel to each node via a network interface line, and each node is connected together via an address line and an equivalent resistor. The main control MCU includes three ports, namely port 1, port 2, and port 3. Ports 1 and 2 are communication ports, and port 3 is an address generation control port that operates in a push-pull output state. Port 1 of each node is connected to a voltage measurement function circuit, and port 2 of each node is connected to a voltage control port of an open-drain module. The open-drain module is an NMOS transistor. The circuit automatically determines node addresses for an MCU network, providing a low-cost solution. Network node addresses can be automatically generated without human intervention, and hot-swappable functionality is supported. If this circuit is combined with software technology to store the association between network node addresses and globally unique identifiers of each MCU, it can even implement multi-network joint networking and cross-network routing functions. Therefore, the MCU network address automatic generation circuit provided by the present invention is not only simple in circuitry and low in cost, but also has strong scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a schematic structural diagram of a circuit for automatically generating a network address for an MCU supporting hot plugging provided by an embodiment of the present invention;

[0021] Figure 2 1 is a schematic diagram of the line structure of each node port 1 and port 2 provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] The present invention proposes an automatic network address generation circuit for an MCU supporting hot plugging. The circuit includes: a main control MCU, multiple nodes, multiple voltage measurement circuits, multiple equivalent resistors, and multiple open-drain modules. The number of nodes is set to N, and one node corresponds to one voltage measurement circuit, one equivalent resistor, and one open-drain module. The number of voltage measurement circuits, equivalent resistors, and open-drain modules is consistent with the number of nodes. The main control MCU end is connected to each node in parallel via a network interface connection line, and each node is connected together in parallel via an address line and an equivalent resistor. The main control MCU includes three ports, namely port 1, port 2, and port 3, wherein port 1 and port 2 are communication ports, and port 3 is an address generation control port that operates in a push-pull output state; port 1 of each node is connected to the voltage measurement circuit, which can usually be expressed as an AD conversion port, and the converted data is actually the voltage value of the port; port 2 of each node is connected to the voltage control port of the open-drain module, and the open-drain module is an NMOS tube.

[0024] When the voltage of the main control MCU port 3 is at a high level, the change in the voltage across the resistor connected to the node is controlled by setting the connection and disconnection of each node port 2. The network address of the node can be uniquely determined through the voltage measurement function (AD conversion port) of each node port 1.

[0025] The high-impedance input voltage measurement circuit connected to each node port 1 is usually implemented by an AD converter, which appears to be a high-impedance input state to the outside and is used to connect the AD conversion function within the circuit; port 2 of each node operates in open-drain output mode and can only output a low level to the outside, but cannot directly output a high level. It is usually implemented equivalently by an N-type MOS transistor. When node port 2 outputs a high level, the NMOS transistor is turned on, and the right end of the resistor corresponding to the node on the address line will be directly connected to the ground. At this time, the voltage at the left end of the resistor is measured by the voltage measurement circuit. By comparing it with the reference voltage, the voltage value of node port 1 is obtained according to the series resistor voltage divider formula: V = U*R / (n*R), where U is the reference voltage, R is the resistor value used for the voltage divider of each node, n is the node number in the circuit, and V is the voltage value measured at node port 1 when node port 2 is high.

[0026] Transforming the above formula yields: n = U / V. It can be seen that by calculating the ratio of U to V, the sequence number of the node in the circuit can be obtained, thereby determining the address of the node.

[0027] The node address is generated as follows:

[0028] Step 1: Set the initial state. Set port 3 of the main control MCU to a low level. When the AD conversion value measured by port 1 of each node is 0 (it can be set to less than a certain value such as 10 according to the actual situation), port 2 of each node is set to a high level. The NMOS tubes of all nodes are in the on state. At this time, the address generation function of the circuit is not used.

[0029] Step 2, address generation state, set port 3 of the main control MCU to a high level. At this time, port 2 of node 1 is also high, the NMOS tube of node 1 is turned on, and ports 1 from node 2 to node N in the circuit are all low. At this time, the AD conversion value of port 1 of node 1 is the maximum value. After node 1 records this value, it sets its port 2 to a low level, and the NMOS tube of node 1 is disconnected;

[0030] Step 3: Address generation transfer state. Since the NMOS transistor of node 1 is disconnected, the AD conversion value of port 1 of node 2 is 1 / 2 of the maximum value. Node 2 records this value and sets its port 2 to a low level, disconnecting its corresponding NMOS transistor. In this way, the address generation is transferred. The AD conversion value of port 1 of node 3 is 1 / 3 of the maximum value, and the AD conversion value of port 1 of node N is 1 / N of the maximum value.

[0031] Step 4: Calculate the node address and set the AD conversion value recorded by each node to S n , the number of sampling bits is K, then the maximum value of the sampling is 2 K , calculate the order of the node in the network n = 2 K / S n , each node can use n as the address value of the current node. In the actual circuit, since the AD conversion function of each node may have a certain conversion error, S n The value will not be exactly 1 / n of the maximum conversion value. This error can be eliminated by setting a certain error tolerance range.

[0032] When the circuit is set to the main MCU timing detection address mode, the circuit can also complete the automatic address generation function in the hot plug state.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for automatically generating a network address for an MCU supporting hot plugging, characterized in that: The circuit includes: a main control MCU, multiple nodes, multiple voltage measurement circuits, multiple equivalent resistors and multiple open-drain modules. The main control MCU is connected in parallel with each node via a network interface connection, and each node is connected together in parallel via an address line and an equivalent resistor. The main control MCU includes three ports, namely port 1, port 2 and port 3, wherein port 1 and port 2 are communication ports, and port 3 is an address generation control port that operates in a push-pull output state; port 1 of each node is connected to the voltage measurement circuit, and port 2 of each node is connected to the voltage control port of the open-drain module, and the open-drain module is an NMOS tube.

2. The MCU network address automatic generation circuit supporting hot plugging according to claim 1, characterized in that: When the voltage of the main MCU port 3 is at a high level, the change in the voltage across the resistor connected to the node is controlled by setting the connection and disconnection of each node port 2. The network address of the node is uniquely determined through the voltage measurement function of each node port 1.

3. The MCU network address automatic generation circuit supporting hot plugging according to claim 2, characterized in that: The voltage measurement circuit connected to each node port 1 is implemented by an AD converter, which appears to be a high-impedance input state to the outside and is used to connect the AD conversion function inside the circuit; the port 2 of each node works in the open-drain output mode and can only output a low level to the outside, and cannot directly output a high level. It is equivalently implemented by an NMOS tube. When the node port 2 outputs a high level, the NMOS tube is turned on, and the right end of the resistor corresponding to the node on the address line will be directly connected to the ground. At this time, the voltage at the left end of the resistor is measured by the voltage measurement circuit. By comparing it with the reference voltage, the voltage value of the node port 1 is obtained by the series resistor voltage divider formula: V = U*R / (n*R), where U is the reference voltage, R is the resistance value used for the voltage divider of each node, n is the serial number of the node in the circuit, and V is the voltage value measured at the node port 1 when the node port 2 is high. Transforming the above formula yields: n = U / V. By calculating the ratio of U to V, the sequence number of the node in the circuit can be obtained, thereby determining the address of the node.

4. The MCU network address automatic generation circuit supporting hot plugging according to claim 3, characterized in that: The node address is generated as follows: Step 1: Set the initial state. Set port 3 of the master MCU to a low level. When the AD conversion value measured by port 1 of each node is 0, port 2 of each node is set to a high level. The NMOS tubes of all nodes are in the on state. At this time, the address generation function of the circuit is not used. Step 2, address generation state, set port 3 of the main control MCU to a high level. At this time, port 2 of node 1 is also high, the NMOS tube of node 1 is turned on, and ports 1 from node 2 to node N in the circuit are all low. At this time, the AD conversion value of port 1 of node 1 is the maximum value. After node 1 records this value, it sets its port 2 to a low level, and the NMOS tube of node 1 is disconnected; Step 3: Address generation transfer state. Since the NMOS transistor of node 1 is disconnected, the AD conversion value of port 1 of node 2 is 1 / 2 of the maximum value. Node 2 records this value and sets its port 2 to a low level, disconnecting its corresponding NMOS transistor. In this way, the address generation is transferred. The AD conversion value of port 1 of node 3 is 1 / 3 of the maximum value, and the AD conversion value of port 1 of node N is 1 / N of the maximum value. Step 4: Calculate the node address and set the AD conversion value recorded by each node to S n , the number of sampling bits is K, then the maximum value of the sampling is 2 K , calculate the order of the node in the network n = 2 K / S n , each node uses n as the address value of the current node.

Images