A fast-response three-ring LDO circuit structure

Abstract

The application discloses a kind of fast response three-ring LDO circuit structures, including operational amplifier circuit, current bias circuit, control voltage generation circuit, flip voltage follower.Flip voltage follower includes super source follower, push-pull output stage, fast negative feedback loop.The structure makes full use of the characteristics of push-pull output structure gate voltage common reduction, greatly improves the ability of pull current, while by increasing additional gain stage, the power supply noise rejection ratio at low frequency is improved.In addition, due to the adoption of super source follower structure, the node impedance is reduced by negative feedback, and the loop stability is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuits, and particularly relates to a fast-response three-ring LDO circuit structure. Background Technology

[0002] Low-dropout linear regulators (LDOs) play a crucial role in integrated circuits and are key circuits in wired and wireless communication systems, providing stable and adjustable voltages. Currently, many LDO circuits primarily employ traditional single-transistor or FVF (Folded-Voltage-Fold) structures. Traditional single-transistor LDOs typically consist of a negative feedback loop composed of an error amplifier and a regulating transistor. This type of LDO usually boasts a good PSR (Power Supply Rejection Ratio), but its response speed to varying loads is limited by bandwidth and slew rate. Compared to traditional LDOs, FVF LDOs are simpler in structure and have lower quiescent power consumption. They also possess their own feedback loop with a large loop bandwidth, resulting in fast response and good stability even without external capacitors. However, the folded circuit topology reduces the loop gain of the FVF LDO, leading to a decrease in power supply noise rejection ratio (PSRR), a phenomenon particularly pronounced in nanometer-scale processes. To achieve a high PSRR, additional gain stages are generally required, but this reduces loop bandwidth, resulting in a slower response speed. In summary, the key to designing an LDO circuit is to ensure both high transient response speed and high power supply rejection ratio.

[0003] like Figure 3 The image shows an LDO circuit structure from the literature “M. Al-Shyoukh, H. Lee and R. Perez, A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation,” in IEEE Journal of Solid-State Circuits, vol.42, no.8, pp.1732-1742, Aug.2007. This structure employs a conventional single-regulator transistor design. The circuit utilizes a feedforward ripple cancellation (FFRC) method to improve the power supply noise rejection ratio, but this approach cannot improve the transient response speed.

[0004] like Figure 4The image shows an LDO circuit structure from the literature “Y.Lu, W.-H.Ki and CPYue, 17.11A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems,” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 306-307.” This structure employs a flip-flop voltage follower. The circuit uses buffer impedance attenuation to increase loop bandwidth, thereby improving transient response speed. However, this approach cannot improve loop gain, thus failing to achieve a good power supply noise rejection ratio, and its current-pull capability is limited. Summary of the Invention

[0005] The purpose of this invention is to provide a fast-response three-loop LDO circuit structure, which fully utilizes the characteristic of the gate voltage reduction of the push-pull output structure to significantly improve the pull-up current capability. At the same time, by adding an NMOS fast loop feedback circuit, the power supply noise rejection ratio at low frequencies is improved, thereby solving the technical problems existing in the background art.

[0006] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0007] A fast-response three-loop LDO circuit structure is characterized by comprising three parts: an operational amplifier circuit, a control voltage generation circuit, and a flip-flop voltage follower.

[0008] The operational amplifier circuit output terminal is connected to the negative input terminal, and the reference voltage source V REF Connecting the positive input terminal to the operational amplifier circuit and the negative input terminal to the output terminal creates a unity-gain negative feedback loop. The voltage at the output terminal of the operational amplifier circuit is equal to the reference voltage source V. REF ;

[0009] The output of the operational amplifier circuit is connected to the input of the control voltage generating circuit, generating the output voltage V of the control voltage generating circuit. CTRL ;

[0010] The output of the control voltage generation circuit is connected to the input of the flip-flop voltage follower. Then, the reference voltage source V is connected to the control voltage generation circuit. REF Copy to the output V of the flip voltage follower OUT ;

[0011] The flip-voltage follower includes a push-pull output stage, a fast negative feedback loop, and a super source follower;

[0012] The push-pull output stage includes a fourth MOSFET M4 and a first MOSFET M1;

[0013] The fast negative feedback loop includes a fourth MOSFET M4, a third MOSFET M3, a second MOSFET M2, and a first MOSFET M1;

[0014] The super source follower includes a third MOS transistor M3 and a fifteenth MOS transistor M15;

[0015] The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2 and the drain of the fourth MOSFET M4.

[0016] The drain of the second MOSFET M2 is connected to the gate of the third MOSFET M3 and the gate of the fourth MOSFET M4.

[0017] The gate of the first MOSFET M1 is connected to the source of the third MOSFET M3 and the drain of the fifteenth MOSFET M15.

[0018] The drain of the third MOSFET M3 is connected to the gate of the fifteenth MOSFET M15.

[0019] Furthermore, the operational amplifier circuit includes an operational amplifier (OPA);

[0020] The control voltage generation circuit includes the tenth MOSFET M10 and the twelfth MOSFET M12;

[0021] The flip-flop voltage follower also includes the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the sixteenth MOSFET M16;

[0022] The sources of the first MOSFET M1, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are connected to the power supply.

[0023] Current source I BIAS The input terminal, the gate of the sixth MOSFET M6, the gate of the seventh MOSFET M7, the gate of the eighth MOSFET M8, and the gate of the fifth MOSFET M5 are connected to the drain of the fifth MOSFET M5.

[0024] The drain of the ninth MOSFET M9 is connected to the drain of the eighth MOSFET M8 and the gate of the ninth MOSFET M9.

[0025] The drain of the first MOSFET M1 is connected to the load capacitor C. LOAD One end, output terminal V OUT ;

[0026] The gate of the second MOSFET M2 is connected to the drain of the tenth MOSFET M10, the gate of the tenth MOSFET M10, and the drain of the twelfth MOSFET M12.

[0027] The drain of the second MOSFET M2 is connected to the drain of the sixteenth MOSFET M16;

[0028] The drain of the third MOSFET M3 is connected to the drain of the fourteenth MOSFET M14;

[0029] The drain of the sixth MOSFET M6 is connected to the drain of the eleventh MOSFET M11, the gate of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12.

[0030] The drain of the seventh MOSFET M7 is connected to the gate of the thirteenth MOSFET M13, the drain of the thirteenth MOSFET M13, the gate of the fourteenth MOSFET M14, and the gate of the sixteenth MOSFET M16.

[0031] The source of the tenth MOSFET M10 is connected to the negative input terminal and the output terminal of the operational amplifier OPA.

[0032] Current source I BIAS The other end, the source of the eleventh MOSFET M11, the source of the twelfth MOSFET M12, the source of the thirteenth MOSFET M13, the source of the fourteenth MOSFET M14, the source of the fifteenth MOSFET M15, the source of the sixteenth MOSFET M16, the source of the fourth MOSFET M4, and the load capacitor C. LOAD The other end is grounded to GND.

[0033] The fast-response three-loop LDO circuit structure of the present invention has the following advantages: This structure fully utilizes the characteristic of the common reduction of gate voltage in the push-pull output structure, significantly improving the pull-up current capability. Simultaneously, by adding an NMOS fast-loop feedback loop, the power supply noise rejection ratio at low frequencies is improved. Furthermore, this structure employs a super source follower structure, increasing the node impedance by adding a negative feedback loop, thereby increasing the loop bandwidth and effectively improving the transient response speed.

[0034] First, it fully utilizes the characteristic of the push-pull output structure where the gate voltage is reduced together. The fourth MOSFET M4 and the first MOSFET M1 serve as the push-pull output stage, and their gate voltages can be reduced synchronously, which greatly improves the ability to output transient current to the load and solves the problem of slow pull-up current response of FVF LDO.

[0035] Second: The fourth MOSFET M4 and the third MOSFET M3 form a fast negative feedback loop, and at the same time, an additional gain stage is added, which improves the power supply noise rejection ratio.

[0036] Third: The third MOSFET M3 and the fifteenth MOSFET M15 form a super source follower. By constructing a negative feedback loop, the gate node impedance of the first MOSFET M1 is effectively reduced, and the secondary pole is pushed to a higher frequency, thereby increasing the loop bandwidth. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a fast-response three-ring LDO circuit structure according to the present invention;

[0038] Figure 2 This is a block diagram of the negative feedback system of the present invention;

[0039] Figure 3 The single-regulating LDO circuit described in document 10.1109 / JSSC.2009.2039685;

[0040] Figure 4 This is a circuit diagram of a flip-flop voltage follower (LDO) described in document 10.1109 / ISSCC.2014.6757446. Detailed Implementation

[0041] To better understand the purpose, structure, and function of this invention, a fast-response FVF LDO circuit structure of this invention will be described in further detail below with reference to the accompanying drawings.

[0042] Example 1: The fast-response three-loop LDO circuit structure of the present invention adopts the following technical solution:

[0043] It consists of three parts: operational amplifier circuit 1, control voltage generation circuit 2, and flip voltage follower 3;

[0044] Operational amplifier circuit 1 includes operational amplifier OPA;

[0045] The control voltage generation circuit 2 includes the tenth MOSFET M10 and the twelfth MOSFET M12;

[0046] The flip-flop voltage follower 3 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a sixteenth MOSFET M16.

[0047] The sources of the first MOSFET M1, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are connected to the power supply.

[0048] Current source I BIAS The input terminal, the gate of the sixth MOSFET M6, the gate of the seventh MOSFET M7, the gate of the eighth MOSFET M8, and the gate of the fifth MOSFET M5 are connected to the drain of the fifth MOSFET M5.

[0049] The drain of the ninth MOSFET M9 is connected to the gate of the first MOSFET M1, the source of the third MOSFET M3, the drain of the eighth MOSFET M8, the gate of the ninth MOSFET M9, and the drain of the fifteenth MOSFET M15.

[0050] The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2, the drain of the fourth MOSFET M4, and the load capacitor C. LOAD One end, output terminal V OUT ;

[0051] The gate of the second MOSFET M2 is connected to the drain of the tenth MOSFET M10, the gate of the tenth MOSFET M10, and the drain of the twelfth MOSFET M12.

[0052] The drain of the second MOSFET M2 is connected to the gate of the third MOSFET M3, the gate of the fourth MOSFET M4, and the drain of the sixteenth MOSFET M16.

[0053] The drain of the third MOSFET M3 is connected to the drain of the fourteenth MOSFET M14 and the gate of the fifteenth MOSFET M15.

[0054] The drain of the sixth MOSFET M6 is connected to the drain of the eleventh MOSFET M11, the gate of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12.

[0055] The drain of the seventh MOSFET M7 is connected to the gate of the thirteenth MOSFET M13, the drain of the thirteenth MOSFET M13, the gate of the fourteenth MOSFET M14, and the gate of the sixteenth MOSFET M16.

[0056] The source of the tenth MOSFET M10 is connected to the negative input terminal and the output terminal of the operational amplifier OPA.

[0057] Current source I BIAS The other end, the source of the eleventh MOSFET M11, the source of the twelfth MOSFET M12, the source of the thirteenth MOSFET M13, the source of the fourteenth MOSFET M14, the source of the fifteenth MOSFET M15, the source of the sixteenth MOSFET M16, the source of the fourth MOSFET M4, and the load capacitor C. LOAD The other end is grounded to GND.

[0058] Operational amplifier circuit 1 connects its output terminal to its negative input terminal, and the reference voltage source VREF is connected to the positive input terminal of operational amplifier circuit 1. The negative input terminal of operational amplifier circuit 1 is connected to its output terminal, forming a unity-gain negative feedback. The voltage at the output terminal is equal to V. REF ;

[0059] The output of operational amplifier circuit 1 is connected to the input of control voltage generation circuit 2, which is the source of the tenth MOSFET M10. The voltage at this point is reduced by the gate-source voltage V of the tenth MOSFET M10. SG The control voltage generation circuit 2 outputs voltage V. CTRL ;

[0060] The output of voltage generation circuit 2 is connected to the input of inverting voltage follower 3. Then, the output voltage V of voltage generation circuit 2 is controlled by... CTRL Add the gate-source voltage V of the second MOSFET M2 SG Get V OUT The reference voltage V is about to be used. REF Copy to the output V of the flip voltage follower 3 OUT .

[0061] The flip-flop voltage follower 3 uses the fourth MOSFET M4 and the first MOSFET M1 as a push-pull output stage, allowing their gate voltages to decrease synchronously, significantly improving the ability to provide transient current to the load. The fourth MOSFET M4 and the third MOSFET M3 form a fast negative feedback loop, while also adding a gain stage to improve the power supply noise rejection ratio. The third MOSFET M3 and the fifteenth MOSFET M15 form a super source follower, which, by constructing a negative feedback loop, effectively reduces the gate node impedance of the first MOSFET M1, pushing the secondary pole to a higher frequency, thereby increasing the loop bandwidth.

[0062] The working principle of the fast-response three-loop LDO circuit of the present invention is as follows:

[0063] like Figure 1As shown, the operational amplifier is configured as a unity-gain negative feedback structure, with the output voltage equal to the reference voltage. M5, M6, M7, M8, and M9 form a current mirror, replicating the current from the current source ISS to each branch. The drain current of M12, after multiple replications, is proportional to the drain current of M16. The ratio of the currents in the two branches... Ratio to gate width Equal. The ratio of the gate width of M10 to that of M2. Therefore, the gate-source voltages of M2 and M10 are equal, thus making the output voltage equal to the reference voltage. M3 and M15 form a super source follower, adding a negative feedback loop to the original source follower structure, which reduces the source impedance of M3, thereby increasing the loop bandwidth.

[0064] like Figure 2 As shown, when the power supply voltage changes, the circuit reduces the impact on the output voltage through PMOS and NMOS feedback loops, thereby improving the power supply noise rejection ratio. The closed-loop transfer function is calculated as follows: V dd ·A CG1 -V out ·A CG2 ·(A CS4 +A CD3 ·A CS1 ) = V out V dd It is the power supply voltage, V out It is the output voltage, A CG2 It is the common-gate gain of M2, A CD3 It is the common-drain gain of M3, A CS4 It is the common-source gain of M4, A CG1 It is the common-gate gain of M1, A CS1 It is the common-source gain of M1, V dd ·A CG1 =V out ·[1+A CG2 ·(A CS4 +A CD3 ·A CS1 )].like Figure 1 As shown,

[0065]

[0066] A CS3 ≈1

[0067] Substituting into the transfer function yields the power supply rejection ratio at low frequencies.

[0068] When the load current suddenly increases, the response process is as follows. The load capacitor first discharges, causing the output voltage V to drop. outThe leakage current of M2 decreases rapidly, thus reducing the drain voltage of M2, which in turn lowers the gate voltage of M4, thereby reducing the leakage current of M4. Consequently, some current from M1 flows to the load. Furthermore, because the drain voltage of M2, which is the gate voltage of M3, decreases, the leakage current of M1 increases. Therefore, the gate capacitance of M1 discharges rapidly in response, resulting in a decrease in the gate voltage of M1, which in turn increases the leakage current of M2.

[0069] Once sufficient load current is provided, the output capacitor stops discharging, and the output voltage no longer decreases.

[0070] The advantages of the circuit proposed in this article are:

[0071] First, it fully utilizes the characteristic of the push-pull output structure to reduce the gate voltage together, thus solving the problem of slow pull-up current response in FVF LDO.

[0072] Second: The addition of an NMOS fast-loop feedback circuit improves the power supply noise rejection ratio.

[0073] Third: A super source follower structure is adopted, which effectively reduces node impedance by constructing a negative feedback loop, thereby increasing the loop bandwidth.

[0074] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A fast response three loop LDO circuit structure, characterized in that, The inverting voltage follower comprises a push-pull output stage, a fast negative feedback loop and a super source follower. The output terminal of the operational amplifier circuit (1) is connected to the negative input terminal, and a reference voltage source V REF The positive input terminal of the operational amplifier circuit (1) is connected to the output terminal, and the negative input terminal of the operational amplifier circuit (1) is connected to the output terminal to form a unit gain negative feedback, and the voltage at the output terminal of the operational amplifier circuit (1) is equal to the reference voltage source V REF ; The output terminal of the operational amplifier circuit (1) is connected to the input terminal of the control voltage generating circuit (2), and the control voltage generating circuit (2) generates an output voltage V CTRL ; The output terminal of the control voltage generating circuit (2) is connected to the input terminal of the inverting voltage follower (3), and then the reference voltage source V REF is copied to the output terminal V OUT of the inverting voltage follower (3); The push-pull output stage comprises a fourth MOS transistor M4 and a first MOS transistor M1. The fast negative feedback loop comprises the fourth MOS transistor M4, a third MOS transistor M3, a second MOS transistor M2 and the first MOS transistor M1. The super source follower comprises the third MOS transistor M3 and a fifteenth MOS transistor M15. The drain of the first MOS transistor M1 is connected to the source of the second MOS transistor M2 and the drain of the fourth MOS transistor M4. The drain of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4. The gate of the first MOS transistor M1 is connected to the source of the third MOS transistor M3 and the drain of the fifteenth MOS transistor M15. The drain of the third MOS transistor M3 is connected to the gate of the fifteenth MOS transistor M15. The operational amplifier circuit (1) comprises an operational amplifier OPA. The control voltage generating circuit (2) comprises a tenth MOS transistor M10 and a twelfth MOS transistor M12. The inverting voltage follower (3) further comprises a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14 and a sixteenth MOS transistor M16. The source of the first MOS transistor M1, the source of a fifth MOS transistor M5, the source of a sixth MOS transistor M6, the source of the seventh MOS transistor M7, the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are connected to a power supply. The drain of the ninth MOS transistor M9 is connected to the drain of the eighth MOS transistor M8 and the gate of the ninth MOS transistor M9. Current source I BIAS the input terminal of the first MOS transistor Ml, the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7, the gate of the eighth MOS transistor M8, and the gate of the fifth MOS transistor M5 are connected to the drain of the fifth MOS transistor M5; The gate of the second MOS transistor M2 is connected to the drain of the tenth MOS transistor M10, the gate of the tenth MOS transistor M10 and the drain of the twelfth MOS transistor M12. The drain of the first MOS transistor M1 is connected to one end of the load capacitor C LOAD The output terminal V OUT out The drain of the second MOS transistor M2 is connected to the drain of the sixteenth MOS transistor M16. The drain of the third MOS transistor M3 is connected to the drain of the fourteenth MOS transistor M14. The drain of the sixth MOS transistor M6 is connected to the drain of an eleventh MOS transistor M11, the gate of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12. The drain of the seventh MOS transistor M7 is connected to the gate of the thirteenth MOS transistor M13, the drain of the thirteenth MOS transistor M13, the gate of the fourteenth MOS transistor M14 and the gate of the sixteenth MOS transistor M16. The source of the tenth MOS transistor M10 is connected to the negative input of the operational amplifier OPA and the output of the operational amplifier OPA. ​ current source I BIAS the other end of the current source I, the source of the eleventh MOS transistor M11, the source of the twelfth MOS transistor M12, the source of the thirteenth MOS transistor M13, the source of the fourteenth MOS transistor M14, the source of the fifteenth MOS transistor M15, the source of the sixteenth MOS transistor M16, the source of the fourth MOS transistor M4, the load capacitor C LOAD the other end of the load capacitor C is connected to the ground line GND.

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