I2c interface and interface chip

Abstract

The application discloses an I2C interface and an interface chip, the I2C interface comprises a push-pull output module and a data interface; the push-pull output module is used for controlling the in-chip data signal of a target chip to be output from the data interface to outside the chip in response to a first configuration signal, and the first configuration signal is used for representing that the I2C interface is configured as a push-pull mode in an I3C mode. The application controls the in-chip data signal of the target chip to be output from the data interface to outside the chip based on the push-pull mode in the I3C mode in response to the first configuration signal through the push-pull output module, so that the I2C interface of the application can be compatible with the push-pull mode in the I3C mode, the communication rate is greatly improved, the application scene of the I2C interface is expanded, and the adaptability is more extensive.

Description

Technical Field

[0001] This application relates to the field of communication interface technology, specifically to an I2C interface and an interface chip. Background Technology

[0002] The Inter-Integrated Circuit (IIC) interface, also known as the I2C interface, is a half-duplex, bidirectional two-wire serial communication interface, mainly used to connect microcontrollers and other peripheral devices, such as sensors, memory, and displays.

[0003] Based on the I2C protocol, I2C communication only requires two signal lines to complete information exchange, thus simplifying wiring and reducing costs. However, the I2C communication speed in related technologies is relatively slow; even in high-speed mode, its maximum transmission rate is only 3.4 Mbps, which greatly limits the application scenarios of the I2C interface. Summary of the Invention

[0004] In view of the above problems, this application provides an I2C interface and an interface chip to solve the above technical problems.

[0005] In a first aspect, this application provides an I2C interface, which includes a push-pull output module and a data interface; the push-pull output module is used to control the on-chip data signal of the target chip to be output from the data interface to the off-chip in response to a first configuration signal; wherein, the first configuration signal is used to characterize the I2C interface as a push-pull mode in I3C mode.

[0006] In one possible implementation of this application, the push-pull output module includes a first switching unit and a push-pull control unit. A first end of the first switching unit is connected to a power output terminal, and a second end of the first switching unit is connected to an open-drain output module of a data interface and an I2C interface. The control terminal of the first switching unit is connected to the push-pull control unit. The push-pull control unit is used to output an inverted data signal of the on-chip data signal to the first switching unit in response to a first configuration signal. The first switching unit is used to cooperate with the open-drain output module to generate an interface output signal in response to the inverted data signal and output it to the data interface. The interface output signal is inverted from the inverted data signal.

[0007] In one possible implementation of this application, the push-pull control unit includes a push-pull mode configuration subunit, a signal output subunit, and a first OR gate; the push-pull mode configuration subunit is used to invert a first configuration signal to obtain a first inverted signal and output it to the first OR gate; wherein, the first inverted signal is a low-level signal; the signal output subunit is used to invert an on-chip data signal to obtain an inverted data signal and output it to the first OR gate; the first OR gate is used to perform an OR operation on the first inverted signal and the inverted data signal, and output the inverted data signal to the first switching unit.

[0008] In one possible implementation of this application, the push-pull mode configuration subunit includes a first AND gate and a first NOT gate. The first configuration signal includes an output configuration signal, a first enable signal, and a push-pull enable signal, all configured to be active. The first AND gate performs an AND operation on the output configuration signal, the first enable signal, and the push-pull enable signal to generate a push-pull drive signal. The output configuration signal, configured to be active, indicates that the SDA data line of the I2C interface is in output mode. The first enable signal, configured to be active, indicates that the I2C interface is operating in I3C mode. The push-pull enable signal, configured to be active, indicates that the I2C interface operating in I3C mode is configured in push-pull mode. The first NOT gate inverts the push-pull drive signal to obtain a first inverted signal.

[0009] In one possible implementation of this application, the I2C interface further includes an open-drain output module connected to the data interface; the open-drain output module is used to control the on-chip data signal to be output from the data interface to the off-chip in response to a second configuration signal or a third configuration signal; wherein, the second configuration signal is used to characterize the open-drain mode of the I2C interface operating in I3C mode; the third configuration signal is used to characterize the open-drain mode of the I2C interface operating in I2C mode.

[0010] In one possible implementation of this application, the open-drain output module includes a second switching unit and an open-drain control unit. The first end of the second switching unit is connected to a data interface, and the data interface is also connected to a pull-up resistor. The second end of the second switching unit is connected to a ground terminal, and the control terminal of the second switching unit is connected to the open-drain control unit. The open-drain control unit is used to output an inverted data signal of the on-chip data signal to the second switching unit in response to a second configuration signal or a third configuration signal. The second switching unit is used to generate an interface output signal in response to the inverted data signal and output it to the data interface. The interface output signal is inverted from the inverted data signal.

[0011] In one possible implementation of this application, the open-drain control unit includes a first open-drain configuration subunit, a second open-drain configuration subunit, a second OR gate, a signal output subunit, and a second AND gate. The first open-drain configuration subunit is used to generate a second drive signal based on a second configuration signal and output it to the second OR gate when the I2C interface is operating in open-drain mode under I2C mode, and to output an inverted signal of the second drive signal to the second OR gate when the I2C interface is operating in open-drain mode under I2C mode; wherein the second drive signal is a high-level signal. The second open-drain configuration subunit is used to generate a signal based on a third configuration signal when the I2C interface is operating in open-drain mode under I2C mode. The third drive signal is output to the second OR gate, and when the I2C interface is operating in open-drain mode under I3C mode, the inverted signal of the third drive signal is output to the second OR gate; wherein, the third drive signal is a high-level signal; the second OR gate is used to perform an OR operation on the inverted signals of the second and third drive signals, or the inverted signals of the third and second drive signals, and outputs the first valid signal to the second AND gate; the signal output subunit is used to invert the on-chip data signal and output the inverted data signal to the second AND gate; the second AND gate is used to perform an AND operation on the first valid signal and the inverted data signal and output the inverted data signal to the second switching unit.

[0012] In one possible implementation of this application, the first open-drain configuration subunit includes a third AND gate, a fourth AND gate, a third OR gate, and a fifth AND gate; the second configuration signal includes an open-drain enable signal, an output configuration signal, and a first enable signal, all configured to be active, and a push-pull enable signal configured to be inactive; wherein the active open-drain enable signal indicates that the I2C interface is configured in open-drain mode, the active output configuration signal indicates that the SDA data line of the I2C interface is in output mode, and the active first enable signal... The third AND gate is used to characterize the I2C interface operating in I3C mode; the third AND gate is used to perform an AND operation on the inverted signals of the open-drain enable signal and the push-pull enable signal to generate a first signal output to the third OR gate; the fourth AND gate is used to perform an AND operation on the inverted signal of the open-drain enable signal and the push-pull enable signal to generate a second signal output to the third OR gate; the third OR gate is used to perform an OR operation on the first signal and the second signal to generate a third signal output to the fifth AND gate; the fifth AND gate is used to perform an AND operation on the third signal, the output configuration signal and the first enable signal to generate a second drive signal.

[0013] In one possible implementation of this application, the second open-drain configuration subunit includes a sixth AND gate, and the third configuration signal includes an output configuration signal and an open-drain enable signal configured to be active, and a first enable signal configured to be inactive. The active output configuration signal indicates that the SDA data line of the I2C interface is in output mode, the inactive first enable signal indicates that the I2C interface is operating in I2C mode, and the active open-drain enable signal indicates that the I2C interface operating in I2C mode is configured in open-drain mode. The sixth AND gate performs an AND operation on the output configuration signal, the inverted signal of the first enable signal, and the open-drain enable signal to generate the third drive signal.

[0014] Secondly, this application also provides an interface chip, including a chip body and an I2C interface disposed on the chip body as in any possible implementation of the first aspect.

[0015] From the above, it can be concluded that this application has the following beneficial effects:

[0016] The I2C interface provided in this application responds to the first configuration signal through a push-pull output module, controlling the on-chip data signal of the target chip to be output from the data interface to the off-chip in the push-pull mode of I3C mode. This makes the I2C interface of this application compatible with the push-pull mode of I3C mode, thereby greatly improving the communication speed, expanding the application scenarios of the I2C interface, and making it more adaptable. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a connection used to implement I2C communication in related technologies;

[0019] Figure 2 This is a schematic diagram of one structure of the I2C interface provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of a push-pull output module provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of a structure of the first switching unit provided in the embodiments of this application;

[0022] Figure 5This is a schematic diagram of a push-pull control unit provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of a push-pull mode configuration subunit provided in the embodiments of this application;

[0024] Figure 7 This is another schematic diagram of the I2C interface provided in the embodiments of this application;

[0025] Figure 8 This is a schematic diagram of an open-drain output module provided in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of a structure of the second switching unit provided in the embodiments of this application;

[0027] Figure 10 This is a schematic diagram of a structure of the open-drain control unit provided in the embodiments of this application;

[0028] Figure 11 This is another structural schematic diagram of the open-drain control unit provided in the embodiments of this application;

[0029] Figure 12 This is another structural schematic diagram of the open-drain control unit provided in the embodiments of this application;

[0030] Figure 13 This is another schematic diagram of the I2C interface provided in the embodiments of this application. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0034] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0035] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0036] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0037] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0038] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0039] Before introducing the I2C interface and interface chip of this application, we will first introduce the relevant background information of the embodiments of this application.

[0040] The I2C bus uses a master-slave bus architecture. Each device on the bus has a specific device address to distinguish it from other devices on the same I2C bus. Devices connected to the I2C bus can be used as either a master or a slave; and I2C communication is always initiated by the master device, while the slave device passively receives responses.

[0041] like Figure 1 As shown, Device 1 and Device 2 are each equipped with an I2C interface. This I2C interface uses a two-wire structure for data transmission, including one serial data line (SDA) and one serial clock line (SCL). The SDA line is used for bidirectional data transmission, while the SCL line is used as a clock signal for synchronous data transmission. This simple wiring method makes interconnection between devices very easy and reduces communication costs.

[0042] However, the traditional I2C communication has a low data transmission rate. The data transmission rate in standard mode is only 0.1Mbps, and the data transmission rate in fast mode is only 0.4Mbps. Even in high-speed mode, the data transmission rate can only reach a maximum of 3.4Mbps, which makes the I2C interface unsuitable for application scenarios with higher communication rate requirements.

[0043] Based on this, this application provides an I2C interface and an interface chip. This I2C interface can not only realize traditional I2C communication, but also be compatible with I3C communication, thereby greatly improving the communication speed and expanding the application scenarios of the I2C interface.

[0044] The I2C interface and interface chip provided in this application will be described in detail below.

[0045] First, this application provides an I2C interface, such as... Figure 2 As shown, the I2C interface 10 may include a push-pull output module 100 and a data interface 200. The push-pull output module 100 may be used to control the on-chip data signal of the target chip 20 to be output from the data interface 200 to the off-chip in response to a first configuration signal. The first configuration signal may be used to indicate that the I2C interface is configured as a push-pull mode in I3C mode.

[0046] The I2C interface 10 is connected to the target chip 20 and can transmit on-chip data to off-chip data or vice versa. The specific signal flow direction can be determined according to the actual application scenario. In some embodiments, the I2C interface 10 can also be integrated into the target chip 20 to realize signal transmission.

[0047] In this embodiment, the target chip 20 can be any existing controller such as a microcontroller unit (MCU) or a single-chip microcomputer. The first configuration signal can be a signal generated by the target chip 20 or other control units in the device; for example, the target chip 20 can generate the first configuration signal and output it to the push-pull output module 100 by configuring a general-purpose input / output (GPIO) port; or the target chip 20 can also generate the first configuration signal and output it to the push-pull output module 100 by configuring registers in software. This first configuration signal can drive the push-pull output module 100 to operate, causing the I2C interface 10 to operate in push-pull mode under I3C conditions.

[0048] Specifically, after receiving the first configuration signal, the push-pull output module 100 can respond to the first configuration signal to start signal transmission and control the on-chip data signal from the target chip 20 to be output by the data interface 200 in push-pull mode under I3C mode. That is, the I2C interface 10 in this embodiment can be compatible with the I3C interface to realize push-pull mode under I3C mode; it can be understood that the transmission rate of I3C communication is much higher than that of I2C communication, therefore, the data transmission rate of I2C interface 10 can be improved.

[0049] The I2C interface 10 provided in this application embodiment responds to the first configuration signal through the push-pull output module 100, controlling the on-chip data signal of the target chip 20 to be output from the data interface 200 to the off-chip based on the push-pull mode in I3C mode. This makes the I2C interface 10 compatible with the push-pull mode in I3C mode, thereby greatly improving the communication speed, expanding the application scenarios of the I2C interface 10, and making it more adaptable.

[0050] Next, continue with Figure 2 The modules shown are described in detail, along with the specific implementation methods that may be used in practical applications.

[0051] like Figure 3As shown, in some embodiments of this application, the push-pull output module 100 may include a first switching unit 110 and a push-pull control unit 120. The first end of the first switching unit 110 may be connected to the power output terminal, the second end of the first switching unit 110 may be connected to the data interface 200, and the control terminal of the first switching unit 110 may be connected to the push-pull control unit 120. The push-pull control unit 120 may be used to output an inverted data signal of the on-chip data signal to the first switching unit 110 in response to a first configuration signal. The first switching unit 110 may be connected to the open-drain output module 300 of the I2C interface 10 and used to cooperate with the open-drain output module 300 to generate an interface output signal in response to the inverted data signal and output it to the data interface 200. The interface output signal is inverted from the inverted data signal.

[0052] Understandably, the I2C interface 10 can also be configured with an open-drain output module 300, which can also be connected to the data interface 200 to realize the open-drain mode in the I2C mode.

[0053] In this embodiment, the push-pull control unit 120 can be connected to the target chip 20, access the on-chip data signal, and upon receiving the first configuration signal, output an inverted data signal to the control terminal of the first switching unit 110 in response to the first configuration signal; it can be understood that the inverted data signal is the inverted signal of the on-chip data signal. The first switching unit 110 can then invert the inverted data signal again to generate an interface output signal to be output to the data interface 200. It can be understood that the interface output signal at this time is a signal in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the external interface.

[0054] In this embodiment, the first switching unit 110 can be implemented using a switching transistor, including but not limited to a metal-oxide-semiconductor field-effect transistor (MOSFET / MOS), a triode, a parallel triode or MOS transistor, etc. The specific implementation can be determined according to the actual application scenario, and is not limited here.

[0055] like Figure 4 As shown, as an example, the first switching unit 110 includes a P-type MOS transistor. The gate of the P-type MOS transistor is connected to the push-pull control unit 120 and receives an inverted data signal; the source is connected to the power output terminal and receives the voltage signal vddpp output by the power output terminal; the drain is connected to the data interface 200, and the output interface outputs a signal to the data interface 200.

[0056] Based on the characteristics of the P-type MOSFET, when the inverted data signal is low level "0", the P-type MOSFET is turned on. Since its source is connected to a voltage signal vddpp, the interface output signal generated to the data interface 200 is high level "1", realizing the inversion of the interface output signal with the inverted data signal. Since the inverted data signal is out of phase with the on-chip data signal, the interface output signal is in phase with the on-chip data signal, realizing the output of the on-chip data signal to the off-chip.

[0057] Since the on-resistance Rds(on) between the drain and source of a P-type MOSFET is much smaller than the pull-up resistor (not shown in the figure) used for open-drain output at data interface 200, the use of a P-type MOSFET as a pull-up resistor greatly improves the signal transmission rate compared to I2C mode.

[0058] When the inverted data signal is high level "1", the P-type MOS transistor is turned off. At this time, the open-drain output module 300 can be controlled to function, generating a low level "0" interface output signal to be output to the data interface 200, thereby realizing the transmission of on-chip data signals.

[0059] like Figure 5 As shown, in some embodiments of this application, the push-pull control unit 120 may include a push-pull mode configuration subunit 1201, a signal output subunit 1202, and a first OR gate OR1; the push-pull mode configuration subunit 1201 may be used to invert a first configuration signal to obtain a first inverted signal and output it to the first OR gate OR1; wherein, the first inverted signal is a low-level signal "0"; the signal output subunit 1202 may be used to invert an on-chip data signal to obtain an inverted data signal and output it to the first OR gate OR1; the first OR gate OR1 may be used to perform an "OR" operation on the first inverted signal and the inverted data signal to output the inverted data signal to the first switching unit 110.

[0060] In this embodiment of the application, the push-pull mode configuration subunit 1201 can be connected to the target chip 20 or other control unit, receive the first configuration signal, and then perform inversion processing on the first configuration signal to obtain the first inverted signal output to the first OR gate OR1.

[0061] The signal output subunit 1202 can be connected to the target chip 20, receive the on-chip data signal, and perform inversion processing on the on-chip data signal to obtain an inverted data signal output to the first OR gate OR1. In this embodiment, the signal output subunit 1202 can be any existing inverter or logic NOT circuit, which can be determined according to the actual application scenario and is not limited here.

[0062] The first OR gate OR1 performs an OR operation on the input first inverted signal and the inverted data signal. Since the inverted data signal needs to be output to the first switching unit 110, according to the working principle of the OR gate, when one of the two input signals is low level "0", the output signal of the OR gate depends on the other input signal. Therefore, in this embodiment, the first inverted signal is a low level signal "0", and the corresponding first configuration signal is a high level signal "1". This ensures that the inverted data signal, which is inverse of the on-chip data signal, is output to the first switching unit 110. After being inverted again by the first switching unit 110, an interface output signal in phase with the on-chip data signal is generated and output from the data interface 200, thereby realizing the transmission of the on-chip data signal to the off-chip.

[0063] like Figure 6 As shown, in some embodiments of this application, the push-pull mode configuration subunit 1201 may include a first AND gate AND1 and a first NOT gate NOT1. The first configuration signal may include an output configuration signal sda_set, a first enable signal i3c_en, and a push-pull enable signal pp_output_en, all configured to be active. The first AND gate AND1 can be used to perform an AND operation on the output configuration signal sda_set, the first enable signal i3c_en, and the push-pull enable signal pp_output_en to generate a push-pull drive signal. The output configuration signal sda_set, configured to be active, can be used to indicate that the SDA data line of the I2C interface 10 is in output mode. The first enable signal i3c_en, configured to be active, can be used to indicate that the I2C interface 10 is operating in I3C mode. The push-pull enable signal pp_output_en, configured to be active, can be used to indicate that the I2C interface 10 operating in I3C mode is configured in push-pull mode. The first NOT gate NOT1 can be used to invert the push-pull drive signal to obtain a first inverted signal.

[0064] In this embodiment, the output configuration signal sda_set, the first enable signal i3c_en, and the push-pull enable signal pp_output_en can all be configured to be active levels. The active level can be a high level "1" or a low level "0". The specific level can be determined according to the actual application scenario, and is not limited here.

[0065] As an example, if the effective level is high level "1", then the output configuration signal sda_set, the first enable signal i3c_en, and the push-pull enable signal pp_output_en are input to the first AND gate AND1. After the first AND gate AND1 performs an AND operation, a push-pull drive signal that is also high level "1" is obtained and output to the first NOT gate NOT1. Then, the push-pull drive signal is inverted by the first NOT gate NOT1 to generate a low level "0" first inverted signal, which is output to the first OR gate OR1. This allows the output of the first OR gate OR1 to depend entirely on the inverted data signal, ensuring that the on-chip data signal can be output to the off-chip quickly and accurately in push-pull mode.

[0066] like Figure 7 As shown, in some embodiments of this application, the I2C interface 10 may further include an open-drain output module 300 connected to the data interface 200; the open-drain output module 300 may be used to control the output of on-chip data signals from the data interface to off-chip in response to a second configuration signal or a third configuration signal; wherein, the second configuration signal may be used to characterize the open-drain mode of the I2C interface 10 operating in I3C mode; the third configuration signal may be used to characterize the open-drain mode of the I2C interface 10 operating in I2C mode.

[0067] In this embodiment, both the second and third configuration signals can be signals generated by the target chip 20 or other control units in the device. For example, the target chip 20 can generate the second or third configuration signal and output it to the open-drain output module 300 by configuring GPIO; or the target chip 20 can generate the second or third configuration signal and output it to the open-drain output module 300 by configuring registers in software. The second configuration signal can drive the open-drain output module 300 to operate, enabling the I2C interface 10 to operate in open-drain mode under I2C mode; the third configuration signal can drive the open-drain output module 300 to operate, enabling the I2C interface 10 to operate in open-drain mode under I2C mode, thus realizing the open-drain transmission function of the traditional I2C interface.

[0068] Specifically, after receiving the second configuration signal, the open-drain output module 300 can respond to the second configuration signal to enable signal transmission, controlling the on-chip data signal from the target chip 20 to be output by the data interface 200 in open-drain mode based on I3C mode. Alternatively, after receiving the third configuration signal, the open-drain output module 300 can respond to the third configuration signal to enable signal transmission, controlling the on-chip data signal from the target chip 20 to be output by the data interface 200 in open-drain mode based on I2C mode.

[0069] In other words, the I2C interface 10 in this embodiment is compatible with the I3C interface. In addition to the open-drain mode in the traditional I2C mode, it can also realize three signal transmission modes in the I3C mode: push-pull mode and open-drain mode. This greatly expands the application scenarios of the I2C interface 10 and makes it more adaptable.

[0070] like Figure 8 As shown, in some embodiments of this application, the open-drain output module 300 may include a second switching unit 310 and an open-drain control unit 320. The first end of the second switching unit 310 may be connected to the data interface 200, and the data interface 200 may also be connected to a pull-up resistor (not shown in the figure). The second end of the second switching unit 310 may be connected to the ground terminal GND, and the control terminal of the second switching unit 310 may be connected to the open-drain control unit 320. The open-drain control unit 320 may be used to output an inverted data signal of the on-chip data signal to the second switching unit 310 in response to a second configuration signal or a third configuration signal. The second switching unit 310 may be used to generate an interface output signal in response to the inverted data signal and output it to the data interface 200. The interface output signal is inverted from the inverted data signal.

[0071] In this embodiment, the open-drain control unit 320 can be connected to the target chip 20, access the on-chip data signal, and upon receiving a second configuration signal or a third configuration signal, output an inverted data signal to the control terminal of the second switching unit 310 in response to the received configuration signal; it can be understood that this inverted data signal is the inverted signal of the on-chip data signal. The second switching unit 310 can then invert the inverted data signal again to generate an interface output signal to be output to the data interface 200. It can be understood that the interface output signal at this time is a signal in phase with the on-chip data signal, thereby realizing the output of the on-chip data signal to the external interface.

[0072] In this embodiment, the second switching unit 310 can also be implemented using a switching transistor, including but not limited to MOSFETs, transistors, parallel transistors or MOSFETs, etc. The specific type can be determined according to the actual application scenario, and is not limited here.

[0073] like Figure 9 As shown, as an example, the second switching unit 310 includes an N-type MOS transistor. The gate of the N-type MOS transistor is connected to the open-drain control unit 320 and receives an inverted data signal; the drain is connected to the data interface 200 and the output interface outputs a signal to the data interface 200; the source is connected to the ground terminal GND.

[0074] Based on the characteristics of an N-type MOSFET, when the inverted data signal is high ("1"), the N-type MOSFET is turned on. Since its source is connected to ground (GND), the potential of the data interface 200 is pulled low to ground, resulting in a low-level "0" output signal to the data interface 200. When the inverted data signal is low ("0"), the N-type MOSFET is turned off. Since the data interface 200 is connected to a pull-up resistor (not shown in the figure), the pull-up resistor can pull the potential of the data interface 200 high, resulting in a high-level "1" output signal to the data interface 200. Because the inverted data signal is out of phase with the on-chip data signal, the interface output signal is in phase with the on-chip data signal, thus enabling the on-chip data signal to be output to the external device.

[0075] like Figure 10 As shown, in some embodiments of this application, the open-drain control unit 320 may include a first open-drain configuration subunit 3201, a second open-drain configuration subunit 3202, a second OR gate OR2, a signal output subunit, and a second AND gate AND2; the first open-drain configuration subunit 3201 may be used to generate a second drive signal according to a second configuration signal and output it to the second OR gate OR2 when the I2C interface 10 is operating in the open-drain mode of I2C mode, and to output the inverted signal of the second drive signal to the second OR gate OR2 when the I2C interface 10 is operating in the open-drain mode of I2C mode; wherein, the second drive signal is a high-level signal; the second open-drain configuration subunit 3202 may be used to generate a second drive signal according to a third configuration signal and output it to the second OR gate OR2 when the I2C interface 10 is operating in the open-drain mode of I2C mode, and to output the inverted signal of the second drive signal to the second OR gate OR2; wherein, the second drive signal is a high-level signal; the second open-drain configuration subunit 3202 may be used to generate a second drive signal according to a third configuration signal and output it to the second OR gate OR2 when the I2C interface 10 is operating in the open-drain mode of I2C mode. The signal generation generates a third drive signal and outputs it to the second OR gate OR2. When the I2C interface 10 is operating in open-drain mode under I3C mode, the inverted signal of the third drive signal is output to the second OR gate OR2. The third drive signal is a high-level signal. The second OR gate OR2 can be used to perform an OR operation on the inverted signals of the second and third drive signals, or the inverted signals of the third and second drive signals, and output a first valid signal to the second AND gate AND2. The signal output subunit can be used to invert the on-chip data signal to obtain an inverted data signal and output it to the second AND gate AND2. The second AND gate AND2 can be used to perform an AND operation on the first valid signal and the inverted data signal and output the inverted data signal to the second switching unit 310.

[0076] Reference Figure 10 In this embodiment, the signal output subunit of the open-drain control unit 320 can reuse the signal output subunit 1202 in the push-pull control unit 120, simplifying the circuit structure.

[0077] It is understandable that in some other embodiments, the signal output subunit of the open-drain control unit 320 may also be a separate unit module distinct from the signal output subunit 1202, for example... Figure 11 The first signal output subunit 3203 shown in the figure can also be connected to the target chip 20, receive the on-chip data signal, and perform inversion processing on the on-chip data signal to obtain an inverted data signal output to the second AND gate AND2. In this embodiment, the first signal output subunit 3203 can also be any existing inverter or logic NOT circuit, which can be determined according to the actual application scenario, and is not limited here.

[0078] The first open-drain configuration subunit 3201 can be connected to the target chip 20 or other control units, receive the second configuration signal, and when the I2C interface 10 is operating in open-drain mode under I3C mode, generate a second drive signal based on the second configuration signal and output it to the second OR gate OR2. Similarly, the second open-drain configuration subunit 3202 can also be connected to the target chip 20 or other control units. When the I2C interface 10 is operating in open-drain mode under I3C mode, it can output the inverted signal of the third drive signal to the second OR gate OR2. Since the third drive signal is a high level "1", its inverted signal is a low level "0", while the second drive signal is a high level "1". Thus, the first valid signal output by the second OR gate OR2 is a high level "1". According to the working principle of the AND gate, when one of its two input signals is a high level "1", its output signal depends on the other input signal. That is, the output of the second AND gate AND2 depends on the inverted data signal. This ensures that the inverted data signal, which is inverse of the on-chip data signal, is output to the second switching unit 310. After being inverted again by the second switching unit 310, an interface output signal in phase with the on-chip data signal is generated and output from the data interface 200. This enables the on-chip data signal to be transmitted to the off-chip when the I2C interface 10 is operating in the open-drain mode of the I3C mode.

[0079] When the I2C interface 10 operates in open-drain mode under I2C mode, the second open-drain configuration subunit 3202 can generate a third drive signal based on the received third configuration signal and output it to the second OR gate OR2; the first open-drain configuration subunit 3201 can output the inverted signal of the second drive signal to the second OR gate OR2; since the second drive signal is high level "1", its inverted signal is low level "0", and the third drive signal is high level "1", so the first valid signal output by the second OR gate OR2 is still high level "1"; similarly, at this time, the output of the second AND gate AND2 depends on the inverted data signal, ensuring that the inverted data signal that is inverted from the on-chip data signal is output to the second switching unit 310. After being inverted again by the second switching unit 310, an interface output signal that is in phase with the on-chip data signal is generated and output from the data interface 200, so that the on-chip data signal can be transmitted to the off-chip when the I2C interface 10 operates in open-drain mode under I2C mode.

[0080] like Figure 12 As shown, in some embodiments of this application, the first open-drain configuration subunit 3201 may include a third AND gate AND3, a fourth AND gate AND4, a third OR gate OR3, and a fifth AND gate AND5; the second configuration signal may include an open-drain enable signal od_mode_en, an output configuration signal sda_set, and a first enable signal i3c_en, all configured to be active, and a push-pull enable signal pp_output_en, configured to be inactive; wherein, the active open-drain enable signal od_mode_en can be used to characterize that the I2C interface 10 is configured in open-drain mode, the active output configuration signal sda_set can be used to characterize that the SDA data line of the I2C interface 10 is in output mode, and the active first enable signal i3c_en can be used to characterize that the I2C interface 10 is in output mode. The I2C interface 10 is characterized to operate in I3C mode; the third AND gate AND3 can be used to perform an AND operation on the open-drain enable signal od_mode_en and the inverted push-pull enable signal pp_output_enb to generate a first signal output to the third OR gate OR3; the fourth AND gate AND4 can be used to perform an AND operation on the inverted open-drain enable signal od_mode_enb and the push-pull enable signal pp_output_en to generate a second signal output to the third OR gate OR3; the third OR gate OR3 can be used to perform an OR operation on the first and second signals to generate a third signal output to the fifth AND gate AND5; the fifth AND gate AND5 can be used to perform an AND operation on the third signal, the output configuration signal sda_set, and the first enable signal i3c_en to generate a second drive signal.

[0081] In this embodiment, the third AND gate AND3, the fourth AND gate AND4, and the fifth AND gate AND5 can be connected to the target chip 20 or other control units to access the second configuration signal. When the I2C interface 10 is operating in the open-drain mode of the I3C mode, the second configuration signal can include an open-drain enable signal od_mode_en configured to be active, an output configuration signal sda_set configured to be active, a first enable signal i3c_en configured to be active, and a push-pull enable signal pp_output_en configured to be inactive.

[0082] For example, if a high level "1" is the effective level for each signal, then the push-pull enable signal pp_output_en is a low level "0", and its inverted signal pp_output_enb is a high level "1". Therefore, the open-drain enable signal od_mode_en (high level "1") and the inverted signal pp_output_enb (high level "1") of the push-pull enable signal are ANDed by the third AND gate AND3, outputting the first signal (high level "1") to the third OR gate OR3; while the inverted signal od_mode_enb (low level "0") of the open-drain enable signal... The push-pull enable signal pp_output_en, which is enb and low-level "0", is ANDed by the fourth AND gate AND4, and outputs a second signal with low-level "0" to the third OR gate OR3. The third OR gate OR3 performs an OR operation on the first signal with high-level "1" and the second signal with low-level "0", and outputs a third signal with high-level "1" to the fifth AND gate AND5. Since the output configuration signal sda_set and the first enable signal i3c_en are also high-level "1", the fifth AND gate AND5 outputs a second drive signal with high-level "1" to the second OR gate OR2.

[0083] When the I2C interface 10 is operating in open-drain mode under I2C mode, since the first enable signal i3c_en is low level "0", the fifth AND gate AND5 outputs a low level "0", which is the inverted signal of the second drive signal to the second OR gate OR2.

[0084] When the I2C interface 10 operates in push-pull mode under I3C mode, the inverted signal pp_output_enb of the low-level "0" open-drain enable signal od_mode_en and the push-pull enable signal pp_output_enb are ANDed by the third AND gate AND3, outputting a low-level "0" first signal to the third OR gate OR3; while the inverted signal od_mode_enb of the high-level "1" open-drain enable signal od_mode_enb and the push-pull enable signal pp_output_enb of the high-level "1" are ANDed by the fourth AND gate AND4, outputting a high-level "1" second signal to the third OR gate OR3; the third OR gate OR3 performs an OR operation on the high-level "1" second signal and the low-level "0" first signal, producing a high-level "1" signal. The third signal is output to the fifth AND gate AND5. Since the output configuration signal sda_set and the first enable signal i3c_en are both high level "1", the fifth AND gate AND5 outputs a high level "1" second drive signal to the second OR gate OR2, ensuring that the second OR gate OR2 outputs a high level "1" first valid signal to the second AND gate AND2. Since the other input signal of the second AND gate AND2 is an inverted data signal, when the inverted data signal is high level "1" and causes the first switch unit 110 to be turned off, the second switch unit 310 can be turned on based on the high level "1" inverted data signal, thereby pulling the potential of the data interface 200 low and forming a low level "0" interface output signal, ensuring that the interface output signal is in phase with the on-chip data signal.

[0085] Please continue reading. Figure 12 In some embodiments of this application, the second open-drain configuration subunit 3202 may include a sixth AND gate AND6, and the third configuration signal may include an output configuration signal sda_set and an open-drain enable signal od_mode_en configured to be active, and a first enable signal i3c_en configured to be inactive. The active output configuration signal sda_set can be used to indicate that the SDA data line of the I2C interface 10 is in output mode, the inactive first enable signal i3c_en can be used to indicate that the I2C interface 10 is operating in I2C mode, and the active open-drain enable signal od_mode_en can be used to indicate that the I2C interface 10 operating in I2C mode is configured in open-drain mode. The sixth AND gate AND6 can be used to perform an AND operation on the output configuration signal sda_set, the inverted signal i3c_enb of the first enable signal, and the open-drain enable signal od_mode_en to generate the third drive signal.

[0086] In this embodiment, the sixth AND gate AND6 can be connected to the target chip 20 or other control unit and access the third configuration signal. When the I2C interface 10 is working in the open-drain mode of I2C mode, the third configuration signal can include the open-drain enable signal od_mode_en configured to be active, the output configuration signal sda_set configured to be active, and the first enable signal i3c_en configured to be inactive.

[0087] For example, if a high level "1" is the effective level for each signal, then the open-drain enable signal od_mode_en of high level "1", the output configuration signal sda_set of high level "1" and the inverted signal i3c_enb of the first enable signal of high level "1" are ANDed by the sixth AND gate AND6, and the third drive signal of high level "1" is output to the second OR gate OR2.

[0088] When the I2C interface 10 is operating in open-drain mode under I3C mode, since the first enable signal i3c_en is low level "1", the inverting signal i3c_enb is low level "0", so the sixth AND gate AND6 outputs low level "0", which is the inverted signal of the third drive signal to the second OR gate OR2.

[0089] like Figure 13 As shown, the signal output subunit 1202 may include a second NOT gate 2, which inverts the on-chip data signal data_out to form an inverted data signal output. It is understood that, in addition to outputting the on-chip data signal data_out from the data interface 200 to the external chip, the I2C interface 10 in this embodiment can also receive signals from the data interface 200, transmitting signals from the external chip to the internal chip, allowing the target chip 20 to receive the data_in signal. Specifically, after the external data signal is received by the data interface 200, it can be processed by a Schmitt trigger one, an interference signal filter, and a Schmitt trigger two to form the data_in signal, which is then transmitted to the target chip 20.

[0090] The I2C interface 10 in this embodiment can realize I2C communication or I3C communication by configuring different configuration signals. Based on the traditional I2C interface, push-pull mode and open-drain mode in I3C mode are added, which improves the signal transmission rate, expands the application range, and has wider adaptability.

[0091] Based on the above embodiments, this application also provides an interface chip, which may include a chip body and such as Figures 2 to 13 The corresponding I2C interface in any embodiment.

[0092] The interface chip can be an integrated circuit (IC), also known as a microcircuit, microchip, or wafer / chip. This chip can be, but is not limited to, a system-on-chip (SOC) or system-in-package (SIP) chip.

[0093] Because this interface chip is equipped with the I2C interface of the above embodiments, it has all the beneficial effects of the I2C interface in any of the above embodiments, which will not be repeated here.

[0094] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An I2C interface, characterized in that, Includes push-pull output module and data interface; The push-pull output module is used to control the on-chip data signal of the target chip to be output from the data interface to the off-chip in response to the first configuration signal; wherein, the first configuration signal is used to indicate that the I2C interface is configured as a push-pull mode in I3C mode; The push-pull output module includes a first switching unit and a push-pull control unit. The first end of the first switching unit is connected to a power output terminal, the second end of the first switching unit is connected to the open-drain output module of the data interface and the I2C interface, and the control terminal of the first switching unit is connected to the push-pull control unit.

2. The I2C interface according to claim 1, characterized in that, The push-pull control unit is configured to respond to the first configuration signal by outputting an inverted data signal of the on-chip data signal to the first switching unit. The first switching unit is used to cooperate with the open-drain output module to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted with the inverted data signal.

3. The I2C interface according to claim 2, characterized in that, The push-pull control unit includes a push-pull mode configuration subunit, a signal output subunit, and a first OR gate; The push-pull mode configuration subunit is used to invert the first configuration signal to obtain a first inverted signal and output it to the first OR gate; wherein, the first inverted signal is a low-level signal; The signal output subunit is used to invert the on-chip data signal to obtain the inverted data signal and output it to the first OR gate. The first OR gate is used to perform an OR operation on the first inverted signal and the inverted data signal, and output the inverted data signal to the first switching unit.

4. The I2C interface according to claim 3, characterized in that, The push-pull mode configuration subunit includes a first AND gate and a first NOT gate. The first configuration signal includes an output configuration signal, a first enable signal, and a push-pull enable signal, all configured to be active. The output configuration signal, configured to be active, indicates that the SDA data line of the I2C interface is in output mode. The first enable signal, configured to be active, indicates that the I2C interface is operating in I3C mode. The push-pull enable signal, configured to be active, indicates that the I2C interface operating in I3C mode is configured in push-pull mode. The first AND gate is used to perform an AND operation on the output configuration signal, the first enable signal, and the push-pull enable signal to generate a push-pull drive signal. The first NOT gate is used to invert the push-pull drive signal to obtain the first inverted signal.

5. The I2C interface according to claim 1, characterized in that, The open-drain output module is used to control the on-chip data signal to be output from the data interface to the off-chip in response to a second configuration signal or a third configuration signal; wherein, the second configuration signal is used to characterize the open-drain mode of the I2C interface operating in I3C mode; and the third configuration signal is used to characterize the open-drain mode of the I2C interface operating in I2C mode.

6. The I2C interface according to claim 5, characterized in that, The open-drain output module includes a second switching unit and an open-drain control unit. The first end of the second switching unit is connected to the data interface, and the data interface is also connected to a pull-up resistor. The second end of the second switching unit is connected to the ground terminal, and the control terminal of the second switching unit is connected to the open-drain control unit. The open-drain control unit is configured to output an inverted data signal of the on-chip data signal to the second switching unit in response to the second configuration signal or the third configuration signal; The second switching unit is used to generate an interface output signal in response to the inverted data signal and output it to the data interface; wherein the interface output signal is inverted compared to the inverted data signal.

7. The I2C interface according to claim 6, characterized in that, The open-drain control unit includes a first open-drain configuration subunit, a second open-drain configuration subunit, a second OR gate, a signal output subunit, and a second AND gate; The first open-drain configuration subunit is configured to generate a second drive signal and output it to the second OR gate according to the second configuration signal when the I2C interface is operating in the open-drain mode of I3C mode, and to output the inverted signal of the second drive signal to the second OR gate when the I2C interface is operating in the open-drain mode of I2C mode; wherein, the second drive signal is a high-level signal; The second open-drain configuration subunit is used to generate a third drive signal and output it to the second OR gate according to the third configuration signal when the I2C interface is operating in the open-drain mode of I2C mode, and to output the inverted signal of the third drive signal to the second OR gate when the I2C interface is operating in the open-drain mode of I3C mode; wherein, the third drive signal is a high-level signal; The second OR gate is used to perform an OR operation on the inverted signal of the second driving signal and the third driving signal, or the inverted signal of the third driving signal and the second driving signal, and output a first valid signal to the second AND gate; The signal output subunit is used to invert the on-chip data signal to obtain the inverted data signal and output it to the second AND gate. The second AND gate is used to perform an AND operation on the first valid signal and the inverted data signal, and output the inverted data signal to the second switching unit.

8. The I2C interface according to claim 7, characterized in that, The first open-drain configuration subunit includes a third AND gate, a fourth AND gate, a third OR gate, and a fifth AND gate; the second configuration signal includes an open-drain enable signal, an output configuration signal, and a first enable signal, all configured to be active, and a push-pull enable signal configured to be inactive; wherein, the open-drain enable signal configured to be active indicates that the I2C interface is configured in open-drain mode, the output configuration signal configured to be active indicates that the SDA data line of the I2C interface is in output mode, and the first enable signal configured to be active indicates that the I2C interface is operating in I3C mode; The third AND gate is used to perform an AND operation on the inverted signals of the open-drain enable signal and the push-pull enable signal to generate a first signal and output it to the third OR gate. The fourth AND gate is used to perform an AND operation on the inverted signal of the open-drain enable signal and the push-pull enable signal to generate a second signal which is output to the third OR gate. The third OR gate is used to perform an OR operation on the first signal and the second signal to generate a third signal which is output to the fifth AND gate. The fifth AND gate is used to perform an AND operation on the third signal, the output configuration signal, and the first enable signal to generate the second drive signal.

9. The I2C interface according to claim 7, characterized in that, The second open-drain configuration subunit includes a sixth AND gate, and the third configuration signal includes an output configuration signal and an open-drain enable signal configured to be active, and a first enable signal configured to be inactive; wherein, the output configuration signal configured to be active is used to indicate that the SDA data line of the I2C interface is in output mode, the first enable signal configured to be inactive is used to indicate that the I2C interface is working in I2C mode, and the open-drain enable signal configured to be active is used to indicate that the I2C interface working in I2C mode is configured in open-drain mode; The sixth AND gate is used to perform an AND operation on the output configuration signal, the inverted signal of the first enable signal, and the open-drain enable signal to generate the third drive signal.

10. An interface chip, characterized in that, It includes a chip body and an I2C interface as described in any one of claims 1-9 disposed on the chip body.

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