SAR-TDC type ADC circuit and module for high-frame-rate image sensor

Abstract

The invention discloses an SAR-TDC type ADC circuit and module for a high-frame-rate image sensor, and relates to the technical field of image sensor design. The device comprises a signal preprocessing part, an SAR-ADC part, a VTC part, a sign bit judgment part, a TDC part and a data processing part. According to the invention, an ADC (Analog to Digital Converter) of a voltage-time mixed domain architecture is designed, 11-bit quantization of two columns of pixel signals {Vref, 1, Vsig, 1} to {Vref, 2, Vsig, 2} is decomposed into 6bit coarse quantization through an SAR-ADC part and 5bit fine quantization through a TDC (Time to Digital Converter) part; compared with a traditional SS ADC, the quantization speed is increased by nearly ten times; compared with a traditional pipled-SAR ADC, the circuit area of the invention is smaller, and the ADC is more suitable for a high-frame-rate CIS.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically to: 1. a SAR-TDC type ADC circuit for a high frame rate image sensor; 2. a SAR-TDC type ADC module for a high frame rate image sensor. Background Art

[0002] Image sensors (Complementary Metal Oxide Semiconductor Image Sensors, or CIS) are widely used in digital cameras, mobile phone cameras, and surveillance cameras. Their function is to convert optical signals into digital signals. The analog-to-digital converter (ADC) is one of the most important components in a CIS, converting the electrical signals generated by the photosensitive element into digital signals. The performance of the ADC directly affects the image quality of the CIS.

[0003] The increasing demand for high-frame-rate CIS requires high-speed, low-power, and compact ADCs for pixel voltage signal readout. However, increasing the conversion accuracy by one bit with traditional single-slope analog-to-digital converters (SS ADCs) requires exponentially increased conversion time and power consumption. Consequently, the conversion speed significantly decreases at high precision requirements, making it difficult to meet these requirements. While traditional pipelined-SAR ADCs offer high-speed processing, their large circuit area and high voltage requirements make them difficult to achieve high-frame-rate readout in advanced pixels.

[0004] Therefore, providing a usable ADC for high frame rate CIS and making it meet the requirements of high speed and small area has become the main research direction of the present invention.

[0005] In addition, power consumption is also an important factor that needs to be considered in ADC design; and existing ADCs are easily affected by PVT (process, voltage and temperature). Therefore, improving the ADC's anti-PVT performance and reducing the ADC's power consumption are also taken into account in the present invention. Summary of the Invention

[0006] Based on this, it is necessary to address the problem that traditional ADC cannot meet the requirements of high frame rate CIS, and provide a SAR-TDC type ADC circuit and module for high frame rate image sensors.

[0007] The present invention is achieved by adopting the following technical solutions:

[0008] In a first aspect, the present invention provides a SAR-TDC ADC circuit for a high frame rate image sensor, for processing pixel signals {V ref,1 ,V sig,1}~{Vref,2 ,V sig,2}Perform 11-bit quantization in sequence.

[0009] The SAR-TDC ADC circuit for high frame rate image sensors includes: a signal preprocessing unit, a SAR-ADC unit, a VTC unit, a sign bit judgment unit, a TDC unit, and a data processing unit.

[0010] The signal preprocessing unit is used to calculate V ref,n With V sig,n The difference between the two is amplified to obtain the gain signal V pixel ; n∈[1,2].

[0011] The SAR-ADC section is used to: combine the common-mode voltage V cm and control voltage V H 、V L V pixel Perform coarse quantization to obtain code value D<11:6>, and generate a residual voltage V after the coarse quantization is completed. res .

[0012] The VTC part is used to combine the control signals CK, CKB and the power supply voltage VDD and the gain voltage VDD' to res Converted into time signal S P 、S N ; Among them, CK and CKB are opposite signals.

[0013] The sign bit judgment unit is used to: combine VDD according to S P 、S N Generate the sign bit D in the order of <5> , and output the time signal T P 、T N ; Among them, T P The phase is in front, T N The phase is behind.

[0014] TDC is used to: combine VDD with T P 、T N Fine quantization is performed to obtain code values ​​D<4:0>.

[0015] The data processing unit is used to: <5> Perform corresponding addition and subtraction on D<11:6> and D<4:0> to obtain the quantized result B<10:0>; where D <5> When it is 1, perform addition; D <5> When it is 0, subtraction is performed.

[0016] The implementation of the SAR-TDC type ADC circuit for a high frame rate image sensor is a method or process according to an embodiment of the present disclosure.

[0017] In a second aspect, the present invention discloses a SAR-TDC ADC module for a high frame rate image sensor, which adopts the layout of a SAR-TDC ADC circuit for a high frame rate image sensor disclosed in the first aspect.

[0018] The implementation of the SAR-TDC type ADC module for a high frame rate image sensor is a method or process according to an embodiment of the present disclosure.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The present invention designs an ADC with a voltage-time hybrid domain architecture, which converts the pixel signals of two columns {V ref,1 ,V sig,1}~{V ref,2 ,V sig,2 The 11-bit quantization of the present invention is decomposed into 6-bit coarse quantization by the SAR-ADC part and 5-bit fine quantization by the TDC part; compared with the traditional SS ADC, the quantization speed of the present invention is increased by nearly ten times; compared with the traditional pipelined-SAR ADC, the circuit area of ​​the present invention is smaller and more suitable for high frame rate CIS.

[0021] 2. The present invention establishes a current tracking relationship between the VTC part and the TDC part. In the VTC part, not only the component settings are adjusted, but also the corresponding gain voltage VDD' is introduced, thereby improving the anti-PVT performance of the entire circuit; an improved delay unit is designed in the TDC part, effectively reducing the power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a schematic structural diagram of a SAR-TDC ADC circuit for a high frame rate image sensor provided by the present invention;

[0024] Figure 2 for Figure 1 The circuit structure diagram of the signal preprocessing unit in FIG.

[0025] Figure 3 for Figure 1 Circuit diagram of the SAR-ADC part;

[0026] Figure 4 for Figure 1Circuit diagram of the VTC section;

[0027] Figure 5 for Figure 1 The circuit structure diagram of the sign bit judgment unit;

[0028] Figure 6 for Figure 5 The working timing diagram of the sign bit judgment unit;

[0029] Figure 7 for Figure 1 Circuit diagram of the TDC section;

[0030] Figure 8 for Figure 6 Circuit structure diagram of the delay unit;

[0031] Figure 9 for Figure 1 Circuit diagram of the data processing unit;

[0032] Figure 10 This is a diagram of the anti-PVT simulation results at different voltages and temperatures provided by the present invention;

[0033] Figure 11 This is a diagram of the anti-PVT simulation results under different process angles provided by the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] Example 1

[0038] This embodiment 1 provides a SAR-TDC ADC circuit for a high frame rate image sensor.

[0039] First of all, it should be noted that this SAR-TDC ADC circuit is designed to process two columns of pixel signals {V ref,1 ,V sig,1}~{V ref,2 ,V sig,2}Perform 11-bit quantization in sequence.

[0040] Among them, V ref,n Represents the pixel reset signal; V sig,n Represents the pixel readout signal; n∈[1,2].

[0041] Next see Figure 1 , which shows the structural diagram of the SAR-TDC ADC circuit. According to the functional division, the SAR-TDC ADC circuit includes: signal preprocessing unit, SAR-ADC unit, VTC unit, sign bit determination unit, TDC unit, and data processing unit.

[0042] The following is an introduction to each part:

[0043] 1. Signal preprocessing unit is used to calculate V ref,n With V sig,n The difference between the two is amplified to obtain the gain signal V pixel .

[0044] See Figure 2 , the signal pre-processing unit can be designed to include: 2 switches S w1 ~S w2 , 1 gain amplifier Amp1.

[0045] S w1 The first end of the ref,1 ,V sig,1};S w2 The first end of the ref,2 ,V sig,2};S w1 、S w2 The second end is connected to the input of Amp1; the output of Amp1 is used to output V pixel ;

[0046] In this way, by w1 、S w2 Control them so that they are not closed simultaneously but in sequence, so that {V ref,1 ,V sig,1}、{V ref,2 ,V sig,2Amp1 uses a programmable gain amplifier, which has the function of reducing the effect of the pixel output bus on the noise of the subsequent ADC, and subtracts its two inputs to generate V pixel This enables the function of analog multi-sampling and reduces the noise caused by pixels.

[0047] Specifically, first turn on S w1 , disconnect S w2 ,{V ref,1 ,V sig,1} is input to Amp1, and Amp1 converts V ref,1 、V sig,1 Subtract and amplify the difference to get V pixel . Then turn on S w2 , disconnect S w1 ,{V ref,2 ,V sig,2} is input to Amp1, and Amp1 converts V ref,2 、V sig,2 Subtract and amplify the difference to get V pixel .

[0048] That is to say: ref,1 ,V sig,1} input, V pixel is V after gain amplification ref,1 、V sig,1 Difference; {V ref,2 ,V sig,2} input, V pixel is V after gain amplification ref,2 、V sig,2 Difference.

[0049] Of course, the signal preprocessing unit may also adopt other circuit designs, but it needs to meet the above-mentioned signal input and processing requirements.

[0050] 2. SAR-ADC is used to: Combine the common-mode voltage V cm and control voltage V H 、V L V pixel Perform coarse quantization to obtain code value D<11:6>, and generate a residual voltage V after the coarse quantization is completed. res .

[0051] See Figure 3 The SAR-ADC part performs 6-bit coarse quantization and can be designed to include: a SAR logic part SAR-logic, a capacitor DAC part CDAC, a comparator Comp, a latch Latch1, and a switch S1.

[0052] like Figure 3 As shown, the CDAC includes: a capacitor array portion and a switch array portion.

[0053] The capacitor array includes: 6 capacitors C A ~C F , 1 bridge capacitor C U ; C D ~C F The upper board is connected to C U The first end of C A ~C C The upper board is connected to C U The second end, output voltage V DAC .

[0054] It should be noted that C U The capacitance values ​​of C0, C3 are the same; the ratio of C0 to C2 is 1:2:4; the ratio of C3 to C5 is also 1:2:4; using this bridging method can save the area of ​​the capacitor array.

[0055] The switch array section includes: 18 switches S A0 ~S F0 、S A1 ~S F1 、S A2 ~S F2 ;Switch S σ0 The first end of the switch S σ1 The first end of the switch S σ2 The first end is connected to C σ Lower level board; S σ2 The second end is connected to V CM ;S σ1 The second end is connected to V H ;S σ0 The second end is connected to V L ;σ∈[A,B,C,D,E,F].

[0056] The first end of S1 is connected to V pixel , the second end is connected to V DAC ;Comp's negative input is connected to V DAC , the positive input terminal is connected to V cm , the output end is used to output comparison signals VP and VN; the control end of SAR-logic is connected to VP and VN, output end 1 is used to output the control signal group Ctrl for the switch array part, and output 2 is connected to the input end of Latch1; the output end of Latch1 is used for D<11:6>.

[0057] Among them, when the signal preprocessing unit performs signal processing, S1 is closed; when quantization starts, S1 is opened.

[0058] SAR-logic uses asynchronous SAR logic. Since there are 18 switches in the switch array, Ctrl actually contains 18 corresponding switch control signals (i.e. Ctrl_S A0 ~Ctrl_S F0 , Ctrl+S A1 ~Ctrl_S EF1 , Ctrl+S A2 ~Ctrl_S F2 ), to respectively A0 ~S F0 、S A1 ~S F1 、S A2 ~S F2 Take control.

[0059] Thus, as the coarse quantization proceeds, Latch1 latches the output of SAR-logic, thereby obtaining D<11:6>. Of course, after the coarse quantization is completed, V DAC That is, as V res .

[0060] 3. The VTC section is used to combine the control signals CK, CKB, the power supply voltage VDD, and the gain voltage VDD' to res Converted into time signal S P 、S N Among them, CK and CKB are opposite signals.

[0061] See Figure 4 The VTC part can be designed to include: 2 differential pairs of transistors DIF1~DIF2 with eliminated clock feedthrough, 1 pre-charge unit Pre, 2 inverters INV1~INV2, and 2 D flip-flops DFF1~DFF2.

[0062] DIF1 and DIF2 are connected to form nodes DP and DN; the control end of DIF1 is connected to V res , control terminal 2 connected to V cm , control terminal 3 is connected to CK, control terminal 4 is connected to CKB; control terminal 1 and control terminal 2 of DIF2 are both connected to V cm , control terminal three is connected to CK, control terminal four is connected to CKB; Pre is used to precharge DP and DN to VDD'; DP is connected to the timing control terminal of DFF1 through INV1; D input terminal of DFF1 is connected to VDD, Q output terminal is used to output S P DN is connected to the timing control terminal of DFF2 through INV2; the D input terminal of DFF2 is connected to VDD and the Q output terminal is used to output S N .

[0063] It should be noted that although the traditional starved VTC five-tube circuit has a fast switching speed, it has a serious third harmonic problem, resulting in low VTC linearity. However, in the present invention: the VTC part uses a differential pair of tubes with eliminated clock feedthrough, and DP and DN are precharged to VDD' instead of VDD. Among them, VDD' satisfies: VDD'=α(V cm -V TH ); where α represents the gain multiple; V TH Represents the operating threshold voltage of the transistor.

[0064] The following is a detailed introduction:

[0065] Ⅰ. Such as Figure 4 As shown, DIF1 includes: 4 NMOS tubes M1~M3, M9; among them, the source of M1 is connected to the source of M2 and the drain of M3; the gate of M1 serves as the control terminal 1 of DIF1; the gate of M2 serves as the control terminal 2 of DIF1; the gate of M3 serves as the control terminal 3 of DIF1; the gate of M9 serves as the control terminal 4 of DIF1; the drain of M1 is connected to DP; the drain of M2 is connected to DN; the source of M3, the source of M9, and the drain of M9 are grounded GND.

[0066] DIF2 includes: 4 NMOS transistors M6~M8, M12; among them, the source of M6 is connected to the source of M7 and the drain of M8; the gate of M6 serves as the control terminal 1 of DIF2; the gate of M7 serves as the control terminal 2 of DIF2; the gate of M8 serves as the control terminal 3 of DIF2; the gate of M12 serves as the control terminal 4 of DIF2; the drain of M6 is connected to DP; the drain of M7 is connected to DN; the source of M8, the source of M12, and the drain of M12 are grounded GND.

[0067] DIF1 and DIF2 add M9 and M12 as dummy transistors, with the width-to-length ratio of M9 set to half that of M3 and the width-to-length ratio of M12 set to half that of M8. This allows for the circuit to operate at high frequencies, where input signals of opposite polarity generate pulse signals of opposite polarity at the input terminals. These signals cancel each other out, eliminating the clock feedthrough effect caused by the high-frequency clock.

[0068] M3 and M8 serve as tail current transistors for DIF1 and DIF2. Their width-to-length ratios are generally designed to be large enough (no less than 100) to negligibly reduce their on-resistance and minimize their impact on discharge. Furthermore, the specifications of M1, M2, M6, and M7 in DIF1 and DIF2 are identical, eliminating interference with discharge caused by inconsistent MOS transistor specifications.

[0069] Ⅱ. Figure 4 As shown, Pre includes: 4 NMOS tubes M4, M5, M10, M11, 2 capacitors Cp1 ~C p2 Among them, the gates of M4 and M11 are connected to CK; the gates of M10 and M5 are connected to CKB; the source of M4, the source of M11, the source of M10, the drain of M10, the source of M5, and the drain of M5 are connected to VDD'; the drain of M4 is connected to C p1 The first terminal of M11 is DP; the drain of M11 is connected to C p2 The first end, DN; C p1 、C p2 The second end is grounded GND.

[0070] It should be noted that C p1 、C p2 The capacitance value is the same, both are C.

[0071] Of course, similar to the differential pair tubes, Pre eliminates the clock feedthrough effect by adding M10 and M11 as dummy tubes and making the width-to-length ratio of M10 half of that of M4 and the width-to-length ratio of M11 half of that of M5.

[0072] Through the above settings, S is eliminated. P 、S N The third-order distortion of the phase difference ΔT.

[0073] In general, the VTC has a reset phase and a conversion phase:

[0074] ①. In the reset phase, CK is low, CKB is high, M4 and M5 are turned on, DP and DN are precharged to VDD', and M10 and M11 are responsible for eliminating the clock feedthrough effect during charging.

[0075] ②. In the conversion stage, CK is high, CKB is low, M4 and M5 are turned off, M1, M2, M3, M6, M7, and M8 are turned on, DP and DN start to discharge, and M9 and M12 are responsible for eliminating the clock feedthrough effect of discharge.

[0076] Among them, DP and DN have the first differential pair current I at DIF1. P (flowing through M1, M3), I N (flows through M2 and M3). Since the gates of M1 and M2 are connected to V res 、V cm , the difference between these two voltage values ​​leads to I P , I N different.

[0077] DP and DN have a second pair of differential currents I C1 (flowing through M6, M8), I C2 (flows through M7 and M8). Since the gates of M6 and M7 are both connected to Vcm , making I C1 , I C2 Same (can be regarded as current I C ). Among them, I C It can be written as: β P Indicates the transconductance parameter of the MOS tube.

[0078] Therefore, the discharge rate of DP and DN depends on I P , I N , which depends on V res 、V cm size.

[0079] When DP and DN are reduced to V TH When DP and DN drop to GND, DFF1~DFF2 output S P 、S N At this time, the VTC stops working until the reset stage, so the power consumption is very small.

[0080] It should be noted that ΔT and V res There is a positive linear correlation:

[0081] Since the third-order distortion is eliminated, ΔT can be written as:

[0082] Then, VDD'=α(V cm -V TH ) into ΔT, we have:

[0083] 4. The sign bit judgment unit is used to: combine VDD according to S P 、S N Generate the sign bit D in the order of <5> , and output the time signal T P 、T N It should be emphasized that T P The phase is in front, T N The phase is behind.

[0084] Due to the characteristics of the VTC department, S P 、S N The order of the front and back is not certain, so the sign bit judgment unit needs to shape it to obtain T with a strict front and back order. P 、T N , to ensure that TDC can convert correctly.

[0085] See Figure 5The sign bit judgment unit can be designed to include: 1 latch Latch2, 4 delays Delay1~Delay4, and 2 multiplexers MUX1~MUX2.

[0086] like Figure 5 As shown, Lacth2 is designed to include: 4 PMOS transistors MP1 to MP4, and 4 NMOS transistors MN1 to MN4. Among them, the sources of MP1 to MP4 are connected to VDD; the gates of MP1 and MN1 are connected to S P The drain of MP1 is connected to the drain of MP2, the drain of MN1, the gate of MP3, and the gate of MN4; the gate of MP2 is connected to the gate of MN3, the drain of MN2, the drain of MP3, and the drain of MP4, and is used to output D <5> ; Gate connection S of MP4 and MN2 N ; The source of MN1 is connected to the drain of MN3; the source of MN2 is connected to the drain of MN4; the sources of MN3 and MN4 are grounded GND.

[0087] The input of Delay1 is connected to S P , the output end is connected to the input end of MUX1; the input end of Delay2 is connected to S N , the output end is connected to the second input end of MUX1; the control end of MUX1 is connected to D <5> , the output terminal is used to output T P ; The input of Delay3 is connected to S N , the output end is connected to the input end of MUX2; the input end of Delay4 is connected to S P , the output end is connected to the second input end of MUX2; the control end of MUX2 is connected to D <5> , the output terminal is used to output T N .

[0088] The following combination Figure 6 The timing diagram of the sign bit judgment unit is explained as follows:

[0089] In S P 、S N Before it arrives, the sign bit judgment unit is in reset state, D <5> is high level.

[0090] See Figure 6 (a) area in: If S P Before S N Arrival, that is, there is a period S P High level, S N During the low level period, MP1 and MP2 are turned off, MP4 is turned on, and the gate of MP3 is discharged to a low level. MP3 is turned on to make D <5> Stable at a high level - this means that the final quantization result is the sum of coarse quantization and fine quantization. P With S NEnter MUX1~MUX2: In D <5> Under the action, MUX1 outputs T P , MUX2 output T N , and keep T P The phase is in front, T N The phase is behind.

[0091] See Figure 6 Region (b): If S N Before S P Arrival, that is, there is a period S N High level, S P The time period of low level, at this time MP1 is turned on, MP4 is turned off, D <5> The voltage drops, MP2 turns on, the MP3 gate is pulled up to a high level, and MP3 turns off; under the action of positive feedback, D <5> The voltage drops rapidly to a low level, which means that the final quantization result is the difference between the coarse quantization and the fine quantization. P With S N Enter MUX1~MUX2: In D <5> Under the action, MUX1 outputs T P , MUX2 output T N , and make T P The phase is in front, T N The phase is behind.

[0092] 5. TDC is used to: combine VDD to T P 、T N Fine quantization is performed to obtain code values ​​D<4:0>.

[0093] Specifically, the TDC portion itself has a time difference Δt (ie, the delay of its internal delay unit), and ΔT / Δt is calculated based on time-to-digital conversion to serve as D<4:0>.

[0094] See Figure 7 The TDC part can be designed to include: 1 ring oscillator VCO, 5 D flip-flops D0~D4, 1 decoder Decoder, and 1 latch Latch3.

[0095] First, the VCO is used to adjust the VDD, T P 、T N Oscillation is performed to generate five output signals T0 to T4.

[0096] It should be noted that the VCO of the present invention adopts Figure 8 The design includes five delay units U0 to U4. i It includes: 5 NMOS tubes MO1~MO5 and 1 XNOR gate.

[0097] like Figure 8As shown, the input of XNOR is connected to T P , input terminal 2 is connected to T N , the output terminal is used to output the control signal T T The source of MO1 and MO2 is connected to VDD; the gate of MO1 is connected to the input signal IN; the drain of MO1 is connected to the drain of MO2, the drain of MO3, and the drain of MO4, and is used to output T i+1 ;MO3's gate is connected to T i , the source is connected to the drain of MO5; the gate of MO4 is connected to T T , the source is grounded GND; the gate of MO5 is connected to T P , the source is grounded GND. i∈[0,1,2,3,4].

[0098] Among them, in U0, IN is T P ;In U1~U4, IN is VDD.

[0099] It should be noted that the size of MO5, the tail current tube of the delay unit, is the same as that of M3 and M8.

[0100] It should be emphasized that the traditional VCO is in T P After reaching T P and T N Reset at the same time. But after analysis, N After reading the delay loop state, the VCO can stop working. i Added an additional MOS tube MO4, and through T T Resetting T1 output by U0 to 0 not only reduces power consumption, but also makes the starting point of each VCO working state consistent, further improving accuracy.

[0101] Secondly, for other components in the TDC unit, the timing control terminals of D1 to D5 are connected to T N ;D i The D input terminal is connected to T i , Q output terminal outputs thermometer code Q i The input of the decoder is connected to the Q output of D1 to D5, and is used to convert Q0 to Q4 into binary code. The input of latch3 is connected to the output of the decoder, and the output is used to output D<4:0>.

[0102] T P Before T N Entering VCO, at this time T T When the timer turns to low level, MO1 and MO4 of all delay units are turned off, MO5 is turned on, and the delay unit starts to discharge (the discharge current flowing through MO5 is set to I U), the VCO starts to oscillate. When T N When it arrives, D0~D4 record the output of the corresponding delay unit, that is, Q0~Q4; the decoder then converts Q0~Q4 into binary code and sends it to Latch3 to form D<4:0>.

[0103] In addition, see the above record, in T N Upon arrival, T T It becomes a high level, MO4 tube is turned on, and T1 is forced to be pulled to a low level, so that the VCO is reset and stops working until the next fine quantization starts.

[0104] For the TDC part, its conversion accuracy depends on the charge and discharge time of U0~U4, and the discharge current of U0~U4 is much greater than the charging current. Therefore, Δt can be written as: C P Represents the parasitic capacitance of the delay unit.

[0105]

[0106] Among them, α is the set value, which can resist the influence of PVT; C and C P The ratio of V res The ratio to VDD is a fixed value and does not change with PVT. Since the size of MO5 is the same as M3 and M8, I U with I C They have the same PVT response and their ratio does not change with PVT.

[0107] Therefore, the value of ΔT / Δt does not change with PVT changes, making the SAR-TDC circuit robust to PVT.

[0108] 6. Data processing unit is used for: <5> Perform corresponding addition and subtraction on D<11:6> and D<4:0> to obtain the quantized result B<10:0>; where D <5> When it is 1, perform addition; D <5> When it is 0, subtraction is performed.

[0109] See Figure 9 The data processing unit can be designed to include: 1 addition and subtraction timer Counter and 1 latch Latch4.

[0110] The input terminal of the counter is connected to D<11:6>, the input terminal is connected to D<4:0>, and the control terminal is connected to D <5> , the output end is connected to the input end of Latch4; the output end of Latch4 is used to output B<10:0>.

[0111] The data processing department processes data as follows:

[0112] ①, in D <5> When it is 1, D<11:6> is shifted back by 1 bit as a whole, and the last 5 bits are padded with 0, and then added to D<4:0> to obtain B<10:0>;

[0113] ②In D <5> When it is 0, D<11:6> is shifted back by 1 bit as a whole, and the last 5 bits are padded with 0, and then subtracted from D<4:0> to obtain B<10:0>.

[0114] Simulation Verification

[0115] To illustrate the overall effectiveness of this SAR-TDC ADC circuit (SAR-TDC-ADC), circuit simulations were performed and compared with existing circuits (including Sensors'20, VLSI'22, and TCAS-I'20). The results are shown in Table 1. Sensors'20 is an SS ADC that is an improvement on the traditional SS ADC.

[0116] Table 1 Circuit performance comparison

[0117] index Sensors'20 VLSI'22 TCAS-I'20 SAR-TDC-ADC DNL 4.25 0.83 0.83 0.83 INL 5.73 3.31 3.31 1.80 Quantization speed (MS / s) 2.4 0.1 0.2 20

[0118] As shown in Table 1, the SAR-TDC ADC circuit achieves the optimal DNL (differential nonlinearity) and INL (integral nonlinearity), and the quantization speed of the SAR-TDC ADC circuit is nearly ten times faster than that of Sensors'20, demonstrating the superior performance of the present invention.

[0119] In order to illustrate the anti-PVT performance of this SAR-TDC ADC circuit, circuit simulations were performed under different PVT conditions. The results are shown in Figures 10 and 11 .

[0120] Depend on Figures 10 and 11 It can be seen that under different process angles, temperatures, and voltages, the SNDR performance curve of this SAR-TDC ADC circuit fluctuates very little, indicating that it has good anti-PVT performance.

[0121] To illustrate the power-saving effect of this SAR-TDC ADC circuit, a simulation comparison of the TDC unit was conducted. The results showed that the power consumption of the TDC unit was reduced from 1.02mW to 0.76mW before and after the addition of MOS transistor MO4, demonstrating the superiority of the TDC unit in power consumption.

[0122] Example 2

[0123] This embodiment 2 discloses a SAR-TDC ADC module for a high frame rate image sensor, which adopts the layout of the SAR-TDC ADC circuit for a high frame rate image sensor disclosed in embodiment 1. The packaging mode makes it easier to promote and apply the above circuit.

[0124] The SAR-TDC ADC module for a high frame rate image sensor includes a signal preprocessing module (corresponding to the signal preprocessing unit), a SAR-ADC module (corresponding to the SAR-ADC unit), a VTC module (corresponding to the VTC unit), a sign bit determination module (corresponding to the sign bit determination unit), a TDC module (corresponding to the TDC unit), and a data processing module (corresponding to the data processing unit). The specific circuit layout is described in Example 1 and will not be repeated here.

[0125] This embodiment 2 also simultaneously discloses a CMOS image sensor, which adopts the above-mentioned SAR-TDC ADC module for high frame rate image sensors.

[0126] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A SAR-TDC ADC circuit for a high frame rate image sensor, which is used to convert two columns of pixel signals {V ref,1 ,V sig,1 }~{V ref,2 ,V sig,2 }11bit quantization is performed sequentially; it is characterized in that, It includes: Signal pre-processing unit, which is used to calculate V ref,n With V sig,n The difference between the two is amplified to obtain the gain signal V pixel ;n∈[1,2]; SAR-ADC section, which is used to: combine the common mode voltage V cm and control voltage V H 、V L V pixel Perform coarse quantization to obtain code value D<11:6>, and generate a residual voltage V after the coarse quantization is completed. res ; The VTC part is used to combine the control signals CK, CKB and the power supply voltage VDD and the gain voltage VDD' to res Converted into time signal S P 、S N ; Among them, CK and CKB are opposite signals; The sign bit judgment unit is used to: combine VDD according to S P 、S N Generate the sign bit D in the order of <5> , and output the time signal T P 、T N ; Among them, T P The phase is in front, T N The phase is behind; TDC section, which is used to: combine VDD to T P 、T N Perform fine quantization to obtain code values ​​D<4:0>; and Data processing unit, which is used to: <5> Perform corresponding addition and subtraction on D<11:6> and D<4:0> to obtain the quantized result B<10:0>; where D <5> When it is 1, perform addition; D <5> When it is 0, subtraction is performed.

2. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 1, wherein: The signal pre-processing unit includes: 2 switches S w1 ~S w2 , 1 gain amplifier Amp1; S w1 The first end of the ref,1 ,V sig,1 };S w2 The first end of the ref,2 ,V sig,2 };S w1 、S w2 The second end is connected to the input of Amp1; the output of Amp1 is used to output V pixel .

3. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 1, wherein: The SAR-ADC unit includes: a SAR logic unit SAR-logic, a capacitor DAC unit CDAC, a comparator Comp, a latch Latch1, and a switch S1; CDAC includes: a capacitor array part and a switch array part; wherein the capacitor array part includes: 6 capacitors C A ~C F , 1 bridge capacitor C U ; C D ~C F The upper board is connected to C U The first end of C A ~C C The upper board is connected to C U The second end, output voltage V DAC ; The switch array includes: 18 switches S A0 ~S F0 、S A1 ~S F1 、S A2 ~S F2 ;Switch S σ0 The first end of the switch S σ1 The first end of the switch S σ2 The first end is connected to C σ Lower level board; S σ2 The second end is connected to V CM ;S σ1 The second end is connected to V H ;S σ0 The second end is connected to V L ;σ∈[A,B,C,D,E,F]; The first end of S1 is connected to V pixel , the second end is connected to V DAC ;Comp's negative input is connected to V DAC , the positive input terminal is connected to V cm , the output end is used to output comparison signals VP and VN; the control end of SAR-logic is connected to VP and VN, the output end 1 is used to output the control signal group Ctrl for the switch array part, and the output end 2 is connected to the input end of Latch1; the output end of Latch1 is used for D<11:6>; Among them, after the coarse quantization is completed, V DAC That is, as V res .

4. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 1, wherein: The VTC section includes: two differential pairs of transistors DIF1 and DIF2 with eliminated clock feedthrough, a precharge unit Pre, two inverters INV1 and INV2, and two D flip-flops DFF1 and DFF2; DIF1 and DIF2 are connected to form nodes DP and DN; the control end of DIF1 is connected to V res , control terminal 2 connected to V cm , control terminal 3 is connected to CK, control terminal 4 is connected to CKB; control terminal 1 and control terminal 2 of DIF2 are both connected to V cm , control terminal three is connected to CK, control terminal four is connected to CKB; Pre is used to precharge DP and DN to VDD'; DP is connected to the timing control terminal of DFF1 through INV1; D input terminal of DFF1 is connected to VDD, Q output terminal is used to output S P DN is connected to the timing control terminal of DFF2 through INV2; the D input terminal of DFF2 is connected to VDD and the Q output terminal is used to output S N ; Among them, S P 、S N The phase difference ΔT and V res There is a positive linear correlation.

5. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 4, wherein: DIF1 includes: 4 NMOS transistors M1 to M3, M9; among them, the source of M1 is connected to the source of M2 and the drain of M3; the gate of M1 serves as the control terminal 1 of DIF1; the gate of M2 serves as the control terminal 2 of DIF1; the gate of M3 serves as the control terminal 3 of DIF1; the gate of M9 serves as the control terminal 4 of DIF1; the drain of M1 is connected to DP; the drain of M2 is connected to DN; the source of M3, the source of M9, and the drain of M9 are grounded GND; DIF2 includes: 4 NMOS transistors M6 to M8, M12; among them, the source of M6 is connected to the source of M7 and the drain of M8; the gate of M6 serves as the control terminal 1 of DIF2; the gate of M7 serves as the control terminal 2 of DIF2; the gate of M8 serves as the control terminal 3 of DIF2; the gate of M12 serves as the control terminal 4 of DIF2; the drain of M6 is connected to DP; the drain of M7 is connected to DN; the source of M8, the source of M12, and the drain of M12 are grounded GND; Pre includes: 4 NMOS tubes M4, M5, M10, M11, 2 capacitors C p1 ~C p2 Among them, the gates of M4 and M11 are connected to CK; the gates of M10 and M5 are connected to CKB; the source of M4, the source of M11, the source of M10, the drain of M10, the source of M5, and the drain of M5 are connected to VDD'; the drain of M4 is connected to C p1 The first terminal of M11 is DP; the drain of M11 is connected to C p2 The first end, DN; C p1 、C p2 The second end is grounded to GND; Among them, the width-to-length ratio of M3 and M8 shall not be less than 100; the specifications of M1, M2, M6 and M7 shall be the same; VDD'=α(V cm -V TH ); α represents the gain multiple; V TH Represents the operating threshold voltage of the transistor.

6. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 1, wherein: The sign bit judgment unit includes: 1 latch Latch2, 4 delays Delay1 to Delay4, and 2 multiplexers MUX1 to MUX2; Lacth2 includes: 4 PMOS tubes MP1~MP4, 4 NMOS tubes MN1~MN4; the source of MP1~MP4 is connected to VDD; the gate of MP1 and MN1 is connected to S P The drain of MP1 is connected to the drain of MP2, the drain of MN1, the gate of MP3, and the gate of MN4; the gate of MP2 is connected to the gate of MN3, the drain of MN2, the drain of MP3, and the drain of MP4, and is used to output D <5> ; Gate connection S of MP4 and MN2 N The source of MN1 is connected to the drain of MN3; the source of MN2 is connected to the drain of MN4; the sources of MN3 and MN4 are grounded GND; The input of Delay1 is connected to S P , the output end is connected to the input end of MUX1; the input end of Delay2 is connected to S N , the output end is connected to the second input end of MUX1; the control end of MUX1 is connected to D <5> , the output terminal is used to output T P ; The input of Delay3 is connected to S N , the output end is connected to the input end of MUX2; the input end of Delay4 is connected to S P , the output end is connected to the second input end of MUX2; the control end of MUX2 is connected to D <5> , the output terminal is used to output T N .

7. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 5, wherein: The TDC section includes: a ring oscillator VCO, five D flip-flops D0 to D4, a decoder Decoder, and a latch Latch3; VCO is used to adjust the VDD, T P 、T N Oscillate to generate five output signals T0 to T4; The timing control terminals of D1 to D5 are connected to T N ;D i The D input terminal is connected to T i , Q output terminal outputs thermometer code Q i ; i∈[0,1,2,3,4]; The input end of the decoder is connected to the Q output end of D1~D5, which is used to convert Q0~Q4 into binary code; the input end of Latch3 is connected to the output end of the decoder, and the output end is used to output D<4:0>.

8. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 6, wherein: The VCO includes five delay units U0 to U4; among them, the delay unit U i Includes: 5 NMOS tubes MO1~MO5, 1 XNOR gate; The input of XNOR is connected to T P , input terminal 2 is connected to T N , the output terminal is used to output the control signal T T ; The sources of MO1 and MO2 are connected to VDD; the gate of MO1 is connected to the input signal IN; the drain of MO1 is connected to the drain of MO2, the drain of MO3, and the drain of MO4, and is used to output T i+1 ;MO3's gate is connected to T i , the source is connected to the drain of MO5; the gate of MO4 is connected to T T , the source is grounded GND; the gate of MO5 is connected to T P , source ground GND; Among them, the size of MO5 is the same as M3 and M8; in U0, IN is T P ;In U1~U4, IN is VDD.

9. The SAR-TDC ADC circuit for a high frame rate image sensor according to claim 1, wherein: The data processing unit includes: 1 addition and subtraction timer Counter, 1 latch Latch4; The input terminal of the counter is connected to D<11:6>, the input terminal is connected to D<4:0>, and the control terminal is connected to D <5> , the output end is connected to the input end of Latch4; the output end of Latch4 is used to output B<10:0>; Among them, in D <5> When D<11:6> is 1, the whole D<11:6> is shifted back by 1 bit, and the last 5 bits are filled with 0, and then added to D<4:0> to get B<10:0>; <5> When it is 0, D<11:6> is shifted back by 1 bit as a whole, and the last 5 bits are padded with 0, and then subtracted from D<4:0> to obtain B<10:0>.

10. A SAR-TDC ADC module for a high frame rate image sensor, characterized in that: A layout of a SAR-TDC type ADC circuit for a high frame rate image sensor according to any one of claims 1 to 9 is adopted.

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