Three-dimensional semiconductor memory device and electronic system including same

Abstract

A three-dimensional semiconductor memory device may include a first cell array structure on a substrate, the first cell array structure including a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure, the second cell array structure being located on the first cell array structure, the second cell array structure including a plurality of second gate electrodes stacked in the first direction; a first through via in the first cell array structure and extending in the first direction; and a second through-path in contact with a top surface of the first through-path and extending in the first direction from the top surface of the first through-path in the first cell array structure into the second cell array structure.

Description

Technical Field

[0001] The present disclosure relates to a three-dimensional semiconductor memory device and an electronic system including the same. Background Art

[0002] Data storage in electronic systems may require semiconductor devices that can store large amounts of data. In order to meet consumer demand for large data storage capacity, superior performance, and low prices, higher integration of semiconductor devices is required. In the case of two-dimensional or planar semiconductor devices, since the integration level may be mainly determined by the area occupied by the unit memory cell, the integration level may be affected by the precision level of fine pattern forming technology. However, improving the pattern fineness may require expensive process equipment, which may impose practical limitations on improving the integration level of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0003] Embodiments of the inventive concept provide a three-dimensional semiconductor memory device having improved productivity and an electronic system including the same.

[0004] According to an embodiment of the present invention, a three-dimensional (3D) semiconductor memory device may include: a first cell array structure, the first cell array structure being located on a substrate, the first cell array structure including a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure, the second cell array structure being located on the first cell array structure, the second cell array structure including a plurality of second gate electrodes stacked in the first direction; a first penetrating via, the first penetrating via being in the first cell array structure and extending in the first direction; and a second penetrating via contacting a top surface of the first penetrating via in the first cell array structure and extending from the top surface of the first penetrating via into the second cell array structure in the first direction.

[0005] According to an embodiment of the present inventive concept, a three-dimensional (3D) semiconductor memory device may include: a peripheral circuit structure located on a substrate; a first cell array structure located on the peripheral circuit structure, the first cell array structure including a first stack including a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure located on the first cell array structure, the second cell array structure including a second stack including a plurality of second gate electrodes stacked in the first direction; a first through-via extending into the first stack in the first direction; and a second through-via extending into the second stack in the first direction. The second through-via may contact a top surface of the first through-via without a bonding pad therebetween and may be electrically connected to the peripheral circuit structure through the first through-via.

[0006] According to an embodiment of the present invention, an electronic system may include: a three-dimensional semiconductor memory device; and a controller electrically connected to the three-dimensional semiconductor memory device via input / output pads and configured to control the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include: a first cell array structure located on a substrate, the first cell array structure including a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure located on the first cell array structure, the second cell array structure including a plurality of second gate electrodes stacked in the first direction; a first through-via located in the first cell array structure and extending in the first direction; and a second through-via contacting a top surface of the first through-via in the first cell array structure and extending from the top surface of the first through-via in the first direction into the second cell array structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a block diagram illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0008] Figure 1B is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0009] Figure 1C is a perspective view schematically illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0010] Figure 1D and Figure 1E It is along Figure 1C 1 is a cross-sectional view taken along line II′ of FIG. 1 to illustrate a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0011] Figure 2 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0012] Figure 3A and Figure 3B Both show Figure 2 An enlarged cross-sectional view of the "P1" portion of the PCB.

[0013] Figure 4 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0014] Figure 5 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0015] Figure 6 It shows Figure 5 An enlarged cross-sectional view of the "P2" portion of the PCB.

[0016] Figure 7 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0017] Figure 8 It shows Figure 7 An enlarged cross-sectional view of the "P3" portion of the PCB.

[0018] Figure 9 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0019] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 and Figure 19 is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Example embodiments of the present invention will now be described more fully with reference to the accompanying drawings showing example embodiments. The terms "first," "second," etc., may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. The terms "include" and / or "comprise" as used herein indicate the presence of the elements described, but do not exclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more related listed items. The term "connected" may be used herein to indicate physical and / or electrical connections. When a component or layer is referred to herein as being "directly" on, or "in direct contact with," or "directly connected to," there are no intermediate components or layers. Similarly, when components are "close" to each other, there may be no intermediate components.

[0021] Figure 1A is a block diagram illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0022] refer to Figure 1A The three-dimensional semiconductor memory device may include a memory cell array 1 and a peripheral circuit 2 for controlling the memory cell array 1. The peripheral circuit 2 may include a row decoder 3, a page buffer 4, a common source line (CSL) voltage controller 5, a voltage generator 6, and control logic 7.

[0023] The memory cell array 1 may include a plurality of memory blocks BLK1-BLKz. Each of the memory blocks BLK1-BLKz may include a plurality of memory cells arranged in a three-dimensional manner. For example, the memory blocks BLK1-BLKz may include a plurality of stacked memory cells. In response to a block select signal, a data read or write operation may be performed on one of the memory blocks BLK1-BLKz. An erase operation may be performed on a memory cell in each memory block of the memory cell array 1.

[0024] In an embodiment, the three-dimensional semiconductor memory device may be a vertical NAND FLASH memory device. For the vertical NAND FLASH memory device, the memory blocks BLK1 -BLKz may include a plurality of cell strings arranged to form a NAND structure.

[0025] The row decoder 3 may be configured to decode address information transmitted from the outside, select at least one of the memory blocks BLK1, BLK2, ..., and BLKz based on the decoded address information, and select a word line WL, a string selection line SSL, and a ground selection line GSL in the selected memory block. The row decoder 3 may transmit an operating voltage to the word line WL of the selected memory block.

[0026] The page buffer 4 may be connected to the memory cell array 1 through the bit lines BL and may be used to determine data stored in the memory cells.

[0027] In a program operation, the page buffer 4 may function as a write driver that applies a voltage corresponding to data to be stored in the memory cell array 1 to the bit line BL, and in a read operation, the page buffer 4 may function as a sense amplifier that senses data stored in the memory cell array 1. The operation of the page buffer 4 may be controlled by a control signal transmitted from the control logic 7.

[0028] The CSL voltage controller 5 may be connected to the memory cell array 1 through the common source line CSL. The CSL voltage controller 5 may apply a common source voltage (eg, power supply or ground voltage) to the common source line CSL under the control of the control logic 7.

[0029] The voltage generator 6 may generate voltages required for internal operations of the memory cell array 1 (eg, a program voltage, a read voltage, an erase voltage, a pass voltage, a verification voltage, etc.) under the control of the control logic 7 .

[0030] The control logic 7 may generate various control signals required for programming, reading, and erasing the memory cell array 1 based on commands, addresses, and control signals.

[0031] Figure 1B is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0032] refer to Figure 1B According to an embodiment of the present inventive concept, an electronic system 1000 may include a three-dimensional semiconductor memory device 1100 and a controller 1200 electrically connected to each other. The electronic system 1000 may be a storage device including one or more three-dimensional semiconductor memory devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system provided with at least one three-dimensional semiconductor memory device 1100.

[0033] The three-dimensional semiconductor memory device 1100 may be a non-volatile memory device (eg, a NAND FLASH memory device). Figure 1A As described above, the three-dimensional semiconductor memory device 1100 may include a memory cell array 1 and a peripheral circuit 2 for controlling the memory cell array 1. The peripheral circuit 2 may include a row decoder 3, a page buffer 4, a CSL voltage controller 5, a voltage generator 6, and a control logic 7.

[0034] The three-dimensional semiconductor memory device 1100 may communicate with the controller 1200 through the input / output pads 1101 electrically connected to the control logic 7. The input / output pads 1101 may be electrically connected to the control logic 7 through the input / output interconnection lines 1135.

[0035] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In an embodiment, the electronic system 1000 may include a plurality of three-dimensional semiconductor memory devices 1100 , and in this case, the controller 1200 may be used to control the plurality of three-dimensional semiconductor memory devices 1100 .

[0036] The processor 1210 can control the overall operation of the electronic system 1000 including the controller 1200. Based on specific firmware, the processor 1210 can perform operations to control the NAND controller 1220 and access the three-dimensional semiconductor memory device 1100. The NAND controller 1220 can include a NAND interface 1221 for communicating with the three-dimensional semiconductor memory device 1100. The NAND interface 1221 can be configured to send and receive control commands for controlling the three-dimensional semiconductor memory device 1100, and to send data written to the memory cells of the three-dimensional semiconductor memory device 1100 and receive data read from the memory cells of the three-dimensional semiconductor memory device 1100. The host interface 1230 can be configured to allow communication between the electronic system 1000 and an external host. If a control command is provided from the external host via the host interface 1230, the processor 1210 can control the three-dimensional semiconductor memory device 1100 in response to the control command.

[0037] Figure 1C is a perspective view schematically illustrating an electronic system including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0038] refer to Figure 1C , the electronic system 2000 may include a main substrate 2001 and a controller 2002, one or more semiconductor packages 2003, and a DRAM 2004 mounted on the main substrate 2001. The semiconductor package 2003, the DRAM 2004, and the controller 2002 may be connected to each other through an interconnection pattern 2005 formed in the main substrate 2001.

[0039] Main substrate 2001 may include a connector 2006 containing multiple pins for coupling to an external host. The number and arrangement of pins in connector 2006 may vary depending on the communication interface between electronic system 2000 and the external host. In embodiments, electronic system 2000 may communicate with the external host using one or more interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS) M-Phy, and the like. In embodiments, electronic system 2000 may be driven by power supplied from the external host via connector 2006. Electronic system 2000 may also include a power management integrated circuit (PMIC) for separately supplying power from the external host to controller 2002 and semiconductor package 2003.

[0040] The controller 2002 may control a write or read operation on the semiconductor package 2003 and may increase an operation speed of the electronic system 2000 .

[0041] DRAM 2004 may be a buffer memory configured to alleviate technical difficulties caused by the speed difference between semiconductor package 2003, which serves as a data storage device, and an external host. In an embodiment, DRAM 2004 in electronic system 2000 may be used as a cache memory and may be used as a storage space for temporarily storing data during control operations of semiconductor package 2003. In the case where electronic system 2000 includes DRAM 2004, controller 2002 may further include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0042] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package provided with a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 below the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 provided on the package substrate 2100 to cover the semiconductor chip 2200 and the connection structure 2400.

[0043] The package substrate 2100 may be a printed circuit board including upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 1B Input / output pads 1101. Each semiconductor chip 2200 may include a stack 3210 and a vertical structure 3220. Each semiconductor chip 2200 may include a three-dimensional semiconductor memory device, which will be described below.

[0044] In an embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the upper pad 2130. Thus, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in the form of bonding wires and may be electrically connected to the upper pad 2130 of the package substrate 2100. In other embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) rather than via the connection structure 2400 provided in the form of bonding wires.

[0045] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on an independent interposer substrate prepared independently of the main substrate 2001 and may be connected to each other through interconnection lines provided in the interposer substrate.

[0046] Figure 1D and Figure 1E It is along Figure 1C 1 is a cross-sectional view taken along line II′ of FIG. 1 to illustrate a semiconductor package including a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0047] refer to Figure 1D and Figure 1E In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed on the top surface of the package substrate body 2120, a lower pad 2125 disposed on or exposed through the bottom surface of the package substrate body 2120, and an internal wire 2135 disposed in the package substrate body 2120 to electrically connect the upper pad 2130 to the lower pad 2125. The upper pad 2130 may be electrically connected to the connection structure 2400. Figure 1C As shown, the lower pad 2125 may be connected to the interconnection pattern 2005 of the main substrate 2001 of the electronic system 2000 through the conductive connection portion 2800 .

[0048] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region in which a peripheral interconnect line 3110 is provided. The second structure 3200 may include a source structure 3205, a stack 3210 provided on the source structure 3205, a vertical structure 3220 and a separation structure 3230 provided to penetrate the stack 3210, a bit line 3240 electrically connected to the vertical structure 3220, and a cell contact plug (not shown) electrically connected to a word line WL of the stack 3210.

[0049] In the drawings, the stack 3210 is shown as having a stepped structure, but the inventive concept is not limited to this example. For example, the stack 3210 may not have a stepped structure, and the layers of the stack 3210 may have substantially the same length.

[0050] In the drawings, the second structure 3200 is shown as a single object, but the present invention is not limited to this example. For example, a third structure (not shown) having the same or similar structure as the second structure 3200 may be provided on the second structure 3200. Here, the third structure may be electrically connected to the first structure 3100 via an additional penetrating structure (not shown). Alternatively, two or more structures similar or otherwise similar to the second structure 3200 may be further provided on the second structure 3200.

[0051] Each semiconductor chip 2200 may include a penetration line 3245 that is electrically connected to the peripheral interconnection line 3110 of the first structure 3100 and extends into the second structure 3200. The penetration line 3245 may be disposed outside the stack 3210, and in an embodiment, at least one penetration line 3245 may be disposed to penetrate the stack 3210. Each semiconductor chip 2200 may also include Figure 1C The input / output pads 2210 are electrically connected to the peripheral interconnection lines 3110 of the first structure 3100 through the lines 3265 .

[0052] refer to Figure 1E In the semiconductor package 2003A, each semiconductor chip 2200a may include: a semiconductor substrate 4010, a first structure 4100 located on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner.

[0053] The first structure 4100 may include a peripheral circuit region having peripheral interconnect lines 4110 and a first junction structure 4150 disposed therein. The second structure 4200 may include a source structure 4205, a stack 4210 disposed between the source structure 4205 and the first structure 4100, a vertical structure 4220 and a separation structure 4230 disposed through the stack 4210, and a second junction structure 4250 electrically connected to the vertical structure 4220 and the word lines WL of the stack 4210. For example, the second junction structure 4250 may be electrically connected to the vertical structure 4220 and the word lines WL via a bit line 4240 and a cell contact plug (not shown), each connected to the vertical structure 4220 and the word lines WL, respectively. The first junction structure 4150 of the first structure 4100 may contact and bond with the second junction structure 4250 of the second structure 4200. The bonding portion between the first junction structure 4150 and the second junction structure 4250 may be formed, for example, of copper (Cu).

[0054] In the drawings, the stack 4210 is shown as having a stepped structure, but the inventive concept is not limited to this example. For example, the stack 4210 may not have a stepped structure, and the layers of the stack 4210 may have substantially the same length.

[0055] In the drawings, the second structure 4200 is shown as a single object, but the present invention is not limited to this example. For example, a third structure (not shown) having the same or similar structure as the second structure 4200 may be provided on the second structure 4200. Here, the third structure may be electrically connected to the first structure 4100 via an additional penetrating structure (not shown). Alternatively, two or more structures similar to the second structure 4200 may be further provided on the second structure 4200.

[0056] Each semiconductor chip 2200a may further include Figure 1C The input / output pads 2210 are electrically connected to the peripheral interconnection lines 4110 of the first structure 4100 through the lines 4265 .

[0057] Figure 1D The semiconductor chip 2200 and Figure 1E The semiconductor chips 2200a may be electrically connected to each other through connection structures 2400 provided in the form of bonding wires. However, in an embodiment, the semiconductor chips (eg, Figure 1D The semiconductor chip 2200 and Figure 1E The semiconductor chips 2200 a ) may be electrically connected to each other through connection structures such as through silicon vias (TSVs).

[0058] Figure 2 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 3Aand Figure 3B Both show Figure 2 An enlarged cross-sectional view of the "P1" portion of the PCB.

[0059] refer to Figure 2 The three-dimensional semiconductor memory device may include: a substrate 10, a peripheral circuit structure PS located on the substrate 10, a first cell array structure CS1 located on the peripheral circuit structure PS, and a second cell array structure CS2 located on the first cell array structure CS1. The substrate 10 may correspond to Figure 1D semiconductor substrate 3010 or Figure 1E The peripheral circuit structure PS may correspond to the semiconductor substrate 4010. Figure 1D The first structure 3100 or Figure 1E The first cell array structure CS1 may correspond to the first structure 4100. Figure 1D The second structure 3200 or Figure 1E The second cell array structure CS2 may correspond to the reference Figure 1D or Figure 1E In the drawings, two cell array structures are shown as being stacked on the peripheral circuit structure PS, but the present invention is not limited to this example. For example, three or more cell array structures may be provided on the peripheral circuit structure PS.

[0060] According to embodiments of the present invention, the first cell array structure CS1 and the second cell array structure CS2 can be bonded to the peripheral circuit structure PS. In this case, the three-dimensional semiconductor memory device can have an increased cell capacity per unit area. Furthermore, the peripheral circuit structure PS, the first cell array structure CS1, and the second cell array structure CS2 can be manufactured separately and then bonded to each other through additional processes. This prevents damage to the peripheral transistor PTR, which will be described below, from various thermal treatment processes. This can improve the electrical characteristics and reliability of the three-dimensional semiconductor memory device.

[0061] The substrate 10 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a structure including a single crystal silicon substrate and a single crystal epitaxial layer grown therefrom. The top surface of the substrate 10 may be perpendicular to the first direction D1. The substrate 10 may include a cell array region CAR, a first extension region EXR1, and a second extension region EXR2.

[0062] The peripheral circuit structure PS on the substrate 10 may include a peripheral transistor PTR, a peripheral contact plug 31, a peripheral circuit interconnection line 33 electrically connected to the peripheral transistor PTR through the peripheral contact plug 31, a first bonding pad BP1 electrically connected to the peripheral circuit interconnection line 33, and a first insulating layer 30 provided to surround them. The terms "surround" or "surround" or "cover" or "fill" as used herein may not necessarily completely surround or surround or cover or fill the described element or layer, but may, for example, refer to partially surrounding or surrounding or covering or filling the described element or layer, with one or more interruptions or gaps. The peripheral transistor PTR may be provided on the active area of ​​the substrate 10.

[0063] In an embodiment, the peripheral transistor PTR may constitute a reference Figure 1A and Figure 1B The row decoder 3, page buffer 4, CSL voltage controller 5 and control logic 7 are described.

[0064] The peripheral circuit interconnection line 33 and the first bonding pad BP1 may be electrically connected to the peripheral transistors PTR via the peripheral contact plug 31. Each peripheral transistor PTR may be, for example, an NMOS transistor or a PMOS transistor.

[0065] In an embodiment, the peripheral contact plug 31 may have an increasing horizontal width as the height in the first direction D1 increases. The peripheral contact plug 31 and the peripheral circuit interconnection line 33 may be formed of or include at least one of a conductive material (e.g., a metal material).

[0066] The first insulating layer 30 may have a multilayer structure including a plurality of insulating layers. In an embodiment, the first insulating layer 30 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. In this specification, a low-k dielectric material may be defined as a material having a lower dielectric constant than silicon oxide.

[0067] In an embodiment, the first bonding pads BP1 may be formed of, or include, copper (Cu).The first bonding pads BP1 may make contact with and be electrically connected to the second bonding pads BP2, respectively.

[0068] The first cell array structure CS1 may be disposed on the peripheral circuit structure PS. The first cell array structure CS1 may include a first stack ST1, a first vertical structure VS1, a first bit line BL1, a first common source line CSL1, a first common source plug CSP1, a first cell contact plug CP1, a first penetration plug TP1, a first interconnection line 43, a first contact plug 41, a second bonding pad BP2, and a second insulating layer 40 covering them.

[0069] In an embodiment, each of the first interconnect line 43 and the first contact plug 41 may be formed of or include at least one conductive material (e.g., a metal material). The first contact plug 41 may have an increasing horizontal width as the height in the first direction D1 increases. In an embodiment, the second bonding pad BP2 may be formed of or include copper (Cu). The second insulating layer 40 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0070] The first stack ST1 may be provided on the first insulating layer 30. In an embodiment, a plurality of first stacks ST1 may be provided. As an example, when viewed in a top view, the first stacks ST1 may extend in a direction parallel to the top surface of the substrate 10 and be parallel to each other. Hereinafter, for the sake of brevity, only one first stack ST1 will be described, but other first stacks ST may also have similar or substantially the same features as described below.

[0071] The first stack ST1 may include first gate electrodes GE1 stacked in a first direction D1, first mold patterns ML1 disposed at the same height as the first gate electrodes GE1, and a first interlayer insulating layer (not shown) disposed between the first gate electrodes GE1 and between the first mold patterns ML1. The first interlayer insulating layer may be part of the second insulating layer 40.

[0072] The first gate electrode GE1 may extend continuously from the cell array region CAR to the second extension region EXR2. In an embodiment, the first gate electrode GE1 may have substantially the same length in its extension direction. The first mold pattern ML1 may extend horizontally on each of the cell array region CAR, the first extension region EXR1, and the second extension region EXR2.

[0073] In embodiments, the first gate electrode GE1 may be formed of, or include at least one of, a doped semiconductor material (e.g., doped silicon), a metal material (e.g., tungsten, copper, aluminum, and molybdenum), a conductive metal nitride material (e.g., titanium nitride and tantalum nitride), or a transition metal (e.g., titanium and tantalum). In embodiments, the first interlayer insulating layer may be formed of, or include at least one of, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. The first mold pattern ML1 may include an insulating material (e.g., silicon nitride) having an etch selectivity relative to the first interlayer insulating layer.

[0074] The first stack ST1 may be interposed between first separation patterns SP1 extending in a direction parallel to the top surface of the substrate 10. The first separation pattern SP1 may be formed of or include an insulating material (eg, silicon oxide).

[0075] The first vertical structure VS1 may be provided on the cell array region CAR to penetrate the first stack ST1 in the first direction D1 and may extend in the first direction D1. Specifically, the first vertical structure VS1 may penetrate the first gate electrode GE1 in the first direction D1. In embodiments, a plurality of first vertical structures VS1 may be provided. When viewed in a top view, the first vertical structures VS1 may be arranged in a zigzag shape in a direction parallel to the top surface of the substrate 10.

[0076] As the height in the first direction D1 increases, a portion of the first vertical structure VS1 may have an increasing horizontal width. Specifically, the first vertical structure VS1 may include a first portion configured to penetrate the lower portion of the first stack ST1 and a second portion configured to penetrate the upper portion of the first stack ST1. As the height in the first direction D1 increases, each of the first portion and the second portion of the first vertical structure VS1 may be configured to have an increasing horizontal width. The first portion and the second portion of the first vertical structure VS1 may define a step difference near the boundary therebetween or form a stepped structure, but the present inventive concept is not limited to this example.

[0077] The first vertical structure VS1 may be composed of multiple thin films. In embodiments, the first vertical structure VS1 may include a semiconductor pattern (not shown) comprising a semiconductor material (e.g., silicon (Si) or germanium (Ge)), a charge storage layer (not shown) serving as a data storage layer for a NAND FLASH memory device, a blocking insulating layer (not shown), and a tunnel insulating layer (not shown). In embodiments, the charge storage layer may be surrounded by the blocking insulating layer and the tunnel insulating layer and may be a trap insulating layer, a floating gate electrode, or an insulating layer having conductive nanodots.

[0078] The first bit line BL1 in the cell array region CAR may be interposed between the peripheral circuit structure PS and the first stack ST1, but the present invention is not limited to this example. The first bit line BL1 in the cell array region CAR may be disposed on the top surface of the first stack ST1. In an embodiment, the first bit line BL1 may be formed of or include at least one of conductive materials (e.g., metal materials).

[0079] In an embodiment, a plurality of first bit lines BL1 may be provided. Each first bit line BL1 may be electrically connected to a first vertical structure VS1 arranged along the extending direction of the first bit line BL1 through a first contact plug 41. The first bit line BL1 may be electrically connected to a second bonding pad BP2 through a first interconnect line 43 and the first contact plug 41. Thus, the first bit line BL1 may be electrically connected to the peripheral circuit structure PS through the aforementioned peripheral components.

[0080] In an embodiment, the first common source line CSL1 may be disposed on the first stack ST1, but the present invention is not limited to this example. For example, the first common source line CSL1 may be interposed between the peripheral circuit structure PS and the first stack ST1. In an embodiment, the first common source line CSL1 may be formed of or include at least one of a doped semiconductor material (e.g., doped silicon), a metal material (e.g., tungsten, molybdenum, nickel, copper, and aluminum), a conductive metal nitride material (e.g., titanium nitride and tantalum nitride), or a transition metal (e.g., titanium and tantalum).

[0081] The first common source line CSL1 may be electrically connected to the first vertical structure VS1 through the first contact plug 41. The first common source line CSL1 may extend from the cell array region CAR to the first extension region EXR1.

[0082] A first common source plug CSP1 may be disposed on the first extension region EXR1. The first common source plug CSP1 may penetrate the first mold pattern ML1 along a first direction D1. A through-pad TD may be disposed below the first common source plug CSP1. The first common source plug CSP1 and the through-pad TD may be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or a metal nitride material (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0083] The first common source plug CSP1 may be electrically connected to the first common source line CSL1 through the first contact plug 41. Therefore, the first common source line CSL1 may be electrically connected to the second bonding pad BP2 through the first common source plug CSP1, the penetration pad TD, the first contact plug 41, and the first interconnection line 43. Therefore, the first common source line CSL1 may be electrically connected to the peripheral circuit structure PS through the above-mentioned peripheral elements.

[0084] A first cell contact plug CP1 and a first through-plug TP1 may be disposed on each of the first extension region EXR1 and the second extension region EXR2 to penetrate the first gate electrode GE1 in the first direction D1. The first cell contact plug CP1 and the first through-plug TP1 may be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or a metal nitride material (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). The first cell contact plug CP1 may be electrically connected to the first through-plug TP1 via a first contact plug 41 and a first interconnect line 43. The first through-plug TP1 may be electrically connected to the second bonding pad BP2 via a through-pad TD, the first contact plug 41, and the first interconnect line 43. Thus, the first cell contact plug CP1 may be electrically connected to the peripheral circuit structure PS via the aforementioned peripheral components.

[0085] In an embodiment, a plurality of first cell contact plugs CP1 may be provided. The first cell contact plugs CP1 may be provided on the first extension region EXR1 and the second extension region EXR2. Each first cell contact plug CP1 may penetrate at least one first gate electrode GE1 and may contact and be electrically connected to the corresponding first gate electrode GE1. The first cell contact plugs CP1 may have different vertical lengths and may have bottom surfaces formed at different vertical heights relative to the substrate 10. In an embodiment, the vertical length of the first cell contact plugs CP1 may increase or decrease as the distance from the cell array region CAR increases.

[0086] Insulating spacers IS may be interposed between the first cell contact plug CP1 and the first gate electrode GE1 and between the first through plug TP1 and the first gate electrode GE1. In an embodiment, the insulating spacers IS may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

[0087] A first dam DAM1 may be provided on the cell array region CAR and the first and second extension regions EXR1 and EXR2 to penetrate the first stack ST1 in the first direction D1. Each first dam DAM1 may be interposed between the first gate electrode GE1 and the first mold pattern ML1 and may extend along the first direction D1 between the first gate electrode GE1 and the first mold pattern ML1. The first gate electrode GE1 may be separated from the first mold pattern ML1 by the first dam DAM1. In embodiments, the first dam DAM1 may include an insulating material.

[0088] The first through-via TV1 may be provided on each of the cell array region CAR, the first extension region EXR1, and the second extension region EXR2 to penetrate the first stack ST1 in the first direction D1. For example, the first through-via TV1 may penetrate the first mold pattern ML1 in the first direction D1. The first through-via TV1 may be surrounded by the first dam DAM1. Similar to the first vertical structure VS1, the first through-via TV1 may be provided to form a stepped structure (for example, defining a step difference along the sidewalls between the upper and lower portions of the first through-via TV1). For example, as the height in the first direction D1 increases relative to the substrate 10, the width of a portion of the first through-via TV1 may increase in a direction parallel to the top surface of the substrate 10.

[0089] In an embodiment, a plurality of first through vias TV1 may be provided. Each first through via TV1 may be electrically connected to the second bonding pad BP2 through the through pad TD, the first contact plug 41, and the first interconnection line 43. Therefore, the first through via TV1 may be electrically connected to the peripheral circuit structure PS through the above-mentioned peripheral elements.

[0090] refer to Figure 2 as well as Figure 3A and Figure 3B The first through-via TV1 may include a through-portion TO and a barrier pattern BM surrounding a side surface of the through-portion TO. As an example, the through-portion TO may be formed of or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). The barrier pattern BM may be formed of or include at least one of metal nitride materials (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0091] Return Reference Figure 2 The second cell array structure CS2 may be disposed on the first cell array structure CS1. The second cell array structure CS2 may include a second stack ST2, a second vertical structure VS2, a second bit line BL2, a second common source line CSL2, a second common source plug CSP2, a second cell contact plug CP2, a second penetration plug TP2, a second interconnection line 53, a second contact plug 51, and a third insulating layer 50 covering them.

[0092] The second interconnection line 53, the second contact plug 51, and the third insulating layer 50 may be provided to have similar or substantially the same features as the first interconnection line 43, the first contact plug 41, and the second insulating layer 40, respectively. The second contact plug 51 may have a decreasing horizontal width with increasing height in the first direction D1.

[0093] The second stack ST2 may be provided on the second insulating layer 40. The second stack ST2 may be provided to have similar or substantially the same features as the first stack ST1.

[0094] The second stack ST2 may include: second gate electrodes GE2 stacked along the first direction D1; second mold patterns ML2 disposed at the same height (relative to the substrate 10) as the second gate electrodes GE2; and a second interlayer insulating layer (not shown) disposed between the second gate electrodes GE2 and between the second mold patterns ML2. The second interlayer insulating layer may be part of the third insulating layer 50. The second gate electrode GE2, the second mold pattern ML2, and the second interlayer insulating layer may be configured to have similar or substantially the same features as the first gate electrode GE1, the first mold pattern ML1, and the first interlayer insulating layer, respectively.

[0095] The second stack ST2 may be interposed between second separation patterns SP2 extending in a direction parallel to the top surface of the substrate 10 and parallel to each other. The second separation patterns SP2 may be provided to have similar or substantially the same features as the first separation patterns SP1.

[0096] The second vertical structure VS2 may be provided on the cell array region CAR to penetrate the second stack ST2 in the first direction D1 and may extend in the first direction D1. In detail, the second vertical structure VS2 may penetrate the second gate electrode GE2 in the first direction D1. The second vertical structure VS2 may be provided to have similar or substantially the same features as the first vertical structure VS1. The second vertical structure VS2 may be spaced apart from the first vertical structure VS1 in the first direction D1. The first vertical structure VS1 and the second vertical structure VS2 may be symmetrically arranged relative to a horizontal plane therebetween (such as an interface BS between the first cell array structure CS1 and the second cell array structure CS2). For example, as the height in the first direction D1 increases relative to the substrate 10, a portion of the first vertical structure VS1 may have an increasing horizontal width, and a portion of the second vertical structure VS2 may have a decreasing horizontal width.

[0097] As an example, the second bit line BL2 may be disposed on the second stack ST2 on the cell array region CAR, but the present invention is not limited to this example. As another example, the second bit line BL2 may be disposed between the first stack ST1 and the second stack ST2 on the cell array region CAR. In an embodiment, the second bit line BL2 may be formed of the same material as the first bit line BL1, or include the same material as the first bit line BL1.

[0098] In an embodiment, a plurality of second bit lines BL2 may be provided, and each second bit line BL2 may be electrically connected to the second vertical structure VS2 arranged along the extending direction of the second bit line BL2 through a second contact plug 51 .

[0099] In an embodiment, the second common source line CSL2 may be interposed between the first stack ST1 and the second stack ST2, but the present invention is not limited to this example. For example, the second common source line CSL2 may be disposed on the second stack ST2. The second common source line CSL2 may be formed of the same material as the first common source line CSL1, or include the same material as the first common source line CSL1.

[0100] The second common source line CSL2 may be electrically connected to the second vertical structure VS2 through the second contact plug 51. The second common source line CSL2 may extend from the cell array region CAR to the first extension region EXR1.

[0101] A second common source plug CSP2 may be disposed on the first extension region EXR1 so as to penetrate the second mold pattern ML2 along the first direction D1. A portion of the second common source plug CSP2 (e.g., located at a height higher than the second vertical structure VS2) may have a shape similar to (or a mirror image of) the through-pad TD relative to a horizontal plane. As an example, the second common source plug CSP2 may include the same material as the first common source plug CSP1. The second common source plug CSP2 may be electrically connected to the second common source line CSL2 via a second contact plug 51.

[0102] The second cell contact plug CP2 and the second penetration plug TP2 may be provided on each of the first extension region EXR1 and the second extension region EXR2 to penetrate the second gate electrode GE2 in the first direction D1. In an embodiment, the second cell contact plug CP2 and the second penetration plug TP2 may be formed of the same material as the first cell contact plug CP1 and the first penetration plug TP1, or include the same material as the first cell contact plug CP1 and the first penetration plug TP1, respectively. The second cell contact plug CP2 may be electrically connected to the second penetration plug TP2 through the second contact plug 51 and the second interconnection line 53.

[0103] In an embodiment, a plurality of second cell contact plugs CP2 may be provided. Each second cell contact plug CP2 may penetrate at least one second gate electrode GE2 and may contact and be electrically connected to the corresponding second gate electrode GE2. The vertical length of the second cell contact plug CP2 may have substantially the same characteristics as the vertical length of the first cell contact plug CP1.

[0104] Insulating spacers IS may be interposed between the second cell contact plug CP2 and the second gate electrode GE2 and between the second penetration plug TP2 and the second gate electrode GE2 .

[0105] The second dam DAM2 may be provided on each of the cell array region CAR, the first extension region EXR1, and the second extension region EXR2 to penetrate the second stack ST2 in the first direction D1. The second dam DAM2 may be interposed between the second gate electrode GE2 and the second mold pattern ML2, respectively, and may extend in the first direction D1. The second gate electrode GE2 may be spaced apart from the second mold pattern ML2 by the second dam DAM2. In embodiments, the second dam DAM2 may include an insulating material.

[0106] The second through-via TV2 may be provided on each of the cell array region CAR, the first extension region EXR1, and the second extension region EXR2 to penetrate the second stack ST2 in the first direction D1. In an embodiment, the second through-via TV2 may be provided to penetrate the second mold pattern ML2 in the first direction D1. The second through-via TV2 may be surrounded by the second dam DAM2. Similar to the second vertical structure VS2, the second through-via TV2 may be provided to form a stepped structure (e.g., defining a step difference along the sidewalls between the upper and lower portions of the second through-via TV2). In an embodiment, as the height in the first direction D1 increases, a portion of the second through-via TV2 may have a decreasing width in a direction parallel to the top surface of the substrate 10. The vertical length of the second through-via TV2 may be greater than the vertical length of the second vertical structure VS2 in the first direction D1.

[0107] The second penetration via TV2 may be provided on the top surface Ta of the first penetration via TV1. The second penetration via TV2 may be in contact with the top surface Ta of the first penetration via TV1 and may extend continuously from the top surface Ta of the first penetration via TV1 to the second unit array structure CS2 in the first direction D1. The second penetration via TV2 may be electrically connected to the first penetration via TV1. The second penetration via TV2 may vertically overlap with the first penetration via TV1 in the first direction D1. When viewed along a line extending in a specific direction or in a plane perpendicular to a specific direction, the components or layers described with reference to "overlap" in a specific direction may be at least partially obscured from each other. A portion of the second penetration via TV2 may be located or may exist in the first unit array structure CS1.

[0108] In an embodiment, a plurality of second penetration vias TV2 may be provided. At least one of the second penetration vias TV2 may be electrically connected to the second bit line BL2 through the second interconnection line 53 and the second contact plug 51. At least one of the second penetration vias TV2 may be electrically connected to the second common source line CSL2 through the second interconnection line 53, the second contact plug 51, and the second common source plug CSP2. At least one of the second penetration vias TV2 may be electrically connected to the second cell contact plug CP2 through the second interconnection line 53, the second contact plug 51, and the second penetration plug TP2. At least one of the second penetration vias TV2 may be electrically connected to the input / output pad IOP through the second interconnection line 53 and the second contact plug 51.

[0109] Each second through-via TV2 may be provided on the top surface of the corresponding first through-via TV1. Each second through-via TV2 may be electrically connected to the corresponding first through-via TV1. Thus, each of the second bit line BL2, the second common source line CSL2, the second cell contact plug CP2, and the input / output pad IOP may be electrically connected to the peripheral circuit structure PS through the first through-via TV1 and the second through-via TV2.

[0110] According to an embodiment of the present inventive concept, the second through-via TV2 may contact the top surface Ta of the first through-via TV1 in the first cell array structure CS1 and may extend from the top surface Ta of the first through-via TV1 into the second cell array structure CS2 in a first direction D1. That is, the second through-via TV2 may extend continuously from the second cell array structure CS2 into the first cell array structure CS1, beyond the interface BS therebetween, to directly contact the top surface Ta of the first through-via TV1 below the interface between the cell array structures CS1 and CS2. Although no additional or distinct elements such as the first and second bonding pads BP1 and BP2 are provided, each of the second bit line BL2, the second common source line CSL2, the second cell contact plug CP2, and the input / output pad IOP may be electrically connected to the peripheral circuit structure PS via the first and second through-vias TV1 and TV2, which are in direct contact with each other without a bonding pad therebetween. Therefore, the process of forming additional elements such as the first and second bonding pads BP1 and BP2 may be omitted, simplifying the manufacturing process. This may enable the production and manufacture of a three-dimensional semiconductor memory device.

[0111] Furthermore, since the first through via TV1 and the second through via TV2 are directly bonded to each other without additional or different intermediate elements (such as the first bonding pad BP1 and the second bonding pad BP2) therebetween, the resistance between the first through via TV1 and the second through via TV2 can be reduced. Therefore, the electrical characteristics of the three-dimensional semiconductor memory device can be improved.

[0112] refer to Figure 3A and Figure 3B The second through-via TV2 may include a through-via portion TO, a connecting portion CO disposed between the through-via portion TO and the first through-via TV1, and a barrier pattern BM disposed to surround the through-via portion TO and the connecting portion CO. The through-via portion TO and the connecting portion CO may be distinguished from each other at a first height LV1. In an embodiment, the first height LV1 may be defined as the height at which the through-via portion TO and the connecting portion CO connect to form a stepped structure or step difference. In an embodiment, the through-via portion TO and the connecting portion CO may be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). The through-via portion TO and the connecting portion CO may be disposed to form a single object or member. The barrier pattern BM may be formed of or include at least one of a metal nitride material (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0113] The penetration portion TO may be a portion of the second penetration via TV2 penetrating the second stack ST2. A portion of the penetration portion TO may have a decreasing width in a direction parallel to the top surface of the substrate 10 as the height in the first direction D1 increases (relative to the substrate 10).

[0114] The connection portion CO may be located between the first stack ST1 and the second stack ST2. The side surface or sidewall of the connection portion CO may have a stepped structure or a step difference at a second height LV2 between the upper and lower portions of the connection portion CO. As described above, the second height LV2 may be defined as the height at which the side surface of the connection portion CO has the stepped structure or the step difference. The second height LV2 may be located at a height higher than the bonding surface BS (i.e., the interface between the second cell array structure CS2 and the first cell array structure CS1) relative to the substrate 10. The connection portion CO may include an upper portion COy located at a height higher than the second height LV2 and a lower portion COx located at a height lower than the second height LV2. The lower portion COx of the connection portion CO may be located above the first cell array structure CS1. The upper portion COy of the connection portion CO may be located below the second cell array structure CS2. When measured parallel to the top surface of the substrate 10, the width W2 of the upper portion COy of the connection portion CO may be greater than the width W1 of the lower portion COx of the connection portion CO, thereby defining the step difference.

[0115] The blocking pattern BM may cover the side surface of the connection portion CO and may extend continuously along the first direction D1 to the area between the penetration portion TO and the second stack ST2. The blocking pattern BM may be interposed between the connection portion CO and the first penetration via TV1. In an embodiment, the blocking pattern BM may be in contact with each of the connection portion CO and the first penetration via TV1.

[0116] Return Reference Figure 2 A protective layer PL may be disposed on the second cell array structure CS2. The protective layer PL may be a single layer made of a single material, or a composite layer including two or more materials. In an embodiment, the protective layer PL may have a structure in which silicon oxide, silicon nitride, and a polyimide-based material (e.g., photosensitive polyimide (PSPI)) are sequentially stacked, but the present inventive concept is not limited to this example.

[0117] The input / output pad IOP may be provided in the protection layer PL. A portion of the input / output pad IOP may be externally exposed or exposed to the outside through an opening in the protection layer PL. In an embodiment, the input / output pad IOP may be formed of or include at least one of conductive materials (e.g., a metal material).

[0118] In the following, reference will be made to Figures 4 to 9 Various examples of three-dimensional semiconductor memory devices are described in more detail. For brevity of description, previously described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0119] Figure 4is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0120] refer to Figure 4 , one of the peripheral transistors PTR may be used to control a voltage applied to each of the first common source line CSL1 and the second common source line CSL2 .

[0121] In detail, the first common source plug CSP1 and the first through-via TV1 adjacent to each other can be electrically connected to one of the second bonding pads BP2 via the first interconnect line 43 and the first contact plug 41. The second common source plug CSP2 can be electrically connected to the first through-via TV1 adjacent to the first common source plug CSP1 via the second through-via TV2. As described above, the first common source line CSL1 can be electrically connected to the first common source plug CSP1, and the second common source line CSL2 can be electrically connected to the second common source plug CSP2. In other words, the first common source line CSL1 and the second common source line CSL2 can be electrically connected to one of the second bonding pads BP2. Therefore, the voltage applied to each of the first common source line CSL1 and the second common source line CSL2 can be controlled by the peripheral transistor PTR electrically connected to one of the second bonding pads BP2.

[0122] Figure 5 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 6 It shows Figure 5 An enlarged cross-sectional view of the "P2" portion of the PCB.

[0123] refer to Figure 5 and Figure 6 , the first buffer layer BF1 and the second buffer layer BF2 may be disposed near the bonding surface BS. In detail, the first buffer layer BF1 may be disposed on the upper portion of the first cell array structure CS1, and the second buffer layer BF2 may be disposed on the lower portion of the second cell array structure CS2. The second buffer layer BF2 may be disposed on the first buffer layer BF1. The top surface of the first buffer layer BF1 and the bottom surface of the second buffer layer BF2 may contact each other. The contact surface between the top surface of the first buffer layer BF1 and the bottom surface of the second buffer layer BF2 may be defined as the bonding surface BS. In an embodiment, each of the first buffer layer BF1 and the second buffer layer BF2 may be formed of SiCN, or include SiCN.

[0124] The connection portion CO of the second through via TV2 may penetrate the first and second buffer layers BF1 and BF2 along the first direction D1. The connection portion CO of the second through via TV2 may have a stepped structure or a step difference at a height lower than the bonding surface BS. In an embodiment, the connection portion CO of the second through via TV2 may have a stepped structure or a step difference at the same height as the bottom surface of the first buffer layer BF1.

[0125] Figure 7 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 8 It shows Figure 7 An enlarged cross-sectional view of the "P3" portion of the PCB.

[0126] refer to Figure 7 and Figure 8 , the first cell array structure CS1 and the second cell array structure CS2 may directly contact each other without reference Figure 5 and Figure 6 The first buffer layer BF1 and the second buffer layer BF2 are described. The upper portion COy of the connection portion CO of the second through via TV2 may be partially located in the first cell array structure CS1. In other words, the connection portion CO of the second through via TV2 may have a stepped structure at a height lower than the bonding surface BS.

[0127] Figure 9 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0128] refer to Figure 9 , the first penetrating via TV1 may include a first word line penetrating via WTV1 electrically connected to the first penetrating plug TP1. The second penetrating via TV2 may include a second word line penetrating via WTV2 electrically connected to the second penetrating plug TP2. The structural relationship (eg, position and connection) between the first word line penetrating via WTV1 and the second word line penetrating via WTV2 may be the same as that of the reference Figure 2 The structural relationship between the first penetration via TV1 and the second penetration via TV2 described is the same or similar.

[0129] With reference Figure 2Unlike the described embodiment, the first dam DAM1 may not be interposed between the first word line penetration via WTV1 and the first penetration plug TP1, and the second dam DAM2 may not be interposed between the second word line penetration via WTV2 and the second penetration plug TP2. The first word line penetration via WTV1 may penetrate the first gate electrode GE1 along the first direction D1, and the second word line penetration via WTV2 may penetrate the second gate electrode GE2 along the first direction D1. Here, to electrically disconnect the first gate electrode GE1 from the first word line penetration via WTV1, an insulating spacer IS may be interposed between the first gate electrode GE1 and the first word line penetration via WTV1. Similarly, to electrically disconnect the second gate electrode GE2 from the second word line penetration via WTV2, an insulating spacer IS may be interposed between the second gate electrode GE2 and the second word line penetration via WTV2.

[0130] In the following, reference will be made to Figures 10 to 19 A method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept is described in more detail. For brevity of description, previously described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0131] Figures 10 to 15 is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0132] refer to Figure 10 , a peripheral circuit structure PS can be formed on the substrate 10. The formation of the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the active area of ​​the substrate 10, and forming a peripheral contact plug 31 electrically connected to the peripheral transistor PTR, a peripheral circuit interconnection line 33 and a first bonding pad BP1, and a first insulating layer 30 covering them. In the description of the manufacturing method, the substrate 10 will be referred to as the first substrate 10.

[0133] A top surface of the first bonding pad BP1 may be substantially coplanar with a top surface of the first insulating layer 30. In embodiments, a planarization process may be performed to form substantially coplanar surfaces.

[0134] refer to Figure 11 , through pads TD may be formed on an upper portion of the second substrate 15. A first stack ST1 in which first mold patterns ML1 and first interlayer insulating layers are alternately stacked in a first direction D1 may be formed on the second substrate 15. In an embodiment, the second substrate 15 may include a semiconductor substrate.

[0135] The first channel hole CA1, the first penetrating via hole VH1, the first source via hole SH1, and the first plug via hole PH1 may be formed to penetrate the first stack ST1 in the first direction D1. In an embodiment, the first channel hole CA1, the first penetrating via hole VH1, the first source via hole SH1, and the first plug via hole PH1 may be formed simultaneously, but the inventive concept is not limited to this example.

[0136] The first vertical structure VS1 may be formed in the first channel hole CA1. As an example, the formation of the first vertical structure VS1 may include sequentially forming a blocking insulating layer (not shown), a charge storage layer (not shown), a tunnel insulating layer (not shown), and a semiconductor pattern (not shown) in the first channel hole CA1.

[0137] The first dam DAM1 may be formed to penetrate the first stack ST1 in the first direction D1.

[0138] A trench may be formed to penetrate the first interlayer insulating layer and the first mold pattern ML1 in a first direction D1 and expose the second substrate 15. By replacing the first mold pattern ML1 exposed by the trench with a conductive material, a first gate electrode GE1 may be formed between the first interlayer insulating layers. The first mold pattern ML1 surrounded by the first dam DAM1 may remain in place without being replaced by the first gate electrode GE1. A first separation pattern SP1 may be formed to fill the inner region of the trench.

[0139] A first through-via TV1 may be formed to fill the first through-via hole VH1. A first common source plug CSP1 may be formed to fill the first source via hole SH1. An insulating spacer IS may conformally cover the inner surface of the first plug via hole PH1. Thereafter, a first through-plug TP1 may be formed to fill the remaining space of the first plug via hole PH1.

[0140] At least one of the first cell contact plugs CP1 may be formed to penetrate at least one of the first gate electrodes GE1 in the first direction D1 and to contact one of the first gate electrodes GE1. One of the first cell contact plugs CP1 may be formed to contact the uppermost one of the first gate electrodes GE1. Before forming the first cell contact plugs CP1, insulating spacers IS may be formed in the region where the first cell contact plugs CP1 are to be formed.

[0141] A second insulating layer 40 may be formed (eg, see Figure 2 ) to completely cover the first stack ST1.

[0142] First contact plugs 41 may be formed on top surfaces of the first vertical structure VS1 , the first common source plug CSP1 , the first cell contact plug CP1 , and the first penetration plug TP1 , respectively.

[0143] The first common source line CSL1 may be formed to cover a top surface of the first contact plug 41 in contact with a top surface of the first vertical structure VS1 and may extend to an area on the top surface of the first contact plug 41 in contact with a top surface of the first common source plug CSP1 .

[0144] Each of the first interconnection lines 43 may be formed to cover a top surface of the first contact plug 41 in contact with a top surface of the first cell contact plug CP1 and may extend to a region on a top surface of the first through plug TP1 .

[0145] The second insulating layer 40 may be formed by two or more different steps (eg, see Figure 2 Considering the time of performing the steps of forming the first common source line CSL1, the first contact plug 41 and the first interconnection line 43, the second insulating layer 40 may be formed at different time points (eg, see Figure 2 ) first part 40a.

[0146] A first connection hole CH1 may be formed on the first penetration via TV1. The first connection hole CH1 may vertically overlap with the first penetration via hole VH1, respectively. A first sacrificial layer SAL1 may be formed to fill the first connection hole CH1. In an embodiment, the first sacrificial layer SAL1 may be formed of or include at least one of C, polysilicon, W, or TiN. In an embodiment, during the formation of the first sacrificial layer SAL1, a planarization process may be further performed on the upper portion of the first sacrificial layer SAL1. In this case, the first sacrificial layer SAL1 may be formed to have a flat surface with respect to the second insulating layer 40 (e.g., see FIG. 4 ). Figure 2 ) is substantially coplanar with the top surface of the first portion 40a.

[0147] refer to Figure 12 , a second stack ST2 in which second mold patterns ML2 and second interlayer insulating layers are alternately stacked in the first direction D1 may be formed on the third substrate 20. In embodiments, the third substrate 20 may include a semiconductor substrate.

[0148] The second channel hole CA2 , the second through via hole VH2 , the second source via hole SH2 , and the second plug via hole PH2 may be formed to penetrate the second stack ST2 in the first direction D1 .

[0149] A second vertical structure VS2 may be formed in the second channel hole CA2. Figure 11 The formation of the second vertical structure VS2 is performed using the same method described for the formation of the first vertical structure VS1 .

[0150] The second dam DAM2 may be formed to penetrate the second stack ST2 in the first direction D1.

[0151] A trench may be formed to penetrate the second interlayer insulating layer and the second mold pattern ML2 in the first direction D1 and expose the third substrate 20. By replacing the second mold pattern ML2 exposed by the trench with a conductive material, a second gate electrode GE2 may be formed between the second interlayer insulating layers. The second mold pattern ML2 surrounded by the second dam DAM2 may remain in place without being replaced by the second gate electrode GE2. A second separation pattern SP2 may be formed to fill the interior area of ​​the trench.

[0152] The second sacrificial layer SAL2 may be formed to fill the second source via hole SH2 and the second plug via hole PH2. In an embodiment, during the formation of the second sacrificial layer SAL2, a planarization process may be further performed on an upper portion of the second sacrificial layer SAL2.

[0153] At least one of the second cell contact plugs CP2 may be formed to penetrate at least one of the second gate electrodes GE2 in the first direction D1 and to contact one of the second gate electrodes GE2. One of the second cell contact plugs CP2 may be formed to contact the uppermost one of the second gate electrodes GE2. Before forming the second cell contact plugs CP2, insulating spacers IS may be formed in the region where the second cell contact plugs CP2 are to be formed.

[0154] A third insulating layer 50 may be formed (eg, see Figure 2 ) to completely cover the second stack ST2.

[0155] Second contact plugs 51 may be formed on top surfaces of the second vertical structure VS2, the second sacrificial layer SAL2 filling the second source via hole SH2, the second cell contact plug CP2, and the second sacrificial layer SAL2 filling the second plug via hole PH2, respectively.

[0156] The second common source line CSL2 may be formed to cover a top surface of the second contact plug 51 contacting a top surface of the second vertical structure VS2 and may extend to an area on the top surface of the second contact plug 51 contacting a top surface of the second sacrificial layer SAL2 filling the second source via hole SH2.

[0157] Each second interconnection line 53 may be formed to cover a top surface of the second contact plug 51 in contact with a top surface of the second cell contact plug CP2 and may extend to a region on a top surface of the second sacrificial layer SAL2 filling the second plug via hole PH2 .

[0158] The third insulating layer 50 may be formed by two or more different steps (eg, see Figure 2 Considering the time of performing the steps of forming the second common source line CSL2, the second contact plug 51 and the second interconnection line 53, the third insulating layer 50 may be formed at different time points (eg, see Figure 2 ) first part 50a.

[0159] A second connection hole CH2 may be formed on the second through via hole VH2. The second connection holes CH2 may vertically overlap with the second through via holes VH2. The diameter of the second connection holes CH2 may be larger than the diameter of the first connection holes CH1. A second sacrificial layer SAL2 may be formed to fill the second through via hole VH2 and the second connection hole CH2. In embodiments, the second sacrificial layer SAL2 may be formed of or include at least one of C, polysilicon, W, or TiN.

[0160] refer to Figure 13 The second cell array structure CS2 may be vertically inverted. The inverted second cell array structure CS2 may then be bonded to the first cell array structure CS1, defining an interface along a bonding surface BS therebetween. The top surface of each first sacrificial layer SAL1 may be bonded to the bottom surface of the corresponding second sacrificial layer SAL2. Thus, the second sacrificial layers SAL2 may vertically overlap with the first through vias TV1, respectively.

[0161] refer to Figure 14 , the third substrate 20 may be removed, and thus the second sacrificial layer SAL2 may be exposed externally or to the outside. The exposed second sacrificial layer SAL2 may be removed from the areas above the second through via hole VH2, the second connection hole CH2, the second source via hole SH2, and the second plug via hole PH2. The first sacrificial layer SAL1 may be removed from the area above the first connection hole CH1.

[0162] Thereafter, the second through vias TV2 may be formed to fill the second through via hole VH2, the first connection hole CH1, and the second connection hole CH2. Each second through via TV2 may be formed to contact the corresponding first through via TV1. Therefore, even when there is no additional or different element (such as a reference hole CH1), the second through via TV2 may be formed to contact the corresponding first through via TV1. Figure 2The first and second cell array structures CS1 and CS2 may also be electrically connected to each other through the first and second through vias TV1 and TV2 when the first and second bonding pads BP1 and BP2 described above are disposed therebetween.

[0163] According to an embodiment of the present inventive concept, the diameter of each second connection hole CH2 can be larger than the diameter of the corresponding first connection hole CH1. Therefore, the second through via TV2 can easily fill the first connection hole CH1 and the second connection hole CH2. For example, the formation of voids in the second through via TV2 can be prevented, thereby improving the electrical characteristics of the three-dimensional semiconductor memory device.

[0164] A second common source plug CSP2 may be formed to fill the second source via hole SH2. A second penetrating plug TP2 may be formed to fill the second plug via hole PH2. Before forming the second penetrating plug TP2, an insulating spacer IS may be formed in the second plug via hole PH2.

[0165] A third insulating layer 50 may be formed (eg, see Figure 2 ) of the second portion 50b to completely cover the second stack ST2.

[0166] refer to Figure 15 , the first cell array structure CS1 and the second cell array structure CS2 bonded to each other may be vertically inverted. The second cell array structure CS2 may be attached to a carrier substrate 25. In embodiments, the carrier substrate 25 may be a glass substrate or a semiconductor substrate.

[0167] The second substrate 15 may be removed. A second insulating layer 40 (eg, see Figure 2 ) of the second portion 40b to completely cover the first stack ST1.

[0168] A second bonding pad BP2 may be formed in an upper portion of the first cell array structure CS1. In order to electrically connect the second bonding pad BP2 to the first vertical structure VS1 and the through pad TD, a second insulating layer 40 (eg, see FIG. 4 ) may be formed. Figure 2 ) is formed in the second portion 40b of the PCB.

[0169] The second insulating layer 40 may be formed by one or more steps (eg, see Figure 2 Considering the time of performing the steps of forming the second bonding pad BP2, the first contact plug 41 and the first interconnection line 43, the second insulating layer 40 may be formed at different time points (eg, see Figure 2 ) of the second portion 40b. In an embodiment, in addition to the first portion 40a and the second portion 40b, the second insulating layer 40 (eg, see Figure 2 ) may also include a first interlayer insulating layer.

[0170] Return Reference Figure 2 , the first cell array structure CS1 and the second cell array structure CS2 bonded to each other can be vertically inverted again. Thereafter, the first bonding pads BP1 in the peripheral circuit structure PS can respectively contact the second bonding pads BP2 in the first cell array structure CS1. Therefore, the peripheral circuit structure PS and the first cell array structure CS1 and the second cell array structure CS2 can be bonded to each other.

[0171] The carrier substrate 25 may be removed. The second portion 50b of the third insulating layer 50 (eg, see Figure 15 ) is formed on the third portion (not shown) of the third insulating layer 50. In an embodiment, the third insulating layer 50 may include a first portion 50a (eg, see Figure 15 ), the second portion 50b (see, for example, Figure 15 ), the third part and the second interlayer insulating layer.

[0172] A second bit line BL2, a second interconnection line 53, and a second contact plug 51 may be formed in the third insulating layer 50. A protection layer PL may be formed on the third insulating layer 50. An input / output pad IOP may be formed in the protection layer PL.

[0173] Figure 16 is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0174] refer to Figure 16 , in reference Figure 11 After the formation of the first sacrificial layer SAL1 described above, a first buffer layer BF1 may be formed on the first cell array structure CS1. Since the first buffer layer BF1 is formed, the top surface of the first sacrificial layer SAL1 may be prevented from being damaged by external factors.

[0175] In addition, in the reference Figure 12 After the formation of the second sacrificial layer SAL2 described above, a second buffer layer BF2 may be formed on the second cell array structure CS2. Since the second buffer layer BF2 is formed, the top surface of the second sacrificial layer SAL2 may be prevented from being damaged by external factors.

[0176] Thereafter, the second cell array structure CS2 may be vertically inverted, and then the first and second cell array structures CS1 and CS2 may be bonded to each other such that a top surface of the first buffer layer BF1 contacts a bottom surface of the second buffer layer BF2.

[0177] Return Reference Figure 5 , you can remove the reference Figure 16 The third substrate 20 described and the reference Figure 16 The second sacrificial layer SAL2 is described. Therefore, the reference Figure 16 A portion of the second buffer layer BF2 is depicted. The exposed portion of the second buffer layer BF2 and a portion of the first buffer layer BF1 may be removed. Next, the first sacrificial layer SAL1 may be removed.

[0178] Thereafter, the above method can be used to make reference Figure 5 The remainder of the three-dimensional semiconductor memory device is described.

[0179] Figure 17 is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0180] refer to Figure 17 , in reference Figure 11 After the formation of the first sacrificial layer SAL1 described above, a second insulating layer 40 (eg, see Figure 2 ) is formed to have a top surface located at a height higher than the top surface of the first sacrificial layer SAL1 (relative to the substrate 15). In this case, the top surface of the first sacrificial layer SAL1 can be prevented from being damaged by external causes.

[0181] In reference Figure 12 After the formation of the second sacrificial layer SAL2 as described above, a third insulating layer 50 (eg, see Figure 2 ) is formed to have a top surface located at a height higher than the top surface of the second sacrificial layer SAL2 (relative to the substrate 20). In this case, the top surface of the second sacrificial layer SAL2 can be prevented from being damaged by external causes.

[0182] Thereafter, the second cell array structure CS2 may be vertically inverted, and the first cell array structure CS1 and the second cell array structure CS2 may be bonded to each other.

[0183] Return Reference Figure 7 , the third substrate 20 and the second sacrificial layer SAL2 may be removed. The third insulating layer 50 (eg, see Figure 2 ) of the first portion 50a and the second insulating layer 40 (eg, see Figure 2 Next, the first sacrificial layer SAL1 may be removed.

[0184] Thereafter, the above method can be used to make reference Figure 7 The remainder of the three-dimensional semiconductor memory device is described.

[0185] Figure 18 and Figure 19 is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0186] refer to Figure 18 , in reference Figure 11 In the process of forming the first dam DAM1 described above, the first dam DAM1 may not be formed between the first penetration plug TP1 and the first penetration via TV1 and between the first cell contact plug CP1 and the first penetration via TV1. The first penetration via TV1 adjacent to the first penetration plug TP1 may penetrate the first gate electrode GE1 in the first direction D1. The insulating spacer IS may be formed on the side surface of the first penetration via TV1 adjacent to the first penetration plug TP1. The first penetration via TV1 adjacent to the first penetration plug TP1 may constitute a reference Figure 9 A first word line penetration via WTV1 is described.

[0187] refer to Figure 19 , in reference Figure 12 In the process of forming the second dam DAM2, the second dam DAM2 may not be formed between the second plug via hole PH2 and the second penetration via hole VH2 adjacent to each other, and between the second cell contact plug CP2 and the second penetration via hole VH2. The second sacrificial layer SAL2 filling the second penetration via hole VH2 adjacent to the second plug via hole PH2 may penetrate the second gate electrode GE2 in the first direction D1. Next, referring to Figure 9 The second sacrificial layer SAL2 in the second through via hole VH2 adjacent to the second plug via hole PH2 may be replaced by the second through via TV2. The second through via TV2 may constitute a second word line through via WTV2.

[0188] Thereafter, the above method can be used to make reference Figure 9 The remainder of the three-dimensional semiconductor memory device is described.

[0189] According to an embodiment of the present invention, the second through-via can contact the top surface of the first through-via in the first cell array structure and can extend along the first direction on the top surface of the first through-via into the second cell array structure. Because the first through-via and the second through-via are in direct contact with each other without a separate or distinct intermediate element (such as a first bonding pad and a second bonding pad) between them, each of the second bit line, the second common source line, the second cell contact plug, and the input / output pad can be electrically connected to the peripheral circuit structure through the first through-via and the second through-via. Therefore, the process of forming separate or distinct intermediate elements (such as a first bonding pad and a second bonding pad) can be omitted, simplifying the manufacturing process. As a result, the productivity of manufacturing three-dimensional semiconductor memory devices can be improved.

[0190] Furthermore, since the first through via and the second through via are in direct contact with each other without a separate or distinct intermediate element (such as a first bonding pad and a second bonding pad) therebetween, the resistance between the first through via and the second through via can be reduced. Consequently, the electrical characteristics of the three-dimensional semiconductor memory device can be improved.

[0191] According to an embodiment of the present invention, the second connection hole can be formed to have a larger diameter than the first connection hole. Therefore, the internal space of each of the first and second connection holes can be more easily filled with the second through-via. Therefore, a void can be eliminated in the second through-via, and the electrical characteristics of the three-dimensional semiconductor memory device can be improved.

[0192] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device, comprising: a first cell array structure, the first cell array structure being located on a substrate, the first cell array structure comprising a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure, the second cell array structure being located on the first cell array structure, the second cell array structure comprising a plurality of second gate electrodes stacked in the first direction; a first penetrating via extending in the first direction in the first cell array structure; as well as a second through via in contact with a top surface of the first through via in the first cell array structure, wherein the second through via extends from the top surface of the first through via into the second cell array structure in the first direction.

2. The three-dimensional semiconductor memory device according to claim 1, wherein The first cell array structure includes a first vertical structure extending into the first gate electrode in the first direction, wherein the second cell array structure includes a second vertical structure extending into the second gate electrode in the first direction, and The first vertical structure and the second vertical structure are spaced apart from each other in the first direction.

3. The three-dimensional semiconductor memory device according to claim 1, wherein The first cell array structure includes a first vertical structure extending into the first gate electrode in the first direction, wherein the second cell array structure includes a second vertical structure extending into the second gate electrode in the first direction, and The first vertical structure and the second vertical structure are symmetrical with respect to an interface between the first unit array structure and the second unit array structure.

4. The three-dimensional semiconductor memory device according to claim 1, wherein The second penetration via includes a penetration portion, a connection portion between the penetration portion and the first penetration via, and a blocking pattern extending around the penetration portion and the connection portion.

5. The three-dimensional semiconductor memory device according to claim 4, wherein The blocking pattern is located between the connecting portion and the first penetration via.

6. The three-dimensional semiconductor memory device according to claim 4, wherein The side wall of the connection portion includes a step difference between an upper portion and a lower portion of the connection portion.

7. The three-dimensional semiconductor memory device according to claim 4, wherein In a direction parallel to the top surface of the substrate, a width of an upper portion of the connection portion is greater than a width of a lower portion of the connection portion.

8. The three-dimensional semiconductor memory device according to claim 4, wherein The penetration portion vertically overlaps each of the connection portion and the first penetration via.

9. The three-dimensional semiconductor memory device according to claim 4, wherein The penetrating portion and the connecting portion are a single member.

10. The three-dimensional semiconductor memory device according to claim 1, further comprising: a peripheral circuit structure, the peripheral circuit structure being located between the substrate and the first cell array structure, The second penetrating via is electrically connected to the peripheral circuit structure through the first penetrating via.

11. The three-dimensional semiconductor memory device according to claim 1, wherein In a second direction perpendicular to the first direction, a width of a portion of the second penetration via decreases as it becomes farther from the top surface of the substrate in the first direction.

12. The three-dimensional semiconductor memory device according to claim 1, wherein In a second direction perpendicular to the first direction, a width of a portion of the first penetration via increases as it becomes farther from the top surface of the substrate in the first direction.

13. The three-dimensional semiconductor memory device according to claim 1, wherein The second cell array structure further includes: a second vertical structure extending into the second gate electrode, and In the first direction, a vertical length of the second penetrating via is greater than a vertical length of the second vertical structure.

14. A three-dimensional semiconductor memory device, comprising: A peripheral circuit structure, wherein the peripheral circuit structure is located on the substrate; a first cell array structure, the first cell array structure being located on the peripheral circuit structure, the first cell array structure comprising a first stack including a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure, the second cell array structure being located on the first cell array structure, the second cell array structure comprising a second stack, the second stack comprising a plurality of second gate electrodes stacked in the first direction; a first through-via extending into the first stack in the first direction; as well as a second through via extending into the second stack in the first direction, The second through via contacts a top surface of the first through via and is electrically connected to the peripheral circuit structure through the first through via.

15. The three-dimensional semiconductor memory device according to claim 14, wherein The second penetration path includes a penetration portion and a connecting portion between the penetration portion and the first penetration path, and The side wall of the connection portion includes a step difference between an upper portion and a lower portion of the connection portion.

16. The three-dimensional semiconductor memory device according to claim 15, wherein The second through via further includes a blocking pattern between the connection portion and the first through via.

17. The three-dimensional semiconductor memory device according to claim 14, wherein The first cell array structure further includes a first vertical structure extending into the first gate electrode in the first direction, The second cell array structure further includes a second vertical structure extending into the second gate electrode in the first direction, and The first vertical structure and the second vertical structure are spaced apart from each other in the first direction.

18. The three-dimensional semiconductor memory device according to claim 14, wherein The first cell array structure further includes a first vertical structure extending into the first gate electrode in the first direction, The second cell array structure further includes a second vertical structure extending into the second gate electrode in the first direction, and The first vertical structure and the second vertical structure are symmetrical with respect to an interface between the first unit array structure and the second unit array structure.

19. An electronic system, comprising: Three-dimensional semiconductor memory devices; as well as a controller electrically connected to the three-dimensional semiconductor memory device through input / output pads and configured to control the three-dimensional semiconductor memory device, Wherein, the three-dimensional semiconductor memory device comprises: a first cell array structure, the first cell array structure being located on a substrate, the first cell array structure comprising a plurality of first gate electrodes stacked in a first direction perpendicular to a top surface of the substrate; a second cell array structure, the second cell array structure being located on the first cell array structure, the second cell array structure comprising a plurality of second gate electrodes stacked in the first direction; a first penetrating via extending in the first direction in the first cell array structure; a second through via in contact with a top surface of the first through via in the first cell array structure, wherein the second through via extends from the top surface of the first through via into the second cell array structure in the first direction.

20. The electronic system according to claim 19, wherein the three-dimensional semiconductor memory device further comprises: a peripheral circuit structure, the peripheral circuit structure being located between the substrate and the first cell array structure, The second penetrating via is electrically connected to the peripheral circuit structure through the first penetrating via.

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