Semiconductor device

Abstract

Embodiments of the inventive concepts provide a semiconductor device including: a bit line extending in a first horizontal direction; an intermediate insulating layer on at least one side of the bit line and extending in a first horizontal direction; a channel structure including a lower portion on the bit line and the intermediate insulating layer, and an upper portion extending upward from the lower portion; and a word line on a lower portion of the channel structure and extending in a second horizontal direction intersecting the first horizontal direction to intersect the bit line, a lower portion of the channel structure includes a first portion covering an upper surface of the bit line, and a second portion extending downward from one end of the first portion and covering at least a portion of a side surface of the bit line on the intermediate insulating layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0035685 filed on March 14, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device. Background Art

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration level of semiconductor devices is also increasing. Therefore, when manufacturing semiconductor devices with fine patterns corresponding to the trend of high integration of semiconductor devices, it is necessary to realize patterns with fine widths and / or fine spacing. Summary of the Invention

[0004] An aspect of the inventive concept provides a semiconductor device that advantageously enhances on-current by increasing a contact area between a bit line and a channel structure.

[0005] According to one aspect of the present invention, a semiconductor device includes: a bit line extending in a first horizontal direction; an intermediate insulating layer on at least one side of the bit line and extending in the first horizontal direction so that the intermediate insulating layer contacts at least a portion of a side surface of the bit line; a channel structure including a lower portion and an upper portion, the lower portion of the channel structure being on the bit line and the intermediate insulating layer, and the upper portion of the channel structure extending upward from one end of the lower portion; and a word line on the lower portion of the channel structure and extending in a second horizontal direction to cross the bit line, the second horizontal direction intersecting the first horizontal direction, wherein the lower portion of the channel structure includes a first portion and a second portion, the first portion covering the upper surface of the bit line, and the second portion extending downward from one end of the first portion and covering at least a portion of the side surface of the bit line on the intermediate insulating layer.

[0006] According to one aspect of the present invention, a semiconductor device includes: a bit line extending in a first horizontal direction; an intermediate insulating layer extending in the first horizontal direction from at least one side of the bit line and having an upper surface at a height lower than an upper surface of the bit line; a channel structure including a lower portion and an upper portion, the lower portion of the channel structure being on the bit line and the intermediate insulating layer, and the upper portion of the channel structure extending upward from one end of the lower portion, the lower portion of the channel structure further comprising: a first line portion covering the upper surface of the bit line, and a second line portion extending downward from one end of the first line portion and covering a side surface of the bit line on the intermediate insulating layer; a word line on the lower portion of the channel structure and extending in a second horizontal direction to intersect the bit line, the second horizontal direction intersecting the first horizontal direction; and a dielectric structure extending in the second horizontal direction to intersect the bit line and the intermediate insulating layer, wherein the dielectric structure covers an outer surface of the lower portion of the channel structure and at least a portion of an upper surface of the intermediate insulating layer.

[0007] According to one aspect of the present invention, a semiconductor device includes: a lower insulating layer; a bit line on the lower insulating layer; an intermediate insulating layer on the side surface of a lower region of the bit line; a channel structure on the bit line; a word line on the channel structure so that the side surface of the word line faces the side surface of the channel structure; a dielectric structure between the word line and the channel structure; and a pad structure on the channel structure, wherein the bit line includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence, and the channel structure is in contact with the upper surface and side surfaces of the third conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view of a semiconductor device according to at least one example embodiment;

[0010] Figure 2 and Figure 3A is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0011] Figure 3B yes Figure 3A An enlarged view of a portion of the semiconductor device is shown;

[0012] Figures 4A to 4C is a partially enlarged view of a semiconductor device according to an example embodiment;

[0013] Figure 5 is a plan view of a semiconductor device according to at least one example embodiment;

[0014] Figure 6 is a cross-sectional view of a semiconductor device according to at least one example embodiment;

[0015] 7A to 22B are vertical cross-sectional views shown according to process sequence to explain a method of manufacturing a semiconductor device according to at least one example embodiment; and

[0016] Figure 23 is a schematic diagram of an electronic device according to at least one embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, exemplary embodiments of the present inventive concept will be described with reference to the accompanying drawings. It will be understood that when the term "approximately" or "substantially" is used in conjunction with a numerical value and / or geometric term in this specification, it is intended to indicate that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the numerical value. Furthermore, it will be understood that regardless of whether the numerical value and / or geometric term is modified by "approximately" or "substantially," these values ​​should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value and / or geometric term.

[0018] Furthermore, it will be understood that when a material layer is referred to as being "on" or "over" a substrate or other layer, the material layer can be directly on the substrate or other layer, or intervening layers can also be present. It will also be understood that such spatially relative terms, such as "above," "top," etc., are intended to encompass different orientations of the device when in use or operation other than the orientation depicted in the figures, and that the device may be otherwise oriented (rotated 90 degrees or at other orientations), so the spatially relative terms used herein should be interpreted accordingly. Furthermore, in the following embodiments, the materials included in each layer are examples, and other materials may be used in addition to or in place of the materials.

[0019] Figure 1 is a plan view of a semiconductor device according to at least one example embodiment.

[0020] Figure 2 and Figure 3A is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 FIG. 1 is a vertical cross-sectional view of the semiconductor device taken along line II′. Figure 3A It is along Figure 1 FIG. 1 is a vertical cross-sectional view of the semiconductor device taken along line II-II′.

[0021] Figure 3B yes Figure 3A An enlarged view of a portion of a semiconductor device is shown. Figure 3B It may be an enlarged view, in which the first upper insulating layer 81 a is not shown for convenience of explanation.

[0022] refer to Figures 1 to 3B, the semiconductor device 100 according to at least one example embodiment of the present disclosure may include a lower structure LS, a bit line 50 , an upper structure US, and an information storage structure 87 .

[0023] The lower structure LS may include a substrate 3 , a circuit element TR, a peripheral plug 20 , a peripheral interconnection 23 , a first peripheral insulating layer 30 , and a second peripheral insulating layer 32 .

[0024] Substrate 3 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, a Group IV semiconductor may include silicon, germanium, or silicon germanium. Substrate 3 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, and / or a substrate including an epitaxial layer.

[0025] The circuit element TR may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit. The circuit element TR may include a peripheral transistor. For example, the peripheral transistor may include a gate structure 12 disposed on a peripheral active region 9a defined by a device isolation region 9b in the substrate 3, and peripheral source / drain regions 15 disposed on both sides of the gate structure 12 within the peripheral active region 9a.

[0026] The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers, for example, a first conductive layer 12b1 and a second conductive layer 12b2 on the first conductive layer 12b1.

[0027] The peripheral plugs 20 may be connected to the corresponding peripheral source / drain regions 15 and extend vertically, and the peripheral interconnects 23 may be provided on the peripheral plugs 20. The peripheral interconnects 23 may be electrically connected to the circuit elements TR through the peripheral plugs 20. The first peripheral insulating layer 30 may surround the side surfaces of the peripheral gate electrodes 12 b and the peripheral plugs 20. The second peripheral insulating layer 32 may be provided on the first peripheral insulating layer 30 and may surround the peripheral plugs 20 and the peripheral interconnects 23. The upper surface of the second peripheral insulating layer 32 may be coplanar with the upper surface of the peripheral interconnects 23.

[0028] In at least one example embodiment, peripheral plug 20 and peripheral interconnect 23 may include a metal layer and a barrier layer configured to cover the side surfaces and lower surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, RuTiN, etc., and the metal layer may include a metal material such as W or Mo. First and second peripheral insulating layers 30 and 32 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, and / or combinations thereof.

[0029] The semiconductor device 100 may further include an etch stop layer 40 disposed on the lower structure LS. The etch stop layer 40 may cover the peripheral interconnection 23 and the second peripheral insulating layer 32. The etch stop layer 40 may include SiBN, SiCN, SiN, a combination thereof, or the like.

[0030] The bit lines 50 may be disposed on the lower structure LS. The bit lines 50 may extend in the Y direction and may be spaced apart from each other in the X direction. The semiconductor device 100 may further include a bit line plug 53 disposed below the bit line 50, and a lower insulating layer 56 surrounding the bit line 50 and the bit line plug 53. The bit line 50 may be electrically connected to a circuit element TR (e.g., a sensor amplifier) ​​of the lower structure LS via the bit line plug 53.

[0031] The bit line 50 may include multiple conductive patterns. In at least one example embodiment, the bit line 50 may include first to third conductive patterns 50a, 50b, and 50c stacked sequentially on the lower insulating layer 56. The first conductive pattern 50a may include a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The second conductive pattern 50b may include, for example, a metal nitride (e.g., titanium nitride (TiN)) or a silicide material (e.g., titanium silicide (TiSi)). The third conductive pattern 50c may include a semiconductor material (e.g., polysilicon). The third conductive pattern 50c may be a layer doped with impurities. However, the materials, number of layers, and thicknesses forming the bit line 50 may vary depending on the embodiment. The bit line plug 53 may include the same material as the peripheral plug 20 and the peripheral interconnect 23. The lower insulating layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, or a combination thereof.

[0032] An upper structure US may be disposed on the bit line 50. The upper structure US may include a mold structure MS, an intermediate insulating layer 54, a channel structure 73, a word line 79, an upper insulating structure 81, an upper capping layer 82, and a landing pad structure 83.

[0033] The mold structure MS may be disposed on the bit line 50. In a plan view, the mold structures MS may extend in the X direction and may be spaced apart from each other in the Y direction. The mold structure MS may include a lower mold layer M1 and an upper mold layer M2. The upper mold layer M2 may be disposed on the lower mold layer M1, and the lower mold layer M1 and the upper mold layer M2 may extend in the X direction.

[0034] The lower mold layer M1 and the upper mold layer M2 may include an insulator material (e.g., silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc.). In at least one example embodiment, the lower mold layer M1 and the upper mold layer M2 may include different materials. For example, the lower mold layer M1 may include silicon oxide, and the upper mold layer M2 may include silicon nitride.

[0035] An intermediate insulating layer 54 (or “bit line insulating layer” or “middle insulating layer”) may be provided on at least one side of the bit line 50 and extend in the Y direction. Figure 3B , the lower surface of the intermediate insulating layer 54 may be in contact with the upper surface of the lower insulating layer 56. The upper surface of the intermediate insulating layer 54 may be at a lower height than the upper surface of the bit line 50. Accordingly, the intermediate insulating layer 54 may be in contact with at least a portion of the side surface of the bit line 50, and a portion of the remaining side surface of the bit line 50 may be in contact with the channel structure 73. The intermediate insulating layer 54 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, a combination thereof, or the like. The intermediate insulating layer 54 may include a material different from that of the lower insulating layer 56. For example, the lower insulating layer 56 may include silicon oxide or a low-κ dielectric material, while the intermediate insulating layer 54 may include silicon nitride.

[0036] As described above, the bit lines 50 may include a plurality of bit lines 50 parallel to each other. The plurality of intermediate insulating layers 54 may be alternately arranged with the plurality of bit lines 50. For example, each of the plurality of intermediate insulating layers 54 may be disposed between a pair of adjacent bit lines of the plurality of bit lines 50.

[0037] Channel structure 73 may be disposed on bit line 50. Channel structure 73 may include a lower portion 73L contacting and electrically connected to bit line 50, and an upper portion 73S extending upward from one end of lower portion 73L in the Y direction. Upper portion 73S may be referred to as a vertical channel portion.

[0038] refer to Figure 3A and Figure 3B , the lower portion 73L can be defined as including: a first portion 73La covering the upper surface of the bit line 50, a second portion 73Lb extending downward from one end of the first portion 73La along the side surface of the bit line 50, and a third portion 73Lc extending horizontally from one end of the second portion 73Lb along the upper surface of the intermediate insulating layer 54. The third portion 73Lc can have an end 73Le on the intermediate insulating layer 54. For example, in a plan view, the plurality of channel structures 73 can be spaced apart from each other in the X direction. In some cases, the first portion 73La can be referred to as a first line portion, and the second portion 73Lb and the third portion 73Lc can be collectively referred to as a second line portion.

[0039] Since the second portion 73Lb of the channel structure extends downward from one end of the first portion 73La and covers the side surface of the bit line 50, the contact area between the channel structure 73 and the bit line 50 can be increased, thereby advantageously enhancing the reliability of the conduction current.

[0040] refer to Figure 2The upper portion 73S may extend upward from one end of the lower portion 73L along the side surface of the mold structure MS. The upper portion 73S may extend in a direction inclined to the vertical direction (Z direction), but the present inventive concept is not limited thereto.

[0041] The channel structure 73 may be formed of a semiconductor material such as silicon. The channel structure 73 may be formed of single-crystal silicon or polycrystalline silicon. However, the channel structure 73 is not limited to semiconductor materials such as silicon, but may be formed of other semiconductor materials that can function as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer, a two-dimensional material layer, or the like that can function as a channel region of a transistor.

[0042] The oxide semiconductor layer may be indium gallium zinc oxide (IGZO). However, the present inventive concept is not limited thereto. For example, the oxide semiconductor layer may include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), indium tin zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), indium gallium silicon oxide (InGaSiO), and the like.

[0043] The two-dimensional material layer may include at least one of a transition metal disulfide material layer, a black phosphorus material layer, and a hexagonal boron nitride (hBN) material layer that may have semiconductor properties. For example, the two-dimensional material layer may include at least one of BiOSe, Cr1, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials that can form two-dimensional semiconductor materials.

[0044] The dielectric structure 76 may extend in the X direction on the bit line 50 and the intermediate insulating layer 54 to cross the bit line 50 and the intermediate insulating layer 54 .

[0045] refer to Figure 3BThe dielectric structure 76 may extend in the X direction while covering the upper surface of the intermediate insulating layer 54 and at least a portion of the surface of the lower portion 73L of the channel structure. The dielectric structure 76 on the lower portion 73L of the channel structure may have a plurality of stepped portions s1 and s2. The first stepped portion s1 may be located on the second portion 73Lb of the lower portion 73L, and the second stepped portion s2 may be located on the third portion 73Lc of the lower portion 73L.

[0046] refer to Figure 3A The dielectric structure 76 may extend upward from one end of the lower portion 73L of the channel structure between the upper portion 73S of the channel structure and the word line 79. The upper surface of the dielectric structure 76 may be at substantially the same height as the upper surface of the mold structure MS, but the inventive concept is not limited thereto.

[0047] The dielectric structure 76 may be a tunnel dielectric layer that does not include an information storage layer. For example, the entire dielectric structure 76 may include at least one of silicon oxide and a high-κ dielectric. The high-κ dielectric may include a metal oxide and / or a semi-metal oxide. For example, the high-κ dielectric may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but the present disclosure is not limited thereto. The dielectric structure 76 may be formed of a single layer or multiple layers of the above materials.

[0048] In another example, dielectric structure 76 may include an information storage layer and a dielectric layer. For example, dielectric structure 76 may have polarization characteristics that depend on an electric field and may include a ferroelectric layer that exhibits remanent polarization due to a dipole even in the absence of an external electric field. This polarization state in the ferroelectric layer can be used to record data. Accordingly, dielectric structure 76 may include a ferroelectric layer, which may be referred to as an information storage layer. The ferroelectric layer, which may serve as the information storage layer, may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound having a ferroelectric material phase. For example, the Hf-based compound may be an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer, which may serve as the information storage layer, may include impurities (e.g., a ferroelectric material doped with at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr). For example, the ferroelectric layer that can serve as an information storage layer can be a material in which at least one of HfO2, ZrO2 and HZrO is doped with impurities (for example, at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc and Sr) and has a ferroelectric material phase.

[0049] In the dielectric structure 76 , the information storage layer is not limited to the above-mentioned material types and may include any material for storing information.

[0050] When viewed in a plan view, the word lines 79 may intersect the bit lines 50. For example, the word lines 79 may extend along the side surfaces of the mold structure MS in the X direction and may be spaced apart from each other in the Y direction. The word lines 79 may be disposed on the channel structure 73. For example, the word lines 79 may be disposed on the lower portion 73L of the channel structure 73 and vertically overlap with the upper portion 73S of the channel structure 73. The upper ends of the word lines 79 may be located at a height lower than the upper surface of the mold structure MS.

[0051] Upper insulating structures 81 may be respectively disposed between adjacent mold structures MS and may cover word lines 79. Upper insulating structures 81 may extend in the X direction and may be spaced apart from each other in the Y direction. Upper insulating structures 81 may be alternately disposed with mold structures MS in the Y direction.

[0052] The upper insulating structure 81 may include a first upper insulating layer 81a and a second upper insulating layer 81b. The first upper insulating layer 81a may be conformally disposed along the surfaces of the bit line 50, the channel structure 73, the dielectric structure 76, and the word line 79. The second upper insulating layer 81b may be disposed on the first upper insulating layer 81a and may fill the space between the mold structures MS. In at least one example embodiment, a portion of the first upper insulating layer 81a may cover a portion of the dielectric structure covering the upper surface of the upper mold layer M2. The first upper insulating layer 81a and the second upper insulating layer 81b may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric, or a combination thereof. For example, the first upper insulating layer 81a may include silicon nitride, and the second upper insulating layer 81b may include silicon oxide.

[0053] The upper capping layer 82 may cover the mold structure MS and the upper insulating structure 81 and may extend in the horizontal direction. The upper capping layer 82 may contact the upper surface of the first upper insulating layer 81a and the upper surface of the second upper insulating layer 81b. The upper capping layer 82 may include silicon nitride.

[0054] The landing pad structure 83 may be disposed on the channel structure 73 and may penetrate the upper capping layer 82 to contact the upper portion 73S of the channel structure 73. The landing pad structure 83 may be electrically connected to the bit line 50 through the channel structure 73.

[0055] The bonding pad structure 83 may include a pad portion, a connecting portion, and a contact portion. The pad portion may refer to a portion of the bonding pad structure 83 that is disposed on the upper capping layer 82 and may be in contact with the first electrode 88a of the information storage structure 87 described below. The connecting portion may be disposed below the pad portion and may vertically penetrate the upper capping layer 82. For example, the connecting portion may refer to a portion of the bonding pad structure 83 that is disposed between the lower surface of the pad portion and the upper surface of the molding structure MS. The contact portion may be disposed below the connecting portion and may be in contact with the upper surface of the channel structure 73. For example, the contact portion may refer to a portion of the bonding pad structure 83 that is located between the upper molding layer M2 of the molding structure MS and the upper end of the dielectric structure 76.

[0056] The landing pad structure 83 may include a metal layer and a barrier layer (not shown) covering a lower surface of the metal layer. The metal layer may include a metal material such as W or Mo, and the barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN.

[0057] In at least one example, the information storage structure 87 can be a capacitor configured to store information in a DRAM. For example, the dielectric layer 88b of the information storage structure 87 can be a capacitor dielectric layer of a DRAM, and the dielectric layer 88b can include a high-κ dielectric material, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like.

[0058] In another example, information storage structure 87 may be a structure configured to store information in a memory other than DRAM. For example, information storage structure 87 may be a capacitor of a ferroelectric RAM (FeRAM). For example, dielectric layer 88b may be a ferroelectric layer configured to record data using polarization states. In another example, dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. Here, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-κ dielectric.

[0059] In at least one example embodiment, when the dielectric structure 76 includes an information storage layer, the information storage structure 87 may be omitted.

[0060] Figures 4A to 4C is a partially enlarged view of a semiconductor device according to example embodiments.

[0061] refer to Figure 4A , except that the side surface 50S of the bit line 50 has an inclined or curved shape relative to the lower surface of the bit line 50 and the intermediate insulating layer 54 is located below the middle height 50ML of the bit line 50, the semiconductor device 100a can be similar to Figures 1 to 3B The semiconductor devices described in the accompanying drawings are the same as or substantially similar to those described in the accompanying drawings.

[0062] The bit line 50 of the semiconductor device 100a may have a side surface 50S that is inclined relative to the lower surface of the bit line 50. On the other hand, the horizontal width of the bit line 50 in the X direction may increase as approaching the lower surface of the bit line 50 from the upper surface of the bit line 50. Accordingly, the second portion 73Lb of the lower portion 73L of the channel structure 73 may also have a side surface that is inclined relative to the lower surface of the lower insulating layer 56.

[0063] The upper region of the side surface 50S of the bit line 50 may have an upwardly curved shape. The upper region of the side surface 50S of the bit line 50 may be defined as a region extending from the upper surface of the bit line 50 to the inclined portion of the side surface 50S. Accordingly, the upper region of the second portion 73Lb of the lower portion 73L of the channel structure 73 may also have an upwardly curved shape.

[0064] In the semiconductor device 100a, the intermediate insulating layer 54 may have a downwardly curved shape. Furthermore, the lower and upper surfaces of the intermediate insulating layer 54 may also have downwardly curved shapes. Accordingly, the lower surfaces of the second portion 73Lb and the third portion 73Lc of the lower portion 73L of the channel structure 73 may also have downwardly curved shapes. Furthermore, the surface of the end portion 73Le of the third portion 73Lc located on the intermediate insulating layer 54 may be inclined relative to the upper surface of the intermediate insulating layer 54.

[0065] Meanwhile, the uppermost height 54L of the intermediate insulating layer 54 may be located below the intermediate height 50ML of the bit line 50, where the intermediate height 50ML of the bit line 50 may be defined as being located midway between the heights of the upper and lower surfaces of the bit line 50. Based on the intermediate height 50ML, the bit line 50 may be defined as having an upper region 50UR located above it and a lower region 50LR located below it. Accordingly, the intermediate insulating layer 54 may be in contact with the outer surface of the lower region 50LR of the bit line 50.

[0066] The outer side surfaces of the plurality of stepped portions s1 and s2 of the dielectric structure 76 may have an upwardly curved shape. In addition, the dielectric structure 76 on the second portion 73Lb may have an inclined portion 76c1, and the dielectric structure 76 on the third portion 73Lc may have an inclined portion 76c2.

[0067] refer to Figure 4B , except that the intermediate insulating layer 54 has a concave portion 54c that is concave downward in an upper region thereof, the semiconductor device 100b may be similar to Figures 1 to 4A The semiconductor devices described in the accompanying drawings are the same as or substantially similar to those described in the accompanying drawings.

[0068] The intermediate insulating layer 54 may have a concave portion 54c that is recessed downward near the surface of the end portion 73Le of the third portion 73Lc of the channel structure 73. The outer surface of the concave portion 54c of the intermediate insulating layer 54 may be a surface that continuously extends from the surface of the end portion 73Le of the third portion 73Lc. The concave portion 54c of the intermediate insulating layer 54 may extend in the Y direction on at least one side of the bit line 50.

[0069] The dielectric structure 76 may include a portion filling the recessed portion 54c of the intermediate insulating layer 54. Accordingly, a lower surface of the dielectric structure 76 may be located at a height lower than a lowermost height of the channel structure 73.

[0070] refer to Figure 4C , except that the intermediate insulating layer 54 is located above the middle height 50ML of the bit line 50, the semiconductor device 100c can be Figures 1 to 4B The semiconductor devices described in the accompanying drawings are the same as or substantially similar to those described in the accompanying drawings.

[0071] An uppermost height 54L of the intermediate insulating layer 54 may be located above the middle height 50ML of the bit line 50. Accordingly, the intermediate insulating layer 54 may be in contact with an outer side surface 50 of the upper region 50UR of the bit line.

[0072] Figure 5 is a plan view of a semiconductor device according to at least one example embodiment.

[0073] Figure 6 is a cross-sectional view illustrating a semiconductor device according to at least one example embodiment. Figure 6 It is along Figure 5 FIG. 1 is a vertical cross-sectional view of the semiconductor device taken along line III-III′.

[0074] refer to Figure 5 and Figure 6 In addition to including the shielding pattern 60, the semiconductor device 200 according to at least one embodiment of the present inventive concept may be Figures 1 to 4B The semiconductor devices described in the accompanying drawings are the same as or substantially similar to those described in the accompanying drawings.

[0075] The semiconductor device 200 may further include shield patterns 60 extending in the Y direction and spaced apart from each other in the X direction. The shield patterns 60 may be alternately arranged with the bit lines 50 in the X direction. The lower surfaces of the shield patterns 60 may be arranged at a height lower than that of the lower surfaces of the bit lines 50, and the upper surfaces of the shield patterns 60 may be arranged at a height lower than that of the upper surfaces of the bit lines 50. The shield patterns 60 may reduce capacitance between the bit lines 50.

[0076] The shielding pattern 60 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0077] 7A to 20 are vertical cross-sectional views shown according to process sequence to explain a method of fabricating a semiconductor device according to at least one example embodiment.

[0078] Specifically, Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 is with Figure 2 Corresponding vertical cross-section. Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B is with Figure 3A Corresponding vertical cross-section.

[0079] refer to Figure 7A and Figure 7B , the lower structure LS can be formed. Figure 2 and Figure 3A As described, the lower structure LS may include a substrate 3, a circuit element TR on the substrate 3, a peripheral interconnection 23 and a peripheral plug 20 electrically connected to the circuit element TR, a first peripheral insulating layer 30 surrounding the side surface of the peripheral plug 20 and the side surface of the circuit element TR, and a second peripheral insulating layer 32 surrounding the peripheral interconnection 23 and the peripheral plug 20.

[0080] An etch stop layer 40 and a lower insulating layer 56 may be formed on the lower structure LS. The etch stop layer 40 may cover the peripheral interconnection 23 and the second peripheral insulating layer 32. The lower insulating layer 56 may cover the etch stop layer 40.

[0081] Bit line 50 and bit line plug 53 may be formed on etch stop layer 40 and lower insulating layer 56. For example, bit line plug 53 may be formed to penetrate etch stop layer 40 and lower insulating layer 56 to contact peripheral interconnection 23, and bit line 50 may be formed on bit line plug 53.

[0082] refer to Figure 8A and Figure 8B , the bit line 50 may be a patterned form of a plurality of bit lines 50 spaced apart from each other in the X direction.

[0083] After forming a predetermined mask layer on the bit line 50, the mask layer may be used to form an opening OP1 exposing the upper surface of the lower insulating layer 56. The predetermined mask layer may be, for example, a photoresist layer.

[0084] The openings OP1 may be formed to be spaced apart from each other in the X-direction, and accordingly, the bit lines 50 may be spaced apart from each other in the X-direction.

[0085] refer to Figure 9A and Figure 9B , an intermediate insulating layer 54 may be formed on at least one side of the bit line 50 .

[0086] In forming the insulating material to fill the Figure 8A and Figure 8B After forming the opening OP1 and covering the upper surface of the bit line 50, a planarization process may be performed on the insulating material. Accordingly, an intermediate insulating layer 54 may be formed having an upper surface substantially coplanar with the upper surface of the bit line 50. The intermediate insulating layer 54 may extend in the Y direction on at least one side of the bit line 50 and may be spaced apart from each other in the X direction.

[0087] refer to Figure 10A and Figure 10B , a portion of the intermediate insulating layer 54 may be removed to expose at least a portion of a side surface of the bit line 50 .

[0088] according to Figure 9A and Figure 9B , a predetermined mask layer may be formed on the bit line 50 and the intermediate insulating layer 54. Thereafter, using the mask layer, an opening OP2 exposing at least a portion of a side surface of the bit line 50 in the X direction may be formed.

[0089] An upper region of the intermediate insulating layer 54 may be removed via the opening OP2 .

[0090] refer to Figure 11A and Figure 11B , mold structures MS may be formed on the bit lines 50 , respectively.

[0091] A lower insulating material and an upper insulating material may be sequentially stacked to cover the bit line 50 and the intermediate insulating layer 54, and then the lower insulating material and the upper insulating material may be patterned to form a lower mold layer M1 and an upper mold layer M2. The lower mold layer M1 and the upper mold layer M2 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0092] The mold structures MS may extend on the bit line 50 in the X direction and may be spaced apart from each other in the Y direction. In at least one example embodiment, each mold structure MS may have a tapered shape whose horizontal width in the Y direction decreases moving upward, but the inventive concept is not limited thereto.

[0093] In at least one example embodiment, the lower mold layer M1 and the upper mold layer M2 may include different materials. For example, the lower mold layer M1 may include silicon oxide, and the upper mold layer M2 may include silicon nitride. In some example embodiments, the lower mold layer M1 and the upper mold layer M2 may include the same material and may be integrally formed.

[0094] refer to Figure 12A and Figure 12B , a channel material layer 73p can be formed.

[0095] The channel material layer 73p may be formed to cover the bit line 50, the intermediate insulating layer 54, and the mold structure MS. For example, the channel material layer 73p may conformally cover the mold structure MS.

[0096] refer to Figure 13A and Figure 13B , the channel material layer 73p can be patterned.

[0097] The channel material layer 73p may be patterned by means of an etching process (e.g., a chemical and / or mechanical etching process). Accordingly, the upper surface of the mold structure MS and the upper surface of the intermediate insulating layer 54 may be partially exposed, and a channel structure 73 may be formed. The channel structure 73 may include a lower portion 73L that contacts the bit line 50 and extends in a horizontal direction, and an upper portion 73S that extends upward along the side surface of the mold structure MS.

[0098] As reference Figure 3A and Figure 3B As described above, the lower portion 73L may include a portion 73La covering the upper surface of the bit line 50 , and portions 73Lb and 73Lc covering the side surfaces of the bit line 50 on the intermediate insulating layer 54 .

[0099] In at least one embodiment, the upper portion 73S may extend in a direction other than the vertical direction (Z direction), but the present invention is not limited thereto. In some embodiments, the upper portion 73S may extend in the vertical direction. The channel structures 73 may be spaced apart from each other in the X direction and the Y direction (see FIG. Figure 1 ).

[0100] The etching process may be performed by forming a predetermined mask layer on the channel material layer 73 p .

[0101] refer to Figure 14A and Figure 14B, a dielectric structure 76 and a conductive layer 79p can be formed.

[0102] The dielectric structure 76 may be conformally formed along the channel structure 73 , the intermediate insulating layer 54 , and the mold structure MS. A conductive layer 79 p may cover the dielectric structure 76 .

[0103] refer to Figure 15A and Figure 15B , the conductive layer 79 p may be etched by an anisotropic etching process to form a word line 79 .

[0104] In a plan view, the word lines 79 may intersect the bit lines 50. For example, the word lines 79 may be disposed on side surfaces of the mold structure MS to extend in the X direction and may be spaced apart from each other in the Y direction.

[0105] refer to 16A to 16B , an upper insulating structure 81 and an upper capping layer 82 can be formed.

[0106] The upper insulating structure 81 may include a first upper insulating layer 81a and a second upper insulating layer 81b. The first upper insulating layer 81a may be conformally formed along the bit line 50, the intermediate insulating layer 54, the channel structure 73, the dielectric structure 76, and the word line 79. The second upper insulating layer 81b may be formed by depositing an insulating material to cover the first upper insulating layer 81a and then planarizing the insulating material to expose the upper surface of the first upper insulating layer 81a. The upper insulating structures 81 may extend in the X direction and may be spaced apart from each other in the Y direction. The upper insulating structures 81 may be alternately arranged with the mold structures MS in the Y direction.

[0107] The upper capping layer 82 may cover the upper surface of the upper insulating structure 81 .

[0108] refer to Figure 17 , the upper capping layer 82 may be etched by means of an anisotropic etching process, and an opening OP3 exposing the channel structure 73 may be formed.

[0109] The opening OP3 may expose the upper surface of the vertical channel portion 73S. The opening OP3 may also expose the upper mold layer M2, the dielectric structure 76, and the upper insulating structure 81.

[0110] refer to Figure 18 , the channel structure 73 can be selectively etched.

[0111] Etching the channel structure 73 may include performing a first wet etching process. An etchant may flow into the opening OP3, and the upper portion of the upper portion 73S of the channel structure 73 may be selectively etched by the etchant. In at least one example embodiment, the upper surface of the etched upper portion 73S may be above the upper surface of the lower mold layer M1. The side surface of the dielectric structure 76 may be partially exposed by means of the first wet etching process.

[0112] refer to Figure 19 , a conductive layer 83 p may be formed to fill the opening OP3 and cover the upper capping layer 82 .

[0113] Conductive layer 83p may contact the upper surface of upper portion 73S. Conductive layer 83p may also partially contact the side surface of vertical channel portion 73S. Conductive layer 83p may be electrically connected to bit line 50 through channel structure 73. In an example, conductive layer 83p may include a metal layer and a barrier layer.

[0114] refer to Figure 20 , the conductive layer 83p can be patterned to form a landing pad structure 83.

[0115] Reference together Figure 2 After depositing an insulating material to cover the landing pad structure 83, the insulating material may be planarized to expose the upper surface of the landing pad structure 83, thereby forming an insulating pattern 86. The insulating pattern 86 may be disposed at the same height as the landing pad structure 83 and may electrically insulate the landing pad structures 83 from one another. The mold structure MS, the channel structure 73, the dielectric structure 76, the word line 79, the upper insulating structure 81, the upper capping layer 82, the landing pad structure 83, and the insulating pattern 86 may form an upper structure US.

[0116] An information storage structure 87 may be formed on the upper structure US to manufacture the semiconductor device 100. Figures 1 to 3B As described above, the information storage structure 87 may include a first electrode 88a electrically connected to and in contact with the landing pad structure 83, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0117] Figures 21A to 22B are vertical cross-sectional views shown according to process sequence to explain a method of fabricating a semiconductor device according to at least one example embodiment. Figures 21A to 22B Can be targeted and referenced Figures 7A to 20 Describes process diagrams of different individual manufacturing methods for semiconductor device manufacturing methods. Figure 21A and Figure 22A is with Figure 2 The corresponding vertical cross-section, and Figure 21B and Figure 22B is with Figure 3A Corresponding vertical cross-section.

[0118] at the same time, Figure 21A and Figure 21B They can be Figure 9A and Figure 9B The following process diagram. In addition, Figure 22A and Figure 22B The process can be followed by reference to Figure 12A and Figure 12B Describe the process.

[0119] refer to Figure 21A and Figure 21B , according to Figure 9A and Figure 9B After forming the intermediate insulating layer 54 , a mold structure MS may be formed on the bit line 50 .

[0120] After sequentially stacking the lower insulating material and the upper insulating material to cover the bit line 50 and the intermediate insulating layer 54, the lower insulating material and the upper insulating material may be patterned to form a lower mold layer M1 and an upper mold layer M2. Figure 11A and Figure 11B The upper insulation material described is thicker.

[0121] refer to Figure 22A and Figure 22B , the intermediate insulating layer 54 and a portion of the mold structure MS may be removed.

[0122] By means of an etching process, an upper region of the upper mold layer M2 of the mold structure MS may be removed, and a portion of the intermediate insulating layer 54 may also be removed, so that a portion of the side surface of the bit line 50 is exposed.

[0123] The etching process may be performed by forming a predetermined mask layer on the bit line 50 , the intermediate insulating layer 54 , and the mold structure MS.

[0124] Afterwards, as referenced Figure 12A and Figure 12B As described above, the channel material layer 73 p may be formed to conformally cover the bit line 50 , the intermediate insulating layer 54 , and the mold structure MS.

[0125] Similarly, with reference Figures 13A to 20 In the same manner, the semiconductor device 100 may be manufactured by forming the upper structure US and the information storage structure 87 on the upper structure US.

[0126] Figure 23 is a schematic diagram of an electronic device according to at least one embodiment.

[0127] refer to Figure 23 , electronic device 1000 includes one or more electronic device components including a processor (eg, processing circuitry) 1020 and a memory 1030 communicatively coupled together via a bus 1010 .

[0128] The processing circuit 1020 may include one or more instances of a processing circuit (e.g., hardware including logic circuitry, a hardware / software combination such as a processor executing software, or a combination thereof), may be included in one or more instances of the processing circuit, and / or may be implemented by one or more instances of the processing circuit. For example, the processing circuit 1020 may include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC). In some example embodiments, the memory 1030 may include a non-transitory computer-readable storage device (e.g., a solid-state drive (SSD)) storing an instruction program, and the processing circuit 1020 may be configured to execute the instruction program to implement the functions of the electronic device 1000.

[0129] In some example embodiments, the electronic device 1000 may include one or more additional components 1040 coupled to the bus 1010, the one or more additional components 1040 may include, for example, a power supply, a light sensor, a light emitting device, any combination thereof, etc. In some example embodiments, one or more of the processing circuit 1020, the memory 1030, or the one or more additional components 1040 may include a processor according to reference, for example Figures 1-6 Any one of the semiconductor devices of any one of the example embodiments described above.

[0130] According to embodiments of the inventive concept, a semiconductor device having advantageously enhanced on-current may be provided by increasing a contact area between a bit line and a channel structure.

[0131] Specifically, the semiconductor device of the present inventive concept may include a channel structure in contact not only with an upper surface of a bit line but also with at least a portion of a side surface of the bit line, thereby advantageously enhancing an on-current.

[0132] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a bit line extending in a first horizontal direction; an intermediate insulating layer on at least one side of the bit line and extending in the first horizontal direction such that the intermediate insulating layer contacts at least a portion of a side surface of the bit line; a channel structure comprising a lower portion and an upper portion, wherein the lower portion of the channel structure is on the bit line and the intermediate insulating layer, and the upper portion of the channel structure extends upward from one end of the lower portion; as well as a word line on the lower portion of the channel structure and extending in a second horizontal direction to cross the bit line, the second horizontal direction intersecting the first horizontal direction, The lower portion of the channel structure includes a first portion and a second portion, the first portion covers the upper surface of the bit line, and the second portion extends downward from one end of the first portion and covers at least a portion of the side surface of the bit line on the intermediate insulating layer.

2. The semiconductor device according to claim 1, wherein The lower portion of the channel structure further includes a third portion extending from one end of the second portion in the second horizontal direction along the upper surface of the intermediate insulating layer.

3. The semiconductor device according to claim 1, wherein At least a portion of the side surface of the bit line is inclined with respect to a lower surface of the bit line.

4. The semiconductor device according to claim 1, wherein The thickness of the bit line in the second horizontal direction increases from the upper surface of the bit line to the lower surface of the bit line.

5. The semiconductor device according to claim 1, wherein At least one of a lower surface or an upper surface of the intermediate insulating layer has a downwardly curved shape. The semiconductor device according to claim 1 , wherein: A lower surface of the intermediate insulating layer is at a lower height than a lower surface of the bit line.

7. The semiconductor device according to claim 1, wherein The intermediate insulating layer is adjacent to a lower region of the bit line such that the intermediate insulating layer contacts a side surface of the lower region of the bit line.

8. The semiconductor device according to claim 1, wherein The lower portion of the channel structure further includes a third portion extending from one end of the second portion in the second horizontal direction along the upper surface of the intermediate insulating layer and having an end portion on the intermediate insulating layer, and The intermediate insulating layer has a concave portion that is adjacent to the end portion of the third portion and is concave downward in an upper region of the intermediate insulating layer.

9. The semiconductor device according to claim 8, further comprising: a dielectric structure extending on the bit line and the intermediate insulating layer along the second horizontal direction to intersect the bit line and the intermediate insulating layer, The dielectric structure covers an outer surface of the lower portion of the channel structure and a surface of the concave portion of the intermediate insulating layer.

10. The semiconductor device according to claim 9, wherein The concave portion of the intermediate insulating layer extends in the first horizontal direction.

11. The semiconductor device according to claim 1, wherein The intermediate insulating layer is adjacent to the bit line such that the intermediate insulating layer contacts a side surface of the bit line in an upper region of the bit line.

12. The semiconductor device according to claim 1, further comprising: a dielectric structure extending on the bit line and the intermediate insulating layer along the second horizontal direction to intersect the bit line and the intermediate insulating layer, The dielectric structure covers an outer surface of the lower portion of the channel structure and at least a portion of an upper surface of the intermediate insulating layer.

13. The semiconductor device according to claim 12, wherein The dielectric structure extends upward from one end of the lower portion of the channel structure between the upper portion of the channel structure and the word line.

14. A semiconductor device comprising: a bit line extending in a first horizontal direction; an intermediate insulating layer extending in the first horizontal direction from at least one side of the bit line and having an upper surface at a lower height than an upper surface of the bit line; a channel structure comprising a lower portion and an upper portion, the lower portion of the channel structure being on the bit line and the intermediate insulating layer, and the upper portion of the channel structure extending upward from one end of the lower portion, the lower portion of the channel structure further comprising a first line portion covering an upper surface of the bit line, and a second line portion extending downward from one end of the first line portion and covering a side surface of the bit line on the intermediate insulating layer; a word line on the lower portion of the channel structure and extending in a second horizontal direction to cross the bit line, the second horizontal direction intersecting the first horizontal direction; as well as a dielectric structure extending in the second horizontal direction to intersect the bit line and the intermediate insulating layer, The dielectric structure covers an outer surface of the lower portion of the channel structure and at least a portion of an upper surface of the intermediate insulating layer.

15. The semiconductor device according to claim 14, wherein At least a portion of the side surface of the bit line has an upwardly curved shape, and The second line portion on the at least a portion of the side surface of the bit line has an upwardly bent shape.

16. The semiconductor device according to claim 14, wherein The second line portion has an end portion on the intermediate insulating layer, and The dielectric structure comprises: a first inclined portion on the side surface of the bit line; and A second inclined portion is on the end portion of the second line portion of the channel structure.

17. The semiconductor device according to claim 14, wherein The intermediate insulating layer includes silicon nitride.

18. The semiconductor device according to claim 14, wherein The channel structure includes an oxide semiconductor.

19. A semiconductor device comprising: Lower insulation layer; a bit line on the lower insulating layer; an intermediate insulating layer on a side surface of a lower region of the bit line; a channel structure on the bit line; a word line on the channel structure such that a side surface of the word line faces a side surface of the channel structure; a dielectric structure between the word line and the channel structure; as well as a pad structure on the trench structure, The bit line includes a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence, and The channel structure contacts an upper surface and side surfaces of the third conductive layer.

20. The semiconductor device according to claim 19, wherein The thickness of the third conductive layer is greater than the thickness of the first conductive layer, The intermediate insulating layer contacts the side surface of the first conductive layer and the lower surface of the channel structure, and The channel structure is spaced apart from the side surface of the first conductive layer.

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