Semiconductor device

Abstract

The embodiment provides a semiconductor device capable of effectively arranging wiring. According to one embodiment, a semiconductor device includes: a first substrate; and a logic circuit provided on the first substrate. The device is further provided with: a storage unit provided above the logic circuit; and a second substrate provided above the memory cell. The device is further provided with a bonding pad which is provided above the second substrate and is electrically connected to the logic circuit. The device is further provided with a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on July 24, 2019, with application number 201910672567.6 and titled “Semiconductor Device and Method for Manufacturing the Same.”

[0003] [Related Applications]

[0004] This application claims priority based on Japanese Patent Application No. 2019-37626 (filing date: March 1, 2019), and the entire contents of the basic application are incorporated herein by reference. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0006] Since semiconductor devices, such as three-dimensional memories, generally have many wirings, efficient layout of these wirings is important in design. For example, the layout is required to achieve noise reduction, low resistance, and high speed. Summary of the Invention

[0007] Embodiments provide a semiconductor device capable of efficiently laying out wiring and a method of manufacturing the same.

[0008] According to one embodiment, a semiconductor device includes: a first substrate; and a logic circuit disposed on the first substrate. The device further includes: a memory cell disposed above the logic circuit; and a second substrate disposed above the memory cell. The device further includes a bonding pad disposed above the second substrate and electrically connected to the logic circuit. The device further includes wiring disposed above the second substrate and electrically connected to the memory cell, including at least one of a data signal line, a control voltage line, and a power supply line.

[0009] The bonding pads and the wiring are preferably included in the same wiring layer provided on the second substrate.

[0010] The semiconductor device preferably further includes an insulating film provided on an upper surface of the wiring and having an opening that exposes an upper surface of the bonding pad.

[0011] The memory cell is preferably disposed above the logic circuit.

[0012] The wiring is preferably used to transmit an input signal to or output signal from the semiconductor device, to supply a control voltage to the memory cell, or to supply power to the semiconductor device.

[0013] The wiring is preferably provided at a position not in contact with the bonding pad or at a position in contact with the bonding pad.

[0014] According to an embodiment, a semiconductor device capable of efficiently laying out wiring and a method of manufacturing the same are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0016] Figure 2 It is a cross-sectional view showing the structure of the columnar portion according to the first embodiment.

[0017] Figure 3 This is a cross-sectional view for explaining one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Figure 4 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0019] Figure 5 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0020] Figure 6 and Figure 7 It is a cross-sectional view showing the structure of the second plug according to the first embodiment.

[0021] Figure 8 This is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment.

[0022] Figure 9 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0023] Figure 10 It is a plan view showing the structure of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 10 In the drawings, the same or similar components are denoted by the same reference numerals and repeated descriptions are omitted.

[0025] (First embodiment)

[0026] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device is a three-dimensional memory formed by bonding a memory array chip 1 (hereinafter, simply referred to as array chip 1) and a circuit chip 2.

[0027] Array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating layer 12 on memory cell array 11, a substrate 13 on insulating layer 12, an insulating layer 14 on substrate 13, an interlayer insulating film 15 below memory cell array 11, and a first insulating layer 16 below interlayer insulating film 15. Insulating layers 12 and 14 are, for example, silicon oxide films or silicon nitride films. Substrate 13 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 13 is an example of a second substrate.

[0028] Circuit chip 2 is disposed below array chip 1. Symbol S denotes the bonding surface between array chip 1 and circuit chip 2. Circuit chip 2 includes a second insulating layer 17, an interlayer insulating film 18 below second insulating layer 17, and a substrate 19 below interlayer insulating film 18. Substrate 19 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 19 is an example of a first substrate.

[0029] Figure 1 In the present invention, two directions parallel to the surfaces S1 and S2 of the substrate 13 or the surfaces S3 and S4 of the substrate 19 and perpendicular to each other are defined as the X direction and the Y direction, respectively. Here, the direction perpendicular to the paper is defined as the Y direction. In addition, the Z direction perpendicular to the surfaces S1 and S2 of the substrate 13 or the surfaces S3 and S4 of the substrate 19 is defined. In this specification, the direction upward from the paper is the +Z direction, and the direction downward from the paper is the -Z direction. The -Z direction may or may not coincide with the direction of gravity.

[0030] The array chip 1 includes a plurality of word lines WL, a source side select gate SGS, a drain side select gate SGD, and a source line SL as an electrode layer in the memory cell array 11. The memory cell array 11 includes a stepped structure portion 21. Figure 1 As shown, the end of each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22, and the source-side select gate SGS is electrically connected to a source-side select gate wiring layer 25 via a contact plug 24. Furthermore, the drain-side select gate SGD is electrically connected to a drain-side select gate wiring layer 27 via a contact plug 26, and the source line SL is electrically connected to a source wiring layer 30 via a contact plug 29. The columnar portion CL that passes through the word line WL, the source-side select gate SGS, the drain-side select gate SGD, and the source line SL is electrically connected to the bit line BL via a plug 28, and is also electrically connected to the substrate 13.

[0031] Circuit chip 2 includes multiple transistors 31 on substrate 19. Each transistor 31 includes a gate electrode 32 provided on substrate 19 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within substrate 19. Circuit chip 2 also includes multiple plugs 33 provided on the source diffusion layer or drain diffusion layer of each transistor 31; a wiring layer 34 provided on these plugs 33 and including multiple wirings; and a wiring layer 35 provided on wiring layer 34 and including multiple wirings. Circuit chip 2 also includes multiple through-hole plugs 36 provided on wiring layer 35; and multiple second metal pads 37 provided on these through-hole plugs 36 within second insulating layer 17. Circuit chip 2 functions as a control circuit (logic circuit) that controls array chip 1.

[0032] Array chip 1 includes: a plurality of first metal pads 41, each disposed in correspondence with a plurality of second metal pads 37 within first insulating layer 16; a plurality of through-hole plugs 42, each disposed in correspondence with these plurality of first metal pads 41; and a wiring layer 43 including a plurality of wiring lines disposed in correspondence with these through-hole plugs 42. Each word line WL or bit line BL in this embodiment is electrically connected to a corresponding wiring line within wiring layer 43. Array chip 1 further includes: a first plug 44, disposed within interlayer insulating film 15 and insulating layer 12, and disposed on wiring layer 43; a second plug 46, disposed within substrate 13 and insulating layer 14 via insulating film 45, and disposed on first plug 44; and a pad 47, disposed on insulating layer 14, and disposed on second plug 46. The pad 47 is an external connection pad (bonding pad) of the semiconductor device of this embodiment, and can be connected to a mounting substrate or other devices via a solder ball, a metal bump, a bonding wire, or the like.

[0033] Furthermore, in this embodiment, the first insulating layer 16 is formed on the lower surface of the interlayer insulating film 15, but the first insulating layer 16 may be included in and integrated with the interlayer insulating film 15. Similarly, in this embodiment, the second insulating layer 17 is formed on the upper surface of the interlayer insulating film 18, but the second insulating layer 17 may be included in and integrated with the interlayer insulating film 18.

[0034] Figure 2 It is a cross-sectional view showing the structure of the columnar portion according to the first embodiment.

[0035] like Figure 2 As shown, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 alternately stacked on an interlayer insulating film 15. Each word line WL is, for example, a W (tungsten) layer, and each insulating layer 51 is, for example, a silicon oxide film.

[0036] The columnar portion CL includes, in this order, a blocking insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53 is, for example, a silicon nitride film, and the interposed blocking insulating film 52 is formed on the side surfaces of the word line WL and the insulating layer 51. The channel semiconductor layer 55 is, for example, a silicon layer, and the interposed tunnel insulating film 54 is formed on the side surfaces of the charge storage layer 53. Examples of the blocking insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are silicon oxide films or metal insulating films.

[0037] Figure 3 This is a cross-sectional view for explaining one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0038] Figure 3 Array wafer W1 includes multiple array chips 1, and circuit wafer W2 includes multiple circuit chips 2. Array wafer W1 is also called a memory wafer, and circuit wafer W2 is also called a CMOS (complementary metal oxide semiconductor) wafer. Array wafer W1 includes memory cell array 11 and other components formed on substrate 13, while circuit wafer W2 includes transistors 31 and other components formed on substrate 19.

[0039] First, array wafer W1 and circuit wafer W2 are bonded together using mechanical pressure. This bonds first insulating layer 16 to second insulating layer 17. Next, array wafer W1 and circuit wafer W2 are annealed at 400°C. This bonds first metal pad 41 to second metal pad 37.

[0040] After that, the substrates 13 and 19 are thinned by CMP (Chemical Mechanical Polishing), and then the array wafer W1 and the circuit wafer W2 are cut into multiple chips. Figure 1 Furthermore, the insulating layer 14, the insulating film 45, the second plug 46, and the pad 47 are formed on or in the substrate 13 after the substrate 13 is thinned, for example.

[0041] In addition, in this embodiment, the array wafer W1 and the circuit wafer W2 are bonded together, but the array wafers W1 may be bonded together and the circuit chip 2 may be separated from the array wafers W1. Figures 1 to 3 In the above mentioned content, or reference Figures 4 to 10 The contents described below can also be applied to the bonding of array wafers W1 .

[0042] Furthermore, the array wafer W1 includes the memory cell array 11 of a three-dimensional memory in this embodiment, but may instead include a memory cell array of a two-dimensional memory.

[0043] in addition, Figure 1 The interface between the first insulating layer 16 and the second insulating layer 17, or the interface between the first metal pad 41 and the second metal pad 37, is shown, but these interfaces are usually not observed after the annealing. However, the positions of these interfaces can be estimated by detecting, for example, the inclination of the side surface of the first metal pad 41 or the side surface of the second metal pad 37, or the positional deviation between the side surface of the first metal pad 41 and the second metal pad 37.

[0044] Figure 4 is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment, from Figure 1 The semiconductor device according to the first embodiment will be described from different viewpoints. Figure 1 1 shows a set of first plugs 44, insulating films 45, and second plugs 46 provided on the wiring layer 43. Figure 4 Four sets of first plugs 44 , insulating films 45 , and second plugs 46 provided on the wiring layer 43 are shown.

[0045] Figure 4 The wiring layer 20 formed on the insulating layer 14 is further shown. The wiring layer 20 is a metal conductive layer such as an Al (aluminum) layer. The wiring layer 20 includes wiring (routing wiring) 48 that electrically connects one portion between the substrate 13 and the substrate 19 to another portion. Figure 4 In the embodiment, one set of first and second plugs 44 and 46 is electrically connected to one end of the wiring 48 , and the other set of first and second plugs 44 and 46 is electrically connected to the other end of the wiring 48 . Figure 4 The wiring 48 is electrically connected to the logic circuit in the circuit chip 2 via these ends.

[0046] The wiring layer 20 of this embodiment includes not only the wiring 48 but also the pads 47. That is, the pads 47 and the wiring 48 of this embodiment are formed by the same wiring layer 20. Thus, the pads 47 and the wiring 48 can be formed simply. In this embodiment, after the array chip W1 and the circuit chip W2 are bonded together (see FIG. Figure 3 ), an insulating layer 14 and a wiring layer 20 are sequentially formed on a substrate 13, the wiring layer 20 is processed by etching, and a pad 47 and a wiring 48 are formed from the wiring layer 20.

[0047] In addition, for easy understanding of the description, Figure 4, the figure shows a step difference between the upper surface of the pad 47 and the upper surface of the wiring 48, but this step difference does not need to be provided. In addition, in this embodiment, the wiring 48 is provided at a position not in contact with the pad 47, but it can also be provided at a position in contact with the pad 47 as in the embodiment described below. Whether the wiring 48 is provided at a position in contact with the pad 47 is determined by the purpose of the wiring 48, such as a signal line (data signal line), a control voltage line, or a power line.

[0048] Figure 4 The figure further shows a passivation film 49 formed on the wiring layer 20. The passivation film 49 is, for example, an insulating film such as a silicon oxide film. The passivation film 49 covers the upper surface of the wiring 48 and has an opening P that exposes the upper surface of the pad 47. This allows the passivation film 49 to protect the wiring 48 and connect solder balls, metal bumps, bonding wires, etc. to the pad 47 within the opening P.

[0049] Figure 4 The pads 47 are arranged on the two sets of first and second plugs 44 and 46, and are electrically connected to the logic circuit in the chip 2 through these plug circuits. The shapes of these plugs will be described in detail below.

[0050] Figure 5 It is a plan view showing the structure of the semiconductor device according to the first embodiment. Figure 4 Indicates along Figure 5 For the sake of convenience, each component in different XY cross sections is summarized in the figure. Figure 5 For detailed positional relationships between components, please refer to Figure 4 Cross-sectional view, etc.

[0051] Figure 5 The diagram shows four planes 61 constituting the memory cell array 11. The memory cell array 11 includes a plurality of memory cells, and these memory cells operate in units called planes 61. Specifically, writing, reading, and erasing operations on the memory cells are performed in each plane 61. Figure 5 Furthermore, eight row decoders 62, four data processing circuits 63, and two control voltage generating circuits 64 are provided for these planes 61. The row decoders 62, data processing circuits 63, and control voltage generating circuits 64 are located near the memory cell array 11 in the array chip 1 or within the logic circuit in the circuit chip 2.

[0052] The row decoder 62 applies control voltages to control lines such as the word lines WL of the memory cell array 11. Examples of such control voltages include a write voltage (VPRG), an erase voltage (VERASE), an intermediate voltage (VPASS), and a source voltage (VSL). The control voltages are generated by a control voltage generation circuit 64 and supplied to the row decoder 62.

[0053] The data processing circuit 63 processes input signals to or output signals from the semiconductor device. Examples of such signals include a data signal (DQ), a chip enable signal (CEn), a read enable signal (REn), a write enable signal (WEn), an address latch enable signal (ALE), and a command latch enable signal (CLE).

[0054] and Figure 4 Likewise, Figure 5 4 and 5 show pads 47 and wiring 48 included in the wiring layer 20. As an example, Figure 5 10 pads 47 and 10 wirings 48 denoted by reference numerals A1 to A8, B1, and B2 are shown. The wirings 48 are also appropriately referred to as "wirings A1 to A8, B1, and B2." Figure 5 Furthermore, the positions of the second plugs 46 electrically connected to these wirings 48 are schematically shown.

[0055] Symbol Wx represents the width of each pad 47 in the X direction, symbol Wy represents the width of each pad 47 in the Y direction, and symbol W represents the width of each wiring 48. In this embodiment, the width W of the wiring 48 is set to be thinner than the widths Wx and Wy of the pads 47 (W<Wx, W<Wy). Furthermore, the widths Wx and Wy of the pads 47 may differ from one another. Similarly, the widths W of the wiring 48 may differ from one another.

[0056] Wirings A1 to A8 electrically connect one data processing circuit 63 to another data processing circuit 63 and transmit the input or output signals. These wirings A1 to A8 extend in the Y direction, and the width W of wirings A1 to A8 corresponds to the length of wirings A1 to A8 in the X direction.

[0057] Wirings B1 and B2 electrically connect one control voltage generating circuit 64 to two row decoders 62, supplying the control voltage generated by the control voltage generating circuit 64 to the row decoders 62. These wirings B1 and B2 have a first portion extending in the X direction and a second portion extending in the Y direction. The width W of wirings B1 and B2 in the first portion corresponds to the length of wirings B1 and B2 in the Y direction, and in the second portion corresponds to the length of wirings B1 and B2 in the X direction.

[0058] Figure 5The portions of these wirings 48 that contact the second plugs 46 (in the example shown, the ends of the wirings 48) are schematically shown as circles. However, please note that these circles are shown to facilitate understanding of the positions of the second plugs 46 and do not represent the shapes of the wirings 48. Each wiring 48 is electrically connected to the row decoder 62, the data processing circuit 63, the control voltage generating circuit 64, and the like via the second plugs 46. In this embodiment, the width W of each wiring 48 remains constant, both in the portion contacting the second plug 46 and in other portions.

[0059] Figure 6 and Figure 7 It is a cross-sectional view showing the structure of the second plug 46 according to the first embodiment.

[0060] Figure 4 Four first plugs 44 are shown, each of which is as follows Figure 6 or Figure 7 As shown, it can also be composed of multiple thin plugs. Figure 6 The first plug 44 is shown as being provided under the bonding pad 47 and being composed of a plurality of thin plugs V1 . Figure 7 The first plug 44 is shown as being provided under the wiring 48 and being composed of a plurality of thin plugs V2.

[0061] According to the present embodiment, by forming each first plug 44 with a plurality of thin plugs, the resistance can be reduced compared to the case where each first plug 44 is formed with a single thin plug.

[0062] like Figure 6 As shown, the two first plugs 44 under the pad 47 are composed of a plurality of plugs V1. The two first plugs 44 under the pad 47 are composed of, for example, 100 plugs V1. Figure 7 As shown, the two first plugs 44 below the wiring 48 are each composed of a plurality of plugs V2. For example, each of the two first plugs 44 below the wiring 48 is composed of 50 plugs V2. In this case, the semiconductor device of this embodiment includes one set of plugs V1 below the pad 47 and two sets of plugs V2 below the wiring 48. One set of plugs V1 includes 100 plugs V1, and one set of plugs V2 includes 50 plugs V2. The reason the number of plugs V2 is smaller is that the width W of the wiring 48 is smaller than the widths Wx and Wy of the pad 47.

[0063] In addition, each second plug 46 may be composed of a plurality of thin plugs, similarly to the first plug 44 .

[0064] Figure 8 This is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment.

[0065] Figure 8The diagram shows a plurality of planes 61 constituting the memory cell array 11 , and a plurality of row decoders 62 , a plurality of SA / DL units 71 , a plurality of XDL units 72 , and a plurality of YLOG units 73 provided for these planes 61 . Figure 8 Furthermore, a series circuit 74, an I / O (Input / Output) circuit 75, a low voltage generating circuit 81, a high voltage generating circuit 82, a row control circuit 83, and a column control circuit 84 are shown. These are located near the memory cell array 11 in the array chip 1 or in the logic circuit in the circuit chip 2. Figure 8 Next, the controller 3 included in the semiconductor device of this embodiment is shown.

[0066] Each SA / DL unit 71 comprises a sense amplifier circuit and a data latch circuit that senses data read from the bit lines BL of plane 61. Each XDL unit 72 comprises a data latch circuit that stores data transmitted from the SA / DL unit 71 or the I / O circuit 75. Each YLOG unit 73 decodes a column address and selects a latch circuit within the XDL unit 72 based on the decoding result. The series circuit 74 provides a serial bus, etc., shared by multiple planes 61. The I / O circuit 75 exchanges input and output signals with the controller 3.

[0067] The low voltage generating circuit 81 and the high voltage generating circuit 82 constitute the control voltage generating circuit 64 and generate a low voltage and a high voltage, respectively, for use as control voltages. The row control circuit 83 and the column control circuit 84 respectively control the rows and columns of each plane 61.

[0068] The wirings A1 to A8 of this embodiment (see Figure 5 ) is used, for example, to transmit and receive input signals or output signals between the I / O circuit 75 and the XDL unit 72. In addition, the wirings B1 and B2 (see Figure 5 ) is used, for example, to supply a control voltage from the low voltage generating circuit 81 or the high voltage generating circuit 82 to the row decoder 62.

[0069] Below, reference Figure 4 and Figure 5 , the semiconductor device of this embodiment is described in detail.

[0070] like Figure 4 As shown, in the semiconductor device of this embodiment, a bonding pad 47 is provided at a position higher than the memory cell array 11 or the logic circuit, and a space for arranging a structure is reserved near the bonding pad 47. Therefore, in this embodiment, a wiring 48 is arranged near the bonding pad 47, and the wiring 48 is used as a signal line or a control voltage line.

[0071] Thus, according to this embodiment, wiring can be efficiently arranged within a semiconductor device, as in the following example. For example, by arranging a certain wiring as wiring 48 above substrate 13 rather than between substrate 13 and substrate 19, the congestion of wiring between substrate 13 and substrate 19 can be alleviated. In addition, when wiring 48 is used as a signal line, since wiring 48 is located above substrate 13, which is less susceptible to noise, the noise of the signal within the signal line can be reduced. In addition, by reducing the number of wirings between substrate 13 and substrate 19, the number of wiring layers between substrate 13 and substrate 19 can be reduced. As a result, the thickness of the semiconductor device can be reduced, or the operation of the semiconductor device can be accelerated by shortening the length of the wiring. In addition, when wiring 48 is used as a control voltage line, by making use of the extra space to make wiring 48 thicker, the influence of wiring resistance on the control voltage can be reduced.

[0072] Furthermore, in this embodiment, the wiring 48 is formed from the same wiring layer 20 as the pad 47. However, as long as the wiring 48 and the pad 47 are on the same surface (here, on the insulating layer 14), they may be formed from another wiring layer 20 formed by a different process. However, as described above, if the wiring 48 is also formed simultaneously in the same wiring layer 20 during the formation step of the pad 47, for example, the manufacturing steps of the semiconductor device can be simplified.

[0073] As described above, according to this embodiment, by arranging not only the pads 47 but also the wirings 48 above the substrate 13 , it is possible to efficiently lay out the wirings in the semiconductor device.

[0074] (Second embodiment)

[0075] Figure 9 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0076] Figure 9 Represents Figure 4 Same cross-section. But, Figure 4 The wiring 48 is provided at a position where it does not contact the pad 47. Figure 9 The wiring 48 is provided at a position in contact with the pad 47. The wiring 48 of this embodiment is formed by the same wiring layer 20 as the pad 47 as in the first embodiment, but may be formed by a wiring layer 20 different from the pad 47. In addition, for easy understanding of the description, Figure 9 4 shows a step between the upper surface of the pad 47 and the upper surface of the wiring 48 , but such a step may not be provided.

[0077] Figure 10 It is a plan view showing the structure of a semiconductor device according to a second embodiment. Figure 9 Indicates along Figure 10 But please note that Figure 9 In order to facilitate the understanding of the description, the position of the second plug 46 under the wiring 48 is the same as Figure 10 different.

[0078] Figure 10 and Figure 9 Likewise, pads 47 and wirings 48 included in the wiring layer 20 are shown. Figure 10 As an example, ten pads 47 and two wirings 48 indicated by reference numerals C1 and C2 are shown. These pads 47 include two power supply pads 47a and 47b. The wirings 48 are also appropriately referred to as "wirings C1 and C2." Figure 10 Furthermore, the positions of the second plugs 46 electrically connected to these wirings 48 are schematically shown.

[0079] Symbol Wx represents the width of each pad 47 in the X direction, symbol Wy represents the width of each pad 47 in the Y direction, and symbol W represents the width of each wiring 48. As in the first embodiment, the width W of the wiring 48 in this embodiment is set to be narrower than the widths Wx and Wy of the pad 47 (W < Wx, W < Wy). Furthermore, the widths Wx and Wy of the pads 47 may differ from one another. Similarly, the widths W of the wiring 48 may also differ from one another.

[0080] Wiring C1 electrically connects power pad 47a to the peripheral circuits of the semiconductor device, supplying power to the semiconductor device. Similarly, wiring C2 electrically connects power pad 47b to the peripheral circuits of the semiconductor device, supplying power to the semiconductor device. Wirings C1 and C2 have a first portion extending in the X direction and a second portion extending in the Y direction. The width W of wirings C1 and C2 in the first portion corresponds to the length of wirings C1 and C2 in the Y direction, and in the second portion corresponds to the length of wirings C1 and C2 in the X direction.

[0081] Examples of wirings C1 and C2 are power supply lines that supply a ground voltage (VSS voltage), a power supply voltage (VDD voltage), or another power supply voltage (VDDQ voltage). For example, wiring C1 is a VSS voltage line, and wiring C2 is a VDD voltage line. In this case, power supply pad 47a is used to apply the VSS voltage to the semiconductor device, and power supply pad 47b is used to apply the VDD voltage to the semiconductor device.

[0082] Figure 10The positions of the second plugs 46 electrically connected to these wirings 48 are schematically indicated by circles. However, please note that these circles are shown to facilitate understanding of the positions of the second plugs 46 and do not represent the shapes of the second plugs 46. Each wiring 48 is electrically connected to the peripheral circuits of the semiconductor device via these second plugs 46. The width W of each wiring 48 in this embodiment is set to the same value in the portion directly above these second plugs 46 and in other portions. In addition, please note that in the semiconductor device of this embodiment, a second plug 46 is also provided under each pad 47 (see FIG. Figure 9 ).

[0083] According to this embodiment, similar to the first embodiment, wiring can be efficiently arranged within the semiconductor device. For example, when wiring 48 is used as a power line, the influence of wiring resistance on power supply power can be reduced by making wiring 48 thicker by utilizing the remaining space.

[0084] also, Figure 5 The arrangement of the wiring 48 shown is similar to Figure 10 The arrangement of the wiring 48 shown can also be applied to the same semiconductor device. In addition, the semiconductor device of the first embodiment or the second embodiment is a three-dimensional memory manufactured from two wafers (array wafer W1 and circuit wafer W2), but these embodiments can also be applied to semiconductor devices manufactured from a single wafer or semiconductor devices other than three-dimensional memories.

[0085] While several embodiments have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. The novel devices and methods described in this specification may be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications may be made to the devices and methods described in this specification without departing from the spirit of the invention. The scope of the appended claims and their equivalents are intended to encompass such aspects and variations within the scope or spirit of the invention.

[0086] [Explanation of symbols]

[0087] 1 Array Chip

[0088] 2 circuit chips

[0089] 3 Controller

[0090] 11 Memory Cell Array

[0091] 12 Insulation layer

[0092] 13 substrate

[0093] 14 Insulation layer

[0094] 15. Interlayer insulation film

[0095] 16 First insulation layer

[0096] 17 Second insulation layer

[0097] 18 interlayer insulating film

[0098] 19 substrate

[0099] 20 Wiring layer

[0100] 21 Step structure

[0101] 22 contact plugs

[0102] 23-bit wiring layer

[0103] 24 contact plugs

[0104] 25 Source side selection gate wiring layer

[0105] 26 contact plugs

[0106] 27 Drain side selection gate wiring layer

[0107] 28 plug

[0108] 29 contact plug

[0109] 30 Source wiring layer

[0110] 31 transistors

[0111] 32 gate electrode

[0112] 33 Plug

[0113] 34 Wiring layer

[0114] 35 wiring layer

[0115] 36 through-hole plugs

[0116] 37 Second metal pad

[0117] 41 1st metal pad

[0118] 42 through-hole plug

[0119] 43 Wiring layer

[0120] 44 1st plug

[0121] 45 Insulation film

[0122] 46 2nd plug

[0123] 47 solder pad

[0124] 47a Power Pad

[0125] 47b Power Pad

[0126] 48 Wiring

[0127] 49 passivation film

[0128] 51 Insulation layer

[0129] 52 barrier insulating film

[0130] 53 Charge storage layer

[0131] 54 Tunnel insulating film

[0132] 55 channel semiconductor layer

[0133] 56 core insulation film

[0134] 61 plane (memory cell array)

[0135] 62-line decoder

[0136] 63 Data processing circuit

[0137] 64 Control voltage generation circuit

[0138] 71 SA / DL Department

[0139] 72 XDL Department

[0140] 73 YLOG Department

[0141] 74 Series Circuit

[0142] 75 I / O circuit

[0143] 81 Low voltage generating circuit

[0144] 82 High voltage generating circuit

[0145] 83 line control circuit

[0146] 84 column control circuit

Claims

1. A semiconductor device comprising: An array chip having a storage unit; a circuit chip disposed below the array chip and comprising a substrate and a transistor, wherein the transistor comprises a gate insulating layer on the substrate and a gate electrode on the gate insulating layer; wherein the array chip comprises a plurality of first metal pads below the memory cells, wherein the circuit chip comprises a plurality of second metal pads above the transistors, and wherein the plurality of first metal pads are electrically connected to the plurality of second metal pads; a plurality of first plugs electrically connected to the plurality of first metal pads; and A wiring is provided above the memory cell and electrically connected to at least two of the plurality of first plugs, wherein the wiring is a metal conductive layer.

2. The semiconductor device according to claim 1, further comprising: A plurality of second plugs electrically connected to one of the at least two of the plurality of first plugs.

3. The semiconductor device according to claim 1 or 2, further comprising: A bonding pad is disposed above the memory cell and electrically connected to at least two of the plurality of first plugs.

4. The semiconductor device according to claim 3, further comprising: A plurality of third plugs are electrically connected to one of the plurality of first plugs. 5 . The semiconductor device according to claim 1 , wherein the array chip includes a plurality of electrode layers and a plurality of insulating layers stacked alternately. 6 . The semiconductor device according to claim 5 , wherein the array chip comprises a columnar portion penetrating the plurality of electrode layers and the plurality of insulating layers, the columnar portion comprising a channel semiconductor layer and a charge storage layer between the channel semiconductor layer and the plurality of electrode layers. 7 . The semiconductor device according to claim 6 , wherein the array chip includes a bit line electrically connected to the columnar portion and provided between the columnar portion and the circuit chip. 8 . The semiconductor device according to claim 3 , wherein the bonding pad and the wiring are formed in the same wiring layer.

9. The semiconductor device according to claim 3, further comprising: An insulating film covers the wiring and exposes a portion of the upper surface of the bonding pad. 10 . The semiconductor device according to claim 3 , wherein the wiring is in non-contact with the bonding pad. The semiconductor device according to claim 3 , wherein the wiring is in contact with the bonding pad. The semiconductor device according to claim 1 , wherein the wiring comprises aluminum.

13. A semiconductor device comprising: An array chip having a storage unit; a circuit chip disposed below the array chip and comprising a substrate and a transistor, wherein the transistor comprises a gate insulating layer on the substrate and a gate electrode on the gate insulating layer; in, The array chip comprises a plurality of first metal pads below the memory cells, the circuit chip comprises a plurality of second metal pads above the transistors, and wherein the plurality of first metal pads are electrically connected to the plurality of second metal pads; a bonding pad disposed above the memory cell and electrically connected to at least one of the plurality of first metal pads; The wiring provided above the memory cell includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction, wherein the wiring is a metal conductive layer.

14. The semiconductor device according to claim 13, further comprising: A plurality of first plugs are electrically connected between at least two of the plurality of first metal pads and the bonding pad.

15. The semiconductor device according to claim 14, further comprising: A plurality of second plugs are electrically connected to one of the plurality of first plugs. 16 . The semiconductor device according to claim 13 , wherein the array chip comprises a plurality of electrode layers and a plurality of insulating layers stacked alternately. 17 . The semiconductor device according to claim 16 , wherein the array chip comprises a columnar portion penetrating the plurality of electrode layers and the plurality of insulating layers, the columnar portion comprising a channel semiconductor layer and a charge storage layer between the channel semiconductor layer and the plurality of electrode layers. 18 . The semiconductor device according to claim 17 , wherein the array chip includes a bit line electrically connected to the columnar portion and provided between the columnar portion and the circuit chip.

19. The semiconductor device according to claim 13, wherein the bonding pad and the wiring are formed in the same wiring layer.

20. The semiconductor device according to claim 13, further comprising: An insulating film covers the wiring and exposes a portion of the upper surface of the bonding pad. The semiconductor device according to claim 13 , wherein the wiring is in non-contact with the bonding pad.

22. The semiconductor device according to claim 13, wherein the wiring is in contact with the bonding pad. The semiconductor device according to claim 13 , wherein the wiring comprises aluminum.

24. A semiconductor device comprising: An array chip having multiple memory cells; a circuit chip disposed below the array chip and comprising a substrate and a transistor, wherein the transistor comprises a gate insulating layer on the substrate and a gate electrode on the gate insulating layer; in, The array chip comprises a plurality of first metal pads below the plurality of memory cells, and wherein the circuit chip comprises a plurality of second metal pads above the transistors, and wherein the plurality of first metal pads are electrically connected to the plurality of second metal pads; a bonding pad disposed above the plurality of memory cells and electrically connected to at least one of the plurality of first metal pads; Each of the plurality of wirings provided above the plurality of memory cells includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction, wherein the plurality of wirings are metal conductive layers.

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