Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a plurality of conductive layers, a first gate pillar penetrating the conductive layers, a first channel element surrounding the first gate pillar, a first conductive strip on a sidewall of the first channel element, and a charge storage structure on a surface of the first conductive strip.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and methods for manufacturing the same, and more particularly to three-dimensional semiconductor structures and methods for manufacturing the same. Background Art

[0002] Due to improvements in circuit design, materials, and processes, the size of two-dimensional semiconductor structures has been significantly reduced over the past few decades. However, the smaller the size of the two-dimensional semiconductor structure, the greater the challenges faced in the process, resulting in a technical bottleneck in the miniaturization of two-dimensional semiconductor structures. One potential solution to overcome the technical challenges faced by two-dimensional semiconductor structures is to shift semiconductor structures from a two-dimensional to a three-dimensional architecture. However, most three-dimensional semiconductor structures still have some electrical issues. There is still a need for an improved three-dimensional semiconductor structure and its manufacturing method. Summary of the Invention

[0003] The present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein a gate structure penetrates a conductive layer to form a three-dimensional semiconductor structure with high integration density and excellent electrical performance.

[0004] According to one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes multiple conductive layers, a first gate pillar extending through the multiple conductive layers, a first channel element surrounding the first gate pillar, a first conductive strip on a sidewall of the first channel element, and a charge storage structure on a surface of the first conductive strip.

[0005] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes: forming a first stack and a second stack, wherein the second stack is formed on a sidewall of the first stack; forming a channel element in the first stack; forming a gate pillar in the first stack, wherein the channel element surrounds the gate pillar; forming a plurality of bit lines, wherein the gate pillar extends through the plurality of bit lines; forming a conductive strip on the sidewall of the channel element; and forming a charge storage structure on a surface of the conductive strip.

[0006] In order to better understand the above and other aspects of the present disclosure, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure;

[0008] Figure 1B Draw Figure 1A A schematic top view of the semiconductor structure shown;

[0009] Figure 1C Draw Figure 1A A schematic cross-sectional view of a semiconductor structure shown;

[0010] Figure 2A FIG. 1 is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0011] Figure 2B Draw Figure 2A A schematic top view of the semiconductor structure shown;

[0012] Figure 2C Draw Figure 2A A schematic cross-sectional view of a semiconductor structure shown;

[0013] Figure 3 FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure;

[0014] Figures 4A to 10C A method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is illustrated; and

[0015] 11A to 14C A method for manufacturing a semiconductor structure according to another embodiment of the present disclosure is illustrated.

[0016] Description of Reference Numerals

[0017] 10, 20: Semiconductor structure

[0018] 101: Insulating film

[0019] 101U, 108U, 1041U, 1042U, ST1U, ST2U: Top surface

[0020] 102, 451, 452, 4521: Insulation layer

[0021] 103: Conductive layer

[0022] 104: Gate structure

[0023] 107, 4522: Insulation tape

[0024] 108: Conductive strips

[0025] 108E1: First end

[0026] 108E2: Second end

[0027] 108S: Surface

[0028] 108S1: First side wall

[0029] 108S2: Second side wall

[0030] 108L: bottom surface

[0031] 108W, 114W, 214W, 660W, 760W, 1160W: Maximum width

[0032] 109: Charge Storage Structure

[0033] 114, 214: channel elements

[0034] 114S, 1041S, 1042S, ST2S: sidewall

[0035] 114S1, 214S1: first side wall portion

[0036] 114S2, 214S2: Second side wall portion

[0037] 660: Hole

[0038] 660B: bottom

[0039] 760, 1160: groove

[0040] 1041: Dielectric layer

[0041] 1042: Gate column

[0042] 1042B: bottom surface

[0043] 1091: Dielectric components

[0044] 1092: Conductive components

[0045] AA', BB', CC', DD': hatching

[0046] C1, C2, C3: capacitors

[0047] CST1: First Conductive Stack

[0048] CST2: Second conductive stack

[0049] DI: First Direction

[0050] D2: Second direction

[0051] D3: Third direction

[0052] M1, M2, M3: storage units

[0053] ST: stacked structure

[0054] ST1: First stack

[0055] ST2: First stack

[0056] T1, T2, T3: transistors

[0057] V1, V2, V3, V4: Space DETAILED DESCRIPTION

[0058] The following are relevant embodiments, together with the accompanying drawings, to explain in detail the semiconductor structure and the manufacturing method thereof proposed in the present disclosure. The drawings are simplified to facilitate the clear description of the contents of the embodiments, and the dimensional ratios on the drawings are not drawn in proportion to the actual products. Therefore, the description and the drawings are only used to describe the embodiments, and are not used to limit the scope of protection of the present disclosure. The same or similar element symbols are used to represent the same or similar elements. In addition, the ordinal numbers used in the description and the scope of the claims, such as "first", "second", "third", etc., are used to modify the elements, and they themselves do not mean and represent that the element has any previous ordinal number, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinals is only used to make a component with a certain name clearly distinguishable from another component with the same name.

[0059] The various embodiments of the present disclosure may be applied to various types of three-dimensional semiconductor structures. For example, the embodiments may be applied to, but not limited to, three-dimensional semiconductor structures including dynamic random-access memory (DRAM).

[0060] Please also refer to Figures 1A to 1C . Figure 1A A schematic top view of a semiconductor structure 10 according to an embodiment of the present disclosure is shown. Figure 1B Draw Figure 1A The schematic top view of the semiconductor structure 10 shown corresponds to the plane of the conductive layer 103 . Figure 1C To follow Figure 1A and Figure 1B The schematic cross-sectional view of the semiconductor structure 10 is shown along the AA' section line. The semiconductor structure 10 includes an insulating film 101, multiple insulating layers 102, multiple conductive layers 103, multiple gate structures 104, multiple channel elements 114, multiple insulating strips 107, multiple conductive strips 108, and multiple charge storage structures 109. The multiple insulating layers 102 and the multiple conductive layers 103 are alternately stacked along a first direction D1 and disposed on the upper surface 101U of the insulating film 101. The insulating film 101 may extend in a plane defined by a second direction D2 and a third direction D3. The multiple insulating layers 102 may extend along the second direction D2. The multiple conductive layers 103 may extend along the second direction D2. The multiple insulating layers 102 isolate the multiple conductive layers 103 from each other. The first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. The first direction D1 may be a normal to the upper surface 101U of the insulating film 101. Figure 1C 4 insulating layers 102 and 3 conductive layers 103 are shown, but the present disclosure is not limited thereto. The semiconductor structure 10 may include a greater or lesser number of insulating layers 102 and conductive layers 103 and may be similar. Figure 1C is stacked on the insulating film 101 in a manner of.

[0061] The plurality of gate structures 104 are separated from one another. The plurality of gate structures 104 may be arranged along the second direction D2 in the plurality of insulating layers 102 and the plurality of conductive layers 103. Each gate structure 104 extends along the first direction D1 and penetrates the plurality of insulating layers 102 and the plurality of conductive layers 103. In this embodiment, one end of the gate structure 104 is within the insulating film 101; however, the present disclosure is not limited thereto, and the end of the gate structure 104 may also be within the insulating layer 102. The gate structure 104 includes a dielectric layer 1041 and a gate pillar 1042. The dielectric layer 1041 may surround the gate pillar 1042. The dielectric layer 1041 may be arranged on the sidewalls 1042S and bottom surface 1042B of the gate pillar 1042. A portion of the dielectric layer 1041 is interposed between the gate pillar 1042 and the insulating film 101. A portion of the dielectric layer 1041 is interposed between the gate pillar 1042 and the insulating layer 102. A portion of the dielectric layer 1041 is located between the gate pillars 1042 and the conductive layer 103. The gate pillars 1042 may be disposed along the second direction D2 in the insulating layers 102 and the conductive layers 103. The gate pillars 1042 may extend along the first direction D1 and penetrate the insulating layers 102 and the conductive layers 103. Figure 1A and Figure 1B The cross-section of the gate column 1042 in the plane formed by the second direction D2 and the third direction D3 is shown to be a rectangle, but the present disclosure is not limited thereto. The cross-section of the gate column 1042 in the plane formed by the second direction D2 and the third direction D3 may be a rectangle, a square, an ellipse, a circle, or various other shapes. Figure 1A and Figure 1B Three gate structures 104 are shown, but the disclosure is not limited thereto, and the semiconductor structure 10 may include a greater or lesser number of gate structures 104 . The gate structures 104 are electrically connected to the conductive layer 103 .

[0062] Multiple channel elements 114 are separated from each other. The channel elements 114 may be arranged in the conductive layers 103 along a first direction D1 and a second direction D2. The conductive layer 103 may cover a portion of the sidewalls 114S of the channel elements 114. Specifically, the sidewalls 114S of the channel elements 114 may include a first sidewall portion 114S1 covered by the conductive layer 103 and a second sidewall portion 114S2 uncovered by the conductive layer 103. The channel elements 114 may surround the dielectric layer 1041 and the gate pillar 1042 of the gate structure 104. The channel elements 114 may be arranged on the sidewalls 1041S of the dielectric layer 1041. The channel elements 114 may be interposed between the dielectric layer 1041 and the conductive layer 103. A portion of the dielectric layer 1041 may be interposed between the gate pillar 1042 and the channel elements 114. One channel element 114 may surround only one gate structure 104. A gate structure 104 may be surrounded by a plurality of channel elements 114; for example, Figure 1CAs shown, one gate structure 104 may be surrounded by a plurality of channel elements 114 arranged along the first direction D1 . Figure 1C Although one gate structure 104 is shown surrounded by three channel elements 114, the present disclosure is not limited thereto. A gate structure 104 may be surrounded by a greater or lesser number of channel elements 114. The channel elements 114 may have a hollow cylindrical shape. The channel elements 114 are electrically connected to the conductive layer 103 in which they are located. The channel elements 114 are electrically connected to the gate structure 104 that they surround.

[0063] A plurality of conductive strips 108 are spaced apart from one another and disposed on the upper surface 101U of the insulating film 101. The plurality of conductive strips 108 may be arranged along a first direction D1 and a second direction D2. Each conductive strip 108 extends along a third direction D3. Each conductive strip 108 has a first end 108E1 and a second end 108E2 spaced apart from one another. The first end 108E1 and the second end 108E2 of the conductive strip 108 are located at opposite ends of the conductive strip 108 along the third direction D3. The conductive strip 108 may be disposed on the second sidewall portion 114S2 of the sidewall 114S of the channel element 114 and electrically connected to the channel element 114. The first end 108E1 of the conductive strip 108 may be connected to or in contact with the second sidewall portion 114S2 of the sidewall 114S of the channel element 114. The maximum width 108W of the conductive strip 108 in the second direction D2 may be less than or equal to the maximum width 114W of the channel element 114 in the second direction D2. In one embodiment, the channel element 114 and the conductive strip 108 have a one-to-one correspondence. In other words, a channel element 114 and the conductive strip 108 corresponding to or electrically connected to the channel element 114 may have the same height (or level) in the first direction D1. In one embodiment, the channel element 114, the conductive strip 108, and the conductive layer 103 have a corresponding relationship. In other words, a channel element 114, the conductive strip 108 corresponding to or electrically connected to the channel element 114, and the conductive layer 103 corresponding to or electrically connected to the channel element 114 may have the same height (or level) in the first direction D1.

[0064] A plurality of insulating strips 107 are separated from one another and disposed on the upper surface 101U of the insulating film 101. The insulating strips 107 may be arranged along a first direction D1 and a second direction D2. Each insulating strip 107 extends along a third direction D3. The insulating strips 107 and the conductive strips 108 may be alternately stacked along the first direction D1 on the upper surface 101U of the insulating film 101. The insulating strips 107 isolate the conductive strips 108 from one another. The insulating strips 107 may be disposed on the sidewalls of the insulating layer 102.

[0065] Multiple insulating strips 107 isolate multiple charge storage structures 109 from each other. Each charge storage structure 109 may be disposed on the surface 108S of the conductive strip 108. Each charge storage structure 109 may surround a portion of the conductive strip 108. Each charge storage structure 109 may surround or cover the second end 108E2 of the conductive strip 108. Each charge storage structure 109 may not surround or cover the first end 108E1 of the conductive strip 108. Each charge storage structure 109 may be isolated from the channel element 114. Each charge storage structure 109 is electrically connected to the conductive strip 108 that it surrounds. Each charge storage structure 109 may include a dielectric element 1091 and a conductive element 1092. The dielectric element 1091 is interposed between the conductive element 1092 and the conductive strip 108. The dielectric element 1091 may be disposed on the surface 108S of the conductive strip 108. The conductive element 1092 may be disposed on an outer surface of the dielectric element 1091. In other embodiments, the plurality of conductive elements 1092 arranged along the first direction D1 (ie, the plurality of conductive elements 1092 corresponding to the same gate structure 104 ) may be interconnected, so that the semiconductor structure 10 may not include the insulating strips 107 between the conductive elements 1092 .

[0066] Please also refer to Figures 2A to 2C . Figure 2A FIG. 1 is a schematic top view of a semiconductor structure 20 according to another embodiment of the present disclosure. Figure 2B Draw Figure 2A The schematic top view of the semiconductor structure 20 shown corresponds to the plane of the conductive layer 103 . Figure 2C For the Figure 2A and Figure 2B The schematic cross-sectional view of the semiconductor structure 20 is shown along the BB′ cross-sectional line. Figures 1A to 2C , the same reference numerals represent the same elements and have the same properties, and are not described again. The semiconductor structure 20 differs from the semiconductor structure 10 in that the semiconductor structure 20 includes a plurality of channel elements 214 and each channel element 214 surrounds a plurality of gate structures 104.

[0067] The channel element 214 may extend on a plane formed by the second direction D2 and the third direction D3 and surround the plurality of gate structures 104 arranged along the second direction D2 . Figure 2CWhile one channel element 214 is shown surrounding three gate structures 104, the present disclosure is not limited thereto. One channel element 214 may surround a greater or lesser number of gate structures 104. The channel element 214 is disposed on the sidewalls 1041S of the dielectric layers 1041. A portion of the channel element 214 may be interposed between the dielectric layer 1041 and the conductive layer 103. A portion of the channel element 214 may be interposed between the dielectric layer 1041 and the conductive strip 108. The channel elements 214 are disposed along a first direction D1 within the conductive layers 103. The insulating layers 102 isolate the channel elements 214 from one another in the first direction D1. The conductive layer 103 may cover a portion of the sidewalls 214S of the channel element 214. Specifically, the sidewalls 214S of the channel element 214 may include a first sidewall portion 214S1 covered by the conductive layer 103 and a second sidewall portion 214S2 uncovered by the conductive layer 103. In this embodiment, a plurality of conductive strips 108 at the same level (or a plurality of conductive strips having the same height in the first direction D1 ) are disposed on the second sidewall portion 214S2 of the sidewall 214S of a channel element 214 , and these conductive strips 108 are electrically connected to the channel element 214 .

[0068] A gate structure 104 may be surrounded by a plurality of channel elements 214; for example, Figure 2C As shown, one gate structure 104 may be surrounded by a plurality of channel elements 214 arranged along the first direction D1 . Figure 2C Although one gate structure 104 is shown surrounded by three channel elements 214, the present disclosure is not limited thereto. A gate structure 104 may be surrounded by a greater or lesser number of channel elements 214. The channel elements 214 are electrically connected to the conductive layer 103 in which they are located. The channel elements 214 are electrically connected to the multiple gate structures 104 surrounded by them. In the semiconductor structure 20, the maximum width 108W of the conductive strip 108 in the second direction D2 is smaller than the maximum width 214W of the channel elements 214 in the second direction D2.

[0069] The semiconductor structure 10 / 20 may include multiple transistors and multiple capacitors. The transistors are formed at the intersection of the conductive layer 103 and the conductive strip 108. The conductive strip 108, the dielectric element 1091 of the charge storage structure 109, and the conductive element 1092 of the charge storage structure 109 may form (or function as) a capacitor. A transistor and a capacitor (1T1C) may form a memory cell. The semiconductor structure 10 / 20 may include multiple memory cells. The conductive layer 103 may function as a bit line. The gate structure 104 may function as a word line. The transistor has a first drain / source terminal, a second drain / source terminal, and a gate terminal. The capacitor has a first terminal and a second terminal. The first drain / source terminal of the transistor is electrically connected to the bit line. The second drain / source terminal of the transistor is electrically connected to the first terminal of the capacitor. The gate terminal of the transistor is electrically connected to the word line. The second terminal of the capacitor is electrically connected to the source line. In one embodiment, a first terminal of the capacitor is electrically connected to the conductive strip 108, and a second terminal of the capacitor is electrically grounded. The transistor can be selectively turned on or off to selectively operate the capacitor. In one embodiment, a large amount of charge can be stored in the dielectric element 1091 of the charge storage structure 109 (or can be understood as charging the capacitor) to represent a logic "1" state; or a small amount of charge can be stored in the dielectric element 1091 of the charge storage structure 109 (or can be understood as discharging the capacitor) to represent a logic "0" state. In one embodiment, the memory cell of the semiconductor structure 10 / 20 can be a dynamic random access memory cell, and thus the semiconductor structure 10 / 20 can include a dynamic random access memory device or can be a dynamic random access memory device.

[0070] The following will refer to Figure 3 One of the operation modes applicable to the semiconductor structure of the present disclosure is exemplified. Figure 3 FIG. 1 is a schematic top view of a semiconductor structure 10 according to an embodiment of the present disclosure. The semiconductor structure 10 may include a conductive layer 103 and a conductive layer 104 formed therebetween. Figure 3 The transistor T1 at the intersection of the upper conductive strip 108 is formed between the conductive layer 103 and the conductive layer 104. Figure 3 The transistor T2 at the intersection of the middle conductive strip 108 and the transistor T2 formed between the conductive layer 103 and the conductive layer 104 are connected. Figure 3 The transistor T3 is located at the intersection of the lower conductive strip 108. The semiconductor structure 10 may include a capacitor C1, a capacitor C2, and a capacitor C3. Figure 3 The upper conductive strip 108 and the charge storage structure 109 disposed on the surface of the conductive strip 108 form a capacitor C1 . Figure 3The middle conductive strip 108 and the charge storage structure 109 disposed on the surface of the conductive strip 108 form a capacitor C2 . Figure 3 The lower conductive strip 108 and the charge storage structure 109 disposed on the surface of the conductive strip 108 form a capacitor C3. The transistor T1 and the capacitor C1 electrically connected to the transistor T1 form a memory cell M1. The transistor T2 and the capacitor C2 electrically connected to the transistor T2 form a memory cell M2. The transistor T3 and the capacitor C3 electrically connected to the transistor T3 form a memory cell M3. In an operation mode, a bit line bias is applied to the conductive layer 103, a first source line bias is applied to the source line electrically connected to the capacitor C1 and the capacitor C3, a second source line bias is applied to the source line electrically connected to the capacitor C2, and a bit line bias is applied to the source line electrically connected to the capacitor C1 and the capacitor C3. Figure 3 The upper gate structure 104 and Figure 3 The lower gate structure 104 applies a first word line bias to turn off the transistors T1 and T3 (eg, turn off the pass element 114 of the transistor T1 and the pass element 114 of the transistor T3). Figure 3 The intermediate gate structure 104 applies a second word line bias to turn on the transistor T2 (e.g., turn on the pass element 114 of the transistor T2); at this time, the memory cells M1 and M3 are not selected, and the memory cell M2 is selected for operation. For example, the capacitor C2 included in the selected memory cell M2 can be charged or discharged. In some operating modes, the first word line bias can be different from the second word line bias. When the transistor T2 is turned on, current can flow between the first drain / source terminal and the second drain / source terminal of the transistor T2. Figure 3 The arrows represent one possible direction of current flow. The operation modes of the semiconductor structure may include a read operation, a write operation, and a hold operation. The write operation may include writing a logic "0" and writing a logic "1."

[0071] Table 1 lists several bias configurations that can be used to operate the semiconductor structure of the present disclosure. The conductive layer 103 in the semiconductor structure 10 / 20 can be electrically connected to a sense amplifier (SA). The "selected word line" in Table 1 refers to the word line electrically connected to the selected memory cell, such as the word line electrically connected to the selected memory cell. Figure 3 The “unselected word line” in Table 1 refers to a word line electrically connected to an unselected memory cell, such as a word line electrically connected to Figure 3 The word lines of the memory cells M1 and M3. The “selected bit lines” in Table 1 refer to the bit lines electrically connected to the selected memory cells, such as Figure 3 The word line of the memory cell M2 (i.e., the conductive layer 103 corresponding to the memory cells M1, M2, and M3). The "unselected bit line" in Table 1 refers to the bit line that is not electrically connected to the selected memory cell, such as the bit line electrically connected to Figure 3 The memory cell M2 is located at a bit line of a memory cell in a different layer (eg, other conductive layers 103 located above or below the conductive layers 103 corresponding to the memory cells M1, M2, and M3 in the first direction D1).

[0072] Table 1

[0073]

[0074] Figures 4A to 10C A method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is illustrated.

[0075] Please also refer to Figures 4A to 4C . Figure 4A A schematic top view of the structure showing a stage in the manufacturing method; Figure 4B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 452; Figure 4C A schematic cross-sectional view of the structure at this stage is depicted. An insulating film 101 is provided. A stacked structure ST is formed on the insulating film 101. The stacked structure ST includes a plurality of insulating layers 451 and a plurality of insulating layers 452 stacked alternately along a first direction D1 on the upper surface 101U of the insulating film 101. The plurality of insulating layers 452 isolate the plurality of insulating layers 451 from each other. Figures 4A to 4C show that the topmost and bottommost layers of the stacked structure ST are insulating layers 451, and show four insulating layers 451 and three insulating layers 452, but the present disclosure is not limited thereto. The number and configuration of the insulating layers 451 and 452 can be adjusted arbitrarily. The topmost insulating layer 451 of the stacked structure ST can serve as a hard mask layer. The insulating layer 451 and the insulating layer 452 can include different materials. The insulating film 101 can include an insulating material, and the insulating material includes an oxide. For example, the insulating film 101 can include silicon oxide. The insulating layer 451 may include an insulating material including an oxide, such as silicon oxide. The insulating layer 452 may include an insulating material including a nitride, such as silicon nitride. In one embodiment, the insulating layer 451 is a silicon oxide layer, and the insulating layer 452 is a silicon nitride layer. In one embodiment, the insulating layers 451 and 452 may be formed alternately on the upper surface 101U of the insulating film 101 through a deposition process to form a stacked structure ST.

[0076] Please also refer to Figures 5A to 5C . Figure 5A A schematic top view of the structure showing a stage in the manufacturing method; Figure 5B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 5C To follow Figure 5Aand Figure 5B The structure shown is a schematic cross-sectional view drawn along the CC' section line. Portions of the insulating layer 451 and portion of the insulating layer 452 are removed to form a first stack ST1 and a plurality of second stacks ST2. The plurality of second stacks ST2 are on the sidewall STS of the first stack ST1. The plurality of second stacks ST2 may be adjacent to the first stack ST1. The first stack ST1 and the second stack ST2 may be arranged along a third direction D3. The plurality of second stacks ST2 are arranged along the second direction D2. The second stack ST2 may extend along the third direction D3. The first stack ST1 may include a plurality of insulating layers 102 and a plurality of insulating layers 4521 stacked alternately along the first direction D1 on the upper surface 101U of the insulating film 101. Each second stack ST2 may include a plurality of insulating strips 107 and a plurality of insulating strips 4522 stacked alternately along the first direction D1 on the upper surface 101U of the insulating film 101. In this embodiment, the insulating layer 102 of the first stack ST1 and the insulating strips 107 of the second stack ST2 have a one-to-one correspondence. In other words, an insulating layer 102 and an insulating strip 107 corresponding to the insulating layer 102 may have the same height (or level) in the first direction D1. In this embodiment, the insulating layer 4521 of the first stack ST1 and the insulating strips 4522 of the second stack ST2 have a one-to-one correspondence. In other words, an insulating layer 4521 and an insulating strip 4522 corresponding to the insulating layer 4521 may have the same height (or level) in the first direction D1. The insulating layer 102 is part of the insulating layer 451. The insulating strip 107 is part of the insulating layer 451. The insulating layer 4521 is part of the insulating layer 452. The insulating strip 4522 is part of the insulating layer 452. In one embodiment, the first stack ST1 and the second stack ST2 can be formed by removing portions of the insulating layer 451 and 452 through a photolithography process.

[0077] Please also refer to Figures 6A to 6C . Figure 6A A schematic top view of the structure showing a stage in the manufacturing method; Figure 6B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 6C To follow Figure 6A and Figure 6BThe CC' cross-sectional view shown is a schematic cross-sectional view of the structure. A plurality of holes 660 are formed in the first stack ST1. The plurality of holes 660 are separated from each other. The plurality of holes 660 extend along the first direction D1 and penetrate the plurality of insulating layers 102 and the plurality of insulating layers 4521 of the first stack ST1, and stop at the insulating film 101. The holes 660 expose the sidewalls of the first stack ST1 and the upper surface 101U of the insulating film 101. The holes 660 can have any shape such as a cylinder, an elliptical cylinder, or a square cylinder. Each hole 660 can overlap with a second stack ST2 in the third direction D3. In one embodiment, the holes 660 can be formed by removing part of the insulating layer 102 and part of the insulating layer 4521 through a photolithography process.

[0078] Please also refer to 7A to 7C . Figure 7A A schematic top view of the structure showing a stage in the manufacturing method; Figure 7B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 7C To follow Figure 7A and Figure 7BThe structure is schematically cross-sectionally depicted along the CC' section line. Portions of the insulating layer 4521 are removed to form a plurality of grooves 760. The plurality of grooves 760 are located between the plurality of insulating layers 102. Each groove 760 may connect to a hole 660. In this embodiment, the plurality of grooves 760 arranged along the first direction D1 may connect to a hole 660. The groove 760 may be an annular groove surrounding the hole 660. The maximum width 760W of the groove 760 in the second direction D2 may be greater than the maximum width 660W of the hole 660 in the second direction D2. The maximum width 760W of the groove 760 in the second direction D2 may be less than twice the maximum width 660W of the hole 660 in the second direction D2. The plurality of grooves 760 located at the same level may be isolated from each other by the insulating layer 4521. The plurality of grooves 760 located at different levels may be isolated from each other by the insulating layer 102. The grooves 760 expose the sidewalls ST2S of the second stack ST2. The grooves 760 expose the upper surface of the insulating layer 102, the lower surface of the insulating layer 102, the sidewalls of the insulating layer 4521, and the sidewalls of the insulating strips 4522 of the second stack ST2. In one embodiment, a dry etching process or a wet etching process can be used to remove part of the insulating layer 4521 to form a plurality of grooves 760. The dry etching process at this stage can be, for example, a reactive ion etching (RIE) process. The wet etching process at this stage can be, for example, a wet etching process using phosphoric acid (H3PO4). In one embodiment, the dry etching process or wet etching process used at this stage can remove a portion of the insulating film 101 exposed by the hole 660, thereby increasing the depth of the hole 660 in the first direction D1 and causing the bottom 660B of the hole 660 to be lower than the upper surface 101U of the insulating film 101 in the first direction D1, as shown in FIG. Figure 7C In other embodiments, the dry etching process or wet etching process used in this stage does not change the depth of the hole 660 in the first direction D1; 7A to 7C The depth of the hole 660 obtained after the steps shown in the figure in the first direction D1 is the same as that obtained after the steps shown in the figure. 7A to 7C The depth of the hole 660 in the first direction D1 before the step is shown.

[0079] Please also refer to Figures 8A to 8C . Figure 8A A schematic top view of the structure showing a stage in the manufacturing method; Figure 8B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 8C To follow Figure 8A and Figure 8BThe CC' cross-sectional line is shown as a schematic cross-sectional view of the structure. A plurality of channel elements 114 and a plurality of gate structures 104 are formed in the first stack ST1. The gate structure 104 includes a dielectric layer 1041 and a gate pillar 1042. Each channel element 114 is formed in a recess 760. The channel element 114 may fill the recess 760. Each gate pillar 1042 and each dielectric layer 1041 are formed in a hole 660. The channel element 114 may include an oxide semiconductor material, polycrystalline silicon (polycrystalline silicon), silicon germanium (SiGe), germanium, or any combination thereof. The oxide semiconductor material is, for example, indium oxide (InO x ) and / or indium gallium zinc oxide (IGZO). The dielectric layer 1041 may include a dielectric material, and the dielectric material includes an oxide. For example, the dielectric layer 1041 may include silicon oxide, hafnium (IV) oxide (HfO2), or zirconium oxide (ZrO x The gate pillar 1042 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), cobalt (Co), ruthenium (Ru), or any combination thereof. The gate pillar 1042 may include a multi-layer structure including titanium nitride / tungsten. In one embodiment, a deposition process may be performed to form a channel element 114 in the recess 760. The channel element 114 may be formed on the upper surface of the insulating layer 102 exposed by the recess 760, the lower surface of the insulating layer 102, the sidewalls of the insulating layer 4521, and the sidewalls of the insulating strips 4522 of the second stack ST2. A deposition process may then be performed to form a dielectric layer 1041 in the hole 660. The dielectric layer 1041 may be formed on the sidewalls of the insulating layer 102 exposed by the hole 660, the sidewalls of the channel element 114, and the insulating film 101. A deposition process may then be performed to form a gate pillar 1042 in the remaining space of the hole 660. In the first direction D1, an upper surface 1041U of the dielectric layer 1041 and an upper surface 1042U of the gate pillar 1042 may be lower than an upper surface ST1U of the first stack ST1 and an upper surface ST2U of the second stack ST2, but the present disclosure is not limited thereto.

[0080] Please also refer to Figures 9A to 9C . Figure 9A A schematic top view of the structure showing a stage in the manufacturing method; Figure 9B A schematic top view of the structure at this stage is shown, corresponding to the plane of the conductive layer 103 and the conductive strip 108; Figure 9C To follow Figure 9Aand Figure 9B The structure is schematically cross-sectionally depicted along the CC' cross-section line. Multiple conductive layers 103 and multiple conductive strips 108 are formed. Multiple conductive layers 103 are interposed between multiple insulating layers 102 and multiple channel elements 114. Multiple conductive strips 108 are interposed between multiple insulating strips 107 and channel elements 114. Conductive layers 103 and conductive strips 108 may comprise a conductive material, such as tungsten, doped or undoped silicon, titanium nitride, or any combination thereof. Conductive layers 103 and conductive strips 108 may comprise the same or different materials. In one embodiment, a selective etching process can be performed to remove the plurality of insulating layers 4521 to form a plurality of spaces V1 and the plurality of insulating strips 4522 to form a plurality of spaces V2, while retaining the plurality of insulating layers 102, insulating strips 107, and insulating film 101. The spaces V1 expose the upper and lower surfaces of the insulating layer 102 and the sidewalls of the channel element 114. The spaces V2 expose the upper and lower surfaces of the insulating strips 107 and the sidewalls of the channel element 114. Subsequently, a deposition process can be performed to fill the spaces V1 with the conductive layer 103 and the spaces V2 with the conductive strips 108, thereby forming a first conductive stack CST1 and a plurality of second conductive stacks CST2. The first conductive stack CST1 includes a plurality of insulating layers 102 and a plurality of conductive layers 103 stacked alternately along a first direction D1. Each second conductive stack CST2 includes a plurality of insulating strips 107 and a plurality of conductive strips 108 stacked alternately along the first direction D1. A plurality of second conductive stacks CST2 are arranged on sidewalls of the first conductive stack CST1 along the second direction D2.

[0081] Please also refer to 10A to 10C . Figure 10A A schematic top view of the structure showing a stage in the manufacturing method; Figure 10B A schematic top view of the structure at this stage is shown, corresponding to the plane of the conductive layer 103 and the conductive strip 108; Figure 10C To follow Figure 10A and Figure 10BThe structure is schematically illustrated in a cross-sectional view along the CC' line. Multiple charge storage structures 109 are formed. The charge storage structures 109 and the channel element 114 may be located at opposite ends of the conductive strip 108 along the third direction D3. The charge storage structures 109 may be disposed on the surface 108S of the conductive strip 108. The surface 108S of the conductive strip 108 includes at least an upper surface 108U, a lower surface 108L, a first sidewall 108S1, and a second sidewall 108S2. The upper surface 108U of the conductive strip 108 is opposite to the lower surface 108L. The first sidewall 108S1 of the conductive strip 108 is opposite to the second sidewall 108S2. In this embodiment, each charge storage structure 109 covers a portion of the upper surface 108U, a portion of the lower surface 108L, a portion of the first sidewall 108S1, and a portion of the second sidewall 108S2 of the conductive strip 108. The charge storage structure 109 may surround or cover an end of the conductive strip 108 away from the channel element 114. A portion of the charge storage structure 109 may be located between the conductive strip 108 and the insulating strip 107. In one embodiment, a dry or wet etching process may be used to remove a portion of the insulating strip 107 and / or a portion of the conductive strip 108. Subsequently, a deposition process may be performed to sequentially form a dielectric element 1091 and a conductive element 1092 on the surface of the conductive strip 108 to form the charge storage structure 109. The dielectric element 1091 may include a high-k material such as ZrO, ZrAlO, ZrNbO, ZrHfO, or any combination thereof. The dielectric element 1091 may have a multilayer structure, such as a ZrO / ZrAlO multilayer structure or a ZrNbO / ZrHfO / ZrAlO multilayer structure. The conductive element 1092 may include a conductive material, and the conductive material includes titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), cobalt (C o ), tungsten (W), aluminum (Al), ruthenium (Ru), platinum (Pt), cobalt disilicide (CoSi2) or any combination thereof.

[0082] In one embodiment, by performing the exemplary Figures 4A to 10C The semiconductor structure 10 can be obtained by performing the steps of:

[0083] 11A to 14C A method for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown. Figures 4A to 6C After the manufacturing steps described above, refer to 11A to 14C The manufacturing steps.

[0084] Please also refer to Figures 11A to 11C . Figure 11A A schematic top view of the structure showing a stage in the manufacturing method; Figure 11BA schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 11C To follow Figure 11A and Figure 11B The structure is shown schematically in a cross-sectional view drawn along the DD' section line. Portions of the insulating layer 4521 are removed to form a plurality of grooves 1160. The plurality of grooves 1160 are spaced apart from one another along the first direction D1. The plurality of grooves 1160 are interposed between the plurality of insulating layers 102. Each groove 1160 may connect to a plurality of holes 660 located at the same level. Each groove 1160 may extend in a plane formed by the second direction D2 and the third direction D3 and surround a plurality of holes 660 located at the same level. The maximum width 1160W of the groove 1160 in the second direction D2 may be greater than the maximum width 660W of the hole 660 in the second direction D2. The maximum width 1160W of the groove 1160 in the second direction D2 may be greater than twice the maximum width 660W of the hole 660 in the second direction D2. In this embodiment, the maximum width 1160W of the groove 1160 in the second direction D2 is greater than three times the maximum width 660W of the hole 660 in the second direction D2. In one embodiment, the maximum width 1160W of the recess 1160 in the second direction D2 depends on the number of gate structures 104 to be configured. When the number of gate structures 104 to be configured is n, the maximum width 1160W is greater than the maximum width 660W multiplied by n. The recess 1160 exposes the sidewalls ST2S of the second stack ST2. The recess 1160 exposes the upper surface of the insulating layer 102, the lower surface of the insulating layer 102, the sidewalls of the insulating layer 4521, and the sidewalls of the insulating strips 4522 of the second stack ST2. Each recess 1160 can expose the sidewalls of multiple insulating strips 4522 located at the same level. In one embodiment, a dry etching process or a wet etching process can be used to remove portions of the insulating layer 4521 to form the multiple recesses 1160. The dry etching process at this stage can be, for example, a reactive ion etching process. The wet etching process at this stage can be, for example, a wet etching process using phosphoric acid. In one embodiment, the dry etching process or wet etching process used in this stage can remove a portion of the insulating film 101 exposed by the hole 660, thereby increasing the depth of the hole 660 in the first direction D1 and making the bottom 660B of the hole 660 lower than the upper surface 101U of the insulating film 101 in the first direction D1. Figure 11C In other embodiments, the dry etching process or wet etching process used in this stage does not change the depth of the hole 660 in the first direction D1; Figures 11A to 11C The depth of the hole 660 obtained after the steps shown in the figure in the first direction D1 is the same as that obtained after the steps shown in the figure. Figures 11A to 11C The depth of the hole 660 in the first direction D1 before the step is shown.

[0085] Please also refer to 12A to 12C . Figure 12A A schematic top view of the structure showing a stage in the manufacturing method; Figure 12B A schematic top view of the structure at this stage is shown, corresponding to the plane of the insulating layer 4521 and the insulating strip 4522; Figure 12C To follow Figure 12A and Figure 12B The structure shown is a schematic cross-sectional view drawn along the DD' section line. A plurality of channel elements 214 and a plurality of gate structures 104 are formed in the first stack ST1. The gate structure 104 includes a dielectric layer 1041 and a gate pillar 1042. Each channel element 214 is formed in a recess 1160. The channel element 214 may fill the recess 1160. Each gate pillar 1042 and each dielectric layer 1041 are formed in a hole 660. The channel element 214 may include an oxide semiconductor material, polysilicon, silicon germanium (SiGe), germanium, or any combination thereof. The oxide semiconductor material is, for example, indium oxide (InO x ) and / or indium gallium zinc oxide (IGZO). In one embodiment, a deposition process may be performed to form a channel element 214 in the recess 1160. The channel element 214 may be formed on the upper surface of the insulating layer 102 exposed by the recess 1160, the lower surface of the insulating layer 102, the sidewalls of the insulating layer 4521, and the sidewalls of the insulating strips 4522 of the second stack ST2. Next, a deposition process may be performed to form a dielectric layer 1041 in the hole 660. The dielectric layer 1041 may be formed on the sidewalls of the insulating layer 102 exposed by the hole 660, the sidewalls of the channel element 214, and the insulating film 101. Next, a deposition process may be performed to form a gate pillar 1042 in the remaining space of the hole 660. In the first direction D1 , an upper surface 1041U of the dielectric layer 1041 and an upper surface 1042U of the gate pillar 1042 may be lower than an upper surface ST1U of the first stack ST1 and an upper surface ST2U of the second stack ST2 , but the disclosure is not limited thereto.

[0086] Please also refer to 13A to 13C . Figure 13A A schematic top view of the structure showing a stage in the manufacturing method; Figure 13B A schematic top view of the structure at this stage is shown, corresponding to the plane of the conductive layer 103 and the conductive strip 108; Figure 13C To follow Figure 13A and Figure 13BThe schematic cross-sectional view of the structure is shown along the DD' section line. A plurality of conductive layers 103 and a plurality of conductive strips 108 are formed. The plurality of conductive layers 103 are interposed between the plurality of insulating layers 102 and the plurality of channel elements 214. The plurality of conductive strips 108 are interposed between the plurality of insulating strips 107 and the plurality of channel elements 214. In one embodiment, a selective etching process can be performed to remove the plurality of insulating layers 4521 to form a plurality of spaces V3 and the plurality of insulating strips 4522 to form a plurality of spaces V4, while retaining the plurality of insulating layers 102, insulating strips 107, and insulating film 101. The spaces V3 expose the upper and lower surfaces of the insulating layer 102 and the sidewalls of the channel element 214. The spaces V4 expose the upper and lower surfaces of the insulating strips 107 and the sidewalls of the channel element 214. Subsequently, a deposition process can be performed to fill the spaces V3 with the conductive layer 103 and the spaces V4 with the conductive strips 108, thereby forming a first conductive stack CST1 and a plurality of second conductive stacks CST2. The first conductive stack CST1 includes a plurality of insulating layers 102 and a plurality of conductive layers 103 stacked alternately along a first direction D1. Each second conductive stack CST2 includes a plurality of insulating strips 107 and a plurality of conductive strips 108 stacked alternately along the first direction D1. A via element 214 may contact a plurality of conductive strips 108 located at the same level as the via element 214 .

[0087] Please also refer to 14A to 14C . Figure 14A A schematic top view of the structure showing a stage in the manufacturing method; Figure 14B A schematic top view of the structure at this stage is shown, corresponding to the plane of the conductive layer 103 and the conductive strip 108; Figure 14C To follow Figure 14A and Figure 14B The structure schematic cross-section is drawn along the DD' section line. A plurality of charge storage structures 109 are formed. The charge storage structure 109 and the channel element 214 can be located at opposite ends of the conductive strip 108 along the third direction D3. The structure, configuration, manufacturing method and material of the charge storage structure 109 can be similar to 10A to 10C Related description.

[0088] In one embodiment, by performing the exemplary 11A to 14C The semiconductor structure 20 can be obtained by performing the steps of:

[0089] The manufacturing method of the semiconductor structure disclosed in the present invention can use a stacked structure (e.g., stacked structure ST) comprising an oxide (e.g., insulating layer 451) and a nitride (e.g., insulating layer 452) to form a semiconductor structure. Compared to the comparative example of using a stacked structure comprising silicon and silicon germanium to form a semiconductor structure, the stacked structure formed by oxide and nitride used in the present invention is easy to etch and suitable for etching using a reactive ion etching (RIE) process. Therefore, the manufacturing method of the present invention can simplify the process. Moreover, in the semiconductor structure and its manufacturing method disclosed in the present invention, the channel element (e.g., channel element 114 / 214) comprises indium oxide (InO x ) and / or indium gallium zinc oxide (IGZO), which can improve the leakage problem of the capacitor and enhance the electrical performance, reliability and yield of the semiconductor structure. In addition, in the semiconductor structure and its manufacturing method disclosed herein, the gate structure (such as gate structure 104) penetrates the conductive layer. Compared with the comparative example in which the gate structure does not penetrate the conductive layer, the configuration of the gate structure and the conductive layer disclosed herein is easy to manufacture and can avoid electrical problems caused by contact between multiple gate structures. Moreover, the semiconductor structure disclosed herein can easily increase the number of memory cells per unit area by increasing the number of stacked layers, thereby forming a three-dimensional semiconductor structure with high integration density and excellent electrical performance.

[0090] It should be noted that the drawings, structures and steps described above are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above-mentioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the structures and steps of the examples can be adjusted according to the needs of actual applications. Therefore, the structure of the drawings is only used to illustrate, and is not used to limit the present disclosure. Generally speaking, those with knowledge of the present disclosure should know that the relevant structures and step processes of the present disclosure, such as the arrangement or configuration of the relevant elements and layers in the semiconductor structure, or the details of the manufacturing steps, may be adjusted and changed accordingly according to the requirements of the actual application.

[0091] In summary, although the present disclosure has been disclosed above with reference to the embodiments, these are not intended to limit the present disclosure. Persons skilled in the art will readily be able to make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A semiconductor structure comprising: multiple conductive layers; a first gate column penetrating through the conductive layers; a first channel element surrounding the first gate pillar; a first conductive strip on a side wall of the first channel element; and A charge storage structure is on a surface of the first conductive strip.

2. The semiconductor structure according to claim 1, further comprising: a second gate pillar penetrating through the conductive layers, the first gate pillar being separated from the second gate pillar; and A second channel element surrounds the second gate pillar, and the first channel element and the second channel element are separated.

3. The semiconductor structure according to claim 2, wherein the conductive layers are arranged along a first direction and extend along a second direction, the first direction being perpendicular to the second direction. The first gate pillar and the second gate pillar are arranged along the second direction, and the first channel element and the second channel element are in the conductive layers.

4. The semiconductor structure according to claim 1, further comprising: A second gate pillar penetrates the conductive layers. The first gate pillar is separated from the second gate pillar. The first channel element surrounds the first gate pillar and the second gate pillar.

5. The semiconductor structure according to claim 4, further comprising: A second conductive strip is on the sidewall of the first channel element, wherein the first conductive strip and the second conductive strip are at the same level.

6. The semiconductor structure according to claim 1, further comprising: A memory cell includes a transistor and a capacitor. The transistor is formed at the intersection of the conductive layers and the first conductive strip. The first conductive strip and the charge storage structure form the capacitor. The semiconductor structure according to claim 1 , wherein the first channel element comprises indium oxide and / or indium gallium zinc oxide.

8. A method of manufacturing a semiconductor structure, comprising: forming a first stack and a second stack, wherein the second stack is on a side wall of the first stack; forming a channel element in the first stack; forming a gate pillar in the first stack, wherein the channel element surrounds the gate pillar; forming a plurality of bit lines, wherein the gate pillar passes through the bit lines; forming a conductive strip on a side wall of the channel element; and A charge storage structure is formed on a surface of the conductive strip.

9. The method according to claim 8, further comprising: forming a hole in the first stack; A groove is formed in the first stack, the groove communicating with the hole, The channel element is formed in the groove, and the gate column is formed in the hole. 10 . The method according to claim 9 , wherein the first stack comprises a plurality of first insulating layers and a plurality of second insulating layers that are alternately stacked, and the groove is located between the first insulating layers.

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