Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the same are provided. The semiconductor device includes: a substrate; a circuit element and a wiring portion disposed on the substrate; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the wiring portion; a channel structure penetrating the gate stack structure; an upper insulating layer covering the wiring portion and an upper surface of the gate stack structure; a connection contact structure connected to the circuit element by penetrating the upper insulating layer outside the gate stack structure; and a dummy contact structure disposed adjacent to the connection contact structure and having a lower dielectric constant than the connection contact structure.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0035868 filed on March 14, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to semiconductor devices, and more particularly, to electronic systems including semiconductor devices. Background Art

[0003] Electronic systems requiring data storage require semiconductor devices capable of storing high amounts of data. Consequently, research is underway to increase the data storage capacity of semiconductor devices. For example, semiconductor devices have been proposed that include three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the Invention

[0004] The present disclosure provides a semiconductor device having advantages in high-speed operation by reducing parasitic capacitance and an electronic system including the semiconductor device.

[0005] A semiconductor device may include: a substrate; a circuit element and a wiring portion, which are arranged on the substrate; a gate stack structure, including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the wiring portion; a channel structure, which penetrates the gate stack structure; an upper insulating layer, which covers the upper surface of the wiring portion and the gate stack structure; a connecting contact structure, which is connected to the circuit element by penetrating the upper insulating layer on the outside of the gate stack structure; and a dummy contact structure, which is arranged adjacent to the connecting contact structure and has a lower dielectric constant than that of the connecting contact structure.

[0006] A semiconductor device may include: a substrate; a circuit element and a wiring portion, which are arranged on the substrate; a gate stack structure, which includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the wiring portion; a channel structure, which penetrates the gate stack structure; an upper insulating layer, which covers the upper surface of the wiring portion and the gate stack structure; a connecting contact structure, which is connected to the circuit element by penetrating the upper insulating layer on the outside of the gate stack structure; and a dummy contact structure, which is arranged adjacent to the connecting contact structure and includes a material different from that of the connecting contact structure.

[0007] An electronic system may include: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device may include: a substrate; circuit elements and a wiring portion arranged on the substrate; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the wiring portion; a channel structure penetrating the gate stack structure; an upper insulating layer covering the upper surface of the wiring portion and the gate stack structure; a connecting contact structure connected to the circuit element by penetrating the upper insulating layer on the outside of the gate stack structure; and a dummy contact structure arranged adjacent to the connecting contact structure and having a lower dielectric constant than that of the connecting contact structure.

[0008] According to some embodiments, performance of high-speed operation of a semiconductor device and an electronic system including the semiconductor device may be improved by reducing parasitic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view schematically illustrating a semiconductor device according to some embodiments.

[0010] Figure 2 and Figure 3 It is shown that the Figure 1 1 and 2 are enlarged cross-sectional views of various examples of channel structures in a semiconductor device.

[0011] Figure 4 It shows Figure 1 An enlarged cross-sectional view of semiconductor device P1.

[0012] Figures 5 to 7 are diagrams illustrating various examples of dummy contact structures of a semiconductor device according to some embodiments.

[0013] Figures 8 to 12 are diagrams illustrating various examples of arrangements of connection contact structures and dummy contact structures of a semiconductor device in a plan view according to some embodiments.

[0014] Figure 13 and Figure 14 are plan views illustrating various examples of circuit elements connected to a connection contact structure of a semiconductor device according to some embodiments.

[0015] Figure 15 and Figure 17 is a perspective view illustrating various line structures of a connection line layer connected by a connection contact structure of a semiconductor device according to some embodiments.

[0016] Figure 16 and Figure 18 is a plan view illustrating various line structures of a connection line layer connected by a connection contact structure of a semiconductor device according to some embodiments.

[0017] Figure 19 is a cross-sectional view illustrating a semiconductor device according to some embodiments.

[0018] Figure 20 is a diagram schematically illustrating an electronic system including a semiconductor device according to some embodiments.

[0019] Figure 21 is a perspective view schematically illustrating an electronic system including a semiconductor device according to some embodiments.

[0020] Figure 22 and Figure 23 are cross-sectional views each schematically illustrating a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0021] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which disclosed embodiments are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0022] In order to clearly describe the present invention, parts or components not related to the description are omitted, and identical or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0023] In addition, in the drawings, the size and thickness of each element are arbitrarily shown for ease of description, and the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, areas, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and areas are exaggerated for ease of description.

[0024] It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, the words "on..." or "over..." mean being disposed on or below an object portion, and do not necessarily mean being disposed on the upper side of the object portion based on the direction of gravity.

[0025] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0026] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a section” means observing a section formed by vertically cutting the target portion from the side.

[0027] In the following, reference is made to Figures 1 to 4 , a semiconductor device according to some embodiments will be described.

[0028] Figure 1 is a cross-sectional view schematically illustrating a semiconductor device according to some embodiments. Figure 2 and Figure 3 It is shown that the Figure 1 1 and 2 are enlarged cross-sectional views of various examples of channel structures in a semiconductor device. Figure 4 It shows Figure 1 An enlarged cross-sectional view of semiconductor device P1.

[0029] Reference Figures 1 to 4 According to some embodiments, the semiconductor device 10 includes a cell region 100 and a circuit region 200. The cell region 100 is provided with a memory cell structure, and the circuit region 200 is provided with a peripheral circuit structure configured to control the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may be respectively provided with a memory cell structure. Figure 20 1 and 10. The first and second structures 1100F and 1100S of the semiconductor device 1100 in the electronic system 1000 are shown in FIG. Alternatively, the circuit region 200 and the unit region 100 may be connected to the semiconductor device 1100. Figure 22 3 , corresponding portions of the first structure 3100 and the second structure 3200 of the semiconductor chip 2200 are shown.

[0030] Here, the circuit region 200 may include a peripheral circuit structure formed on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH as a memory cell structure on a second substrate 110 located in the cell array region 102. A first wiring portion 230 electrically connected to the peripheral circuit structure may be located in the circuit region 200, and a second wiring portion 190 electrically connected to the memory cell structure may be located in the cell region 100.

[0031] In some embodiments, the cell region 100 may be located on the circuit region 200. Accordingly, since an area corresponding to the circuit region 200 can be ensured independently of the cell region 100, the area of ​​the semiconductor device 10 can be reduced. However, the embodiment is not limited thereto, and the circuit region 200 may be located near the cell region 100. Various other modifications are possible.

[0032] The circuit region 200 includes a first substrate 210 , and a circuit element 220 and a first wiring portion 230 located on the first substrate 210 .

[0033] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, and may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 210 may be formed of silicon, epitaxial silicon, germanium, silicon germanium, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like.

[0034] The circuit elements 220 formed on the first substrate 210 may include various circuit elements configured to control the operation of the memory cell structure provided in the cell region 100. For example, the circuit elements 220 may configure a peripheral circuit structure such as a decoder circuit (see Figure 20 1110), page buffer (see Figure 20 1120), logic circuit (see Figure 20 1130 ) etc.

[0035] The circuit element 220 may include, for example, a transistor, but is not limited thereto. For example, the circuit element 220 may include not only active elements (such as transistors) but also passive elements (such as capacitors, resistors, inductors, etc.).

[0036] The first wiring portion 230 located on the first substrate 210 can be electrically connected to the circuit element 220. In some embodiments, the first wiring portion 230 includes a plurality of first wire layers 236, which are spaced apart from each other, inserted into the first insulating layer 232, and connected by first contacts 234 to form a desired path. The first wire layers 236 or the first contacts 234 can include various conductive materials, and the first insulating layer 232 can include various insulating materials.

[0037] The cell region 100 includes a cell array region 102 and a connection region 104. In the cell array region 102, a gate stack structure 120 and a channel structure CH may be located on a second substrate 110. A structure for connecting the gate stack structure 120 and / or the channel structure CH located in the cell array region 102 to the circuit region 200 or an external circuit may be located in the connection region 104.

[0038] In some embodiments, the second substrate 110 may include a semiconductor material. For example, the second substrate 110 may include polysilicon doped with impurities. The second substrate 110 may function as a common source line. The second substrate 110 may serve as a source region configured to supply current to a memory cell located on the second substrate 110. The second substrate 110 may be formed in a plate shape. In other words, the second substrate 110 may be formed as a plate common source line.

[0039] In the cell array region 102, a gate stack structure 120 including a cell insulating layer 132 and a gate electrode 130 alternately stacked on a first surface (e.g., a front surface or an upper surface) of a second substrate 110, and a channel structure CH penetrating the gate stack structure 120 to extend in a direction intersecting the second substrate 110 may be positioned.

[0040] Horizontal conductive layers 112 and 114 may be disposed between the second substrate 110 and the gate stack structure 120 in the cell array region 102. The horizontal conductive layers 112 and 114 may be used to electrically connect the channel structure CH to the second substrate 110. For example, the horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 disposed on the first surface of the second substrate 110, and may further include a second horizontal conductive layer 114 disposed on the first horizontal conductive layer 112. In other words, the first horizontal conductive layer 112 may be disposed between the second substrate 110 and the second horizontal conductive layer 114. In a portion of the connection region 104, the first horizontal conductive layer 112 may not be disposed between the second substrate 110 and the gate stack structure 120, but a horizontal insulating layer 116 may be disposed instead. During the manufacturing process, a portion of the horizontal insulating layer 116 may be replaced with the first horizontal conductive layer 112, and another portion of the horizontal insulating layer 116 disposed in the connection region 104 may remain in the connection region 104.

[0041] The first horizontal conductive layer 112 may be used as a portion of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 may be used together with the second substrate 110 as a common source line. Figure 2 As shown in the enlarged view of FIG, the channel structure CH may penetrate the horizontal conductive layers 112 and 114 to extend to the second substrate 110, and the gate dielectric layer 150 may be removed from the portion where the first horizontal conductive layer 112 is located, so that the first horizontal conductive layer 112 may be directly connected to the channel layer 140 on the periphery of the channel layer 140. Therefore, the first horizontal conductive layer 112 may be electrically connected between the second substrate 110 and the channel layer 140.

[0042] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include a semiconductor material (e.g., polysilicon). For example, the first horizontal conductive layer 112 may include polysilicon doped with impurities, and the second horizontal conductive layer 114 may be a layer including polysilicon doped with impurities, or may be a layer including impurities diffused from the first horizontal conductive layer 112. However, embodiments are not limited thereto, and the second horizontal conductive layer 114 may include an insulating material. Alternatively, the second horizontal conductive layer 114 may not be provided separately.

[0043] The gate stack structure 120 in which cell insulating layers 132 and gate electrodes 130 are alternately stacked may be located on the second substrate 110 (eg, on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 formed on the second substrate 110 ).

[0044] In some embodiments, the gate stack structure 120 includes a plurality of gate stack structures 120a and 120b sequentially stacked on the second substrate 110. Thereby, the number of stacked gate electrodes 130 can be increased, and the number of memory cells can be increased in a stable structure. For example, the gate stack structure 120 may include a first gate stack structure 120a and a second gate stack structure 120b, thereby simplifying the structure while increasing data storage capacity. However, embodiments are not limited thereto, and the gate stack structure 120 may be configured as one gate stack structure, or may include three or more gate stack structures.

[0045] In the gate stack structure 120, the gate electrode 130 includes a lower gate electrode 130L, a memory cell gate electrode 130M, and an upper gate electrode 130U, which are sequentially located on the second substrate 110. The lower gate electrode 130L can serve as the gate electrode of the ground select transistor, the memory cell gate electrode 130M can constitute a memory cell, and the upper gate electrode 130U can serve as the gate electrode of the string select transistor. The number of memory cell gate electrodes 130M can be determined based on the data storage capacity of the semiconductor device 10. Depending on the embodiment, the lower gate electrode 130L and the upper gate electrode 130U can each be provided as one, two, or more, and can have the same or different structures as the memory cell gate electrode 130M. In addition, a portion of the gate electrode 130 (e.g., the memory cell gate electrode 130M adjacent to the lower gate electrode 130L and the upper gate electrode 130U) can be a dummy gate electrode.

[0046] The cell insulating layer 132 includes an interlayer insulating layer 132m located below the gate electrode 130 or between two adjacent gate electrodes 130 within the first gate stack structure 120a and the second gate stack structure 120b, and upper insulating layers 132a and 132b located in the upper portions of the first and second gate stack structures 120a and 120b. For example, the upper insulating layers 132a and 132b may include a first upper insulating layer 132a located in the upper portion of the first gate stack structure 120a, and a second upper insulating layer 132b located in the upper portion of the second gate stack structure 120b. In this case, the first upper insulating layer 132a may be an intermediate insulating layer located between the first and second gate stack structures 120a and 120b, and the second upper insulating layer 132b may be an uppermost insulating layer located in the uppermost portion of the gate stack structure 120. The second upper insulating layer 132b may constitute part or all of the cell region insulating layer located entirely in the upper portion of the cell region 100. In some embodiments, the thicknesses of the plurality of unit insulating layers 132 may not all be the same. For example, the thicknesses of the upper insulating layers 132a and 132b may be greater than the thickness of the interlayer insulating layer 132m. However, the shape, structure, etc. of the unit insulating layer 132 may be varied in various ways depending on the embodiment.

[0047] For simplicity of description, the drawings illustrate that in the connection region 104, the unit insulating layer 132 has a boundary between the first gate stack structure 120a and the second gate stack structure 120b. However, embodiments are not limited thereto. In the connection region 104, the plurality of insulating layers may have various stacking structures, and embodiments are not limited thereto.

[0048] The gate electrode 130 may include various conductive materials. For example, the gate electrode 130 may include a metal material (such as tungsten (W), copper (Cu), aluminum (Al), etc.). As another example, the gate electrode 130 may include polysilicon, a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. An insulating layer formed of an insulating material may be positioned on the outer side of the gate electrode 130, or a portion of the gate dielectric layer 150 may be positioned.

[0049] The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a lower k than silicon oxide, or a combination thereof.

[0050] In some embodiments, a channel structure CH may be positioned to penetrate the gate stack structure 120 and extend in a direction crossing the second substrate 110 (eg, a vertical direction perpendicular to the second substrate 110 ) (Z-axis direction in the drawing).

[0051] In more detail, the channel structure CH includes a channel layer 140, and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may further include a core insulating layer 142 located in an interior of the channel layer 140, and may further include a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150.

[0052] Each channel structure CH may form a memory cell string, and in a plan view, a plurality of channel structures CH may be arranged spaced apart from each other to form rows and columns. For example, in a plan view, a plurality of channel structures CH may be arranged in various forms (such as a lattice form, a zigzag form, etc.). The channel structure CH may have a columnar shape. For example, when viewed in cross section, the channel structure CH may have an inclined side surface according to the aspect ratio so that the width becomes narrower as it approaches the second substrate 110. However, the embodiment is not limited thereto, and the arrangement, structure, shape, etc. of the channel structure CH may be changed in various ways.

[0053] The core insulating layer 142 may be provided in the central region of the channel structure CH, and the channel layer 140 may be provided so as to surround the sidewalls of the core insulating layer 142. For example, the core insulating layer 142 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape), and the channel layer 140 may have a planar shape such as a ring shape. However, embodiments are not limited thereto, and the channel layer 140 may have a columnar shape (e.g., a cylindrical shape or a polygonal columnar shape) without providing the core insulating layer 142.

[0054] The channel layer 140 may include a semiconductor material (e.g., polysilicon). The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the materials of the channel layer 140 and the core insulating layer 142 are not limited thereto.

[0055] The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 includes a tunneling layer 152 , a charge storage layer 154 , and a blocking layer 156 sequentially stacked on the channel layer 140 .

[0056] At this time, the tunneling layer 152 may be a layer through which tunneling of charges occurs according to the voltage applied to the gate electrode 130, and may include an insulating material that enables tunneling of charges. The tunneling layer 152 may include a material such as silicon oxide, silicon oxynitride, etc. For example, the tunneling layer 152 may be formed by stacking a layer including silicon oxide and a layer including silicon nitride.

[0057] The charge storage layer 154 disposed between the tunneling layer 152 and the blocking layer 156 may function as a data storage region. For example, the charge storage layer 154 may include silicon nitride, which is capable of trapping charges. When the charge storage layer 154 is formed of silicon nitride, it may provide superior retention compared to when it is formed of polysilicon and may facilitate integration. However, the material of the charge storage layer 154 is not limited thereto.

[0058] A blocking layer 156 may be disposed between the charge storage layer 154 and the gate electrode 130. The blocking layer 156 may include an insulating material that may prevent unwanted charges from flowing into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material, or a combination thereof.

[0059] Here, the high dielectric constant material may refer to a dielectric material having a higher dielectric constant than silicon oxide. For example, the high dielectric constant material may include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), Hafnium Oxide (HfO2), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ), praseodymium oxide (Pr2O3), or a combination thereof.

[0060] The channel pad 144 may be disposed on the channel layer 140 and / or the gate dielectric layer 150. The channel pad 144 may be disposed to cover the upper surface of the core insulating layer 142 and be electrically connected to the channel layer 140. Although the channel pad 144 is shown as covering the upper surface of the gate dielectric layer 150, it is not limited thereto. For example, the channel pad 144 may not cover the upper surface of the gate dielectric layer 150. In this case, the side surface of the channel pad 144 may be surrounded by the gate dielectric layer 150. The side surface of the channel pad 144 may contact the tunneling layer 152. The channel pad 144 may include a conductive material (e.g., polysilicon doped with impurities). However, the material of the channel pad 144 is not limited thereto and may be varied in various ways.

[0061] As described above, when the gate stack structure 120 includes a plurality of gate stack structures 120a and 120b stacked relative to each other, the channel structure CH may be provided with a plurality of channel structures CH1 and CH2 respectively penetrating the plurality of gate stack structures 120a and 120b. The plurality of channel structures CH1 and CH2 may have an interconnected form. When viewed in cross section, each of the plurality of channel structures CH1 and CH2 may have an inclined side surface according to an aspect ratio so that the width becomes narrower as it approaches the second substrate 110. Figure 2 As shown in FIG, a bent portion may be provided by a width difference in a portion connected by a plurality of channel structures CH1 and CH2. As another example, as shown in FIG. Figure 3 As shown in , first and second channel structures CH1 and CH2 may be provided, having continuous inclined side surfaces without a curved portion. However, the shapes of the plurality of channel structures CH1 and CH2 are not limited thereto and may be changed in various ways.

[0062] Figure 1 As an example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of each of the plurality of channel structures CH1 and CH2 are shown as an integral structure formed by extension. However, embodiments are not limited thereto. As another example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of each of the plurality of channel structures CH1 and CH2 may be formed separately and electrically connected to each other.

[0063] In addition, a separate channel pad may be additionally provided to the connection portions of the plurality of channel structures CH1 and CH2. Various other changes are available.

[0064] In some embodiments, in a plan view, the gate stack structure 120 may be divided into a plurality of separation structures 146 extending in a direction intersecting the second substrate 110 (eg, a vertical direction, a Z-axis direction in the drawing) to penetrate the gate stack structure 120 .

[0065] For example, the separation structure 146 may penetrate the gate electrode 130 and the cell insulating layer 132 and extend to the second substrate 110. In a plan view, the separation structures 146 may be provided in a plurality so that they extend in one direction (the Y-axis direction in the drawing) and may be spaced apart from each other at predetermined intervals in a cross direction (the X-axis direction in the drawing) that intersects the one direction. Thus, in a plan view, a plurality of gate stack structures 120 may each extend in one direction (the Y-axis direction in the drawing) and may be spaced apart from each other at predetermined intervals in a cross direction (the X-axis direction in the drawing). The gate stack structures 120 divided by the separation structures 146 may constitute a memory cell block. However, the embodiment is not limited thereto, and the scope of the memory cell block is not limited thereto.

[0066] When viewed in cross section, as an example, the separation structure 146 may have an inclined side surface whose width decreases toward the second substrate 110 due to a high aspect ratio. However, the embodiment is not limited thereto, and the side surface of the separation structure 146 may be perpendicular to the second substrate 110. When viewed in cross section, Figure 2 In the example shown, the separation structure 146 has a continuous inclined side surface in the first gate stack structure 120a and the second gate stack structure 120b and is not provided with a curved portion. However, the embodiment is not limited thereto, and the separation structure 146 may be provided with a curved portion in the boundary portion between the first gate stack structure 120a and the second gate stack structure 120b.

[0067] The separation structure 146 may be filled with various insulating materials. For example, the separation structure 146 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiment is not limited thereto, and the structure, shape, material, etc. of the separation structure 146 may be changed in various ways.

[0068] In addition, an upper separation pattern 148 may be formed in an upper portion of the gate stack structure 120. In a plan view, the upper separation patterns 148 may be provided in a plurality such that they extend in one direction (the Y-axis direction in the drawing) and are spaced apart from each other at predetermined intervals in a crossing direction (the X-axis direction in the drawing) crossing the one direction.

[0069] The upper separation pattern 148 may be formed to penetrate one or more gate electrodes 130, including the upper gate electrode 130U located between the separation structures 146. The upper separation pattern 148 may separate, for example, three gate electrodes 130 from each other in the intersecting direction (the X-axis direction in the drawing). However, the number of gate electrodes 130 separated by the upper separation pattern 148 is not limited thereto and may be varied in various ways. The upper separation pattern 148 may have a form filled with an insulating material. For example, the upper separation pattern 148 may include an insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride). However, the embodiment is not limited thereto, and the structure, shape, material, etc. of the upper separation pattern 148 may be varied in various ways.

[0070] In order to connect the gate stack structure 120 and the channel structure CH disposed in the cell array region 102 to the circuit region 200 or an external circuit, a connection region 104 and a connection portion 180 may be provided.

[0071] Here, the connection portion 180 may include all components configured to electrically connect the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114, and / or the second substrate 110 to the circuit region 200 or an external circuit. For example, the connection portion 180 may include a bit line 182, a gate contact 184, a source contact 186, and contact vias 180a connected thereto, as well as a second wiring portion 190 connecting them.

[0072] Bit line 182 may be located on cell insulating layer 132 of gate stack structure 120 formed in cell array region 102. Bit line 182 may extend in a direction intersecting one direction along which gate electrode 130 extends (the X-axis direction in the drawing). Bit line 182 may be electrically connected to channel structure CH (e.g., channel pad 144) through contact via 180a (e.g., bit line contact via).

[0073] The connection region 104 may be provided near the cell array region 102. A portion of the connection portion 180 may be located in the connection region 104. The gate electrode 130, the horizontal conductive layers 112 and 114, and / or the second substrate 110, and members for connecting to the circuit region 200 may be provided in the connection region 104.

[0074] In more detail, in the connection region 104, the plurality of gate electrodes 130 may be positioned to extend in a single direction (the Y-axis direction in the drawings), and the extension lengths of the plurality of gate electrodes 130 may sequentially decrease as they move away from the second substrate 110 in the connection region 104. For example, the plurality of gate electrodes 130 may be positioned in the connection region 104 in a stepped configuration. In this case, the plurality of gate electrodes 130 may have a stepped configuration in a single direction or in multiple directions. In the connection region 104, the plurality of gate contacts 184 may penetrate the cell insulating layer 132 and be electrically connected to the plurality of gate electrodes 130 extending in the connection region 104.

[0075] Figure 1 An example is shown in which, in the connection region 104, the gate contact 184 penetrates the cell insulating layer 132 to reach the gate electrode 130 and is connected to the gate electrode 130. However, the present invention is not limited thereto, and the gate contact 184 may penetrate the cell insulating layer 132 and the gate electrode 130 and extend to the first wiring portion 230 provided in the circuit region 200. At this time, the gate contact 184 may be provided with a pad to correspond to the gate electrode 130 to be connected among the plurality of gate electrodes 130 included in the gate stack structure 120, and may be insulated from another gate electrode 130 by an insulating material.

[0076] In the connection region 104 , the source contact 186 may penetrate the cell insulating layer 132 and be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110 .

[0077] When viewed in cross section, Figure 1 In the example shown, gate contact 184 and / or source contact 186 may have inclined side surfaces depending on the aspect ratio, such that the width becomes narrower as it approaches second substrate 110, and a curved portion is provided at the boundary between first gate stack structure 120a and second gate stack structure 120b. However, embodiments are not limited thereto. For example, gate contact 184 and / or source contact 186 may not have a curved portion at the boundary between first gate stack structure 120a and second gate stack structure 120b. Various other variations are possible.

[0078] Second wiring portion 190 may be located in cell array region 102 and / or connection region 104. Bit line 182, gate contact 184, and / or source contact 186 may be electrically connected to second wiring portion 190. For example, gate contact 184 and / or source contact 186 may be connected to second wiring portion 190 through contact via 180a.

[0079] In some embodiments, the second wiring portion 190 includes a plurality of second wire layers 196 spaced apart from each other, the plurality of second wire layers 196 being inserted into the second insulating layer 192 and connected through the second contacts 194. The second wire layers 196 or the second contacts 194 may include various conductive materials, and the second insulating layer 192 may include various insulating materials.

[0080] According to some embodiments, the connection portion 180 includes a connection contact structure CC and a dummy contact structure DC. The connection contact structure CC may be located on the outer side of the gate stack structure 120 in the connection region 104. Figure 1 One connection contact structure CC is shown, but is not limited thereto, and a plurality of connection contact structures CC may be provided spaced apart in a direction parallel to the upper surface of the first substrate 210 on the outer side of the gate stack structure 120 in the connection region 104. The connection contact structure CC may penetrate the upper insulating layers 132 a and 132 b covering the upper surfaces of the gate stack structure 120 and the first wiring portion 230.

[0081] The connection contact structure CC may penetrate the first upper insulating layer 132 a located in an upper portion of the first gate stack structure 120 a and the second upper insulating layer 132 b located in an upper portion of the second gate stack structure 120 b . Figure 1 An example is shown in which a boundary exists between the first upper insulating layer 132 a and the second upper insulating layer 132 b , but is not limited thereto. In the connection region 104 , the insulating layer on the outer side of the gate stack structure 120 may have a single layer or various stacked structures.

[0082] The connection contact structure CC may penetrate the upper insulating layers 132a and 132b and be connected to the circuit element 220. Through the connection portion 180 and the first wiring portion 230 including the connection contact structure CC, the bit line 182 connected to the channel structure CH, the gate electrode 130, the horizontal conductive layers 112 and 114, and / or the second substrate 110 may be electrically connected to the circuit element 220 of the circuit region 200.

[0083] The connection contact structure CC includes a connection contact CT configured to connect a plurality of connection line layers CW located in the upper and lower portions of the upper insulating layers 132 a and 132 b in a direction perpendicular to the upper surface of the first substrate 210. The plurality of connection line layers CW include a plurality of lower connection line layers 250 located in the lower portions of the upper insulating layers 132 a and 132 b and a plurality of upper connection line layers 160 located in the upper portions of the upper insulating layers 132 a and 132 b.

[0084] The plurality of lower connection line layers 250 may be spaced apart in a direction (Z direction) perpendicular to the first substrate 210 by the first insulating layer 232 of the first wiring portion 230. The plurality of lower connection line layers 250 may be located on the same layer as the plurality of line layers 236 of the first wiring portion 230. The plurality of lower connection line layers 250 may be connected to the plurality of line layers 236 of the first wiring portion 230.

[0085] The plurality of upper connection line layers 160 may be spaced apart in a direction (Z direction) perpendicular to the first substrate 210 by the second insulating layer 192 of the second wiring portion 190. The plurality of upper connection line layers 160 may be located on the same side as the plurality of second line layers 196 of the second wiring portion 190. The plurality of upper connection line layers 160 may be connected to the plurality of second line layers 196 of the second wiring portion 190.

[0086] The connection contacts CT include lower contacts 187 connecting multiple lower connection line layers 250 or connecting the lower connection line layer 250 and the circuit element 220 , upper contacts 189 connecting multiple upper connection line layers 160 , and through contacts 188 connecting the lower connection line layer 250 and the upper connection line layer 160 .

[0087] The lower contact 187 may connect the plurality of lower connection line layers 250 by penetrating the first insulating layer 232 of the first wiring portion 230, or may connect the lower connection line layer 250 and the circuit element 220. The upper contact 189 may connect the plurality of upper connection line layers 160 by penetrating the second insulating layer 192 of the second wiring portion 190.

[0088] Figure 1In the illustrated example, upper contact 189 connects a plurality of upper connection line layers 160, but the present invention is not limited thereto. Connection region 104 may include input / output pads on second wiring portion 190, and upper contact 189 may connect upper connection line layer 160 and the input / output pads. The plurality of connection line layers CW connected to the input / output pads may include input / output connection lines.

[0089] The through-contact 188 may penetrate the upper insulating layers 132a and 132b and be connected to the lower connection line layer 250. The through-contact 188 may be directly connected to the lower connection line layer 250. The through-contact 188 may connect the lower connection line layer 250 and the upper connection line layer 160. Figure 1 An example is shown in which the through-contact 188 is connected to the upper connection line layer 160 through the contact via 180 a , but is not limited thereto.

[0090] When viewed in cross section, Figure 1 and Figure 4 In the embodiment of the present invention, the connection contact CT may have an inclined side surface according to the aspect ratio so that the width becomes narrower as it approaches the first substrate 210. The through contact 188 may be provided with a bent portion in the boundary portion between the first upper insulating layer 132a and the second upper insulating layer 132b, but is not limited thereto. For example, the through contact 188 may not be provided with a bent portion in the boundary portion between the first upper insulating layer 132a and the second upper insulating layer 132b, and various other variations are possible.

[0091] The plurality of connection line layers CW and the connection contacts CT may comprise conductive materials. For example, the plurality of connection line layers CW may comprise metal, but is not limited thereto. The connection contacts CT may comprise the same material as the plurality of connection line layers CW, or may comprise a conductive material different from that of the plurality of connection line layers CW. The lower contact 187, the through contact 188, and the upper contact 189 may each comprise a different material.

[0092] The connection contact structure CC may electrically connect the lower connection line layer 250 and the upper connection line layer 160. The connection contact structure CC may be electrically connected to the circuit element 220 connected to the lower connection line layer 250. For example, when the connection contact CT is also connected to the input / output pad, the connection contact structure CC may be electrically connected to the input / output pad.

[0093] The dummy contact structure DC may be provided adjacent to the connection contact structure CC. A plurality of dummy contact structures DC may be provided adjacent to the connection contact structure CC. Figures 8 to 12 The arrangement of the plurality of dummy contact structures DC and the connecting contact structures CC is described in detail.

[0094] The dummy contact structure DC includes a dummy contact DCT overlapping the connection contact CT in a direction parallel to the upper surface of the first substrate 210. The dummy contact DCT may extend in a direction perpendicular to the upper surface of the first substrate 210.

[0095] According to some embodiments, the dummy contact DCT may overlap with the through contact 188 in a direction parallel to the upper surface of the first substrate 210. The dummy contact DCT may penetrate the upper insulating layers 132a and 132b. In some embodiments, the dummy contact DCT may be provided with a curved portion at the boundary portion between the first upper insulating layer 132a and the second upper insulating layer 132b, but is not limited thereto. For example, the dummy contact DCT may not be provided with a curved portion at the boundary portion between the first upper insulating layer 132a and the second upper insulating layer 132b, and various other variations are possible.

[0096] The dummy contact structure DC may have a lower dielectric constant than the connection contact structure CC. The dummy contact structure DC may include a material different from the connection contact structure CC. The dummy contact structure DC may include a material having a lower dielectric constant than the connection contact structure CC. According to some embodiments, the dummy contact DCT may include a material having a lower dielectric constant than the connection contact CT overlapping the dummy contact DCT in a direction parallel to the upper surface of the first substrate 210. Figure 1 and Figure 4 In the embodiment, since the dummy contact DCT overlaps the through-contact 188 in a direction parallel to the upper surface of the first substrate 210 , the dummy contact DCT may include a material having a lower dielectric constant than the through-contact 188 .

[0097] The material having a lower dielectric constant than the connection contact CT may include, for example, air, but is not limited thereto. The dummy contact DCT may include, but is not limited thereto, an insulating material and may include a conductive material having lower conductivity than the connection contact CT.

[0098] According to some embodiments, the dummy contact DCT includes a cover layer CV and an air gap AG located within the cover layer CV. The cover layer CV may surround the air gap AG. Figure 1 and Figure 4 In the embodiment, the capping layer CV may separate the air gap AG from the upper insulating layers 132a and 132b.

[0099] In some embodiments, the cover layer CV may include the same material as the connection contact CT. However, embodiments are not limited to the case where the cover layer CV includes the same material as the connection contact CT. In some embodiments, the cover layer CV may include a material different from the connection contact CT. In this case, the material different from the connection contact CT may include a material having a lower dielectric constant than the connection contact CT, or a material having a higher dielectric constant than the connection contact CT. For example, when the cover layer CV includes a material having a higher dielectric constant than the connection contact CT, the entire dummy contact DCT, including the cover layer CV and the air gap AG, may have a lower dielectric constant than the connection contact CT.

[0100] The dummy contact structure DC may be floating. Figure 1 and Figure 4 The dummy contact DCT is shown connected to the lower connection line layer 250 and the upper connection line layer 160 (directly connected to the lower connection line layer 250 and connected to the upper connection line layer 160 through the contact via 180a). However, embodiments are not limited thereto, and the dummy contact DCT may not be connected to the lower connection line layer 250 and the upper connection line layer 160. Alternatively, the dummy contact DCT may not be electrically connected to the lower connection line layer 250 and the upper connection line layer 160. For example, the lines of the lower connection line layer 250 and the upper connection line layer 160 to which the dummy contact DCT is connected may not be connected to other lines of the lower connection line layer 250 and the upper connection line layer 160. As another example, when the dummy contact DCT includes an insulating material, it may not be electrically connected to the lower connection line layer 250 and the upper connection line layer 160.

[0101] The semiconductor device 10 according to some embodiments includes a dummy contact structure DC adjacent to the connection contact structure CC and having a lower dielectric constant than the connection contact structure CC, and thus, parasitic capacitance of the connection contact structure CC in a direction parallel to the upper surface of the first substrate 210 may be reduced.

[0102] In the following, reference will be made to Figures 5 to 7 describe Figure 1 Various examples of the dummy contact structure DC of the semiconductor device 10 are shown.

[0103] Figures 5 to 7 are diagrams illustrating various examples of dummy contact structures of a semiconductor device according to some embodiments. Figures 5 to 7 Can be Figure 1 An enlarged cross-sectional view of P1.

[0104] Reference Figure 5 , as in Figure 4 In the embodiment of the present invention, the dummy contact structure DC may be provided adjacent to the connecting contact structure CC. The dummy contact structure DC is included in the substrate 210 (see FIG. Figure 1) is overlapped with the connection contact CT in a direction parallel to the upper surface of the substrate. The dummy contact DCT can connect the upper connection line layer 160 and the lower connection line layer 250 by penetrating the upper insulating layers 132a and 132b. The dummy contact DCT can be overlapped with the substrate 210 (see Figure 1 ) overlaps with the through contact 188 in a direction parallel to the upper surface of the .

[0105] according to Figure 5 The embodiment shown in Figure 4 In some embodiments, the dummy contact DCT may have the same cross-sectional shape as the connection contact CT. The dummy contact DCT may include a material having a lower dielectric constant than the connection contact CT. According to some embodiments, the dummy contact DCT may have the same cross-sectional shape as the through contact 188. The dummy contact DCT may not include an air gap, and its interior may be completely filled with a material having a lower dielectric constant than the material forming the through contact 188.

[0106] According to some embodiments, in the presence of a substrate 210 (see Figure 1 ) in a direction parallel to the upper surface of the contact 188, the parasitic capacitance of the through contact 188 can be reduced.

[0107] Reference Figure 6 , as in Figure 4 In the embodiment of the present invention, the dummy contact structure DC may be provided adjacent to the connecting contact structure CC. The dummy contact structure DC is included in the substrate 210 (see FIG. Figure 1 ) is overlapped with the connection contact CT in a direction parallel to the upper surface of the substrate 210. The dummy contact DCT may penetrate the upper insulating layers 132a and 132b to be in contact with the substrate 210 (see FIG. Figure 1 ) extends in a direction perpendicular to the upper surface of the substrate 210 (see FIG. Figure 1 ) overlaps with the through contact 188 in a direction parallel to the upper surface of the .

[0108] according to Figure 6 The embodiment shown in Figure 4 In the embodiment, with the substrate 210 (see Figure 1 ), the dummy contact DCT may also overlap with the lower contact 187 that connects the plurality of lower connection line layers 250 by penetrating the first insulating layer 232. Figure 1 ), the dummy contact DCT may also overlap with the upper contact 189 that connects the plurality of upper connection line layers 160 by penetrating the second insulating layer 192. Figure 6 Such an example is shown: in the substrate 210 (see Figure 1), the dummy contact DCT overlaps with the through contact 188 and also overlaps with the lower contact 187 and the upper contact 189, but the embodiment is not limited thereto. For example, in a direction parallel to the upper surface of the substrate 210 (see Figure 1 ), the dummy contact DCT may overlap with the through contact 188 and may also overlap with one of the lower contact 187 and the upper contact 189.

[0109] According to some embodiments, in the presence of a substrate 210 (see Figure 1 ), the dummy contact DCT includes a penetrating dummy contact 178 overlapping with the through contact 188 and includes a dummy contact 178 disposed parallel to the substrate 210 (see FIG. Figure 1 ) and the lower dummy contact 177 overlapping the lower contact 187 in a direction parallel to the upper surface of the substrate 210 (see Figure 1 ) at least one of the upper dummy contacts 179 overlapping the upper contact 189 in a direction parallel to the upper surface of the .

[0110] According to some embodiments, through-dummy contact 178 may have a different internal structure than through-contact 188, and lower dummy contact 177 and upper dummy contact 179 may have the same internal structure as lower contact 187 and upper contact 189, respectively. According to some embodiments, through-dummy contact 178 includes a cover layer CV made of the same material as through-contact 188 and an air gap AG located within cover layer CV, but is not limited thereto. For example, cover layer CV of through-dummy contact 178 may include a different material than through-contact 188. In this case, the different material from through-contact 188 may include a material having a lower dielectric constant than through-contact 188, or a material having a higher dielectric constant than through-contact 188. For example, when cover layer CV of through-dummy contact 178 includes a material having a higher dielectric constant than through-contact 188, the entire through-dummy contact 178, including cover layer CV and air gap AG, may have a lower dielectric constant than through-contact 188.

[0111] According to some embodiments, lower dummy contact 177 and upper dummy contact 179 may have the same cross-sectional shape as lower contact 187 and upper contact 189, respectively. Lower dummy contact 177 and upper dummy contact 179 may be completely filled with the same material as that forming lower contact 187 and upper contact 189, respectively.

[0112] However, embodiments are not limited to the case where only through-dummy contact 178 has a lower dielectric constant than through-contact 188. According to some embodiments, lower dummy contact 177 and upper dummy contact 179 may also have a lower dielectric constant than lower contact 187 and upper contact 189, respectively. For example, lower dummy contact 177 and upper dummy contact 179 may be completely filled with a material having a lower dielectric constant than lower contact 187 and upper contact 189, respectively. In this case, lower dummy contact 177 and upper dummy contact 179 may include different materials. As another example, lower dummy contact 177 and upper dummy contact 179 may include a cover layer CV and an air gap AG located in the cover layer CV of lower dummy contact 177 and upper dummy contact 179, respectively. In this case, cover layer CV of lower dummy contact 177 may include the same or similar material as that of lower contact 187. At this time, the material different from the lower contact 187 may include a material having a lower or higher dielectric constant than the lower contact 187. When the cover layer CV of the lower dummy contact 177 includes a material having a higher dielectric constant than the lower contact 187, the entire lower dummy contact 177 including the cover layer CV and the air gap AG may have a lower dielectric constant than the lower contact 187. The contents described above with respect to the cover layer CV of the lower dummy contact 177 may be equally or similarly applied to the cover layer CV of the upper dummy contact 179.

[0113] Figure 6 An example is shown in which the dummy contact DCT includes one lower dummy contact 177 and one upper dummy contact 179 , but the present invention is not limited thereto. The dummy contact DCT may include a plurality of lower dummy contacts 177 or a plurality of upper dummy contacts 179 .

[0114] According to some embodiments, in the presence of a substrate 210 (see Figure 1 ), the parasitic capacitance of through-contact 188 can be reduced. According to some embodiments, lower dummy contact 177 and upper dummy contact 179 further have a lower dielectric constant than lower contact 187 and upper contact 189, thereby further reducing the parasitic capacitance of lower contact 187 and upper contact 189.

[0115] Reference Figure 7 , as in Figure 4 In the embodiment of the present invention, the dummy contact structure DC can be arranged adjacent to the connecting contact structure CC. Figure 1 ), the dummy contact structure DC includes a dummy contact DCT overlapping the connecting contact CT.

[0116] according to Figure 7 The embodiment shown in Figure 4 In the embodiment, with the substrate 210 (see Figure 1 ), the dummy contact DCT may overlap with the lower contact 187 that connects the plurality of lower connection line layers 250 by penetrating the first insulating layer 232. Figure 1 ), the dummy contact DCT may overlap with the upper contact 189 connecting the plurality of upper connection line layers 160 by penetrating the second insulating layer 192. According to some embodiments, the dummy contact DCT may not penetrate the upper insulating layers 132a and 132b.

[0117] According to some embodiments, a dummy contact DCT may be included between the substrate 210 (see Figure 1 ) in a direction parallel to the upper surface of the substrate 210 (see Figure 1 ) in a direction parallel to the upper surface of the PCB and overlapping with the upper contact 189.

[0118] Figure 7 An example is shown in which the dummy contact DCT includes all of the lower dummy contacts 177 and the upper dummy contacts 179 , but is not limited thereto, and the dummy contact DCT may include only one of the lower dummy contact 177 and the upper dummy contact 179 .

[0119] According to some embodiments, lower dummy contact 177 and upper dummy contact 179 may have different internal structures from lower contact 187 and upper contact 189, respectively. According to some embodiments, lower dummy contact 177 and upper dummy contact 179 include a cover layer CV and an air gap AG located in cover layer CV of lower dummy contact 177 and upper dummy contact 179, respectively. Cover layer CV of lower dummy contact 177 may include the same or similar material as lower contact 187. In this case, the material different from lower contact 187 may include a material having a lower or higher dielectric constant than lower contact 187. When cover layer CV of lower dummy contact 177 includes a material having a higher dielectric constant than lower contact 187, the entire lower dummy contact 177, including cover layer CV and air gap AG, may have a lower dielectric constant than lower contact 187. What is described above with respect to the cover layer CV of the lower dummy contact 177 may be equally or similarly applied to the cover layer CV of the upper dummy contact 179 .

[0120] However, the present disclosure is not limited to the above-described embodiments. According to some embodiments, lower dummy contact 177 and upper dummy contact 179 may be completely filled with a material having a lower dielectric constant than lower contact 187 and upper contact 189, respectively. In this case, lower dummy contact 177 and upper dummy contact 179 may include different materials.

[0121] According to some embodiments, lower dummy contact 177 includes a cover layer CV and an air gap AG located in cover layers CV of lower dummy contact 177 and upper dummy contact 179, respectively, and upper dummy contact 179 may be completely filled with a material having a lower dielectric constant than upper contact 189. Some embodiments in which the structure of lower dummy contact 177 and the structure of upper dummy contact 179 are opposite may be possible.

[0122] According to some embodiments, lower dummy contact 177 may have a lower dielectric constant than lower contact 187, and upper dummy contact 179 may have the same dielectric constant as upper contact 189. In other embodiments, upper dummy contact 179 may have a lower dielectric constant than upper contact 189, and lower dummy contact 177 may have the same dielectric constant as lower contact 187. That is, it is sufficient if at least one of lower dummy contact 177 and upper dummy contact 179 included in dummy contact DCT has a lower dielectric constant than lower contact 187 or upper contact 189 overlapping therewith.

[0123] Figure 7 In the illustrated example, the dummy contact DCT includes one lower dummy contact 177 and one upper dummy contact 179, but is not limited thereto. The dummy contact DCT may include multiple lower dummy contacts 177 or multiple upper dummy contacts 179. The number of lower dummy contacts 177 and upper dummy contacts 179 included in the dummy contact DCT may vary. When the dummy contact DCT includes multiple lower dummy contacts 177, the dummy contacts 177 may include lower dummy contacts 177 having different materials or structures. When the dummy contact DCT includes multiple upper dummy contacts 179, the dummy contacts 179 may include upper dummy contacts 179 having different materials or structures. At least one lower dummy contact 177 or at least one upper dummy contact 179 may have a lower dielectric constant than the overlapping lower contact 187 or upper contact 189.

[0124] According to some embodiments, in the presence of a substrate 210 (see Figure 1 ), the parasitic capacitance of the lower contact 187 and / or the upper contact 189 can be reduced.

[0125] In the following, reference is made to Figures 8 to 12 , will describe Figure 1 Arrangement of the connection contact structure CC and the dummy contact structure DC of the semiconductor device 10 in a plan view.

[0126] Figures 8 to 12 are diagrams illustrating various examples of arrangements of connection contact structures and dummy contact structures of a semiconductor device in a plan view according to some embodiments. Figures 8 to 12can be represented on the substrate 210 (see Figure 1 ) in a direction parallel to the upper surface of the connection contact CT (see Figure 1 ) and dummy contacts DCT (see Figure 1 ) arrangement. Figures 8 to 12 Shown connecting contacts CT (see Figure 1 ) and dummy contacts DCT (see Figure 1 ) is a quadrilateral, but it is understood that this is expressed in an arbitrary shape in order to express the connection contact CT (see Figure 1 ) with dummy contacts DCT (see Figure 1 ) and connect the contact CT (see Figure 1 ) and dummy contacts DCT (see Figure 1 )'s planar shape can be changed in various ways.

[0127] Reference Figures 8 to 12 , the plurality of dummy contact structures DC may be disposed adjacent to the connection contact structure CC. In a plan view, the plurality of dummy contact structures DC may be disposed to surround the connection contact structure CC. Figures 8 to 11 An example is shown in which a plurality of dummy contact structures DC surrounding the connection contact structure CC are arranged in a quadrangular shape, but is not limited thereto, and as shown in FIG. Figure 12 As shown in , they may be arranged circularly. In addition, the arrangement of the plurality of dummy contact structures DC in a plan view may be changed into various forms.

[0128] like Figure 8 、 Figure 10 and Figure 12 As shown in , a plurality of dummy contact structures DC may be arranged to surround the connecting contact structure CC once. Figure 9 and Figure 11 As shown in , the plurality of dummy contact structures DC may be arranged to surround the connecting contact structure CC twice. In this way, the plurality of dummy contact structures DC may be arranged to surround the connecting contact structure CC once or more times. That is, one or more dummy contact structures DC may also be located between the connecting contact structure CC and the dummy contact structure DC.

[0129] Figure 8 、 Figure 10 and Figure 12 An example is shown in which adjacent dummy contact structures DC are disposed to be spaced apart from each other at the same interval, but is not limited thereto. In some embodiments, adjacent dummy contact structures DC may be spaced apart at different intervals to be irregularly disposed.

[0130] The distance between the plurality of dummy contact structures DC and the connection contact structure CC may be as follows: Figure 8 and Figure 10The ones shown in the figure can be modified in various ways. Figure 9 and Figure 11 In the example shown, the plurality of dummy contact structures DC may include a first dummy contact structure surrounding the connecting contact structure CC at a position approximately a first distance away from the connecting contact structure CC, and a second dummy contact structure surrounding the connecting contact structure CC at a position approximately a second distance away from the connecting contact structure CC. In this case, the first distance and the second distance may be varied in various ways.

[0131] In a plan view, a first dummy contact structure DC among the plurality of dummy contact structures DC may be disposed on a first side of the connection contact structure CC, and a second dummy contact structure DC may be disposed on an opposite side of the connection contact structure CC. Figure 8 、 Figure 10 and Figure 12 As shown in FIG, a dummy contact structure DC can be respectively provided on one side and the opposite side of the connection contact structure CC. Figure 9 and Figure 11 As shown in , the two dummy contact structures DC may be respectively disposed on one side and an opposite side of the connecting contact structure CC. That is, the connecting contact structure CC may be located between at least two dummy contact structures DC. Figures 8 to 12 In the example shown, the number of dummy contact structures DC located on the first side of the connection contact structure CC is the same as the number of dummy contact structures DC located on the opposite side of the connection contact structure CC, but the present invention is not limited thereto. In some embodiments, the number of dummy contact structures DC located on the first side of the connection contact structure CC and the number of dummy contact structures DC located on the opposite side of the connection contact structure CC may be different.

[0132] at the same time, Figures 8 to 12 In the example shown, multiple dummy contact structures DC are arranged to surround a connection contact structure CC, but the present invention is not limited thereto. For example, multiple dummy contact structures DC may be arranged to surround multiple connection contact structures CC. For example, multiple connection contact structures CC may be arranged in an array, but the present invention is not limited thereto. Different voltages may be applied to the multiple connection contact structures CC arranged to be surrounded by the multiple dummy contact structures DC.

[0133] In the following, reference is made to Figure 13 and Figure 14 , will describe Figure 1 The connection contact structure CC of the semiconductor device 10 is connected to various planar shapes of the active area of ​​the circuit element 220 .

[0134] Figure 13 and Figure 14are plan views illustrating various examples of circuit elements connected to a connection contact structure of a semiconductor device according to some embodiments. Figure 13 and Figure 14 The circuit element 220 shown in FIG. 2 may be, for example, a transistor.

[0135] The circuit element 220 includes a circuit element located on the substrate 210 (see Figure 1 ) and a plurality of active regions 221 and 222 on the inner side of the surface of the substrate 210 (see Figure 1 ) and a peripheral circuit gate electrode 226 located between a plurality of active regions 221 and 222. The plurality of active regions 221 and 222 include a first active region 221 and a second active region 222. For example, the first active region 221 may be a source region, and the second active region 222 may be a drain region. As another example, the first active region 221 may be a drain region, and the second active region 222 may be a source region.

[0136] Reference Figure 13 , the first to fifth connection contacts CT1, CT2, CT3, CT4, and CT5 may be connected to the first active region 221, and the sixth to tenth connection contacts CT6, CT7, CT8, CT9, and CT10 may be connected to the second active region 222. The first to fifth connection contacts CT1, CT2, CT3, CT4, and CT5 may be connection contacts to which the same voltage is applied. The sixth to tenth connection contacts CT6, CT7, CT8, CT9, and CT10 may be connection contacts to which the same voltage is applied. Different voltages may be applied to the first to fifth connection contacts CT1, CT2, CT3, CT4, and CT5 and the sixth to tenth connection contacts CT6, CT7, CT8, CT9, and CT10.

[0137] Reference Figure 13 In a plan view, at least one active region among the plurality of active regions 221 and 222 may have a quadrilateral shape with at least one corner being chamfered. According to some embodiments, the planar shape of at least one active region among the plurality of active regions 221 and 222 whose influence on the electrical characteristics or performance of the circuit element 220 is lower than a specified level may be a quadrilateral shape with at least one corner being chamfered. Figure 13 In an example, the first active region 221 may have a quadrilateral shape with at least one corner being chamfered, and the second active region 222 may have a quadrilateral shape. In this case, the first active region 221 may have a smaller influence on the electrical characteristics or performance of the circuit element 220 than the second active region 222.

[0138] However, the embodiment is not limited to Figure 13 In the example shown in FIG, and according to some embodiments, the planar shape of each of the first active region 221 and the second active region 222 may be a quadrilateral shape with at least one corner being chamfered. In addition, the number and area of ​​the chamfered corners of each active region may be changed in various ways.

[0139] According to some embodiments, the area of ​​the active region may be small compared to a comparative example in which the planar shape of the active region is a quadrilateral shape with no chamfered corners. When the area of ​​the active region is small, the junction capacitance of the circuit element 220 may be reduced.

[0140] according to Figure 14 The embodiment shown in Figure 13 In the embodiment shown in FIG, the circuit element 220 includes a circuit element 220 located on a substrate (e.g., Figure 1 The first substrate 210 has a plurality of active regions 221 and 222 on the inner side of the surface thereof, and a plurality of active regions 221 and 222 on the inner side of the surface of the first substrate 210 (see Figure 1 ) is formed between a plurality of active regions 221 and 222 on the peripheral circuit gate electrode 226. The plurality of active regions 221 and 222 include a first active region 221 and a second active region 222.

[0141] Reference Figure 14 , the first connection contact CT1 and the second connection contact CT2 may be connected to the first active region 221, and the third to seventh connection contacts CT3, CT4, CT5, CT6, and CT7 may be connected to the second active region 222. The first connection contact CT1 and the second connection contact CT2 may be connection contacts to which the same voltage is applied. The third to seventh connection contacts CT3, CT4, CT5, CT6, and CT7 may be connection contacts to which the same voltage is applied. Different voltages may be applied to the first connection contact CT1 and the second connection contact CT2 and the third to seventh connection contacts CT3, CT4, CT5, CT6, and CT7.

[0142] In a plan view, the first and second connection contacts CT1 and CT2 may have a shape extending along the direction (X direction) in which the peripheral circuit gate electrode 226 extends, but are not limited thereto, and the planar shape of each of the first to seventh connection contacts CT1, CT2, CT3, CT4, CT5, CT6, and CT7 may be changed in various ways.

[0143] according to Figure 14 The embodiment shown in Figure 13, at least one active region among the plurality of active regions 221 and 222 may include a concave portion RC on an edge in a plan view. According to some embodiments, at least one active region among the plurality of active regions 221 and 222 whose influence on the electrical characteristics or performance of the circuit element 220 is lower than a specified level may include a concave portion RC on an edge in a plan view. Figure 14 In the example shown, the first active region 221 includes a concave portion RC on the edge, and the second active region 222 does not include a concave portion RC on the edge. In this case, the first active region 221 may have a smaller influence on the electrical characteristics or performance of the circuit element 220 than the second active region 222.

[0144] However, the embodiment is not limited to Figure 14 , and according to some embodiments, in a plan view, the first active region 221 and the second active region 222 may each include a concave portion RC on an edge. In addition, the number and shape of the concave portion RC included in each active region may be changed in various ways.

[0145] According to some embodiments, the area of ​​the active region may be small. When the area of ​​the active region is small, the junction capacitance of the circuit element 220 may be reduced.

[0146] However, the embodiment is not limited to Figure 13 and Figure 14 According to some embodiments, in a plan view, at least one active region among the plurality of active regions 221 and 222 of the circuit element 220 may have a quadrilateral shape with at least one corner being chamfered, and may include a concave portion RC on an edge.

[0147] In the following, reference is made to Figures 15 to 18 , various structures of a wire of each of the plurality of connection wire layers CW connected by the connection contact structure CC of the semiconductor device 10 will be described.

[0148] Figure 15 and Figure 17 is a perspective view illustrating various line structures of a connection line layer connected by a connection contact structure of a semiconductor device according to some embodiments. Figure 16 and Figure 18 is a plan view illustrating various line structures of a connection line layer connected by a connection contact structure of a semiconductor device according to some embodiments.

[0149] Figures 15 to 18 The connection line layer CW shown in FIG may be the lower connection line layer 250 (see Figure 1 ) or upper connection line layer 160 (see Figure 1 For convenience, Figures 15 to 18Only one connection line layer CW is shown, but the contents to be described later can be applied to the connection line layer CW with the substrate 210 (see FIG. Figure 1 Each of the plurality of connection line layers CW spaced apart in a direction (Z direction) perpendicular to the upper surface of the substrate 210 (see Figure 1 ) in a direction (Z direction) perpendicular to the upper surface of the substrate 210 (see Figure 1 ) extend in directions parallel to the upper surface of the PCB but perpendicular to each other. That is, in a plan view, the lines of the plurality of connection line layers CW may have a grid shape.

[0150] Reference Figures 15 to 18 , the connection line layer CW includes a connection line layer arranged to be connected to the substrate 210 (see Figure 1 ) is provided with a plurality of lines L1 and L2 spaced apart from each other in a first direction DR1 parallel to an upper surface of the PCB. Each of the plurality of lines L1 and L2 may extend in a second direction DR2 perpendicular to the first direction DR1. For example, the first direction DR1 may be Figure 1 Y direction, and the second direction DR2 can be Figure 1 The first direction DR1 and the second direction DR2 are not necessarily limited thereto. The plurality of lines include a first line L1 and a second line L2 adjacent to each other in the first direction DR1. Figures 15 to 18 Only two adjacent lines are shown, but it is not limited thereto, and the connection line layer CW may include more lines.

[0151] For example, the first connection contact CT1 and the second connection contact CT2 may be connected to the first wire L1, and the third connection contact CT3 and the fourth connection contact CT4 may be connected to the second wire L2. The first wire L1 may be connected to the substrate 210 (see FIG. 1 ) through the first connection contact CT1 and the second connection contact CT2. Figure 1 ) in the direction perpendicular to the upper surface (Z direction) Figure 15 and Figure 16 The second line L2 can be connected to the substrate 210 (see FIG. 1 ) through the third connection contact CT3 and the fourth connection contact CT4. Figure 1 ) in the direction perpendicular to the upper surface (Z direction) Figure 15 and Figure 16 The first and second lines L1 and L2 may be connected in another connection line layer CW.

[0152] according to Figure 15 and Figure 16In the embodiment shown in , the first line L1 includes a first portion L1_1 and a second portion L1_2 that are separated from each other. The first line L1 includes a first separated portion L1_P between the first portion L1_1 and the second portion L1_2. The first separated portion L1_P may overlap the second line L2. In this case, the area of ​​the first and second lines L1 and L2 facing each other in the first direction DR1 may correspond to (d1+d2). According to some technologies in which the first line L1 is not separated but extends parallel to the second line L2, the area of ​​the first and second lines L1 and L2 facing each other in the first direction DR1 may correspond to d0. In contrast, according to some embodiments, the area of ​​the first and second lines L1 and L2 facing each other in the first direction DR1 may be reduced.

[0153] according to Figure 17 and Figure 18 In the embodiment shown in , the first line L1 includes a first portion L1_1 and a second portion L1_2 separated from each other, and the second line L2 includes a third portion L2_1 and a fourth portion L2_2 separated from each other. The first line L1 may include a first separated portion L1_P between the first and second portions L1_1 and L1_2. The second line L2 may include a second separated portion L2_P between the third and fourth portions L2_1 and L2_2. The first separated portion L1_P between the first and second portions L1_1 and L1_2 may not overlap with the second separated portion L2_P between the third and fourth portions L2_2 in the first direction DR1. In this case, the area of ​​the first and second lines L1 and L2 facing each other in the first direction DR1 may correspond to (d3+d4+d5).

[0154] According to some technologies in which the first line L1 and the second line L2 are not separated but extend parallel to each other, the area in which the first line L1 and the second line L2 face each other in the first direction DR1 may correspond to d0. In contrast, according to some embodiments, the area in which the first line L1 and the second line L2 face each other in the first direction DR1 may be reduced. In addition, according to Figure 17 and Figure 18 The embodiment shown in Figure 15 and Figure 16 Compared with the embodiment of FIG. 5 , the area in which the first line L1 and the second line L2 face each other in the first direction DR1 may be further reduced.

[0155] In the following, reference is made to Figure 19 , a semiconductor device according to some embodiments will be described.

[0156] Figure 19 is a cross-sectional view illustrating a semiconductor device according to some embodiments.

[0157] because Figure 19The embodiment shown in FIG has many Figures 1 to 4 The same parts as those of the embodiment shown in FIG. 1 are omitted from the description of the same parts, and the differences will be mainly explained. In addition, the same reference numerals are used for the same components as those of the previous embodiment.

[0158] Reference Figure 19 According to some embodiments, the semiconductor device 20 has a chip-to-chip (C2C) structure bonded using a wafer bonding method. That is, a lower chip including the circuit region 200 a and an upper chip including the cell region 100 a may be manufactured, and then the lower chip and the upper chip may be bonded to form the semiconductor device 20 .

[0159] The circuit region 200a may be provided with a first substrate 210a, a circuit element 220, a first wiring portion 230, and a first bonding structure 238. The first bonding structure 238 is electrically connected to the first wiring portion 230 and is located on a surface facing the cell region 100a. On the surface facing the cell region 100a, the area other than the first bonding structure 238 may be covered by a first bonding portion insulating layer 240.

[0160] The cell region 100a may be provided with a second substrate 110a, a gate stack structure 120, a channel structure CH, a second wiring portion 190, and a second bonding structure 198 electrically connected to the second wiring portion 190 and located on a surface facing the circuit region 200a. The region other than the second bonding structure 198 may be covered by a second bonding portion insulating layer 199.

[0161] The second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate made of a semiconductor material, and may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the second substrate 110a may be formed of single crystal silicon or polycrystalline silicon, germanium, silicon germanium, silicon on insulator, germanium on insulator, etc. Alternatively, the second substrate 110a may be configured as a support member including an insulating layer or insulating material. This is because, after the cell region 100a is bonded to the circuit region 200a, the semiconductor substrate provided in the cell region 100a may be removed, and a support member including an insulating layer or insulating material may be formed.

[0162] In some embodiments, the gate stack structure 120 may be sequentially stacked in a lower portion of the second substrate 110a in the drawing, and may be disposed at Figure 1 In the structure where the gate stack structure 120 is inverted as shown in FIG. In addition, the channel structure CH penetrating the gate stack structure 120 may also be arranged Figure 1In the structure in which the gate stack structure 120 is inverted as shown in FIG. Due to this, in cross section, the channel structure CH may have an inclined side surface such that the width narrows from the circuit region 200 a toward the second substrate 110 a. In addition, the channel pad 144 and the second wiring portion 190 located on the gate stack structure 120 may be positioned adjacent to the circuit region 200 a.

[0163] For example, the first bonding structure 238 and / or the second bonding structure 198 may be formed of aluminum, copper, tungsten, or alloys thereof. For example, the first bonding structure 238 and the second bonding structure 198 may include copper, so that the cell region 100a and the circuit region 200a may be bonded by copper-to-copper bonding (e.g., bonded in direct contact).

[0164] In addition to those described individually, the above references also apply Figures 1 to 4 The structures of the gate stack structure 120 and the channel structure CH are described. Figure 19 The electrical connection structure between the channel structure CH and the second substrate 110a is shown. Figure 2 and Figure 3 The embodiment is not limited thereto, and the electrical connection structure between the channel structure CH and the second substrate 110a may be changed in various ways.

[0165] The semiconductor device 20 according to the example may include an input / output pad and an input / output connection line electrically connected thereto. The input / output connection line may be electrically connected to a portion of the second bonding structure 198. For example, the input / output pad may be located on the insulating layer 198b covering the outer surface of the second substrate 110a. Depending on the embodiment, a separate input / output pad electrically connected to the circuit region 200a may be provided.

[0166] As an example, the circuit region 200a and the cell region 100a may be respectively connected to the circuit region 200a and the cell region 100a. Figure 20 1 and 10. The first and second structures 1100F and 1100S of the semiconductor device 1100 in the electronic system 1000 are shown in FIG. Figure 23 4 , corresponding portions of the first structure 4100 and the second structure 4200 of the semiconductor chip 2200 a are shown.

[0167] In the following, reference is made to Figure 20 and Figure 21 , an electronic system including a semiconductor device according to some embodiments will be described.

[0168] Figure 20 is a diagram schematically illustrating an electronic system including a semiconductor device according to some embodiments.

[0169] Reference Figure 20 According to some embodiments, an electronic system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device or an electronic device including a storage device, the electronic device including one or more semiconductor devices 1100. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0170] The semiconductor device 1100 may be a nonvolatile memory device, and for example, may be the one described above with reference to FIG. Figures 1 to 4 The NAND flash memory device described above, or Figure 19 The NAND flash memory device described herein includes a second structure 1100S and a first structure 1100F on a first structure 1100F. In some embodiments, the first structure 1100F and the second structure 1100S may be arranged side by side. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0171] In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied in various ways depending on the embodiment.

[0172] In some embodiments, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0173] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 within the first structure 1100F via first connection lines 1115 extending to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer 1120 within the first structure 1100F via second connection lines 1125 extending to the second structure 1100S.

[0174] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one memory cell transistor selected from a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 in the first structure 1100F through an input / output connection line 1135 extending to the second structure 1100S.

[0175] The controller 1200 includes a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to an embodiment, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0176] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to preset firmware and access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 includes a NAND interface 1221 configured to handle communications with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data written to and read from memory cell transistors MCT of semiconductor device 1100, and the like can be transmitted via NAND interface 1221. Host interface 1230 can provide communication functionality between electronic system 1000 and an external host. Upon receiving a control command from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0177] Figure 21 is a perspective view schematically illustrating an electronic system including a semiconductor device according to some embodiments.

[0178] Reference Figure 21An electronic system 2000 according to some embodiments includes a main substrate 2001, and a controller 2002, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004 mounted on the main substrate 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a line pattern 2005 formed in the main substrate 2001.

[0179] Main substrate 2001 includes a connector 2006 containing multiple pins for coupling to an external host. The number and arrangement of the multiple pins in connector 2006 may vary depending on the communication interface between electronic system 2000 and the external host. In some embodiments, electronic system 2000 may communicate with the external host using one of the interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), and the like. In some embodiments, electronic system 2000 may operate using power supplied from the external host via connector 2006. Electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to controller 2002 and semiconductor package 2003.

[0180] The controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003 and may increase the operating speed of the electronic system 2000 .

[0181] DRAM (2004) can be a buffer memory to mitigate the speed difference between the semiconductor package (2003) and an external host, which serves as a data storage space. DRAM 2004 included in electronic system 2000 can also operate as a high-speed cache memory and can provide space for temporarily storing data during control operations of semiconductor package 2003. When DRAM 2004 is included in electronic system 2000, controller 2002 can also include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0182] The semiconductor package 2003 includes a first semiconductor package 2003a and a second semiconductor package 2003b that are spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chips 2200 on the package substrate 2100 and the connection structure 2400.

[0183] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 includes an input / output pad 2210. The input / output pad 2210 may correspond to Figure 20 Each semiconductor chip 2200 includes a gate stack structure 3210 and a channel structure 3220. The semiconductor chips 2200 may include the gate stack structure 3210 and the channel structure 3220. Figures 1 to 4 The semiconductor device described above or with reference to Figure 20 A semiconductor device is described.

[0184] In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a connection structure including a through-silicon via (TSV, or through-silicon via) instead of the bonding wire method.

[0185] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via wires formed on the interposer.

[0186] Figure 22 and Figure 23 are cross-sectional views each schematically illustrating a semiconductor package according to some embodiments. Figure 22 and Figure 23 Can be shown separately Figure 21 Implementation of the semiconductor package 2003 and may conceptually represent Figure 21 A cross-sectional area of ​​the semiconductor package 2003 taken along II'.

[0187] Reference Figure 22 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate main body 2120, a package upper pad 2130 disposed on the upper surface of the package substrate main body 2120, a package lower pad 2125 disposed on the lower surface of the package substrate main body 2120 or exposed through the lower surface, and an internal wire 2135 electrically connecting the package upper pad 2130 and the package lower pad 2125 within the package substrate main body 2120. The package upper pad 2130 may be electrically connected to the connection structure 2400. The package lower pad 2125 may be connected to the conductive connection portion 2800, such as Figure 21 2005 of a main substrate 2001 of an electronic system 2000 is shown in FIG.

[0188] The semiconductor chip 2200 includes a first structure 3100 and a second structure 3200 sequentially stacked on a semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral line 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line electrically connected to the gate stack structure 3210 (see FIG. 2 ). Figure 20 The gate connection line is marked with the reference numeral WL).

[0189] The semiconductor chip 2200 or the semiconductor device according to some embodiments includes a dummy contact structure DC adjacent to the connection contact structure CC and having a lower dielectric constant than the connection contact structure CC, and thus, parasitic capacitance of the connection contact structure CC in a direction parallel to the upper surface of the first substrate 210 can be reduced.

[0190] Each semiconductor chip 2200 includes a penetration wire 3245 electrically connected to the peripheral line 3110 of the first structure 3100 and extending into the second structure 3200. The penetration wire 3245 may penetrate the gate stack structure 3210 and may also be disposed on the outer side of the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output connection wire 3265 electrically connected to the peripheral line 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connection wire 3265.

[0191] In some embodiments, in the semiconductor package 2003, the plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 in the form of bonding wires. As another example, the plurality of semiconductor chips 2200 or a plurality of parts constituting the same may be electrically connected via a connection structure including through silicon vias (TSVs).

[0192] Reference Figure 23 In the semiconductor package 2003A, each semiconductor chip 2200 a includes a semiconductor substrate 4010 , a first structure 4100 on the semiconductor substrate 4010 , and a second structure 4200 bonded to the first structure 4100 by a wafer bonding method on the first structure 4100 .

[0193] The first structure 4100 includes a peripheral line 4110 and a peripheral circuit region including a first bonding structure 4150. The second structure 4200 includes a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 penetrating the gate stack structure 4210, and word lines electrically connected to the channel structure 4220 and the gate stack structure 4210 (see FIG. 4 ). Figure 20 The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be bonded to each other in contact. The bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be formed of, for example, copper (Cu).

[0194] The semiconductor chip 2200a or the semiconductor device according to some embodiments includes a dummy contact structure DC adjacent to the connection contact structure CC and having a lower dielectric constant than the connection contact structure CC, and thus, parasitic capacitance of the connection contact structure CC in a direction parallel to the upper surface of the first substrate 210 can be reduced.

[0195] Each semiconductor chip 2200a may further include an input / output pad 2210 and an input / output connection line 4265 under the input / output pad 2210. The input / output connection line 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0196] In some embodiments, in the semiconductor package 2003A, the plurality of semiconductor chips 2200a may be electrically connected to each other via a connection structure 2400 in the form of bonding wires. As another example, the plurality of semiconductor chips 2200a or portions thereof may be electrically connected via a connection structure including through silicon vias.

[0197] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the possible claims. Specific features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable subcombination. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be deleted from the combination in some cases, and a combination may refer to a subcombination or a variant of a subcombination.

[0198] While the disclosure has been described in connection with what are presently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: substrate; The circuit elements and the wiring portion are provided on the substrate; A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a wiring portion; a channel structure extending through the gate stack structure; an upper insulating layer covering an upper surface of the wiring portion and the gate stack structure; a connecting contact structure extending through the upper insulating layer outside the gate stack structure and connected to the circuit element; as well as The dummy contact structure is disposed adjacent to the connecting contact structure and has a lower dielectric constant than that of the connecting contact structure.

2. The semiconductor device according to claim 1, wherein The dummy contact structure is floating.

3. The semiconductor device according to claim 2, wherein: The connection contact structure includes: a connection contact connecting a plurality of connection line layers, the plurality of connection line layers being located in upper and lower portions of the upper insulating layer in a direction perpendicular to the upper surface of the substrate; and The dummy contact structure includes a dummy contact overlapping the connection contact in a direction parallel to the upper surface of the substrate.

4. The semiconductor device according to claim 3, wherein Dummy contacts include: a cover layer comprising the same material as the connecting contact; and Air gap, located within the cover layer.

5. The semiconductor device according to claim 3, wherein: The dummy contact has the same cross-sectional shape as the connecting contact; and The dummy contact includes a material having a lower dielectric constant than the connecting contact.

6. The semiconductor device according to claim 3, in, The plurality of connection line layers include: a plurality of lower connection line layers located in the lower portion of the upper insulating layer; and a plurality of upper connection line layers located in the upper portion of the upper insulating layer. The connecting contact includes: a lower contact connecting at least one of: the plurality of lower connection line layers; and the lower connection line layer and the circuit element; an upper contact connecting the plurality of upper connection line layers; and a through contact connecting the lower connection line layer and the upper connection line layer by extending through the upper insulating layer, and The dummy contact overlaps the through contact in a direction parallel to the upper surface of the substrate.

7. The semiconductor device according to claim 6, wherein The dummy contact also overlaps at least one of the upper contact and the lower contact in a direction parallel to the upper surface of the substrate.

8. The semiconductor device according to claim 3, in, The plurality of connection line layers include: a plurality of lower connection line layers located in the lower portion of the upper insulating layer; and a plurality of upper connection line layers located in the upper portion of the upper insulating layer. The connecting contact includes: a lower contact member, connecting the plurality of lower connection line layers to each other, or connecting the plurality of lower connection line layers to a circuit element; upper contacts connecting the plurality of upper connection line layers to each other; and a through contact extending through the upper insulating layer and connecting the lower connection line layer and the upper connection line layer, and The dummy contact overlaps with at least one of the upper contact and the lower contact in a direction parallel to the upper surface of the substrate.

9. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plurality of dummy contact structures; and The plurality of dummy contact structures are arranged around the connecting contact structure.

10. The semiconductor device according to claim 9, wherein A first dummy contact structure of the plurality of dummy contact structures is disposed on a first side of the connecting contact structure, and a second dummy contact structure of the plurality of dummy contact structures is disposed on an opposite side of the connecting contact structure.

11. The semiconductor device according to claim 1, wherein Circuit components include: a plurality of active regions located on the inner side of the surface of the substrate; and a peripheral circuit gate electrode located between the plurality of active regions on the substrate, Wherein, at least one active region among the plurality of active regions has a quadrilateral shape, and wherein at least one corner of the quadrilateral shape is chamfered.

12. The semiconductor device according to claim 1, wherein Circuit components include: a plurality of active regions located on the inner side of the surface of the substrate; and a peripheral circuit gate electrode located between the plurality of active regions on the substrate, At least one active region among the plurality of active regions includes a recess on an edge.

13. The semiconductor device according to claim 1, further comprising a connection line layer, wherein: The connection line layer includes a plurality of lines spaced apart from each other in a first direction parallel to the upper surface of the substrate; The plurality of lines include: a first line; and a second line adjacent to the first line in a first direction; and The first line includes a first portion and a second portion that are separated from each other.

14. The semiconductor device according to claim 13, wherein: The second line includes a third portion and a fourth portion that are separated from each other; and A first separated portion between the first portion and the second portion does not overlap with a second separated portion between the third portion and the fourth portion in the first direction.

15. A semiconductor device comprising: substrate; The circuit elements and the wiring portion are provided on the substrate; A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a wiring portion; a channel structure extending through the gate stack structure; an upper insulating layer covering an upper surface of the wiring portion and the gate stack structure; a connecting contact structure extending through the upper insulating layer outside the gate stack structure and connected to the circuit element; as well as The dummy contact structure is disposed adjacent to the connecting contact structure and includes a material different from that of the connecting contact structure.

16. The semiconductor device according to claim 15, wherein: The connection contact structure includes: a connection contact connecting a plurality of connection line layers, the plurality of connection line layers being located in an upper portion and a lower portion of the upper insulating layer in a direction perpendicular to an upper surface of the substrate; The dummy contact structure includes a dummy contact overlapping the connection contact in a direction parallel to the upper surface of the substrate; and The dummy contact structure is floating.

17. The semiconductor device according to claim 16, wherein Dummy contacts include: a cover layer comprising the same material as the connecting contacts, and Air gap, surrounded by the cover layer.

18. The semiconductor device according to claim 16, in, The plurality of connection line layers include: a plurality of lower connection line layers located in the lower portion of the upper insulating layer; and a plurality of upper connection line layers located in the upper portion of the upper insulating layer. The connecting contact includes: a lower contact member, connecting the plurality of lower connection line layers to each other, or connecting the plurality of lower connection line layers to a circuit element; an upper contact connecting the plurality of upper connection line layers; and a through contact extending through the upper insulating layer and connecting the lower connection line layer and the upper connection line layer, The dummy contact overlaps the through contact in a direction parallel to the upper surface of the substrate.

19. The semiconductor device according to claim 18, wherein The dummy contact also overlaps at least one of the upper contact and the lower contact in a direction parallel to the upper surface of the substrate.

20. An electronic system comprising: main base; a semiconductor device on a main substrate; as well as a controller electrically connected to the semiconductor device on the main substrate, The semiconductor device includes: semiconductor substrates; The circuit elements and the wiring portion are provided on the semiconductor substrate; A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a wiring portion; a channel structure extending through the gate stack structure; an upper insulating layer covering an upper surface of the wiring portion and the gate stack structure; a connecting contact structure extending through the upper insulating layer outside the gate stack structure and connected to the circuit element; and The dummy contact structure is disposed adjacent to the connecting contact structure and has a lower dielectric constant than the connecting contact structure.

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