Semiconductor memory device and manufacturing method thereof

Abstract

The invention provides a semiconductor memory device and a manufacturing method thereof, which can be applied to the technical field of semiconductors. The semiconductor memory device includes: a semiconductor-on-insulator (SOI) substrate including an active region; the gate structure is arranged on the SOI substrate and intersected with the active region, and comprises a first gate electrode and a second gate electrode which are sequentially arranged in the first direction; the source electrode and the drain electrode are located on the two opposite sides of the gate structure in the first direction respectively on the active region, the active region comprises a channel region between the source electrode and the drain electrode, the channel region, the source electrode and the drain electrode have doping of the same conduction type, the length of the first gate electrode in the first direction is larger than that of the second gate electrode in the first direction, and the first gate electrode is located between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode each comprise a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer comprises a ferroelectric material.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a ferroelectric-assisted junction-less semiconductor memory device and a manufacturing method thereof. Background Art

[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory with advantages such as high density, low power consumption, fast read / write speeds, and good scalability. It uses a resistance switching mechanism, changing the material's resistance state via an applied voltage to store data. However, practical applications of RRAM devices still face challenges with reliability, resistance uniformity, and thermal effects. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor memory device and a method for manufacturing the same.

[0004] One aspect of the present disclosure provides a semiconductor memory device, including:

[0005] a semiconductor-on-insulator (SOI) substrate, including an active region;

[0006] A gate structure intersecting the active region on the SOI substrate includes a first gate electrode and a second gate electrode sequentially arranged in a first direction; and

[0007] a source electrode and a drain electrode on the active region and located on opposite sides of the gate structure in a first direction,

[0008] The active region includes a channel region between the source and the drain, and the channel region has the same conductive type of doping as the source and the drain.

[0009] The length of the first gate electrode in the first direction is greater than that of the second gate electrode in the first direction. The first gate electrode and the second gate electrode each include a gate dielectric layer and a gate conductor layer on the gate dielectric layer. The gate dielectric layer includes a ferroelectric material.

[0010] According to an embodiment of the present disclosure, a semiconductor memory device is configured to implement storage of information based on polarization states of ferroelectric materials in first and second gate electrodes.

[0011] According to an embodiment of the present disclosure, a semiconductor memory device is configured to read information stored in the semiconductor memory device based on a resistance value between a source and a drain.

[0012] According to an embodiment of the present disclosure, when the ferroelectric material in the first gate electrode and the ferroelectric material in the second gate electrode are both in the first polarization state, the resistance between the source and the drain is a first resistance value;

[0013] When the ferroelectric material in the first gate electrode is in a first polarization state and the ferroelectric material in the second gate electrode is in a second polarization state, the resistance between the source and the drain is a second resistance value;

[0014] When the ferroelectric material in the first gate electrode is in the second polarization state and the ferroelectric material in the second gate electrode is in the first polarization state, the resistance between the source and the drain is a third resistance value,

[0015] When the ferroelectric material in the first gate electrode and the ferroelectric material in the second gate electrode are both in the second polarization state, the resistance between the source and the drain is a fourth resistance value.

[0016] According to an embodiment of the present disclosure, the ferroelectric material includes hafnium oxide doped with a target element, the target element including at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

[0017] According to an embodiment of the present disclosure, the source and drain respectively include p-type heavily doped regions on both sides of the gate structure in the SOI layer, and the channel region includes a p-type lightly doped region in the SOI layer.

[0018] The semiconductor memory device further includes: p-type heavily doped regions in the SOI layer respectively between the first gate electrode and the second gate electrode.

[0019] According to an embodiment of the present disclosure, a semiconductor memory device is configured as follows:

[0020] When the source, the drain, and the body region are grounded, a programming or erasing operation is performed by applying bias voltages to the first gate electrode and the second gate electrode respectively; and

[0021] A read operation is performed by applying a fixed voltage to the drain and sensing the drain current with the source, the body, the first gate electrode, and the second gate electrode grounded.

[0022] According to an embodiment of the present disclosure, the gate structure also includes a third gate electrode, the length of the third gate electrode in the first direction is different from the length of the first gate electrode in the first direction and the length of the second gate electrode in the first direction, the third gate electrode includes a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer includes a ferroelectric material.

[0023] According to an embodiment of the present disclosure, an SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer, the SOI layer having a thickness that achieves a fully depleted condition.

[0024] According to an embodiment of the present disclosure, the channel region has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the first gate electrode in the portion corresponding to the first gate electrode and thus causes a corresponding resistance value, and has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the second gate electrode in the portion corresponding to the second gate electrode and thus causes a corresponding resistance value.

[0025] Another aspect of the present disclosure provides a method for manufacturing a semiconductor memory device, comprising:

[0026] A gate structure is formed on a semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate includes an active region. The gate structure is formed to intersect the active region and includes a first gate electrode and a second gate electrode sequentially arranged in a first direction, wherein a length of the first gate electrode in the first direction is greater than a length of the second gate electrode in the first direction, and each of the first gate electrode and the second gate electrode includes a gate dielectric layer and a gate conductor layer on the gate dielectric layer, wherein the gate dielectric layer includes a ferroelectric material.

[0027] A source electrode and a drain electrode are formed on opposite sides of the gate structure in the first direction of the active region, respectively.

[0028] The active region includes a channel region between the source and the drain, and the channel region has the same conductive type of doping as the source and the drain.

[0029] According to an embodiment of the present disclosure, forming a gate structure includes:

[0030] forming a first sacrificial gate and a second sacrificial gate sequentially arranged in a first direction on the SOI substrate, wherein a length of the first sacrificial gate in the first direction is greater than a length of the second sacrificial gate in the first direction;

[0031] forming sidewall spacers on sidewalls of the first sacrificial gate and the second sacrificial gate;

[0032] The first sacrificial gate and the second sacrificial gate are replaced with a first gate electrode and a second gate electrode, respectively.

[0033] According to an embodiment of the present disclosure, forming a first sacrificial gate and a second sacrificial gate includes:

[0034] forming a first preliminary sacrificial gate on the SOI substrate;

[0035] forming a first hard mask on the first preliminary sacrificial gate, the first hard mask comprising a stack of a first oxide layer, a first nitride layer, and a second oxide layer;

[0036] patterning the second oxide layer into a pattern corresponding to the first sacrificial gate;

[0037] forming a third oxide layer and a second preliminary sacrificial gate on the first nitride layer having the patterned second oxide layer thereon, thereby obtaining a second hard mask;

[0038] Using the film layer having the pattern corresponding to the second sacrificial gate as a mask, patterning the second hard mask to obtain a pattern corresponding to the first sacrificial gate and a pattern corresponding to the second sacrificial gate; and

[0039] The patterned second hard mask is used as an etching mask to pattern the first preliminary sacrificial gate to obtain a first sacrificial gate and a second sacrificial gate respectively.

[0040] According to an embodiment of the present disclosure, the above method further includes:

[0041] Using the first sacrificial gate, the second sacrificial gate and the sidewall as masks, p-type dopants are implanted into the SOI substrate.

[0042] According to an embodiment of the present disclosure, since the length of the first gate electrode G1 in the first direction is greater than the length of the second gate electrode G2 in the first direction, ferroelectric polarization will cause the channel to be fully depleted or accumulated, resulting in the channel exhibiting different resistance values, which can be read through the resistance change between the source 130 and the drain 140, avoiding charge injection caused by reading through the gate voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0044] Figure 1A Schematically shows a structural diagram of a semiconductor memory device according to an embodiment of the present disclosure;

[0045] Figure 1B Schematically shows a principle diagram of a semiconductor memory device according to an embodiment of the present disclosure;

[0046] Figures 2 to 12 Some stages in a process of manufacturing a semiconductor memory device according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0048] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0049] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0050] The resistance switching mechanism of RRAM devices relies on the formation and rupture of conductive filaments, a process that can lead to device failure and compromise reliability. In large-scale integration, the resistance switching behavior of RRAM devices can be non-uniform, resulting in performance fluctuations. Joule heating generated during the resistance switching process can cause localized temperature increases, generating thermal effects and accelerating material degradation.

[0051] The main problem with ferroelectric transistors (FeFETs) is durability: the storage window of FeFETs decreases during repeated programming and erasing operations. This is because the interface electric field is too high, which leads to an increase in interface traps, further accelerating charge capture, resulting in polarization reversal domain pinning and more severe fatigue behavior. To this end, interface optimization, such as interface nitridation to improve interface quality or increasing interface thickness to reduce the risk of breakdown, is the main solution to improve durability. However, interface nitridation requires high-temperature annealing, and increasing interface thickness increases the equivalent oxide thickness, which reduces the electrical properties of the readout.

[0052] Based on this, the present disclosure provides a semiconductor memory device solution.

[0053] Figure 1A The figure schematically shows a structural diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0054] like Figure 1A As shown, the semiconductor memory device 100 may include an SOI substrate 110 , a gate structure located on the SOI substrate 110 and intersecting the active region, and a source 130 and a drain 140 located on opposite sides of the gate structure 120 in a first direction on the active region.

[0055] According to an embodiment of the present disclosure, the SOI substrate 110 may include a base substrate 111, a buried oxide layer 112 on the base substrate, and an SOI layer 113 on the buried oxide layer 112. The base substrate 111 may include silicon (Si), the buried oxide layer 112 may include an oxide (e.g., silicon oxide), and the SOI layer 113 may include a suitable semiconductor material, such as the same semiconductor material as the base substrate 111, such as Si, or a semiconductor material different from the base substrate 111, such as SiGe. On the SOI substrate 110, an active region may be defined by, for example, local oxidation of silicon (LOCOS). The SOI layer may have a thickness sufficient to achieve full depletion.

[0056] According to an embodiment of the present disclosure, the gate structure 120 includes a first direction (eg, Figure 1A A first gate electrode G1 and a second gate electrode G2 are sequentially disposed on the substrate (in a direction parallel to the right side of the paper). The length of the first gate electrode G1 in the first direction (favorably parallel to the right side of the straight surface) is greater than the length of the second gate electrode G2 in the first direction. The first gate electrode G1 and the second gate electrode G2 each include a gate dielectric layer and a gate conductor layer on the gate dielectric layer. The gate dielectric layer includes a ferroelectric material. For example, the ferroelectric material includes, but is not limited to, hafnium oxide (HfO2) doped with a target element. The target element includes at least one of silicon (Si), aluminum (Al), zirconium (Zr), yttrium (Y), gadolinium (Gd), lanthanum (La), and strontium (Sr).

[0057] According to an embodiment of the present disclosure, since the length of the first gate electrode G1 in the first direction is greater than the length of the second gate electrode G2 in the first direction, ferroelectric polarization will cause the channel to be fully depleted or accumulated, resulting in the channel exhibiting different resistance values, which can be read through the resistance change between the source 130 and the drain 140, avoiding charge injection caused by reading through the gate voltage.

[0058] According to an embodiment of the present disclosure, the active region includes a channel region between the source 130 and the drain 140 . The channel region and the source 130 and the drain 140 are doped with the same conductivity type, thereby making the semiconductor memory device 100 a junction-less semiconductor memory device.

[0059] According to an embodiment of the present disclosure, the semiconductor memory device 100 is configured to store information based on the polarization state of the ferroelectric material in the first gate electrode G1 and the second gate electrode G2. The semiconductor memory device 100 is configured to read the information stored in the semiconductor memory device 100 based on the resistance value between the source 130 and the drain 140.

[0060] According to an embodiment of the present disclosure, the channel region has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the first gate electrode G1 in the portion corresponding to the first gate electrode G1 and thus causes a corresponding resistance value, and has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the second gate electrode G2 in the portion corresponding to the second gate electrode G2 and thus causes a corresponding resistance value.

[0061] The following combination Figure 1B It is explained how the semiconductor memory device 100 in the embodiment of the present disclosure implements storage and reading of information.

[0062] Figure 1B The schematic diagram of the principle of the semiconductor memory device according to the embodiment of the present disclosure is schematically shown.

[0063] Take a semiconductor memory device being a P-type junctionless device as an example. Figure 1B The downward arrow in the indicates upward polarization, and the upward arrow indicates downward polarization. Figure 1B As shown in (a), a positive voltage may be applied to both the first gate electrode G1 and the second gate electrode G2, so that the ferroelectric material in the first gate electrode G1 and the ferroelectric material in the second gate electrode G2 are both in a first polarization state. The first polarization state may be, for example, in a direction away from the SOI substrate (for example, Figure 1B In this state, the first gate electrode G1 and the second gate electrode G2 are in a depleted state. The channel resistance between the source 130 and the drain 140 can be a first resistance value.

[0064] like Figure 1B As shown in (b), a positive voltage may be applied to the first gate electrode G1 and a negative voltage may be applied to the second gate electrode G2, so that the ferroelectric material in the first gate electrode G1 is in a first polarization state and the ferroelectric material in the second gate electrode G2 is in a second polarization state. The second polarization state may be, for example, in a direction away from the SOI substrate (for example, Figure 1B In this state, the channel region corresponding to the first gate electrode G1 is in a depletion state, and the channel region corresponding to the second gate electrode G2 is in an accumulation state. At this point, the channel resistance between the source 130 and the drain 140 can be a second resistance value.

[0065] like Figure 1BAs shown in (c), a negative voltage can be applied to the first gate electrode G1 and a positive voltage can be applied to the second gate electrode G2, causing the ferroelectric material in the first gate electrode G1 to be in the second polarization state and the ferroelectric material in the second gate electrode G2 to be in the first polarization state. In this case, the channel region corresponding to the first gate electrode G1 is in the accumulation state, while the channel region corresponding to the second gate electrode G2 is in the depletion state. At this point, the channel resistance between the source 130 and the drain 140 can be the third resistance value.

[0066] like Figure 1B As shown in (d), a negative voltage can be applied to both the first gate electrode G1 and the second gate electrode G2, causing the ferroelectric material in the first gate electrode G1 and the ferroelectric material in the second gate electrode G2 to be in the second polarization state. In this case, the channel regions corresponding to the first gate electrode G1 and the second gate electrode G2 are in the accumulation state. In this case, the channel resistance between the source 130 and the drain 140 can be the fourth resistance value.

[0067] According to an embodiment of the present disclosure, the source 130 and drain 140 each comprise a heavily p-type doped region on either side of the gate structure in the SOI layer, and the channel region comprises a lightly p-type doped region in the SOI layer. The semiconductor memory device may further include a heavily p-type doped region in the SOI layer between the first gate electrode G1 and the second gate electrode G2.

[0068] According to an embodiment of the present disclosure, data writing of the semiconductor memory device may be performed by applying bias voltages to the first gate electrode G1 and the second gate electrode G2 respectively when the source 130 , the drain 140 and the body region are grounded, thereby performing programming or erasing operations.

[0069] According to the embodiments of the present disclosure, the drain 140 current can reflect the channel resistance between the source 130 and the drain 140. Therefore, data reading in the semiconductor memory device can be performed by applying a fixed voltage to the drain to sense the drain 140 current when the source 130, the body region, the first gate electrode G1, and the second gate electrode G2 are grounded.

[0070] The gate structure proposed in the present disclosure may further include a third gate electrode, the length of the third gate electrode in the first direction being different from the length of the first gate electrode in the first direction and the length of the second gate electrode in the first direction, the third gate electrode including a gate dielectric layer and a gate conductor layer on the gate dielectric layer, the gate dielectric layer including a ferroelectric material.

[0071] According to an embodiment of the present disclosure, referring to Figure 1B By applying different voltages to the first gate electrode G1 , the second gate electrode G2 , and the third gate electrode, more different resistance values ​​can be presented between the source 130 and the drain 140 .

[0072] According to the embodiments of the present disclosure, the semiconductor memory device of the present disclosure separates programming / erasing and readout, so that they do not share the same gate dielectric-semiconductor interface, thereby alleviating the device fatigue problem caused by charge injection at the common gate dielectric-semiconductor interface during programming / erasing and readout. Unlike traditional resistive random access memory, which forms a conductive filament to change the resistance state, the resistance switching of the junctionless semiconductor memory device of the present disclosure is formed by accumulation and depletion of the channel, which has higher stability and reliability.

[0073] Another aspect of the present disclosure provides a method for manufacturing a semiconductor memory device, comprising: forming a gate structure on an SOI substrate, the SOI substrate including an active area, the gate structure being formed to intersect with the active area and including a first gate electrode and a second gate electrode sequentially arranged in a first direction, wherein a length of the first gate electrode in the first direction is greater than a length of the second gate electrode in the first direction, the first gate electrode and the second gate electrode each including a gate dielectric layer and a gate conductor layer on the gate dielectric layer, the gate dielectric layer including a ferroelectric material; forming a source and a drain on opposite sides of the gate structure in the first direction on the active area, respectively, wherein the active area includes a channel region between the source and the drain, and the channel region has the same conductivity type of doping as the source and the drain.

[0074] According to an embodiment of the present disclosure, forming a gate structure includes: forming a first sacrificial gate and a second sacrificial gate arranged in sequence in a first direction on an SOI substrate, wherein the length of the first sacrificial gate in the first direction is greater than the length of the second sacrificial gate in the first direction; forming sidewalls on the sidewalls of the first sacrificial gate and the second sacrificial gate; and replacing the first sacrificial gate and the second sacrificial gate with a first gate electrode and a second gate electrode, respectively.

[0075] According to an embodiment of the present disclosure, the first gate electrode and the second gate electrode may be formed by photolithography machines with different precisions, or may be formed by a photolithography machine with the same relatively high precision.

[0076] According to an embodiment of the present disclosure, forming a first sacrificial gate and a second sacrificial gate includes: forming a first preliminary sacrificial gate on an SOI substrate; forming a first hard mask on the first preliminary sacrificial gate, the first hard mask including a stack of a first oxide layer, a first nitride layer and a second oxide layer; composing the second oxide layer into a pattern corresponding to the first sacrificial gate; forming a third oxide layer and a second preliminary sacrificial gate on the first nitride layer having the patterned second oxide layer thereon, thereby obtaining a second hard mask; using a film layer having a pattern corresponding to the second sacrificial gate as a mask, composing the second hard mask to obtain a pattern corresponding to the first sacrificial gate and a pattern corresponding to the second sacrificial gate; and using the patterned second hard mask as an etching mask, composing the first preliminary sacrificial gate to obtain the first sacrificial gate and the second sacrificial gate, respectively.

[0077] According to an embodiment of the present disclosure, the method may further include: using the first sacrificial gate, the second sacrificial gate, and the spacer as masks, injecting p-type dopants into the SOI substrate.

[0078] The present disclosure may be presented in various forms, some of which are described below. In the following description, reference is made to the selection of various materials. In addition to considering their function (for example, semiconductor materials are used to form active areas and dielectric materials are used to form electrical isolation), the selection of materials also takes into account etching selectivity. In the following description, the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when the following mentions etching a certain material layer, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching can be selective, and the material layer can have etching selectivity relative to other layers exposed to the same etching recipe.

[0079] Figures 2 to 12 Some stages in a process of manufacturing a semiconductor memory device according to an embodiment of the present disclosure are schematically shown.

[0080] like Figure 2 As shown, an SOI substrate 110 is provided. The SOI substrate 110 may include a base substrate 111, a buried oxide layer 112 on the base substrate, and an SOI layer 113 on the buried oxide layer 112. For example, the thickness of the SOI layer 113 may be approximately 10 to 55 nm, and the thickness of the buried oxide layer 112 may be approximately 20 to 145 nm. The SOI layer 113 may be thinned to a thickness of approximately 5 to 15 nm, for example, approximately 1 / 3 of the minimum channel length of the semiconductor memory device, to achieve full depletion.

[0081] like Figure 3 As shown, the active area A1 can be defined in the SOI layer 113 by, for example, using the LOCOS technology. For example, a SiO2 / SiN stack can be used as a hard mask to protect the active area A1, and a furnace oxidation process can be used to fully oxidize the non-active area portion of the SOI layer 113 not covered by the hard mask to serve as isolation between devices.

[0082] A sacrificial gate may be formed on the substrate, particularly an active region defined therein.

[0083] like Figure 4As shown, a gate oxide layer 410, a first preliminary sacrificial gate 420, and a first hard mask 430 can be sequentially formed on the SOI substrate 110, for example, by deposition. For example, the gate oxide layer 410 can include SiO2 with a thickness of approximately 2.5 nm and be formed using an in-situ steam generation (ISSG) process. In this example, since the gate oxide layer 410, the buried oxide layer 112, and the LOCOS isolation are made of the same material (all oxide), they are displayed in the same color in the figure. The first preliminary sacrificial gate 420 can include amorphous silicon and have a thickness of approximately 100 nm. The first hard mask 430 can sequentially include a stack of a first oxide layer 431, a first nitride layer 432, and a second oxide layer 433. The first oxide layer 431 can include SiO2 with a thickness of approximately 10-30 nm, the first nitride layer 432 can include SiN with a thickness of approximately 20-40 nm, and the second oxide layer 433 can include SiO2 with a thickness of approximately 80-100 nm.

[0084] like Figure 5 As shown, the second oxide layer 433 can be patterned into a pattern corresponding to the first sacrificial gate. For example, the second oxide layer 433 can be etched, and the etching can stop at the hard mask nitride layer 432, thereby preliminarily determining the position of the first gate electrode G1.

[0085] like Figure 6 As shown, a third oxide layer 610 (eg, Figure 6 The second hard mask is obtained by forming a second preliminary sacrificial gate 620 (a green area above the middle dotted line portion).

[0086] like Figure 7 As shown, the film layer having the pattern corresponding to the second sacrificial gate is used as a mask to pattern the second hard mask to obtain a pattern corresponding to the first sacrificial gate and a pattern corresponding to the second sacrificial gate.

[0087] like Figure 8 As shown, the first preliminary sacrificial gate is patterned using the patterned second hard mask as an etching mask to obtain a first sacrificial gate 810 and a second sacrificial gate 820 .

[0088] like Figure 9 As shown, a spacer 910 is formed on the sidewalls of the first sacrificial gate 810 and the second sacrificial gate 820 , and p-type dopants are implanted into the SOI substrate using the first sacrificial gate 810 , the second sacrificial gate 820 and the spacer 910 as masks.

[0089] like Figure 10As shown, a filling layer 1010 is formed on the first sacrificial gate 810, the second sacrificial gate 820, and the spacer 910. The filling layer 1010 is planarized, such as by chemical mechanical polishing (CMP), to expose the sacrificial layers within the first sacrificial gate 810 and the second sacrificial gate 820. The filling layer 1010 may comprise SiN. The first sacrificial gate 810 and the second sacrificial gate 820 may be removed by selective wet etching.

[0090] like Figure 11 As shown, the first gate electrode G1 and the second gate electrode G2 are formed in the space released by the removal of the first sacrificial gate 810 and the second sacrificial gate 820. For example, a gate dielectric layer 1110 and a gate conductor layer 1120 can be sequentially formed by deposition. For example, the gate dielectric layer 1110 can include hafnium zirconium oxide (HZO) as a ferroelectric material layer, and the gate conductor layer 1120 can include tungsten (W).

[0091] like Figure 12 As shown, an isolation layer 1210 may be formed on the filling layer 1010, the first gate electrode G1, and the second gate electrode G2. For example, the isolation layer 1210 may be made of SiO2.

[0092] Return Reference Figure 1A Contacts can be formed in isolation layer 1210. For example, contact holes can be formed in isolation layer 1210 using photolithography. A 1-3 nm layer of TiN is grown in the contact hole to act as a diffusion barrier and a seed layer for W growth. A metal layer, which can be 100-300 nm of W, is then formed using chemical vapor deposition (CVD). A planarization process, such as CMP, can be performed, stopping at isolation layer 1210, leaving the diffusion barrier and metal layers within the contact hole. Alternatively, a 20-40 nm layer of TiN can be deposited, followed by photolithography or etching to form the electrode pattern. Figure 1A Only the contacts on the source / drain are schematically shown. Other contacts and interconnects may also be formed.

[0093] The semiconductor memory devices according to the embodiments of the present disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor memory devices, and electronic devices can be constructed from them. Such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and mobile power supplies.

[0094] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0095] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor memory device comprising: A semiconductor-on-insulator SOI substrate, including an active region; A gate structure on the SOI substrate intersecting the active area includes a first gate electrode and a second gate electrode sequentially arranged in a first direction; and a source and a drain located on opposite sides of the gate structure in the first direction on the active region, The active region includes a channel region between the source and the drain, and the channel region has the same conductive type as the source and the drain. The length of the first gate electrode in the first direction is greater than the length of the second gate electrode in the first direction. The first gate electrode and the second gate electrode each include a gate dielectric layer and a gate conductor layer on the gate dielectric layer. The gate dielectric layer includes a ferroelectric material. 2 . The semiconductor memory device according to claim 1 , configured to implement storage of information based on polarization states of ferroelectric materials in the first gate electrode and the second gate electrode. 3 . The semiconductor memory device according to claim 2 , configured to read information stored in the semiconductor memory device based on a resistance value between the source and the drain.

4. The semiconductor memory device according to claim 3, wherein When the ferroelectric material in the first gate electrode and the ferroelectric material in the second gate electrode are both in the first polarization state, the resistance between the source and the drain is a first resistance value; When the ferroelectric material in the first gate electrode is in a first polarization state and the ferroelectric material in the second gate electrode is in a second polarization state, the resistance between the source and the drain is a second resistance value; When the ferroelectric material in the first gate electrode is in the second polarization state and the ferroelectric material in the second gate electrode is in the first polarization state, the resistance between the source and the drain is a third resistance value, When the ferroelectric material in the first gate electrode and the ferroelectric material in the second gate electrode are both in the second polarization state, the resistance between the source and the drain is a fourth resistance value.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein: The ferroelectric material includes hafnium oxide doped with a target element, wherein the target element includes at least one of silicon, aluminum, zirconium, yttrium, gadolinium, lanthanum, and strontium.

6. The semiconductor memory device according to any one of claims 1 to 4, wherein: The source and the drain respectively include p-type heavily doped regions on both sides of the gate structure in the SOI layer, and the channel region includes a p-type lightly doped region in the SOI layer. The semiconductor memory device further includes a heavily p-type doped region in the SOI layer respectively between the first gate electrode and the second gate electrode.

7. The semiconductor memory device according to any one of claims 1 to 4, configured as follows: When the source, the drain, and the body region are grounded, performing a programming or erasing operation by applying bias voltages to the first gate electrode and the second gate electrode respectively; and A read operation is performed by applying a fixed voltage to the drain and sensing a drain current when the source, the body region, the first gate electrode, and the second gate electrode are grounded.

8. The semiconductor memory device according to any one of claims 1 to 4, wherein: The gate structure also includes a third gate electrode, the length of the third gate electrode in the first direction is different from the length of the first gate electrode in the first direction and the length of the second gate electrode in the first direction, the third gate electrode includes a gate dielectric layer and a gate conductor layer on the gate dielectric layer, and the gate dielectric layer includes a ferroelectric material.

9. The semiconductor memory device according to any one of claims 1 to 4, wherein: The SOI substrate includes a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer, wherein the SOI layer has a thickness that realizes a full depletion condition.

10. The semiconductor memory device according to claim 2, wherein The channel region has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the first gate electrode in the part corresponding to the first gate electrode and thus causes a corresponding resistance value, and has a carrier accumulation or depletion state corresponding to the polarization state of the ferroelectric material in the second gate electrode in the part corresponding to the second gate electrode and thus causes a corresponding resistance value.

11. A method for manufacturing a semiconductor memory device, comprising: forming a gate structure on a semiconductor-on-insulator (SOI) substrate, the SOI substrate including an active region, the gate structure being formed to intersect the active region and comprising a first gate electrode and a second gate electrode sequentially arranged in a first direction, wherein a length of the first gate electrode in the first direction is greater than a length of the second gate electrode in the first direction, the first gate electrode and the second gate electrode each comprising a gate dielectric layer and a gate conductor layer on the gate dielectric layer, the gate dielectric layer comprising a ferroelectric material; A source electrode and a drain electrode are formed on opposite sides of the gate structure in the first direction on the active region, respectively. The active region includes a channel region between the source and the drain, and the channel region, the source and the drain are doped with the same conductivity type.

12. The method according to claim 11, wherein Forming the gate structure includes: forming a first sacrificial gate and a second sacrificial gate sequentially arranged in a first direction on the SOI substrate, wherein a length of the first sacrificial gate in the first direction is greater than a length of the second sacrificial gate in the first direction; forming sidewall spacers on sidewalls of the first sacrificial gate and the second sacrificial gate; The first sacrificial gate and the second sacrificial gate are replaced by the first gate electrode and the second gate electrode, respectively.

13. The method according to claim 12, wherein: Forming the first sacrificial gate and the second sacrificial gate includes: forming a first preliminary sacrificial gate on the SOI substrate; forming a first hard mask on the first preliminary sacrificial gate, wherein the first hard mask comprises a stack of a first oxide layer, a first nitride layer, and a second oxide layer; patterning the second oxide layer into a pattern corresponding to the first sacrificial gate; forming a third oxide layer and a second preliminary sacrificial gate on the first nitride layer having the patterned second oxide layer thereon, thereby obtaining a second hard mask; Using a film layer having a pattern corresponding to the second sacrificial gate as a mask, patterning the second hard mask to obtain a pattern corresponding to the first sacrificial gate and a pattern corresponding to the second sacrificial gate; and The first preliminary sacrificial gate is patterned using the patterned second hard mask as an etching mask to obtain the first sacrificial gate and the second sacrificial gate respectively.

14. The method according to claim 12 or 13, further comprising: Using the first sacrificial gate, the second sacrificial gate and the sidewall spacer as masks, p-type dopants are implanted into the SOI substrate.

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