High-voltage fast recovery diode chip and preparation method thereof

Abstract

The invention belongs to the technical field of diodes, and particularly relates to a high-voltage fast recovery diode chip and a preparation method thereof. The high-voltage fast recovery diode chip is composed of two parts of silicon wafers, one part is an anode silicon wafer, an anode P region of the part is provided with a first axial life control region formed by a Pt expansion process, minority carriers injected into the P region can be greatly reduced, and the effects of Irrm and ta are reduced. And a second axial life control region is formed in the intrinsic region above the N region through proton irradiation, so that when the diode reversely recovers to enter an in-vivo unbalanced carrier composite extraction stage, the minority carrier lifetime is shortened, and the reverse recovery time of the device is shortened. Through the formation of the two axial life control regions, the reverse recovery loss of the PIN diode can be greatly reduced, and the junction temperature of the device is not affected. The cathode silicon wafer can be manufactured in an epitaxial mode to form a cathode of a field stop structure (FS) or a buffer layer structure, the two parts of silicon wafers are directly bonded together through silicon, and the finally formed device has high performance and high reliability at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of diodes, and in particular relates to a high-voltage fast recovery diode chip and a preparation method thereof. Background Art

[0002] A PIN diode is a special type of diode consisting of three layers: a P-type semiconductor, an intrinsic semiconductor (I-type), and an N-type semiconductor. PIN diodes exhibit low impedance when forward biased and high impedance when reverse biased, making them widely used in microwave and control circuits.

[0003] As a bipolar device, the minority carrier lifetime of the PIN diode has a significant impact on its reverse recovery characteristics. When the PIN diode is forward-conducting, the P region and N region of the PIN diode will be converted to the intrinsic region (I region) ( Figure 1 ) injects a large number of non-equilibrium carriers (electrons and holes), which form stored charges in the I region, producing a conductivity modulation effect, which reduces the forward voltage drop of the diode. When the diode switches from the forward conduction state to the reverse biased state, these stored non-equilibrium carriers need a certain amount of time to recombine or be swept out of the I region. The minority carrier lifetime refers to the average time that non-equilibrium minority carriers exist in the semiconductor. In PIN diodes, the length of the minority carrier lifetime directly affects the speed of the reverse recovery process. If the minority carrier lifetime is short, then during the reverse recovery process, the stored non-equilibrium carriers can recombine or be swept out of the I region faster, thereby reducing the reverse recovery time. On the contrary, if the minority carrier lifetime is long, then the stored non-equilibrium carriers take longer to recombine or be swept out of the I region, resulting in an increase in the reverse recovery time.

[0004] Conventional minority carrier lifetime control technologies primarily rely on global lifetime control through heavy metal diffusion (Pt or Au) and electron irradiation. Heavy metal diffusion creates a U-shaped distribution within the diode, with higher concentrations in the P and N regions and lower concentrations in the I region. This reduces injection into the P region, effectively shortening the non-equilibrium carrier lifetime. During the diode chip thinning process, the high Pt concentration in the N region is removed without affecting the characteristics. Electron irradiation technology results in uniformly distributed defects within the diode body, with the lifetime of non-equilibrium carriers controlled by the irradiation dose. The resulting defects are distributed throughout the device, requiring increased irradiation doses for high-frequency use. This hardens the reverse recovery waveform and exhibits significant oscillations. The resulting energy level defects are close to the center of the bandgap, significantly increasing the reverse leakage current of the finished device. This can severely affect the junction temperature characteristics of the PIN diode, especially under high-temperature conditions, reducing device reliability. Consequently, devices fabricated using electron irradiation perform poorly in the end-use market.

[0005] Proton and He implantation can precisely control the designated location for minority carrier control, with excellent controllability and repeatability, making them the new favorites in minority carrier lifetime control. However, if proton or He implantation is performed from the front, if it is only in the P region, the effect is basically the same as heavy metal diffusion. If the energy is increased, it will be too close to the PN junction or pass through the PN junction, causing excessive leakage current and making it unusable. Injection from the back below the PN junction is a good option, but because the injection energy of proton and He implantation equipment is controlled by equipment complexity and regulations, there are certain limitations on the depth of the area to be controlled. In particular, for devices with high voltages above 1200V, due to the high breakdown voltage and thick intrinsic region, it is impossible to achieve deep injection from the back, which means that effective minority carrier lifetime control cannot be achieved within the effective area of ​​the intrinsic region (I region). Summary of the Invention

[0006] The purpose of the present invention is to provide a high-voltage fast recovery diode chip and a preparation method thereof.

[0007] The present application provides a method for preparing a high-voltage fast recovery diode chip, comprising: An anode silicon wafer having a first and a second axial lifetime control region is prepared; the first axial lifetime control region is located in the P region, and the second axial lifetime control region is located in the intrinsic region; preparing cathode silicon wafers; Combine the anode silicon wafer and the cathode silicon wafer.

[0008] In one embodiment of the present application, the method for forming the first axial lifetime control region includes: performing Pt expansion processing on a device forming a P-doped active region P region.

[0009] In one embodiment of the present application, the Pt expansion process includes: Sputter a Pt film on the device surface with a thickness of 100 Å to 200 Å; The Pt-Si compound formed on the device surface is diffused through a high-temperature furnace tube to form the first axial lifetime control area.

[0010] In one embodiment of the present application, the method for forming a P-doped active region P region includes: Oxidation and photolithography of the P-implantation area: After cleaning the silicon wafer with N-region and I-region epitaxial growth, it is oxidized to form a field oxide layer on the front of the silicon wafer. Then, the P-implantation window is formed on the front of the silicon wafer through photolithography and etching; P-type impurity ion implantation: Use an ion implanter to implant P-type ions into the active area and the terminal area. The ion implantation energy is 60-150 KeV and the implantation dose is 5E12-5E14. P-impurity push-in: Place the silicon wafer in a high-temperature diffusion furnace to push in P-type impurities, thereby forming a P-doped active area P region with a junction depth of 4 to 6 μm.

[0011] In one embodiment of the present application, a method for forming the second axial lifetime control region includes: Thinning the back of the silicon wafer to a preset thickness; The back of the silicon wafer is subjected to proton irradiation processing to implant ions into the intrinsic region; Proton irradiation defect annealing.

[0012] In an embodiment of the present application, the preset thickness is 50-100 um.

[0013] In one embodiment of the present application, the implanted ions include H+ or He, and the implantation center is 10 to 50 μm below the PN junction in the intrinsic region.

[0014] In one embodiment of the present application, the method of combining the anode silicon wafer and the cathode silicon wafer includes: Direct silicon bonding of the anode silicon wafer and the cathode silicon wafer; and Thinned to 150~500un according to rated breakdown voltage.

[0015] In one embodiment of the present application, the method for preparing the high-voltage fast recovery diode chip further includes: front metallization and back metallization to form a front metal electrode layer and a back metal electrode layer, respectively.

[0016] Accordingly, the present application also provides a high-voltage fast recovery diode chip prepared by the above-mentioned preparation method, comprising: Anode silicon wafer and cathode silicon wafer bonded by silicon; The anode silicon wafer includes a P region and an intrinsic region. A first axial lifetime control region is provided in the P region, and a second axial lifetime control region is provided in the intrinsic region.

[0017] The beneficial effects of the present invention are: Differentiating from the prior art, the present application provides a high-voltage fast recovery diode chip and its fabrication method. This high-voltage fast recovery diode chip consists of two silicon wafers. One is the anode silicon wafer. The anode P region of this portion has a first axial lifetime control region formed by a Pt diffusion process, which significantly reduces the number of minority carriers injected into the P region, thereby reducing Irrm and ta. A second axial lifetime control region is formed in the intrinsic region above the N region through proton irradiation. This reduces the minority carrier lifetime when the diode reverse recovers and enters the non-equilibrium carrier recombination extraction phase, accelerating the device's reverse recovery time. The formation of two axial lifetime control regions significantly reduces the reverse recovery loss of the PIN diode without affecting the device's junction temperature. The second portion is the cathode silicon wafer, which can be manufactured using epitaxial growth to form a cathode with a field stop (FS) structure or a buffer layer structure. The two silicon wafers are bonded together by direct silicon bonding, resulting in a device that exhibits both high performance and high reliability.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a schematic diagram of a prior art PIN diode; Figure 2 It is a flow chart of a method for preparing a high-voltage fast recovery diode chip according to a preferred embodiment of the present invention; Figure 3 This is a comparison chart of reverse recovery characteristics of diodes prepared by a general process and by the process of the present invention; Figure 4 This is a schematic diagram of the anode silicon wafer structure of a high-voltage fast recovery diode chip according to a preferred embodiment of the present invention; Figure 5 It is a structural schematic diagram of a high-voltage fast recovery diode chip according to a preferred embodiment of the present invention.

[0022] In the picture: Oxide layer 1, P region 2, front metal electrode layer 3, first axial lifetime control region 4, intrinsic region 5, first axial lifetime control region 6, FS region 7, back metal electrode layer 8. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] This application provides a high-voltage fast recovery diode chip and a method for manufacturing the same, which are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the description of each embodiment has its own emphasis. For portions not detailed in one embodiment, please refer to the relevant descriptions of other embodiments.

[0025] See also Figure 2 In one embodiment, a method for preparing a high-voltage fast recovery diode chip includes: preparing an anode silicon wafer having first and second axial lifetime control regions, wherein the first axial lifetime control region is located in a P region and the second axial lifetime control region is located in an intrinsic region; preparing a cathode silicon wafer; and combining the anode silicon wafer and the cathode silicon wafer.

[0026] In this embodiment, see Figure 4 and Figure 5 The high-voltage fast recovery diode chip of this embodiment is composed of two silicon wafers. One part is the anode silicon wafer. The anode P region 2 of this part is provided with a first axial lifetime control region 4. This lifetime control region can significantly reduce the minority carriers injected into the P region, thereby reducing the effects of Irrm and ta (see Figure 3 ). At the same time, a second axial lifetime control region 6 is formed in the intrinsic region 5 above the N region through proton irradiation. When the diode reverse recovers and enters the non-equilibrium carrier recombination extraction stage in the body, the minority carrier lifetime is reduced and the reverse recovery time of the device is accelerated. The setting of two axial lifetime control regions can greatly reduce the reverse recovery loss of the PIN diode without affecting the junction temperature of the device. The second part is the cathode silicon wafer, which can be manufactured by epitaxial growth to form a cathode with a field stop structure (FS) or a buffer layer structure. The two parts of the silicon wafer are bonded together by direct silicon bonding (DSB). The final device has both high performance and high reliability.

[0027] Optionally, the method for forming the first axial lifetime control region includes: performing Pt expansion processing on a device forming a P-doped active region P region.

[0028] Specifically, the Pt diffusion process includes: sputtering a Pt film with a thickness of 100 Å to 200 Å on the surface of the device; and diffusing the Pt-Si compound formed on the surface of the device through a high-temperature furnace tube to form a first axial lifetime control area.

[0029] Furthermore, the method for forming a P-doped active region (P region) includes: oxidation and photolithography of a P-implantation region: cleaning a silicon wafer with N region and I region epitaxy and then performing an oxidation treatment to form a field oxide layer on the front side of the silicon wafer, and then photolithography and etching a P-implantation window on the front side of the silicon wafer; P-type impurity ion implantation: using an ion implanter to implant P-type ions into the active region and the terminal region, with an ion implantation energy of 60 to 150 KeV and an implantation dose of 5E12 to 5E14; P-impurity advancement: placing the silicon wafer in a high-temperature diffusion furnace and advancing the P-type impurities to form a P-doped active region (P region) with a junction depth of 4 to 6 μm.

[0030] Furthermore, the method for forming the second axial lifetime control region includes: thinning the back side of the silicon wafer to a preset thickness; performing proton irradiation processing on the back side of the silicon wafer to inject ions into the intrinsic region; and proton irradiation defect annealing.

[0031] Optionally, the preset thickness is 50-100 um.

[0032] Optionally, the implanted ions include H+ or He, and the implantation center is 10 to 50 μm below the PN junction in the intrinsic region.

[0033] Optionally, the method of combining the anode silicon wafer and the cathode silicon wafer includes: performing low-temperature direct silicon bonding on the anode silicon wafer and the cathode silicon wafer; and thinning the anode silicon wafer to 150 to 500 un according to the rated breakdown voltage.

[0034] Furthermore, the method for preparing the high-voltage fast recovery diode chip further includes: front metallization and back metallization to form a front metal electrode layer and a back metal electrode layer, respectively.

[0035] In one application scenario, the method for preparing a high-performance fast recovery diode chip using axial lifetime control in this embodiment can be performed in the following steps: (1) Oxidation and photolithography of the P-implantation area: After cleaning the silicon wafer with the N-region and I-region epitaxial growth, an oxidation treatment is performed to form a field oxide layer 1 on the front of the silicon wafer. Then, a P-implantation window is formed on the front of the silicon wafer by photolithography and etching; (2) P-type impurity ion implantation: Use an ion implanter to implant P-type ions into the active area and the terminal area. The ion implantation energy is 60-150 KeV and the implantation dose is 5E12-5E14. (3) P-impurity push: Place the silicon wafer in a high-temperature diffusion furnace to push the P-type impurities, thus forming a P-doped active region P region 2 with a junction depth of 4 to 6 μm; (4) Pt diffusion processing: a Pt film with a thickness of 100 Å to 200 Å is sputtered on the device surface, and then the Pt-Si compound formed on the device surface is diffused through a high-temperature furnace tube, wherein the diffusion temperature is 750℃~900℃, and the first axial lifetime control region 4 is formed; (5) Front metallization: A layer of Al film with a thickness of 4 to 5 μm is deposited on the front of the device, and then photolithography, etching, and alloying are performed to form a front metal electrode layer 3; (6) Back thinning: Use a grinder or sandblasting to thin the back of the silicon wafer to the required thickness, which can be reduced to 50-100 μm; (7) Proton irradiation processing: Use a high-energy proton implanter to perform proton irradiation processing from the back of the device. The implanted ions are H+ or He. The implantation center is in the intrinsic region 5 (i.e., I region), 10 to 50 μm below the PN junction. The implantation bandwidth and H+ ion implantation dose are determined by the tb value required by the device. (8) Proton irradiation defect annealing: Use an oven or furnace tube to perform proton irradiation defect annealing on the device. The annealing temperature is selected to be the temperature at which H+ is injected to form shallow thermal donor defects after annealing. After the annealing is completed, the second axial lifetime control region 6 is processed.

[0036] (9) Surface treatment is performed on the cathode silicon wafer and the anode silicon wafer, and the completed anode silicon wafer and cathode silicon wafer are combined together through low temperature (100-200°C) direct silicon bonding (DSB), and then thinned to 150-500un according to the required rated breakdown voltage.

[0037] (10) Back metallization: A second axial lifetime control region 6 is formed on the back of the silicon wafer by evaporation or sputtering to form a cathode metal layer. The thickness of the second axial lifetime control region 6 is between 15,000 and 22,000 Å. At this point, the high-performance fast recovery diode chip is completed.

[0038] Accordingly, based on the above embodiment, this embodiment also provides a high-voltage fast recovery diode chip prepared by the preparation method as described above, including: an anode silicon wafer and a cathode silicon wafer bonded by silicon; the anode silicon wafer includes a P region 2 and an intrinsic region 5, a first axial lifetime control region 4 is provided in the P region 2, and a second axial lifetime control region 6 is provided in the intrinsic region 5.

[0039] In this embodiment, the structure of the high-voltage fast recovery diode chip is as described above and will not be described again here.

[0040] In summary, the high-voltage fast recovery diode chip of the present invention is produced by dividing the front and back of the fast recovery diode chip into two silicon wafers for separate processing, and then combining the two into one by low-temperature silicon bonding, thereby reducing equipment capacity limitations and producing high-performance high-voltage fast recovery diodes. The present invention forms a first axial lifetime control region for Pt diffusion in the P region on the front of the fast recovery diode chip, which is used to reduce the non-equilibrium carrier concentration injected from the P region to the I region; from the back of the thinned anode silicon wafer, H+ is injected to form a local second axial lifetime control region at the required depth, forming a soft recovery characteristic that reduces the tail current while maintaining partial tailing. The proton or He injection of the present invention is carried out from the back of the anode silicon wafer, and the distance from the PN junction position is controllable, which will avoid the increase of leakage current and ensure the junction temperature.

[0041] It should be noted that the various devices selected in this application (components whose specific structures are not described) are all universal standard parts or components known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or through conventional experimental methods.

[0042] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0043] Based on the above-mentioned ideal embodiment of the present invention, and through the above description, relevant personnel can make various changes and modifications without departing from the scope of the technical concept of the present invention. The technical scope of the present invention is not limited to the contents of the specification.

Claims

1. A method for preparing a high-voltage fast recovery diode chip, characterized in that: include: An anode silicon wafer having a first and a second axial lifetime control region is prepared; the first axial lifetime control region is located in the P region, and the second axial lifetime control region is located in the intrinsic region; preparing cathode silicon wafers; Combine the anode silicon wafer and the cathode silicon wafer.

2. The method for preparing a high-voltage fast recovery diode chip according to claim 1, wherein: The method for forming the first axial lifetime control region includes: performing Pt expansion processing on a device forming a P-doped active region P region.

3. The method for preparing a high-voltage fast recovery diode chip according to claim 2, wherein: The Pt expansion process includes: Sputter a Pt film on the device surface with a thickness of 100 Å to 200 Å; The Pt-Si compound formed on the device surface is diffused through a high-temperature furnace tube to form the first axial lifetime control area.

4. The method for preparing a high-voltage fast recovery diode chip according to claim 2, wherein: The method for forming a P-doped active region P region comprises: Oxidation and photolithography of the P-implantation area: After cleaning the silicon wafer with N-region and I-region epitaxial growth, it is oxidized to form a field oxide layer on the front of the silicon wafer. Then, the P-implantation window is formed on the front of the silicon wafer through photolithography and etching; P-type impurity ion implantation: Use an ion implanter to implant P-type ions into the active area and the terminal area. The ion implantation energy is 60-150 KeV and the implantation dose is 5E12-5E14. P-impurity push-in: Place the silicon wafer in a high-temperature diffusion furnace to push in P-type impurities, thereby forming a P-doped active area P region with a junction depth of 4 to 6 μm.

5. The method for preparing a high-voltage fast recovery diode chip according to claim 1, wherein: The method of forming the second axial life control zone includes: Thinning the back of the silicon wafer to a preset thickness; The back of the silicon wafer is subjected to proton irradiation processing to implant ions into the intrinsic region; Proton irradiation defect annealing.

6. The method for preparing a high-voltage fast recovery diode chip according to claim 5, characterized in that: The preset thickness is 50-100 μm.

7. The method for preparing a high-voltage fast recovery diode chip according to claim 5, wherein: The implanted ions include H+ or He, and the implantation center is 10 to 50 μm below the PN junction in the intrinsic region.

8. The method for preparing a high-voltage fast recovery diode chip according to claim 1, wherein: The method for combining the anode silicon wafer and the cathode silicon wafer comprises: Direct silicon bonding of the anode silicon wafer and the cathode silicon wafer; and Thinned to 150~500un according to rated breakdown voltage.

9. The method for preparing a high-voltage fast recovery diode chip according to claim 1, wherein: Also includes: The front side is metallized and the back side is metallized to form a front side metal electrode layer and a back side metal electrode layer respectively.

10. A high-voltage fast recovery diode chip prepared by the preparation method according to any one of claims 1 to 9, characterized in that: include: Anode silicon wafer and cathode silicon wafer bonded by silicon; The anode silicon wafer includes a P region and an intrinsic region. A first axial lifetime control region is provided in the P region, and a second axial lifetime control region is provided in the intrinsic region.

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