Preparation method of semiconductor structure
By combining dry and wet etching processes to form grooves in the high-voltage device area and cover it with a protective mask layer, the problem of uneven thickness of the gate oxide dielectric layer of the high-voltage device is solved, and the electrical performance and reliability, especially the stability of the asymmetric high-voltage device, are improved.
Patent Information
- Application Number
- CN202510796488.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art, when integrating high-voltage devices and low-voltage devices, the uneven thickness of the gate oxide dielectric layer of the high-voltage device leads to electrical performance and reliability problems, especially abnormal threshold voltage and breakdown voltage of asymmetric high-voltage devices.
By combining anisotropic dry etching and wet etching processes, a groove is first formed in the high-voltage device area and covered with a protective mask layer to prevent the penetration of wet etching solution, ensure the uniformity of the silicon oxide layer thickness in the channel area, and then form the gate electrode.
The electrical performance and reliability of high-voltage devices are improved, especially the stability of threshold voltage and breakdown voltage of asymmetric high-voltage devices, and the performance abnormality caused by the uneven thickness of the silicon oxide layer is avoided.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure. Background Art
[0002] With the development of integrated circuits, single-chip system integration has become a trend, which requires having both high-voltage devices and low-voltage devices on a single chip.
[0003] In addition to the different designs of well regions, source and drain, the difference between high-voltage devices and low-voltage devices is that the thickness of the gate oxide dielectric layer of high-voltage devices is greater than that of low-voltage devices.
[0004] When integrating high-voltage and low-voltage devices, a thicker gate oxide dielectric layer is generally prepared first for the high-voltage device, followed by a thinner gate oxide dielectric layer for the low-voltage device. However, such a preparation process can easily cause uneven thickness of the gate oxide dielectric layer of the high-voltage device, which ultimately affects the electrical performance (threshold voltage, breakdown voltage, etc.) and reliability of the high-voltage device, especially the asymmetric high-voltage device. Summary of the Invention
[0005] Based on this, the present application provides a method for preparing a semiconductor structure to improve the thickness uniformity of the silicon oxide layer in the first region to ensure the electrical performance and reliability of the device formed in the first region.
[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:
[0007] Providing a substrate, the substrate comprising a first region and a second region, the first region comprising a first channel region and a first source region and a first drain region respectively located on both sides of the first channel region;
[0008] forming a silicon oxide layer covering the first region and the second region;
[0009] Using an anisotropic dry etching process to etch away a portion of the silicon oxide layer in the second region and the first source region and the first drain region, thereby forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively;
[0010] forming a protective mask layer on the silicon oxide layer in the first region and on sidewalls of the first and second grooves, wherein the protective mask layer exposes the remaining silicon oxide layer in the second region and at the bottoms of the first and second grooves;
[0011] Using a wet etching process to remove the remaining silicon oxide layer in the second region and at the bottom of the first groove and the second groove, exposing the second region and the substrate surface of the first source region and the first drain region, wherein the protective mask layer protects the silicon oxide layer in the first channel region from being overetched during the wet etching process;
[0012] removing the protective mask layer to expose the silicon oxide layer in the first channel region;
[0013] A first gate electrode is formed on the silicon oxide layer in the first channel region, and a distance between the first gate electrode and the first source region is smaller than a distance between the first gate electrode and the first drain region.
[0014] In some embodiments of the present application, using a dry etching process to etch away a portion of the silicon oxide layer in the second region and the first source region and the first drain region, and forming a first recess and a second recess in the silicon oxide layer in the first source region and the first drain region, respectively, includes:
[0015] forming a first mask layer on the silicon oxide layer, wherein the first mask layer exposes the surface of the silicon oxide layer in the second region and the first source region and the first drain region;
[0016] Using the first mask layer as a mask, a dry etching process is used to remove a portion of the silicon oxide layer, thereby forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively;
[0017] The first mask layer is removed.
[0018] In some embodiments of the present application, the materials of the first mask layer and the protection mask layer are both photoresist.
[0019] In some embodiments of the present application, the first mask layer has a first opening, a second opening, and a third opening, the first opening exposing the surface of the silicon oxide layer in the second region, and the second opening and the third opening exposing the surfaces of the silicon oxide layer in the first source region and the first drain region, respectively;
[0020] The width of the first groove is equal to the width of the second opening, and the width of the second groove is equal to the width of the third opening;
[0021] Forming the first mask layer includes: forming a first mask layer of photoresist material by a spin coating process; performing a first exposure process and a first development process on the first mask layer of photoresist material to form a first opening, a second opening and a third opening in the first mask layer.
[0022] In some embodiments of the present application, the protective mask layer has a fourth opening, a fifth opening, and a sixth opening. The width of the fifth opening is smaller than the width of the second opening, and the width of the sixth opening is smaller than the width of the third opening. The fourth opening exposes the remaining surface of the silicon oxide layer in the second region, and the fifth opening and the sixth opening expose the remaining surface of the silicon oxide layer at the bottom of the first groove and the bottom of the second groove, respectively.
[0023] Forming the protection mask layer includes: forming a protection mask layer of photoresist material by a spin coating process; performing a second exposure process and a second development process on the protection mask layer of photoresist material to form a fourth opening, a fifth opening and a sixth opening in the protection mask layer.
[0024] In some embodiments of the present application, the same mask is used when performing the first exposure process and the second exposure process; and the exposure energy when performing the second exposure process is less than the exposure energy when performing the first exposure, so that the width of the fifth opening formed is smaller than the width of the second opening, and the width of the sixth opening formed is smaller than the width of the third opening.
[0025] In some embodiments of the present application, a first shallow trench isolation structure is further formed in the substrate of the first region, and a top surface of the first shallow trench isolation structure is higher than a top surface of the silicon oxide layer of the first region;
[0026] A second shallow trench isolation structure is also formed in the substrate of the second region, and a top surface of the second shallow trench isolation structure is higher than a top surface of the silicon oxide layer of the second region.
[0027] In some embodiments of the present application, the formation process of the silicon oxide layer, the first shallow trench isolation structure, and the second shallow trench isolation structure includes:
[0028] forming a first annular trench and a second annular trench in the substrate in the first region and the second region;
[0029] forming a silicon oxide layer on inner wall surfaces of the first annular groove and the second annular groove and on surfaces of the substrate in the first region and the second region;
[0030] forming a stop layer on the surface of the silicon oxide layer between the first annular trenches and on the silicon oxide layer between the second annular trenches;
[0031] forming a filling layer on the silicon oxide layer and the stop layer, wherein the filling layer completely fills the annular first trench and the annular second trench;
[0032] planarizing the filling layer until the stop layer is exposed to form a first shallow trench isolation structure and a second shallow trench isolation structure;
[0033] Remove the stop layer.
[0034] In some embodiments of the present application, the first mask layer and the protection mask layer further cover the first shallow trench isolation structure and the second shallow trench isolation structure;
[0035] After forming the first gate electrode, the method further includes: forming a first source doping region in the first source region, and forming a first drain doping region in the first drain region.
[0036] In some embodiments of the present application, the method further includes: forming a second silicon oxide layer in the second region, wherein the thickness of the second silicon oxide layer is less than the thickness of the silicon oxide layer in the first region; forming a second gate electrode on the second silicon oxide layer; and forming a second source doping region and a second drain doping region in the substrate on both sides of the second gate electrode, respectively.
[0037] The embodiments of the present application may or at least have the following advantages:
[0038] In an embodiment of the present application, a method for preparing a semiconductor structure comprises the following steps: after forming a silicon oxide layer covering a first region and a second region; using an anisotropic dry etching process to etch away a portion of the thickness of the silicon oxide layer in the second region and the first source region and the first drain region, forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively; forming a protective mask layer on the silicon oxide layer in the first region and on the sidewalls of the first groove and the second groove, the protective mask layer exposing the remaining silicon oxide layer in the second region and at the bottom of the first groove and the second groove; using a wet etching process to remove the remaining silicon oxide layer in the second region and at the bottom of the first groove and the second groove, exposing the substrate surface of the second region and the first source region and the first drain region, the protective mask layer protecting the silicon oxide layer in the first channel region from being over-etched during the wet etching process; removing the protective mask layer to expose the silicon oxide layer in the first channel region; and forming a first gate electrode on the silicon oxide layer in the first channel region, wherein the distance between the first gate electrode and the first source region is less than the distance between the first gate electrode and the first drain region. Since the top surface of the silicon oxide layer in the first region (the surface away from the substrate) and the sidewalls of the first and second grooves are all covered by the protective mask layer, that is, the side and top surfaces of the silicon oxide layer remaining on the first channel region (or the silicon oxide layer remaining between the first and second grooves) are all covered by the protective mask layer, when a wet etching process is subsequently used to remove the silicon oxide layer remaining in the second region and at the bottom of the first and second grooves, the protective mask layer on the sidewalls of the first and second grooves can prevent the etching solution used in the wet etching process from penetrating into the top surface of the edge of the silicon oxide layer in the first channel region (or the silicon oxide layer between the first and second grooves). Preventing the etching solution from over-etching the edge of the silicon oxide layer on the first channel region (or the silicon oxide layer between the first groove and the second groove), so that the thickness in the middle of the silicon oxide layer on the first channel region (or the silicon oxide layer between the first groove and the second groove) is consistent with the thickness at the edge, preventing thickness non-uniformity or improving thickness uniformity. After subsequently forming the first gate electrode on the silicon oxide layer on the first channel region (or the silicon oxide layer between the first groove and the second groove), the electrical performance (threshold voltage, breakdown voltage, etc.) and reliability of the device (such as a high-voltage device, especially an asymmetric high-voltage device) formed in the first region can be guaranteed.
[0039] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 A schematic diagram of a structure after a silicon oxide layer and a first mask layer are formed on a first region surface of a substrate in a conventional method for preparing a semiconductor structure;
[0042] Figure 2 A schematic diagram of a structure after a portion of a silicon oxide layer is removed by dry etching and wet etching using a first mask layer as a mask in a conventional method for preparing a semiconductor structure;
[0043] Figure 3 A schematic diagram of a structure after a gate electrode is formed in a conventional method for preparing a semiconductor structure;
[0044] Figure 4 A schematic diagram of a structure after forming a silicon oxide layer on a substrate and inner walls of a first trench and a second trench, and forming a filling layer on the silicon oxide layer, in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0045] Figure 5 A schematic diagram of a structure after planarization of a filling layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0046] Figure 6 A schematic diagram of a structure after removing a stop layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0047] Figure 7 A schematic diagram of a first mask layer structure formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0048] Figure 8 A schematic diagram of a structure after a portion of a silicon oxide layer is removed by dry etching in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0049] Figure 9 A schematic diagram of a structure after removing the first mask layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0050] Figure 10 A schematic diagram of a structure after forming a protective mask layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0051] Figure 11A schematic diagram of a structure after forming a fifth opening and a sixth opening in a protective layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0052] Figure 12 A schematic diagram of the structure after etching the remaining silicon oxide layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0053] Figure 13 This is a schematic diagram of the structure after forming a first gate electrode in a method for preparing a semiconductor structure provided in some embodiments of the present application.
[0054] Description of reference numerals:
[0055] Substrate 100; silicon oxide layer 101; shallow trench isolation structure 102; filling layer 103; stop layer 104; first mask layer 105; second opening 106; third opening 107; first recess 108; second recess 109; protection mask layer 110; fifth opening 111; sixth opening 112; first gate electrode 113; third recess 114; fourth recess 115;
[0056] first region-11; first channel region-11a; first source region-11b; first drain region-11c. DETAILED DESCRIPTION
[0057] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0058] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0059] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.
[0060] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0061] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0062] The structures of the embodiments of the present application should not be limited to the specific shapes shown in the drawings, but include shape deviations due to, for example, manufacturing technology.
[0063] When integrating high-voltage devices and low-voltage devices, a thicker gate oxide dielectric layer of the high-voltage device is generally prepared first, and then a thinner gate oxide dielectric layer of the low-voltage device is prepared. Specifically:
[0064] First, refer to Figure 1 , providing a substrate 100, the substrate 100 including a first region 11 and a second region (not shown in the figure), the first region 11 subsequently forming a high-voltage device, including an asymmetric high-voltage device, and the second region subsequently forming a low-voltage device or a medium-voltage device, the first region 11 including a first channel region 11a and a first source region 11b and a first drain region 11c located on both sides of the first channel region 11a; forming a silicon oxide layer 101 covering the first region 11 and the second region, a first shallow trench isolation structure 102 further formed in the first region 11, the top surface of the first shallow trench isolation structure 102 being higher than a surface of the silicon oxide layer 101 away from the substrate 100; forming a first mask layer 105 on the silicon oxide layer 101 and the first shallow trench isolation structure 102, the first mask layer 105 having a first opening exposing the surface of the silicon oxide layer in the second region, and exposing a portion of the surface of the silicon oxide layer 101 on the first source region 11b and the first drain region 11c;
[0065] refer to Figure 2 Using the first mask layer 105 as a mask, the silicon oxide layer in the second region and a portion of the silicon oxide layer 101 on the first source region 11b and the first drain region 11c are etched away to expose the surface of the substrate 100 in the second region. A third groove 114 and a fourth groove 115 are formed in the silicon oxide layer 101 in the first region 11 to expose a portion of the substrate surface of the first source region 11b and the first drain region 11c. The remaining silicon oxide layer 101 on the first channel region 11a (between the third groove 114 and the fourth groove 115) serves as a gate oxide dielectric layer of the high-voltage device. When etching the silicon oxide layer, an anisotropic dry etching process (such as an anisotropic plasma etching process) is first used to remove a portion of the thickness of the silicon oxide layer. The silicon oxide layer 101 is then removed by wet etching. The purpose of using a dry-wet etching method for etching is to prevent plasma from damaging the substrate 100 and to maintain a good etching morphology. However, such etching still brings some adverse effects. For example, during the wet etching process, part of the wet etching solution is still easy to penetrate from the third groove 114 and the fourth groove 115 into the bottom of the edge of the first mask layer 105 on the first channel region 11a, causing over-etching of the silicon oxide layer 101 at this position, so that the thickness of the edge of the silicon oxide layer 101 on the first channel region 11a will be less than the thickness in the middle, resulting in uneven thickness of the silicon oxide layer 101. Figure 3 After forming the gate electrode of the high voltage device on the silicon oxide layer 101 with uneven thickness, especially the high voltage device is Figure 3 In the asymmetric high-voltage device shown, uneven thickness of the silicon oxide layer 101 may cause abnormal electrical performance (threshold voltage, breakdown voltage, etc.) and reliability of the asymmetric high-voltage device.
[0066] To this end, an embodiment of the present application provides a method for preparing a semiconductor structure. Figure 4-13 A schematic structural diagram of each stage in a method for preparing a semiconductor structure provided in some embodiments of the present application.
[0067] refer to Figure 4 A substrate 100 is provided, the substrate 100 includes a first region 11 and a second region (not shown in the figure), the first region 11 includes a first channel region 11a and a first source region 11b and a first drain region 11c respectively located on both sides of the first channel region 11a; a silicon oxide layer 101 covering the first region 11 and the second region is formed.
[0068] The substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator (SiGe-on-insulator).
[0069] The substrate 100 may be doped with certain impurity ions as needed. In one example, the substrate 100 may be doped with P-type impurity ions, including one or more of boron ions, gallium ions, or indium ions. In another example, the substrate 100 may be doped with N-type impurity ions, including one or more of phosphorus ions, arsenic ions, or antimony ions.
[0070] The substrate 100 includes a first region 11 and a second region (not shown). The first region 11 and the second region may be adjacent or non-adjacent. A high-voltage device is subsequently formed on the first region 11. The high-voltage device includes a high-voltage MOS device. In one specific example, the high-voltage device includes an asymmetric high-voltage device or an asymmetric high-voltage MOS device. A low-voltage device or a medium-voltage device is subsequently formed on the second region. The low-voltage device or the medium-voltage device includes a low-voltage MOS device or a medium-voltage MOS device. The main structural differences between the high-voltage device and the low-voltage device or the medium-voltage device include: the gate oxide dielectric layer thickness of the high-voltage device is greater than that of the low-voltage device or the medium-voltage device. The main performance differences between the high-voltage device and the low-voltage device or the medium-voltage device include: the threshold voltage of the high-voltage device is greater than the threshold voltage of the low-voltage device or the medium-voltage device, the breakdown voltage of the high-voltage device is greater than the breakdown voltage of the low-voltage device or the medium-voltage device, and the withstand voltage of the high-voltage device is greater than the withstand voltage of the low-voltage device or the medium-voltage device.
[0071] The first region 11 also includes a first channel region 11a and a first source region 11b and a first drain region 11c located on either side of the first channel region 11a. The silicon oxide layer 101 on the substrate in the first channel region 11a will later form the gate oxide dielectric layer of the high-voltage device. The substrate 100 in the first source region 11b will later form the source doping region of the high-voltage device. The substrate 100 in the first drain region 11c will later form the drain doping region of the high-voltage device. The silicon oxide layer on the second region of the substrate will subsequently be removed, and a second silicon oxide layer thinner than the silicon oxide layer 101 in the first region will be formed to serve as the gate oxide dielectric layer of the low-voltage or medium-voltage device.
[0072] In some embodiments, reference Figure 5 or Figure 6 A first shallow trench isolation structure 102 is also formed in the substrate 100 in the first region 11. The top surface of the first shallow trench isolation structure 102 (the top surface of the first shallow trench isolation structure 102 is the surface of the first shallow trench isolation structure 102 away from the substrate 100) is higher than the top surface of the silicon oxide layer 101 in the first region 11 (the top surface of the silicon oxide layer 101 is the surface of the silicon oxide layer away from the substrate 100). The first shallow trench isolation structure 102 is used to isolate adjacent active regions in the first region 11, or can also be used to isolate the first region 11 from a second region. In one example, the first shallow trench isolation structure 102 can surround the first channel region 11a, the first source region 11b, and the first drain region 11c. A second shallow trench isolation structure (not shown) is also formed in the substrate 100 in the second region (not shown). The top surface of the second shallow trench isolation structure is higher than the top surface of the silicon oxide layer in the second region.
[0073] In some embodiments, the formation process of the silicon oxide layer 101, the first shallow trench isolation structure 102, and the second shallow trench isolation structure includes:
[0074] refer to Figure 4 , forming an annular first trench (not shown in the figure) and an annular second trench (not shown in the figure) in the substrate 100 in the first region 11 and the second region (not shown in the figure);
[0075] Continue to refer Figure 4 A silicon oxide layer 101 is formed on the inner wall surfaces of the annular first trench and the annular second trench, and on the surface of the substrate 100 in the first region 11 and the second region. The silicon oxide layer 101 can be formed by a substrate process or a thermal oxidation process. The thickness of the silicon oxide layer 101 is 700 angstroms to 900 angstroms, specifically 700 angstroms, 800 angstroms, or 900 angstroms. The silicon oxide layer 101 is formed not only on the surface of the substrate 100 but also on the inner wall surfaces of the annular first trench and the annular second trench. The silicon oxide layer 101 on the substrate surface in the first region 11 subsequently serves as a gate oxide dielectric layer of a high-voltage device, and the silicon oxide layer 101 on the inner wall surfaces of the annular first trench and the annular second trench subsequently serves as a portion of a first shallow trench isolation structure 102 and a portion of a second shallow trench isolation structure. That is, the gate oxide dielectric layer of the high-voltage device and a portion of the first shallow trench isolation structure 102 and a portion of the second shallow trench isolation structure can be formed simultaneously, thereby simplifying the process steps.
[0076] Continue to refer Figure 4 A stop layer 104 is formed on the surface of the silicon oxide layer 101 between the annular first trenches (or on the surface of the silicon oxide layer 101 on the first channel region 11a, the first source region 11b, and the first drain region 11c) and on the silicon oxide layer 101 between the annular second trenches. The stop layer 104 is used to protect the silicon oxide layer 101 so that the silicon oxide layer 101 is not damaged during subsequent processes and maintains a precise thickness. It also serves as a stop interface for subsequent planarization of the fill layer. The material of the stop layer 104 is different from that of the silicon oxide layer 101 and the material of the subsequently formed fill layer. In one example, the material of the stop layer 104 includes silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide.
[0077] Continue to refer Figure 4, forming a filling layer 103 on the silicon oxide layer 101 and the stop layer 104, the filling layer 103 filling the annular first trench and the annular second trench, the material of the filling layer 103 includes silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), and the filling layer 103 can be formed by low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDPCVD);
[0078] Then, refer to Figure 5 , planarization filling layer 103 (reference Figure 4 ), until the stop layer 104 is exposed, forming the first shallow trench isolation structure 102 and the second shallow trench isolation structure, and the planarization filling layer 103 can be formed by a chemical mechanical polishing process;
[0079] Finally, reference Figure 6 , removing the stop layer 104 , and removing the stop layer 104 may adopt an isotropic wet etching process or an isotropic dry etching process.
[0080] refer to Figure 7-Figure 9 A dry etching process is used to etch away a portion of the silicon oxide layer 101 in the second region and the first source region 11b and the first drain region 11c, and a first groove 108 and a second groove 109 are formed in the silicon oxide layer 101 in the first source region 11b and the first drain region 11c, respectively.
[0081] In one embodiment, a dry etching process is used to etch away a portion of the silicon oxide layer 101 in the second region and the first source region 11 b and the first drain region 11 c, and forming a first groove 108 and a second groove 109 in the silicon oxide layer 101 in the first source region 11 b and the first drain region 11 c, respectively, including:
[0082] First, refer to Figure 7A first mask layer 105 is formed on the silicon oxide layer 101. The first mask layer 105 exposes the surface of the silicon oxide layer 101 in the second region and the first source region 11b and the first drain region 11c. Specifically, the first mask layer 105 may have a first opening (not shown in the figure), a second opening 106, and a third opening 107. The first opening exposes the surface of the silicon oxide layer 101 in the second region (not shown in the figure), and the second opening 106 and the third opening 107 expose the surface of the silicon oxide layer 101 in the first source region 11b and the first drain region 11c, respectively. In a specific example, In the embodiment, the material of the first mask layer 105 is photoresist, and forming the first mask layer 105 includes: forming the first mask layer 105 of the photoresist material by a spin coating process; performing a first exposure process and a first development process on the first mask layer 105 of the photoresist material to form a first opening, a second opening 106, and a third opening 107 in the first mask layer 105. In other embodiments, the first mask layer 105 may be made of other suitable materials; in some embodiments, the first mask layer 105 further covers the first shallow trench isolation structure 102 and the second shallow trench isolation structure (not shown in the figure);
[0083] Next, refer to Figure 8 , using the first mask layer 105 as a mask, an anisotropic dry etching process is used to etch away a portion of the thickness of the silicon oxide layer 101, and a first groove 108 and a second groove 109 are formed in the silicon oxide layer 101 of the first source region 11b and the first drain region 11c, respectively. The width of the first groove 108 is equal to the width of the second opening 106, and the width of the second groove 109 is equal to the width of the third opening 107. When the anisotropic dry etching process is used for etching, the first groove 108 and the second groove 109 formed can have good The sidewall morphology and position accuracy of the silicon oxide layer 101 remaining on the first channel region 11a (or the silicon oxide layer 101 remaining between the first groove 108 and the second groove 109) have high side morphology and position accuracy, thereby improving the electrical performance of the subsequently formed high-voltage device. In one example, the anisotropic dry etching process includes an anisotropic plasma etching process, and the etching gas used in the anisotropic plasma etching process includes one or more of CF4, CHF3, C4F8, and C4F6 gases;
[0084] refer to Figure 9 , remove the first mask layer 105. In some embodiments, the first mask layer 105 can be gradually removed during the etching process of the silicon oxide layer 101. In other embodiments, the first mask layer 105 can also be removed using an additional process, such as an ashing process.
[0085] refer to Figure 10 and Figure 11A protective mask layer 110 is formed on the silicon oxide layer 101 in the first region 11 and on the sidewalls of the first groove 108 and the second groove 109 (refer to Figure 11 ), the protective mask layer 110 exposes the second area and the remaining silicon oxide layer 101 at the bottom of the first groove 108 and the second groove 109.
[0086] Since the top surface of the silicon oxide layer 101 in the first region 11 (away from the surface of the substrate 100) and the sidewalls of the first groove 108 and the second groove 109 are all covered by the protective mask layer 110, that is, the side and top surfaces of the silicon oxide layer 101 on the first channel region 11a (or the silicon oxide layer 101 between the first groove 108 and the second groove 109) are all covered by the protective mask layer 110, when a wet etching process is subsequently used to remove the remaining silicon oxide layer 101 in the second region and at the bottom of the first groove 108 and the second groove 109, the protective mask layer 110 on the sidewalls of the first groove 108 and the second groove 109 can prevent the etching solution used in the wet etching process from penetrating into the silicon oxide layer 101 on the first channel region 11a (or the silicon oxide layer 101 between the first groove 108 and the second groove 109). The top surface of the edge of the silicon oxide layer 101) is prevented from over-etching the edge of the silicon oxide layer 101 on the first channel region 11a (or the silicon oxide layer 101 between the first groove 108 and the second groove 109) by the etching solution, so that the thickness of the middle of the silicon oxide layer 101 on the first channel region 11a (or the silicon oxide layer 101 between the first groove 108 and the second groove 109) is consistent with the thickness of the edge, thereby preventing thickness non-uniformity or improving thickness uniformity. After the first gate electrode is subsequently formed on the silicon oxide layer 101 on the first channel region 11a (or the silicon oxide layer 101 between the first groove 108 and the second groove 109), the electrical performance (threshold voltage, breakdown voltage, etc.) and reliability of the device (such as a high-voltage device, especially an asymmetric high-voltage device) formed in the first region can be guaranteed.
[0087] In some embodiments, the material of the protective mask layer 110 is photoresist. The protective mask layer 110 has a fourth opening (not shown in the figure), a fifth opening 111, and a sixth opening 112. The width of the fifth opening 111 is smaller than the width of the second opening 106 (or the first groove 108), and the width of the sixth opening 112 is smaller than the width of the third opening 107 (or the second groove 109). The fourth opening exposes the remaining surface of the silicon oxide layer 101 in the second region, and the fifth opening 111 and the sixth opening 112 expose the remaining surface of the silicon oxide layer 101 at the bottom of the first groove 108 and the second groove 109, respectively.
[0088] Forming the protection mask layer 110 includes: forming the protection mask layer 110 of photoresist material by a spin coating process; performing a second exposure process and a second development process on the protection mask layer 110 of photoresist material to form a fourth opening, a fifth opening 111 and a sixth opening 112 in the protection mask layer 110 .
[0089] In some embodiments, the first mask layer 105 (refer to Figure 5 ) and the second exposure process for the protective mask layer 110 of the photoresist material use the same mask; and the exposure energy during the second exposure process is less than the exposure energy during the first exposure process, so that the width of the formed fifth opening 111 is less than the width of the second opening 106, and the width of the formed sixth opening 112 is less than the width of the third opening 107. In other words, the same mask can be used for the first exposure process for the first mask layer 105 and the second exposure process for the protective mask layer 110, eliminating the need for two different masks. By simply adjusting the exposure process energy appropriately, the fifth opening 111 and the sixth opening 112 with smaller widths can be obtained, thereby reducing manufacturing costs. In other embodiments, the first mask layer 105 can be made of other materials, such as dielectric materials such as silicon nitride.
[0090] In some embodiments, the protection mask layer 110 further covers the first shallow trench isolation structure 102 and the second shallow trench isolation structure (not shown in the figures).
[0091] refer to Figure 12 A wet etching process is used to remove the remaining silicon oxide layer 101 in the second region and at the bottom of the first groove 108 and the second groove 109, exposing the surface of the substrate 100 in the second region and the first source region 11b and the first drain region 11c. The protective mask layer protects the silicon oxide layer 101 in the first channel region 11a from being over-etched during the wet etching process.
[0092] In the present application, the surface of the substrate 100 of the second region and the first source region 11b and the first drain region 11c is exposed, so as to facilitate the subsequent formation of a source doped region in the substrate of the first source region 11b and the formation of a first metal wire electrically connected to the source doped region, and to facilitate the subsequent formation of a drain doped region in the substrate 100 of the first drain region 11c and the formation of a second metal wire electrically connected to the drain doped region.
[0093] After using a wet etching process to remove the remaining silicon oxide layer 101 in the second area and at the bottom of the first groove 108 and the second groove 109, the silicon oxide layer in the second area is completely removed. Subsequently, a thin second silicon oxide layer can be formed in the second area as a gate oxide dielectric layer for a low-voltage device or a medium-voltage device, and the silicon oxide layer 101 between the first groove 108 and the second groove 109 (or the silicon oxide layer 101 in the first channel area 11a) is used as a gate oxide dielectric layer for a high-voltage device (especially an asymmetric high-voltage device).
[0094] In the present application, the silicon oxide layer 101 is etched by a combination of anisotropic dry etching process and wet etching process, the purpose of which is to prevent plasma damage to the substrate caused by the etching process while ensuring good morphology and high position accuracy of the formed etched pattern.
[0095] In some embodiments, the wet etching process uses an etching solution comprising diluted hydrofluoric acid.
[0096] Continue to refer Figure 12 , remove the protective mask layer 110 to expose the silicon oxide layer 101 in the first channel region 11a. In some embodiments, the protective mask layer 110 is removed simultaneously during the wet etching process. In other embodiments, an additional process, such as an ashing process, may be used to remove the protective mask layer 110.
[0097] In some embodiments, reference Figure 13 , further comprising: forming a first gate electrode 113 on the silicon oxide layer 101 in the first channel region 11a, and the distance between the first gate electrode 113 and the first source region 11b is smaller than the distance between the first gate electrode 113 and the first drain region 11c (that is, the first gate electrode 113 is located on the surface of the silicon oxide layer 101 close to the first source region 11b or a source doping region formed subsequently), the first gate electrode 113 serves as the gate electrode of the asymmetric high-voltage device. In one example, the material of the first gate electrode 113 is polysilicon.
[0098] In some embodiments, it also includes: after forming the first gate electrode 113, it also includes: forming a first source doping region (not shown in the figure) in the first source region 11b, and forming a first drain doping region (not shown in the figure) in the first drain region 11c. The first source doping region and the first drain doping region can be formed by an ion implantation process. Depending on the type of asymmetric high-voltage device formed, the ion implantation process implants different types of impurity ions. In one example, when an N-type asymmetric high-voltage device is formed, the impurity ions implanted by ion implantation are N-type impurity ions, that is, the first source doping region and the first drain doping region formed are N-type, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions or antimony ions. In another example, when a P-type asymmetric high-voltage device is formed, the impurity ions implanted by ion implantation are P-type impurity ions, that is, the first source doping region and the first drain doping region formed are P-type, and the P-type impurity ions include one or more of boron ions, gallium ions or indium ions.
[0099] In some embodiments, the present invention further includes: forming a second silicon oxide layer in the second region, wherein the thickness of the second silicon oxide layer is less than the thickness of the silicon oxide layer 101 in the first region 11; forming a second gate electrode on the second silicon oxide layer; and forming a second source doping region and a second drain doping region in the substrate 100 on both sides of the second gate electrode, respectively, the second silicon oxide layer serving as a gate oxide dielectric layer of a low-voltage device (or a medium-voltage device), the second gate electrode serving as a gate electrode of the low-voltage device (or a medium-voltage device), and the second source doping region and the second drain doping region serving as a source doping region and a drain doping region of the low-voltage device (or a medium-voltage device), respectively.
[0100] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of these terms do not necessarily refer to the same embodiment or example.
[0101] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0102] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the first region comprising a first channel region and a first source region and a first drain region respectively located on both sides of the first channel region; forming a silicon oxide layer covering the first region and the second region; Using an anisotropic dry etching process to etch away a portion of the thickness of the silicon oxide layer in the second region and the first source region and the first drain region, thereby forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively; forming a protective mask layer on the silicon oxide layer in the first region and on sidewalls of the first and second grooves, wherein the protective mask layer exposes the second region and the remaining silicon oxide layer at the bottoms of the first and second grooves; Using a wet etching process to remove the remaining silicon oxide layer in the second region and at the bottom of the first groove and the second groove, exposing the second region and the substrate surface of the first source region and the first drain region, wherein the protective mask layer protects the silicon oxide layer in the first channel region from being overetched during the wet etching process; removing the protective mask layer to expose the silicon oxide layer in the first channel region; A first gate electrode is formed on the silicon oxide layer in the first channel region, and a distance between the first gate electrode and the first source region is smaller than a distance between the first gate electrode and the first drain region.
2. The method for preparing a semiconductor structure according to claim 1, wherein: The method of etching and removing a portion of the thickness of the silicon oxide layer in the second region and the first source region and the first drain region by a dry etching process, and forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively, comprises: forming a first mask layer on the silicon oxide layer, wherein the first mask layer exposes the second region and the surface of the silicon oxide layer of the first source region and the first drain region; Using the first mask layer as a mask, a dry etching process is used to remove a portion of the thickness of the silicon oxide layer, thereby forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region, respectively; The first mask layer is removed.
3. The method for preparing a semiconductor structure according to claim 2, wherein: Materials of the first mask layer and the protection mask layer are both photoresist.
4. The method for preparing a semiconductor structure according to claim 3, wherein: The first mask layer has a first opening, a second opening, and a third opening, the first opening exposing the surface of the silicon oxide layer in the second region, and the second opening and the third opening exposing the surfaces of the silicon oxide layer in the first source region and the first drain region, respectively; The width of the first groove is equal to the width of the second opening, and the width of the second groove is equal to the width of the third opening; Forming the first mask layer includes: forming a first mask layer of photoresist material using a spin coating process; A first exposure process and a first development process are performed on the first mask layer of the photoresist material to form the first opening, the second opening, and the third opening in the first mask layer.
5. The method for preparing a semiconductor structure according to claim 4, wherein: The protective mask layer has a fourth opening, a fifth opening, and a sixth opening, wherein the width of the fifth opening is smaller than the width of the second opening, and the width of the sixth opening is smaller than the width of the third opening, the fourth opening exposes the remaining silicon oxide layer surface in the second region, and the fifth opening and the sixth opening expose the remaining silicon oxide layer surface at the bottom of the first groove and the bottom of the second groove, respectively; Forming the protective mask layer includes: forming a protective mask layer of photoresist material using a spin coating process; A second exposure process and a second development process are performed on the protection mask layer of the photoresist material to form the fourth opening, the fifth opening and the sixth opening in the protection mask layer.
6. The method for preparing a semiconductor structure according to claim 5, wherein: The same mask is used when performing the first exposure process and the second exposure process; and the exposure energy when performing the second exposure process is less than the exposure energy when performing the first exposure, so that the width of the fifth opening formed is smaller than the width of the second opening, and the width of the sixth opening formed is smaller than the width of the third opening.
7. The method for preparing a semiconductor structure according to claim 2, wherein: A first shallow trench isolation structure is further formed in the substrate of the first region, and a top surface of the first shallow trench isolation structure is higher than a top surface of the silicon oxide layer of the first region; A second shallow trench isolation structure is further formed in the substrate of the second region, and a top surface of the second shallow trench isolation structure is higher than a top surface of the silicon oxide layer of the second region.
8. The method for preparing a semiconductor structure according to claim 7, wherein: The formation process of the silicon oxide layer, the first shallow trench isolation structure and the second shallow trench isolation structure includes: forming a first annular trench and a second annular trench in the substrate of the first and second regions; forming the silicon oxide layer on the inner wall surfaces of the first annular groove and the second annular groove and the substrate surfaces of the first region and the second region; forming a stop layer on the surface of the silicon oxide layer between the first annular trenches and on the silicon oxide layer between the second annular trenches; forming a filling layer on the silicon oxide layer and the stop layer, wherein the filling layer completely fills the first annular trench and the second annular trench; planarizing the filling layer until the stop layer is exposed, thereby forming the first shallow trench isolation structure and the second shallow trench isolation structure; The stop layer is removed.
9. The method for preparing a semiconductor structure according to claim 8, wherein: The first mask layer and the protection mask layer also cover the first shallow trench isolation structure and the second shallow trench isolation structure; After forming the first gate electrode, the method further includes: forming a first source doping region in the first source region, and forming a first drain doping region in the first drain region.
10. The method for preparing a semiconductor structure according to claim 1, wherein: Also includes: forming a second silicon oxide layer in the second region, wherein the thickness of the second silicon oxide layer is smaller than the thickness of the silicon oxide layer in the first region; A second gate electrode is formed on the second silicon oxide layer; and a second source doping region and a second drain doping region are respectively formed in the substrate on both sides of the second gate electrode.