Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method, and the semiconductor structure comprises a substrate which comprises a first region, a second region, and an interface region located between the first region and the second region; the dielectric layer is located on the substrate, a plurality of grid openings are formed in the dielectric layer, the grid openings are parallel to the first direction, the grid openings extend to the second region from the first region and stretch across the junction region, and the grid openings in the junction region have a first width in the second direction; the gate opening on the first region or the second region has a second width in a second direction, the first width is smaller than the second width, and the first direction is perpendicular to the second direction; and gate structures located in the plurality of gate openings to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of ultra-large-scale integrated circuit technology, the size of MOSFET devices has continued to decrease, typically through reductions in channel length and gate oxide thickness to achieve faster device speeds. However, at the ultra-deep submicron level, particularly at technology nodes of 45nm and below, the increased leakage associated with continued reductions in gate oxide thickness has become unsustainable. The industry introduced high-k gate insulators and metal gates at 45nm and below. After 28nm, the HKMG (high-k gate insulator + metal gate) gate-last process has been standardized due to the thermal stability of high-k (high dielectric constant) materials.

[0003] To improve device carrier mobility, advanced processes now incorporate numerous stress enhancement techniques. These factors have led to an increasing impact of the device's surrounding environment on its electrical characteristics, significantly impacting the device's GIDL current. Since the 28nm CMOS process node, replacement metal gate (RMG) technology has been widely used in HKMG devices. The use of different metal gate work function materials to adjust the N / PMOS threshold voltage has led to the N / P metal boundary effect (MBE). The MBE effect refers to the variation in work function between different types of metal boundaries, namely N-type and P-type metal boundaries, which affects the device's threshold voltage and channel current characteristics, thereby impacting device performance.

[0004] Therefore, reducing the impact of the MBE effect on devices is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region, a second region, and an intersection region between the first region and the second region; a dielectric layer located on the substrate, the dielectric layer having a plurality of gate openings therein, the plurality of gate openings being parallel to a first direction, the gate openings extending from the first region to the second region and spanning the intersection region, the gate openings on the intersection region having a first width in a second direction, the gate openings on the first region or the second region having a second width in the second direction, the first width being smaller than the second width, and the first direction being perpendicular to the second direction; and a gate structure located within the plurality of gate openings.

[0007] Optionally, the gate structure includes a first gate structure located on the first region, a second gate structure located on the second region, and a third gate structure located on the intersection region; the first gate structure includes a first blocking layer and a first work function layer located on the surface of the first blocking layer; the second gate structure includes a second blocking layer and a second work function layer located on the surface of the second blocking layer, and the work functions of the first work function layer and the second work function layer are different.

[0008] Optionally, the first gate structure further includes: a first gate dielectric layer and a first gate layer, the first barrier layer and the first work function layer are located on a surface of the first gate dielectric layer, and the first gate layer is located on a surface of the first work function layer.

[0009] Optionally, the material of the first barrier layer includes titanium nitride, tantalum nitride, or titanium nitride silicon, and the thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms.

[0010] Optionally, the material of the first work function layer includes titanium nitride or titanium aluminum alloy, and the thickness of the first work function layer is 30 angstroms to 85 angstroms.

[0011] Optionally, the second gate structure further includes: a second gate dielectric layer and a second gate layer, the second barrier layer and the second work function layer are located on a surface of the second gate dielectric layer, and the second gate layer is located on a surface of the second work function layer.

[0012] Optionally, the material of the second barrier layer includes titanium nitride, tantalum nitride, or titanium silicide nitride, and the thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms.

[0013] Optionally, the material of the second work function layer includes titanium nitride or titanium aluminum alloy, and the thickness of the second work function layer is 30 angstroms to 85 angstroms.

[0014] Optionally, the third gate structure includes: one or both of the first barrier layer and the second barrier layer located in the gate opening on the junction area, and one or both of the first barrier layer and the second barrier layer fully fill the gate opening on the junction area.

[0015] Optionally, the ratio of the first width to the second width is 0% to 30%.

[0016] Optionally, it further includes: a plurality of discrete fins located on the surface of the substrate, the fins are distributed in parallel along the second direction, and the gate structure spans the fins along the first direction and covers part of the sidewalls and top surfaces of the fins.

[0017] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region, a second region, and an intersection region between the first region and the second region; forming a dielectric layer on the substrate, the dielectric layer having a plurality of gate openings, the plurality of gate openings being parallel to a first direction, the gate openings extending from the first region to the second region and spanning the intersection region, the gate openings on the intersection region having a first width in the second direction, the gate openings on the first region or the second region having a second width in the second direction, the first width being smaller than the second width, and the first direction being perpendicular to the second direction; and forming a gate structure in the plurality of gate openings.

[0018] Optionally, the method for forming the dielectric layer and the plurality of gate openings includes: forming a dummy gate structure on the surface of the substrate, the dummy gate structure being parallel to a first direction, the dummy gate structure extending from the first region to the second region and spanning the junction region, the dummy gate structure on the junction region having a first width in the second direction, the dummy gate structure on the first region or the second region having a second width in the second direction, the first width being smaller than the second width; forming the dielectric layer on the surface of the substrate, the dielectric layer exposing the top surface of the dummy gate structure; and removing the dummy gate structure to form the gate opening.

[0019] Optionally, the method for forming the pseudo gate structure includes: forming a pseudo gate layer and an initial hard mask layer located on the surface of the pseudo gate layer on the surface of the substrate; thinning the sidewall of the initial hard mask layer on the junction area to form a hard mask layer; and etching the pseudo gate layer using the hard mask layer as a mask to form the pseudo gate structure.

[0020] Optionally, the method for thinning the sidewalls of the initial hard mask layer on the junction area includes: forming a patterned layer on the surface of the initial hard mask layer; and thinning the sidewalls of the initial hard mask layer using the patterned layer as a mask to form the hard mask layer.

[0021] Optionally, the method for forming the gate structure includes: filling a first sacrificial layer in the gate opening of the second region and the gate opening on the intersection region; after forming the first sacrificial layer, forming a first gate structure in the gate opening of the first region; after forming the first gate structure, removing the first sacrificial layer; after removing the first sacrificial layer, forming a second gate structure in the gate opening of the second region, and forming a third gate structure in the gate opening of the intersection region.

[0022] Optionally, the first gate structure includes a first gate dielectric layer formed of a high-k dielectric material within the gate opening of the first region; a first barrier layer formed on the surface of the first gate dielectric layer; a first work function layer formed on the surface of the first barrier layer; and a first gate layer formed on the surface of the first work function layer, wherein the material of the first barrier layer includes titanium nitride, tantalum nitride, and titanium silicide, and the thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms; the material of the first work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the first work function layer ranges from 30 angstroms to 85 angstroms.

[0023] Optionally, the second gate structure includes a second gate dielectric layer formed of a high-k dielectric material within the gate opening of the second region; a second barrier layer formed on the surface of the second gate dielectric layer; a second work function layer formed on the surface of the second barrier layer; and a second gate layer formed on the surface of the second work function layer, wherein the material of the second barrier layer includes titanium nitride, tantalum nitride, and titanium silicide, and the thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms; the material of the second work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the second work function layer ranges from 30 angstroms to 85 angstroms.

[0024] Optionally, the third gate structure includes: one or both of the first barrier layer and the second barrier layer formed in the gate opening on the junction area, and one or both of the first barrier layer and the second barrier layer fully fill the gate opening on the junction area.

[0025] Optionally, before forming the dielectric layer, the method further includes etching a portion of the substrate, wherein a plurality of fins are discretely arranged on the substrate, and the width of the intersection region in the first direction is less than or equal to 4 times the pitch between adjacent fins.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the semiconductor structure of the technical solution of the present invention, the gate opening on the intersection area has a first width in the second direction, the gate opening on the first area or the second area has a second width in the second direction, the first width is smaller than the second width, the first direction is perpendicular to the second direction, and the gate structure located in the gate opening utilizes the fact that the first width of the gate opening in the intersection area in the second direction is smaller than the second width of the gate opening in the first area or the second area in the second direction. The blocking layer in the gate structure can fill the gate opening in the intersection area, so that there is no space to form a work function layer in the gate opening in the intersection area, thereby avoiding the diffusion of diffused ions in the work function layer and improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 6 1 is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] As mentioned in the background art, the performance of existing semiconductor structures is relatively poor.

[0030] On this basis, the present invention provides a semiconductor structure, wherein the gate opening on the intersection area has a first width in the second direction, the gate opening on the first area or the second area has a second width in the second direction, the first width is smaller than the second width, the first direction is perpendicular to the second direction, and the gate structure located in the gate opening, utilizes the fact that the first width of the gate opening in the intersection area in the second direction is smaller than the second width of the gate opening in the first area or the second area in the second direction, the barrier layer in the gate structure can fill the gate opening in the intersection area, so that there is no space to form a work function layer in the gate opening in the intersection area, thereby avoiding the diffusion of diffused ions in the work function layer and improving the performance of the formed semiconductor structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 6 1 is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same in one embodiment of the present invention.

[0033] First, please refer to Figure 1 and Figure 2 A substrate 100 is provided, on which a plurality of discretely arranged fins 102 are formed, and an initial dummy gate structure 105 spanning the fins 102 is formed on the surface of the substrate 100.

[0034] Figure 2 for Figure 1 Cross-section along line AA.

[0035] In this embodiment, the substrate 100 includes a first region I, a second region II, and a connecting region III located between the first region I and the second region II.

[0036] In this embodiment, the first region I is used to form a PMOS device, and the second region II is used to form an NMOS device.

[0037] In other embodiments, the first region I is used to form an NMOS device, and the second region II is used to form a PMOS device.

[0038] In this embodiment, the method for forming the fin 102 includes: etching a portion of the thickness of the substrate 100 , and forming a plurality of discretely arranged fins 102 on the substrate 100 .

[0039] In this embodiment, an isolation structure 103 is formed on the surface of the substrate 100 . The top surface of the isolation structure 103 is lower than the top surface of the fin 102 .

[0040] In this embodiment, the method for forming the initial gate structure 105 includes: forming a gate dielectric layer 105 a on the sidewalls and top surface of the fin 102 , and forming a dummy gate layer 105 b on the surface of the gate dielectric layer 105 a .

[0041] Please refer to Figure 3 , the initial dummy gate structure 105 is etched to form a dummy gate structure 104 .

[0042] In this embodiment, the method for forming the pseudo gate structure 104 includes: forming an initial hard mask layer (not shown in the figure) on the surface of the pseudo gate layer 105b; thinning the sidewall of the initial hard mask layer on the intersection area III to form a hard mask layer (not shown in the figure); etching the pseudo gate layer 105b using the hard mask layer as a mask to form the pseudo gate structure 104.

[0043] In this embodiment, the method for thinning the sidewalls of the initial hard mask layer on the junction area III includes: forming a patterned layer (not shown in the figure) on the surface of the initial hard mask layer; and thinning the sidewalls of the initial hard mask layer using the patterned layer as a mask to form the hard mask layer (not shown in the figure).

[0044] In this embodiment, the dummy gate structure 104 is parallel to the first direction (Y), extends from the first region I to the second region II and crosses the intersection region III, and the dummy gate structure 104 on the intersection region III has a first width in the second direction (X). The dummy gate structure 104 on the first region I or the second region II has a second width in the second direction (X), and the first width is smaller than the second width.

[0045] In this embodiment, the width of the connecting region III in the first direction is less than 4 times the pitch between adjacent fins 102 .

[0046] In other embodiments, the width of the junction region III in the first direction may also be equal to 4 times the pitch between adjacent fins 102 .

[0047] In this embodiment, after the dummy gate structure 104 is formed, the hard mask layer and the patterned layer are removed.

[0048] Please refer to Figure 4 and Figure 5 A dielectric layer 106 is formed on the substrate 100 , and a plurality of gate openings 107 are formed in the dielectric layer 106 .

[0049] Figure 5 for Figure 4 Cross-section along line AA.

[0050] In this embodiment, the dielectric layer 106 exposes the top surface of the dummy gate structure 104 ; the dummy gate structure 104 is removed to form the gate opening 107 .

[0051] In this embodiment, the plurality of gate openings 107 are parallel to a first direction (Y), and the gate openings 107 extend from the first region I to the second region II and cross the intersection region III. The gate openings 107 on the intersection region III have a first width in the second direction (X), and the gate openings 107 on the first region I or the second region II have a second width in the second direction (X). The first width is smaller than the second width, and the first direction (Y) is perpendicular to the second direction (X).

[0052] Please refer to Figure 6 , forming a gate structure in the plurality of gate openings 107 .

[0053] Figure 6 The viewing direction and Figure 5 The viewing direction is the same.

[0054] In this embodiment, the method for forming the gate structure includes: filling a first sacrificial layer in the gate opening 107 of the second region II and the gate opening 107 on the intersection region III; after forming the first sacrificial layer, forming a first gate structure 108 in the gate opening 107 of the first region I; after forming the first gate structure 108, removing the first sacrificial layer; after removing the first sacrificial layer, forming a second gate structure 109 in the gate opening 107 of the second region II, and forming a third gate structure 110 in the gate opening 107 in the intersection region III.

[0055] In this embodiment, the first gate structure 108 includes a first gate dielectric layer 108a formed of a high-k dielectric material within the gate opening 107 of the first region I; a first barrier layer 108b formed on the surface of the first gate dielectric layer 108a; a first work function layer 108c formed on the surface of the first barrier layer 108b; and a first gate layer 108d formed on the surface of the first work function layer 108c.

[0056] In this embodiment, the material of the first barrier layer includes titanium nitride, tantalum nitride, or titanium silicide nitride, and the thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms.

[0057] In this embodiment, the first work function layer 108 c is a P-type work function layer. The material of the first work function layer 108 c includes titanium nitride. The thickness of the first work function layer 108 c is 30 angstroms to 85 angstroms.

[0058] In other embodiments, the first work function layer 108 c is also an N-type work function layer, and the material of the first work function layer 108 c includes titanium aluminum alloy, titanium carbon aluminum, and tantalum carbon aluminum.

[0059] In this embodiment, the second gate structure 109 includes a second gate dielectric layer 109a formed of a high-k dielectric material within the gate opening 107 of the second region II; a second barrier layer 109b formed on the surface of the second gate dielectric layer 109a; a second work function layer 109c formed on the surface of the second barrier layer 109b; and a second gate layer 109d formed on the surface of the second work function layer 109c.

[0060] In this embodiment, the material of the second barrier layer includes titanium nitride, tantalum nitride, and titanium silicide nitride, and the thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms.

[0061] In this embodiment, the second work function layer 109 c is an N-type work function layer. The material of the second work function layer 109 c includes titanium nitride or titanium aluminum alloy. The thickness of the second work function layer 109 c is 30 angstroms to 85 angstroms.

[0062] In other embodiments, the second work function layer 109 c may also be a P-type work function layer, and the material of the second work function layer 109 c includes titanium nitride.

[0063] In this embodiment, the third gate structure 110 includes one or both of the first barrier layer 108b and the second barrier layer 109b formed in the gate opening 107 on the intersection region III, and one or both of the first barrier layer 108b and the second barrier layer 109b fill the gate opening 107 on the intersection region III.

[0064] In this embodiment, the first barrier layer 108 b and the second barrier layer 109 b simultaneously fill the gate opening 107 on the junction region III.

[0065] In other embodiments, one of the first barrier layer 108 b and the second barrier layer 109 b fills the gate opening 107 on the junction region III.

[0066] In this embodiment, the third gate structure 110 further includes the first gate dielectric layer 108 a or the second gate dielectric layer 109 a formed in the gate opening 107 on the junction region III.

[0067] In this embodiment, the first width of the gate opening 107 in the intersection region III in the second direction (X) is smaller than the second width of the gate opening 107 in the first region I or the second region II in the second direction (X), and one or both of the first barrier layer 108b and the second barrier layer 109b fill the gate opening 107 in the intersection region III. There is no space for forming a work function layer in the gate opening 107 in the intersection region III, thereby avoiding the diffusion of diffused ions in the work function layer in the intersection region III and improving the performance of the formed semiconductor structure.

[0068] Using the above method, the present invention also provides a semiconductor structure, please refer to Figure 5, including a substrate 100, the substrate 100 including a first region I, a second region II, and an intersection region III located between the first region I and the second region II; a dielectric layer 106 located on the substrate 100, the dielectric layer 106 having a plurality of gate openings 107 therein, the plurality of gate openings 107 being parallel to a first direction (Y), the gate openings 107 extending from the first region I to the second region II and spanning the intersection region III, the gate openings 107 on the intersection region III having a first width in a second direction (X), the gate openings 107 on the first region I or the second region II having a second width in the second direction (X), the first width being smaller than the second width, and the first direction (Y) being perpendicular to the second direction (X); and a gate structure located within the plurality of gate openings 107.

[0069] In this embodiment, the gate structure includes a first gate structure 108 located on the first region I, a second gate structure 109 located on the second region II, and a third gate structure 110 located on the intersection region III; the first gate structure 108 includes a first blocking layer 108b and a first work function layer located on the surface of the first blocking layer 108b; the second gate structure 109 includes a second blocking layer 109b and a second work function layer located on the surface of the second blocking layer 109b, and the work functions of the first work function layer and the second work function layer are different.

[0070] In this embodiment, the first gate structure 108 further includes: a first gate dielectric layer 108a and a first gate layer 108d, the first barrier layer 108b and the first work function layer are located on the surface of the first gate dielectric layer 108a, and the first gate layer 108d is located on the surface of the first work function layer.

[0071] In this embodiment, the material of the first barrier layer includes titanium nitride, tantalum nitride, or titanium silicide nitride, and the thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms.

[0072] In this embodiment, the first work function layer 108 c is a P-type work function layer. The material of the first work function layer 108 c includes titanium nitride or titanium aluminum alloy. The thickness of the first work function layer 108 c is 30 angstroms to 85 angstroms.

[0073] In this embodiment, the second gate structure 109 further includes: a second gate dielectric layer 109a and a second gate layer 109d, the second barrier layer 109b and the second work function layer are located on the surface of the second gate dielectric layer 109a, and the second gate layer 109d is located on the surface of the second work function layer.

[0074] In this embodiment, the material of the second barrier layer 109b includes titanium nitride, tantalum nitride, or titanium nitride silicon. The thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms.

[0075] In this embodiment, the second work function layer 109 c is an N-type work function layer. The material of the second work function layer 109 c includes titanium nitride or titanium aluminum alloy. The thickness of the second work function layer 109 c is 30 angstroms to 85 angstroms.

[0076] In this embodiment, the third gate structure 110 includes: one or both of the first barrier layer 108b and the second barrier layer 109b located in the gate opening 107 on the intersection region III, and one or both of the first barrier layer 108b and the second barrier layer 109b fill the gate opening 107 on the intersection region III.

[0077] In this embodiment, the first barrier layer 108 b and the second barrier layer 109 b simultaneously fill the gate opening 107 on the junction region III.

[0078] In this embodiment, the ratio of the first width to the second width is 0% to 30%.

[0079] In this embodiment, it also includes: a plurality of discrete fins 102 located on the surface of the substrate 100, the fins 102 are distributed in parallel along the second direction (X), and the gate structure spans the fins 102 along the first direction (Y) and covers part of the sidewalls and top surface of the fins 102.

[0080] In this embodiment, the first width of the gate opening 107 in the intersection region III in the second direction (X) is smaller than the second width of the gate opening 107 in the first region I or the second region II in the second direction (X), and one or both of the first barrier layer 108b and the second barrier layer 109b fill the gate opening 107 in the intersection region III. There is no space for forming a work function layer in the gate opening 107 in the intersection region III, thereby avoiding the diffusion of diffused ions in the work function layer in the intersection region III and improving the performance of the formed semiconductor structure.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region, a second region, and a junction region between the first region and the second region; a dielectric layer located on the substrate, the dielectric layer having a plurality of gate openings therein, the plurality of gate openings being parallel to a first direction, the gate openings extending from the first region to the second region and crossing the intersection region, the gate openings in the intersection region having a first width in the second direction, the gate openings in the first region or the second region having a second width in the second direction, the first width being smaller than the second width, and the first direction being perpendicular to the second direction; A gate structure is located within the gate openings.

2. The semiconductor structure according to claim 1, wherein The gate structure includes a first gate structure located on the first area, a second gate structure located on the second area, and a third gate structure located on the intersection area; the first gate structure includes a first blocking layer and a first work function layer located on the surface of the first blocking layer; the second gate structure includes a second blocking layer and a second work function layer located on the surface of the second blocking layer, and the work functions of the first work function layer and the second work function layer are different.

3. The semiconductor structure according to claim 2, wherein: The first gate structure further includes: a first gate dielectric layer and a first gate layer. The first barrier layer and the first work function layer are located on a surface of the first gate dielectric layer. The first gate layer is located on a surface of the first work function layer.

4. The semiconductor structure according to claim 3, wherein: The material of the first barrier layer includes titanium nitride, tantalum nitride, and titanium silicide nitride. The thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms.

5. The semiconductor structure according to claim 3, wherein: The material of the first work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the first work function layer is 30 angstroms to 85 angstroms.

6. The semiconductor structure according to claim 2, wherein: The second gate structure further includes: a second gate dielectric layer and a second gate layer. The second barrier layer and the second work function layer are located on the surface of the second gate dielectric layer. The second gate layer is located on the surface of the second work function layer.

7. The semiconductor structure according to claim 6, wherein: The material of the second barrier layer includes titanium nitride, tantalum nitride, and titanium silicide nitride. The thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms.

8. The semiconductor structure according to claim 6, wherein: The material of the second work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the second work function layer is 30 angstroms to 85 angstroms.

9. The semiconductor structure according to claim 2, wherein: The third gate structure includes: one or both of the first barrier layer and the second barrier layer located in the gate opening on the intersection region, and one or both of the first barrier layer and the second barrier layer fully fill the gate opening on the intersection region.

10. The semiconductor structure according to claim 1, wherein The ratio of the first width to the second width is 0% to 30%.

11. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of discrete fins are located on the surface of the substrate. The fins are distributed in parallel along the second direction. The gate structure spans the fins along the first direction and covers part of the sidewalls and top surfaces of the fins.

12. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region, and a junction region between the first region and the second region; A dielectric layer is formed on the substrate, wherein the dielectric layer has a plurality of gate openings, the plurality of gate openings being parallel to a first direction, the gate openings extending from the first region to the second region and crossing the intersection region, the gate openings on the intersection region having a first width in the second direction, the gate openings on the first region or the second region having a second width in the second direction, the first width being smaller than the second width, and the first direction being perpendicular to the second direction; A gate structure is formed in the plurality of gate openings.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the dielectric layer and the plurality of gate openings comprises: forming a dummy gate structure on the surface of the substrate, the dummy gate structure being parallel to a first direction, the dummy gate structure extending from the first region to the second region and crossing the intersection region, the dummy gate structure on the intersection region having a first width in the second direction, the dummy gate structure on the first region or the second region having a second width in the second direction, the first width being smaller than the second width; forming the dielectric layer on the surface of the substrate, the dielectric layer exposing a top surface of the dummy gate structure; The dummy gate structure is removed to form the gate opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the pseudo gate structure includes: forming a pseudo gate layer and an initial hard mask layer located on the surface of the pseudo gate layer on the surface of the substrate; thinning the sidewall of the initial hard mask layer on the intersection area to form a hard mask layer; and etching the pseudo gate layer using the hard mask layer as a mask to form the pseudo gate structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for thinning the sidewall of the initial hard mask layer on the junction area includes: forming a patterned layer on the surface of the initial hard mask layer; and thinning the sidewall of the initial hard mask layer using the patterned layer as a mask to form the hard mask layer.

16. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the gate structure includes: filling a first sacrificial layer in the gate opening of the second region and the gate opening on the intersection region; after forming the first sacrificial layer, forming a first gate structure in the gate opening of the first region; after forming the first gate structure, removing the first sacrificial layer; after removing the first sacrificial layer, forming a second gate structure in the gate opening of the second region, and forming a third gate structure in the gate opening of the intersection region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The first gate structure includes a first gate dielectric layer formed of a high-k dielectric material within the gate opening of the first region; a first barrier layer formed on the surface of the first gate dielectric layer; a first work function layer formed on the surface of the first barrier layer; and a first gate layer formed on the surface of the first work function layer. The material of the first barrier layer includes titanium nitride, tantalum nitride, and titanium silicide, and the thickness of the first barrier layer ranges from 30 angstroms to 80 angstroms. The material of the first work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the first work function layer ranges from 30 angstroms to 85 angstroms.

18. The method for forming a semiconductor structure according to claim 17, wherein: The second gate structure includes a second gate dielectric layer formed of a high-k dielectric material within the gate opening of the second region; a second barrier layer formed on the surface of the second gate dielectric layer; a second work function layer formed on the surface of the second barrier layer; and a second gate layer formed on the surface of the second work function layer. The material of the second barrier layer includes titanium nitride, tantalum nitride, and titanium silicide, and the thickness of the second barrier layer ranges from 20 angstroms to 45 angstroms. The material of the second work function layer includes titanium nitride and titanium aluminum alloy, and the thickness of the second work function layer ranges from 30 angstroms to 85 angstroms.

19. The method for forming a semiconductor structure according to claim 18, wherein: The third gate structure includes: one or both of the first barrier layer and the second barrier layer formed in the gate opening on the intersection region, and one or both of the first barrier layer and the second barrier layer fully fill the gate opening on the intersection region.

20. The method for forming a semiconductor structure according to claim 12, wherein: Before forming the dielectric layer, the method further includes etching a portion of the substrate, wherein a plurality of fins are arranged discretely on the substrate, and the width of the intersection region in the first direction is less than or equal to 4 times the pitch between adjacent fins.

Images